TWI784566B - Method for processing a substrate - Google Patents

Abstract

The present invention provides a method for processing a substrate, which includes the following steps. First, a substrate is provided, and a lithography etching process is performed to form a patterned oxide layer on the surface of the substrate, and the patterned oxide layer includes a plurality of grooves. And, a thermal oxidation process is performed to form a post-oxide layer on the surface of the substrate, wherein the post-oxide layer has a thicker thickness at positions corresponding to the plurality of grooves of the patterned oxide layer. Further, a removal process is performed to remove the patterned oxide layer and the post-oxide layer, thereby forming a void structure on the surface of the substrate. The present invention further provides a substrate structure processed by the method for processing a substrate, which absorbs the stress accumulation of the epitaxial layer through the void structure on the surface, and suppresses the occurrence of dislocation at the heterostructure between the substrate and the epitaxial layer, thereby improving the quality of the formed epitaxy and the warpage between the substrate and the epitaxial layer.

Description

Substrate processing method

The invention relates to a substrate processing method, and in particular to a substrate processing method for forming a void structure on a substrate surface and a substrate structure processed by the processing method.

When growing heteroepitaxy on a substrate, stress accumulation and threading dislocation (threading dislocation) will occur in the formed epitaxial layer due to the lattice mismatch and the difference in thermal expansion coefficient between the epitaxial layer and the substrate during high temperature growth. ), which will affect the warpage of the wafer and cause the quality of the subsequently grown epitaxial layer to deteriorate.

Generally, technologies such as Epitaxially Lateral Overgrowth (ELOG) or Pendeoepitaxy (PE) can be used to reduce the defect density of the subsequently grown epitaxial layer. Among them, both ELOG and PE provide a pattern on the surface of the substrate before forming the epitaxial layer, so that the dislocation (dislocation) generated during the formation of the epitaxial layer can be limited to a specific area of the substrate (that is, where no pattern is provided). However, using the above method still generates many dislocations in the hetero-interface between the substrate and the epitaxial layer.

Therefore, the present invention improves on the shortcomings of the prior art, and further provides a substrate processing method.

In order to solve the above-mentioned problems of the prior art, the object of the present invention is to provide a substrate processing method for forming a void structure on the surface of the substrate, and the void structure includes a plurality of voids of uniform size.

Based on the above purpose, the present invention provides a substrate processing method, which includes the following steps. Firstly, a substrate is provided, and the substrate has a first surface and a second surface opposite to the first surface. A photolithographic etching process is performed to form a patterned oxide layer including a plurality of grooves on the first surface of the substrate. A thermal oxidation process is performed to form a thicker oxide layer at positions corresponding to the plurality of grooves of the patterned oxide layer on the first surface of the substrate. And, a removal process is performed to remove the patterned oxide layer and the post-oxidation layer, so as to form a void structure on the first surface of the substrate.

Preferably, the step of providing the substrate includes the following steps. First, a device wafer is provided, and the device wafer is soaked in the mixed solution for one hour. A carrier wafer is provided, and a silicon dioxide oxide insulating layer is formed on the carrier wafer by a high-temperature oxidation process. And, the device wafer and the silicon dioxide oxide insulating layer of the carrier wafer are aligned and bonded in a normal pressure vacuum environment, and heat treatment is performed at a temperature ranging from 800°C to 1000°C to obtain Silicon-on-chip wafers.

Preferably, the step of providing the substrate further includes the following steps. First, the silicon-on-insulator wafer is heat-treated at a temperature ranging from 600°C to 1150°C. And, the silicon-on-insulator wafer is thinned by using a diamond grinding wheel, and the surface of the silicon-on-insulator wafer is formed into a rough surface with high uniformity by using a wet planarization process or a dry planarization process.

Preferably, the mixed solution contains sulfuric acid and hydrogen peroxide, and the volume ratio of sulfuric acid to hydrogen peroxide is 3:1, and the temperature of the mixed solution is 90°C.

Preferably, the lithographic etching process includes electron beam lithographic etching, ion beam lithographic etching or direct etching using X-rays.

Preferably, the plurality of grooves have a first width and a second width, and the first width is in a range of 50 nm to 500 μm, and the second width is in a range of 1 mm to 10 mm.

Preferably, the first width of the plurality of grooves is 1 μm, and the second width is 1 mm.

Preferably, the removal process further includes the following steps: removing the patterned oxide layer and the post-oxidation layer with hydrofluoric acid aqueous solution to obtain a substrate with a void structure, and the void structure includes a plurality of voids with uniform sizes.

Preferably, the plurality of voids have a depth ranging from 10 nm to 2 μm.

Based on the above purpose, the present invention further provides a substrate structure, which includes a carrier wafer, a silicon dioxide oxide insulating layer, a device wafer and a void structure. Wherein, the silicon dioxide oxide insulating layer is formed on the surface of the carrying wafer, and the device wafer is bonded on the silicon dioxide oxide insulating layer. In addition, the void structure is formed on the surface of the device wafer and includes a plurality of voids.

Preferably, the plurality of voids have a depth ranging from 10 nm to 2 μm.

To sum up, the present invention provides a substrate processing method, through which a void structure can be formed on the surface of the substrate. The void structure includes a plurality of voids of uniform size, which are used to absorb the stress accumulation of the epitaxial layer, and can suppress the dislocation of the heterogeneous interface between the substrate and the epitaxial layer, thereby improving the quality of the subsequent epitaxial layer And the warpage problem between the substrate and the epitaxial layer.

10: Substrate

101:Device wafer

102: carrier wafer

1021: silicon dioxide oxide insulating layer

1001: first surface

1002: second surface

20: Patterned oxide layer

201: Groove

30: post oxide layer

40: void structure

401: Gap

4011: void depth

S101, S102, S103, S104, S201, S202, S203, S204, S205, S206, S207: steps

In order to illustrate the technical solution of the present invention more clearly, the drawings that need to be used in the embodiments will be briefly introduced below; Fig. 1 is a flow chart of a substrate processing method according to an embodiment of the present invention; Fig. 2 is A flowchart of a method for manufacturing a substrate to be processed according to an embodiment of the present invention; FIG. 3 is a schematic diagram of a substrate to be processed according to an embodiment of the present invention; FIG. 4 is a patterned oxide film formed according to an embodiment of the present invention layer; FIG. 5 is a schematic diagram of a substrate formed with a post-oxidation layer according to an embodiment of the present invention; and FIG. 6 is a schematic diagram of a processed substrate structure according to an embodiment of the present invention.

The advantages, features and technical methods achieved by the present invention will be described in more detail with reference to exemplary embodiments and accompanying drawings to make it easier to understand, and the present invention can be implemented in different forms, so it should not be understood as being limited to what is shown here The stated embodiments, on the contrary, for those with ordinary knowledge in the technical field, the provided embodiments will make this disclosure more thorough, comprehensive and completely convey the scope of the present invention, and the protection scope of the present invention will only be The scope of the appended claims is defined.

It should be understood that although the terms "first", "second" and the like may be used in the present invention to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections Should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer and/or section from another element, component, region, layer and/or section. Accordingly, "first element", "first component", "first region", "first layer" and/or "first portion" discussed below may be referred to as "second element", "second component" , "second region", "second layer" and/or "second part", without departing from the spirit and teachings of the present invention.

In addition, the terms "comprising" and/or "comprising" refer to the presence of stated features, regions, integers, steps, operations, elements and/or parts, but do not exclude one or more other features, regions, integers, steps, operations , the presence or addition of elements, parts and/or combinations thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted to have definitions consistent with their meanings in the context of the relevant art and the present invention, and will not be interpreted as idealistic or overly formal unless otherwise expressly defined herein.

The present invention will be further described in detail below in conjunction with the accompanying drawings. These drawings are all simplified schematic diagrams, which only schematically illustrate the basic structure of the present invention, and exaggerate the proportion and size of components for the sake of clarity, and therefore are not intended to limit the present invention.

Please refer to Fig. 1, Fig. 3, Fig. 4, Fig. 5 and Fig. 6, Fig. 1 is a flowchart of a substrate processing method according to an embodiment of the present invention; Fig. 3 is a flowchart according to an embodiment of the present invention A schematic diagram of the substrate to be processed; Figure 4 is a schematic diagram of a substrate formed with a patterned oxide layer according to an embodiment of the present invention; Figure 5 is a schematic diagram of a substrate formed with a post-oxidation layer according to an embodiment of the present invention; And FIG. 6 is a schematic diagram of a processed substrate structure according to an embodiment of the present invention.

As shown in FIG. 1 , the present invention provides a substrate processing method, which includes the following steps. In step S101 , a substrate 10 is provided, and the substrate 10 has a first surface 1001 and a second surface 1002 opposite to the first surface 1001 . Step S102 , performing a lithographic etching process to form a patterned oxide layer 20 on the first surface 1001 of the substrate 10 , and pattern the oxide layer 20 to form a plurality of grooves 201 . Step S103, performing a thermal oxidation process to form a rear oxide layer 30 on the first surface 1001 of the substrate 10, wherein the rear oxide layer 30 has a thicker thickness at positions corresponding to the plurality of grooves 201 of the patterned oxide layer 20. Spend. And step S104 , performing a removal process to remove the patterned oxide layer 20 and the post-oxidation layer 30 , so as to form the void structure 40 on the first surface 1001 of the substrate 10 .

Specifically, in step S101 , firstly, a silicon-on-insulator wafer is provided as the substrate 10 to be processed. As shown in FIG. 3 , the substrate 10 includes a carrier wafer 102 , a silicon oxide insulating layer 1021 formed on the carrier wafer 102 , and a device wafer 101 bonded to the silicon oxide insulating layer 1021 , wherein, The surface of the device wafer 101 is the first surface 1001 on which the void structure 40 is subsequently formed, and the surface of the carrying wafer 102 opposite to the first surface 1001 is the second surface 1002 . In addition, the method for providing the above-mentioned SOI wafer as the substrate 10 to be processed will be described in detail in another embodiment below.

Further, in step S102 , a lithographic etching process is performed on the substrate 10 to form a patterned oxide layer 20 on the first surface 1001 of the substrate 10 . As shown in FIG. 4 , the patterned oxide layer 20 includes a plurality of grooves 201 of uniform size, and the bottom of each groove 201 exposes a portion of the first surface 1001 of the substrate 10 . With this configuration, in the subsequent heat treatment process, the part of the substrate 10 exposed by each groove 201 can be formed with a thicker post-oxidation layer 30, and the post-oxidation layer 30 with an inconsistent thickness is used for the subsequent void structure 40. Formation.

In this embodiment, electron beam lithography etching is used to perform the above lithography etching process, but the invention is not limited thereto. In other embodiments, the lithography process may include ion beam lithography etching or direct etching using X-rays.

It is worth mentioning that the plurality of grooves 201 formed on the patterned oxide layer 20 on the first surface 1001 of the substrate 10 have a first width and a second width. In this embodiment, the first width is 1 μm, and the second width is 1 mm, but the present invention is not limited thereto. In other embodiments, according to the user's The conditions of the lithographic etching process can be adjusted according to the size requirements of the subsequently formed void structure 40, so that the first width of each groove 201 is in the range of 50 nm to 500 μm, and the second width is in the range of 1 mm to 10 mm. within range. In addition, the groove depth of the plurality of grooves 201 is in the range of 1 nm˜1000 nm.

After step S102 is performed to form the patterned oxide layer 20 on the first surface 1001 of the substrate 10 , step S103 is subsequently performed. In step S103, a thermal oxidation process is performed on the substrate 10 to form a rear oxide layer 30 on the first surface 1001 of the substrate 10, wherein the rear oxide layer 30 has a plurality of grooves 201 corresponding to the patterned oxide layer 20. Thicker thickness. Specifically, the thermal oxidation process described in step S103 includes heat treatment for 15 seconds to 300 seconds at a process temperature ranging from 100° C. to 300° C. As shown in FIG. 5, the substrate 10 exposed by the plurality of grooves 201 of the patterned oxide layer 20 is more susceptible to the impact of the thermal oxidation process, resulting in a higher degree of oxidation, so corresponding to the plurality of grooves 201 The post-oxidation layer 30 at has a relatively thick thickness. Correspondingly, the oxidation degree of the part of the substrate blocked by the patterned oxide layer 20 is lower, so that the thickness of the rear oxide layer 30 here is thinner. With the above configuration, the post-oxidation layer 30 can have different thicknesses corresponding to the patterned oxide layer 20, so after removing the patterned oxide layer 20 and the post-oxidation layer 30, it can be formed on the first surface 1001 of the substrate 10. A plurality of voids 401 of uniform size.

In step S104 , a removal process is performed on the substrate 10 to remove the patterned oxide layer 20 and the post-oxidation layer 30 on the substrate 10 . Specifically, the removal process includes the following steps: using hydrofluoric acid aqueous solution to remove the patterned oxide layer 20 and the post-oxidation layer 30 to obtain the substrate 10 with the void structure 40 , as shown in FIG. 6 . Wherein, the void structure 40 includes a plurality of voids 401 with a uniform size, the void depth 4011 of the plurality of voids 401 is in the range of 10 nm to 2 μm, and the size of the plurality of voids 401 corresponds to the plurality of the patterned oxide layer 20 The size of the groove 201. Through the above steps S101 to S104, the substrate 10 with the void structure 40 formed on the first surface 1001 can be obtained. through the gap The arrangement of the structure 40 can absorb the stress accumulation of the epitaxial layer subsequently formed on the substrate 10 , and can suppress the dislocation of the heterogeneous interface between the substrate 10 and the epitaxial layer.

Please refer to FIG. 2 and FIG. 3. FIG. 2 is a flowchart of a method for manufacturing a substrate to be processed according to an embodiment of the present invention; and FIG. 3 is a schematic diagram of a substrate to be processed according to an embodiment of the present invention.

As shown in FIG. 2 , this embodiment provides a method for manufacturing a silicon-on-insulator wafer, which is used as the substrate 10 to be processed in the first embodiment, and includes the following steps. Step S201 , providing a device wafer 101 . Step S202 , immersing the device wafer 101 in the mixed solution for one hour to obtain a processed device wafer 101 . Step S203 , providing a carrier wafer 102 . In step S204 , a silicon dioxide oxide insulating layer 1021 is formed on the carrier wafer 102 by using a high temperature oxidation process. Step S205, aligning and bonding the device wafer 101 and the silicon dioxide insulating layer 1021 carrying the wafer 102 under normal pressure and vacuum environment, and performing heat treatment at a temperature ranging from 800° C. to 1000° C. to A silicon-on-insulator wafer is obtained. Step S206 , heat-treating the silicon-on-insulator wafer at a temperature ranging from 600° C. to 1150° C. And step S207 , using a diamond grinding wheel to thin the silicon-on-insulator wafer, and using a wet planarization process or a dry planarization process to form the surface of the silicon-on-insulator wafer into a rough surface with high uniformity.

Specifically, in step S201 , a silicon wafer is provided as the device wafer 101 , and the surface of the device wafer 101 is rinsed alternately with deionized water and acetone, so as to preliminarily remove the surface dirt of the device wafer 101 . Then step S202 is executed to further clean the surface of the device wafer 101 by soaking the device wafer 101 in the mixed solution. In this embodiment, the mixed solution contains sulfuric acid and hydrogen peroxide, and the volume ratio of sulfuric acid to hydrogen peroxide is 3:1, and the temperature of the mixed solution is 90°C.

Further, in step S203, another silicon wafer is provided as the carrier wafer 102, and then step S204 is performed to form a layer of highly dense silicon dioxide on one surface of the carrier wafer 102 by performing a high temperature oxidation process. The insulating layer 1021 is oxidized. Wherein, the thickness of the silicon dioxide insulating layer 1021 may range from tens of nanometers to several microns, and in this embodiment, the thickness of the silicon dioxide insulating layer 1021 is 0.5 μm.

Moreover, in step S205, the above-mentioned processed device wafer 101 and the silicon dioxide oxide insulating layer 1021 of the carrier wafer 102 are aligned and bonded in a normal pressure vacuum environment, and the temperature is between 800 ° C ~ 1000 ° C The heat treatment is carried out at a temperature within 1 to 30 minutes, so that a tight physical bonding (bonding) is produced between the device wafer 101 and the carrier wafer 102 to obtain a silicon-on-insulator wafer.

After the device wafer 101 and the carrier wafer 102 are bonded in step S205 to form a silicon-on-insulator wafer, step S206 is performed to place the silicon-on-insulator wafer at a temperature ranging from 600° C. to 1150° C. The heat treatment is carried out at a high temperature for more than 1 hour, so as to further generate chemical bonding on the bonding surface between the device wafer 101 and the carrier wafer 102 , thereby improving the bond strength between the device wafer 101 and the carrier wafer 102 . Finally, in step S207 , the device wafer 101 in the silicon-on-insulator wafer is thinned to tens of microns by using a diamond grinding wheel. In addition, a wet planarization process or a dry planarization process is further used for modification for 0.2 to 30 minutes, so that the surface of the device wafer 101 side of the silicon-on-insulator wafer is formed into a rough surface with high uniformity. Through the steps S201 to S207 above, a silicon-on-insulator wafer serving as the substrate 10 to be processed in the substrate processing method of the first embodiment of the present invention can be obtained, as shown in FIG. 3 . Specifically, in this embodiment, a wet planarization process is used to modify the silicon-on-insulator wafer, which includes cleaning the silicon-on-insulator wafer with hydrogen peroxide to oxidize the surface, and then cleaning with ammonia water to The micro-etching of silicon dioxide by ammonia water removes the particles on the surface of the silicon wafer on the insulating layer, so as to achieve the effect of modification.

Please refer to FIG. 6 , which is a schematic diagram of a processed substrate structure according to an embodiment of the present invention.

As shown in FIG. 6 , the present invention further provides a substrate 10 structure, which is manufactured through the substrate processing method described in the above-mentioned embodiments. A void structure 40 is formed on the first surface 1001 of the substrate 10 structure, and the void structure 40 includes a plurality of voids 401 of uniform size.

Specifically, the structure of the substrate 10 described in the present invention includes a carrier wafer 102 , a silicon dioxide oxide insulating layer 1021 , a device wafer 101 and a void structure 40 . Wherein, the silicon dioxide oxide insulating layer 1021 is formed on the surface of the carrier wafer 102 , and the device wafer 101 is bonded on the silicon dioxide oxide insulating layer 1021 . In addition, the void structure 40 is formed on the surface of the device wafer 101 , and the void structure 40 includes a plurality of voids 401 .

Further, the bonding of the device wafer 101 and the carrier wafer 102 includes the following steps. First, a silicon wafer is provided as the device wafer 101, and another silicon wafer is provided as the carrier wafer 102, and the carrier wafer 102 is processed by a high temperature oxidation process to form the oxide on the surface of the carrier wafer 102. Silicon oxide insulating layer 1021 . The device wafer 101 and the silicon dioxide insulating layer 1021 carrying the wafer 102 are aligned and bonded in a normal pressure vacuum environment, and heat treated at a first temperature. And, the bonded device wafer 101 and the carrier wafer 102 are heat-treated again at a second temperature to obtain a silicon-on-insulator wafer. Wherein, in this embodiment, the first temperature is in the range of 800°C to 1000°C, and the second temperature is in the range of 600°C to 1150°C.

In addition, by using the substrate processing method described in the first embodiment of the present invention to process the silicon-on-insulator wafer, the void structure 40 can be formed on the surface of the device wafer 101. The detailed steps are as in the first As described in the embodiments, details are not repeated here. It is worth mentioning that the void structure 40 contains A plurality of voids 401 of uniform size, and a void depth 4011 of the plurality of voids 401 is in the range of 10 nm to 2 μm.

In summary, the present invention provides a substrate processing method and a substrate structure. Through the substrate processing method of the present invention, a void structure can be formed on the surface of the substrate, and the void structure includes a plurality of voids of uniform size. With the setting of the void structure, the stress accumulation of the epitaxial layer can be absorbed during the subsequent process of growing the epitaxial layer on the substrate, and the generation of dislocation of the heterogeneous interface between the substrate and the epitaxial layer can be suppressed, thereby improving the subsequent formation of the epitaxial layer. Crystal quality and warpage between the substrate and the epitaxial layer.

The present invention has been described with reference to exemplary embodiments, and it will be understood by those skilled in the art that changes in form and details can be made without departing from the concept and scope of the present invention defined by the claims. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application as a principle.

S101, S102, S103, S104: steps

Claims (9)

A substrate processing method, comprising: providing a substrate, the substrate has a first surface and a second surface opposite to the first surface; performing a lithographic etching process to form a substrate on the first surface of the substrate comprising A patterned oxide layer of a plurality of grooves; a thermal oxidation process is performed to form one of a thicker thickness at a position corresponding to the plurality of grooves of the patterned oxide layer on the first surface of the substrate post-oxidation layer; and performing a removal process to remove the patterned oxide layer and the post-oxidation layer to form a void structure on the first surface of the substrate. The substrate processing method as described in claim 1, wherein the step of providing the substrate includes: providing a device wafer, soaking the device wafer in a mixed solution for one hour; providing a carrier wafer, and using a high temperature oxidation process on A silicon dioxide insulating layer is formed on the carrier wafer; and the device wafer and the silicon dioxide insulating layer of the carrier wafer are aligned and bonded under normal pressure and vacuum environment, and the temperature is between 800°C Heat treatment is performed at a temperature in the range of ~1000°C to obtain a silicon-on-insulator wafer. The substrate processing method as described in Claim 2, wherein the step of providing the substrate further comprises: heat-treating the silicon-on-insulator wafer at a temperature ranging from 600°C to 1150°C; The chemical process makes the surface of the silicon-coated wafer on the insulating layer form a rough surface with high uniformity. The substrate processing method according to claim 2, wherein the mixed solution contains sulfuric acid and hydrogen peroxide, and the volume ratio of sulfuric acid to hydrogen peroxide is 3:1, and the temperature of the mixed solution is 90°C. The substrate processing method according to claim 1, wherein the lithographic etching process includes electron beam lithographic etching, ion beam lithographic etching or direct etching using X-rays. The substrate processing method as claimed in claim 1, wherein the plurality of grooves have a first width and a second width, the first width is in the range of 50 nm to 500 μm, and the second width is in the range of In the range of 1mm to 10mm. The substrate processing method according to claim 6, wherein the first width of the plurality of grooves is 1 μm, and the second width is 1 mm. The substrate processing method as described in Claim 1, wherein the removal process further comprises: removing the patterned oxide layer and the post-oxidation layer using hydrofluoric acid aqueous solution to obtain the substrate with the void structure, and the void The structure contains a plurality of voids of uniform size. The substrate processing method as claimed in claim 8, wherein the plurality of voids have a depth ranging from 10 nm to 2 μm.

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