TWI783446B - Voltage tracking circuits and electronic circuits - Google Patents

Abstract

A voltage tracking circuit is provided to track a higher one among a first voltage at a first voltage terminal and a second voltage at a second voltage terminal to generate an output voltage. The voltage tracking circuit includes first and second P-type transistors and a voltage decreasing voltage. The drain of the first P-type transistor is coupled to the first voltage terminal. The voltage decreasing circuit is coupled between the first voltage terminal and the gate of the first P-type transistor. The voltage decreasing circuit decreases the first voltage by a modulation voltage to generate a control voltage and provides the control voltage to the gate of the first P-type transistor. The gate of the second P-type transistor is coupled to the first voltage terminal, and the drain thereof is coupled to the second voltage terminal. The source of the first P-type transistor and the source of the second P-type transistor are coupled to the output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal.

Description

Voltage tracking circuit and electronic circuit

The present invention relates to a voltage tracking circuit, in particular to a voltage tracking circuit for high-voltage circuits.

Generally speaking, when an N-type metal oxide semiconductor (NMOS) is used on the high voltage side of an electronic circuit, overvoltage may occur on its source/base, making the parasitic of the NMOS transistor The bipolar diode conducts, causing leakage current to occur. Leakage current can cause the electronic circuit to overheat and damage the electronic circuit. Therefore, how to reduce the leakage current caused by the overvoltage is an important issue.

In view of this, the present invention proposes a voltage tracking circuit. The voltage tracking circuit is used for tracking one of a first voltage on a first voltage terminal and a second voltage on a second voltage terminal to generate an output voltage. The voltage tracking circuit includes a first P-type transistor, a step-down circuit, and a second P-type transistor. The first P-type transistor has a gate, a drain, and a source, and the drain of the first P-type transistor is coupled to the first a voltage terminal. The step-down circuit is coupled between the first voltage terminal and the gate of the first P-type transistor, and provides a regulated voltage. The step-down circuit reduces the first voltage by adjusting the voltage to generate a control voltage and provides the control voltage to the gate of the first P-type transistor. The second P-type transistor has a gate, a drain, and a source. The gate of the second P-type transistor is coupled to the first voltage end, and the drain of the second P-type transistor is coupled to the second voltage end. The source of the first P-type transistor and the source of the second P-type transistor are coupled to an output end of the voltage tracking circuit, and the output voltage is generated at the output end.

The invention further provides an electronic circuit. The electronic circuit includes a high voltage side element and a voltage tracking circuit. The high-voltage side element has a first electrode end and a second electrode end, and is surrounded by an isolated deep well region. The voltage tracking circuit is coupled to the first electrode terminal and the second electrode terminal, and is used to track one of a first voltage on the first electrode terminal and a second voltage on the second electrode terminal to generate an output terminal an output voltage, and the output voltage is applied to the isolated deep well region surrounding the high side components. The voltage tracking circuit includes a first P-type transistor, a step-down circuit, and a second P-type transistor. The first P-type transistor has a gate, a drain and a source. The drain of the first P-type transistor is coupled to the first electrode terminal. The step-down circuit is coupled between the first electrode terminal and the gate of the first P-type transistor, and provides a regulation voltage. The step-down circuit lowers the first voltage by adjusting the voltage to generate a control voltage, and provides the control voltage to the gate of the first P-type transistor. The second P-type transistor has a gate, a drain, and a source. The gate of the second P-type transistor is coupled to the first electrode end, and the drain of the second P-type transistor is coupled to the second electrode end. The source of the first P-type transistor and the source of the second P-type transistor are coupled to the output end of the voltage tracking circuit.

1: Electronic circuit

10,11: NMOS transistor

12: I/O pad

13: Inductor

14: Voltage tracking circuit

20,21: PMOS transistor

22: Step-down circuit

30~32: PMOS transistor

40~42: Diode

50~52: PMOS transistor

60: Resistor

100: N-type isolated deep well area

101,111,201,211,301,311,321,501,511,521: gate

102,112,202,212,302,312,322,502,512,522: drain

103,113,203,213,303,313,323,5603,513,523: source

104,114,204,214,304,314,324,504,514,524: base

105: P-type well area

106:N type well area

107: N-type doped region

108: P-type doped region

109: P-type well area

110: N-type isolated deep well area

GND: ground terminal

N10: node

N20: input node

N21: Input node

N30, N31: nodes

N40, N41: nodes

N50, N51: nodes

NBL: N-type buried layer

P20, P21: current path

SUB:P type substrate

T10, T11: voltage terminal

T12: output terminal

V22: Control voltage

VD: Voltage

VS/B: voltage

Fig. 1 shows an electronic circuit of an embodiment of the present invention.

FIGS. 2A-2C are schematic diagrams showing the operation of the voltage tracking circuit in FIG. 1 under different voltage conditions according to an embodiment of the present invention.

FIG. 3 shows the voltage tracking circuit shown in FIG. 1 according to an embodiment of the present invention, in which the step-down circuit has a first structure.

FIG. 4 shows the voltage tracking circuit shown in FIG. 1 according to another embodiment of the present invention, in which the step-down circuit has a second structure.

FIG. 5 shows the voltage tracking circuit shown in FIG. 1 according to an embodiment of the present invention, in which the step-down circuit has a third structure.

Fig. 6 shows the voltage tracking circuit of the electronic circuit in Fig. 1 according to another embodiment of the present invention.

FIG. 7 shows the voltage tracking circuit shown in FIG. 6 according to an embodiment of the present invention, in which the step-down circuit has a first structure.

FIG. 8 shows the voltage tracking circuit shown in FIG. 6 according to another embodiment of the present invention, in which the step-down circuit has a second structure.

FIG. 9 shows the voltage tracking circuit shown in FIG. 6 according to an embodiment of the present invention, in which the step-down circuit has a third structure.

Fig. 10 is a cross-sectional view showing the structure of the NMOS transistor on the high voltage side in Fig. 1.

In order to make the above-mentioned purpose, features and advantages of the present invention more comprehensible, a preferred embodiment will be exemplified below and described in detail in conjunction with the accompanying drawings.

Figure 1 is a table of an electronic circuit according to an embodiment of the present invention. Referring to FIG. 1, the electronic circuit 1 includes an N-type metal oxide semiconductor (NMOS) transistor 10 (that is, a high-voltage side element) on the high-voltage side, an input-output pad (PAD) 12, and an inductor. 13, and a voltage tracking circuit 14. In one embodiment, the electronic circuit 1 further includes an NMOS transistor 11 (ie, a low-voltage side element) on the low-voltage side. In this embodiment, the NMOS transistors 10 and 11 are N-type laterally diffused metal oxide semiconductor (LDMOS) transistors, and each is surrounded by an N-type isolated deep well region. In FIG. 1 , the symbol "100" denotes the N-type isolated deep well region surrounding the LDNMOS transistor 10, and the symbol "110" denotes the N-type isolated deep well region surrounding the LDNMOS transistor 11.

The LDNMOS transistor 10 includes four electrode terminals 101 - 104 , which are a gate 101 , a drain 102 , a source 103 , and a bulk 104 . The gate 101 receives signals generated by other components in the electronic circuit 1 . The drain 102 is coupled to the voltage terminal T10 of the voltage tracking circuit 14 . The source 103 and the base 104 are coupled to each other at the node N10. The voltage terminal T11 of the voltage tracking circuit 14 is coupled to the node N10, that is, coupled to the source/base 103/104. The LDNMOS transistor 11 includes four electrode terminals 111 - 114 , which are a gate 111 , a drain 112 , a source 113 , and a base 114 . The gate 111 receives signals generated by other components in the electronic circuit 1 . The drain 112 is coupled to the node N10. Both the source 113 and the base 114 are coupled to the ground terminal GND. The inductor 113 is coupled to the node N10 and between I/O pads 12.

Referring to FIG. 1 , the voltage terminal T10 of the voltage tracking circuit 14 is coupled to the drain 102 of the LDNMOS transistor 10 , and its voltage terminal T11 is coupled to the source/base 103 / 104 of the LDNMOS transistor 10 . When the electronic circuit 1 is in operation, the voltage tracking circuit 14 generates an output on the output terminal T12 according to the higher level of the voltage VD on the drain 102 and the voltage VS/B on the source/base 103/104. The voltage VTH, in other words, the voltage tracking circuit 14 tracks, the voltage VD on the drain 102 and the voltage VS/B on the source/base 103/104 have a higher level, and makes the output voltage VTH equal to the tracking to the voltage. Therefore, it can be known that the voltage tracking circuit 14 can change the output voltage VTH according to the voltages VD and VS/B. The voltage tracking circuit 14 provides the generated output voltage VTH to the N-type isolated deep well region 100 surrounding the LDNMOS transistor 10 . In some cases, when an overvoltage event occurs on the I/O pad 10 , the voltage VS/B increases through the inductor 13 to be higher than the voltage VD. At this time, through the operation of the voltage tracking circuit 14 , the output voltage VTH increases along with the voltage VS/B. The increase of the output voltage VTH can turn off the parasitic bipolar transistor related to the N-type isolated deep well region 100, or can reduce the conduction performance of the parasitic bipolar transistor related to the N-type isolated deep well region 100, thereby avoiding or reducing the leakage current . According to the above, the control of the output voltage VTH applied to the N-type isolated deep well region 100 by the voltage tracking circuit 14 can avoid damage to the electronic components in the electronic circuit 1 due to high temperature caused by the leakage current.

Various embodiments and operations of the voltage tracking circuit 14 will be described below.

Referring to FIGS. 2A , 2B and 2C , they are schematic diagrams illustrating the operation of the voltage tracking circuit under different voltage conditions according to an embodiment of the present invention. The voltage tracking circuit 14 includes a P-type metal oxide semiconductor (N-type metal oxide semiconductor, PMOS) transistors 20 and 21 and a step-down circuit 22 . The PMOS transistor 20 includes four electrode terminals 201 - 204 , which are gate 201 , drain 202 , source 203 , and base 204 . The drain 202 is coupled to the voltage terminal T10 , and its source 203 and base 204 are coupled to the output terminal T12 . The step-down circuit 22 has an input node N20 and an output node N21. The input node N20 is coupled to the voltage terminal T10 , and the output node N21 is coupled to the gate 201 of the PMOS transistor 20 . The PMOS transistor 21 includes four electrode terminals 211 - 214 , which are gate 211 , drain 212 , source 213 , and base 214 . The gate 211 is coupled to the voltage terminal T10 , its drain 212 is coupled to the voltage terminal T11 , and its source 213 and base 214 are coupled to the output terminal T12 .

Referring to FIG. 2A, when the electronic circuit 1 is in operation, the voltage tracking circuit 14 receives the voltage VD through the power terminal T10, and receives the voltage VS/B through the power terminal T11. In the embodiment shown in FIG. 2A , the voltage VS/B is equal to the voltage VD (VS/B=VD), for example, both the voltage VD and the voltage VS/B are 44V. At this time, the PMOS transistor 21 is turned off. The step-down circuit 22 provides a regulated voltage. When the step-down circuit 22 receives the voltage VD through the input node N20, it performs a step-down operation to reduce the voltage VD by adjusting the voltage so as to generate the control voltage V22 at the output node N21. In other words, the step-down circuit 22 generates the control voltage V22 according to the voltage VD, and the control voltage V22 is smaller than the voltage VD (V22<VD). The control voltage V22 is, for example, 41.9V. At this time, the voltage of the gate 201 of the PMOS transistor 20 is equal to the control voltage V22. Since the control voltage V22 is lower than the voltage VD, the PMOS transistor 20 is turned on to provide a current path P20. Through the current path P20, the output voltage VTH on the output terminal T12 increases following the voltage VD, and finally equals to the voltage VD (VTH=VD).

Referring to FIG. 2B, in some cases, the voltage VS/B is less than the voltage VD (VS/B<VD) (eg, the voltage VD is 44V and the voltage VS/B is 0V). At this time, the PMOS transistor 21 is turned off. The step-down circuit 22 performs a step-down operation to regulate voltage to reduce the voltage VD to generate the control voltage V22 at the output node N21. The control voltage V22 is smaller than the voltage VD (V22<VD), and the control voltage V22 is, for example, 41.9V. At this time, the voltage of the gate 201 of the PMOS transistor 20 is equal to the control voltage V22. Since the control voltage V22 is lower than the voltage VD, the PMOS transistor 20 is turned on to provide a current path P20. Through the current path P20, the output voltage VTH on the output terminal T12 increases following the voltage VD, and finally equals to the voltage VD (VTH=VD).

Referring to FIG. 2C, in some cases, the voltage VS/B is greater than the voltage VD (VS/B>VD) (eg, the voltage VD is 44V and the voltage VS/B is 46.5V). The step-down circuit 22 also performs the step-down operation described above. At this time, the PMOS transistor 21 is turned on to provide a current path P21. Through the current path P21, the output voltage VTH on the output terminal T12 increases following the voltage VS/B, and finally equals to the voltage VS/B (VTH=VS/B).

According to the above, the voltage tracking circuit 14 generates the output voltage VTH on the output terminal T12 according to the higher level of the voltage VD and the voltage VS/B. In this way, the output voltage VTH follows the higher level of the voltage VD and the voltage VS/B of the voltage tracking circuit 14 .

The step-down circuit 22 in this case includes a plurality of step-down elements connected in series between the input node N20 and the output node N21, thereby realizing a step-down operation. There are various implementations of the step-down element. The detailed structure of the step-down circuit 22 will be described below through FIGS. 3-5 .

FIG. 3 shows the voltage tracking circuit 14 according to another embodiment of the present invention, wherein the first structure of the step-down circuit 22 is shown. Referring to Fig. 3, the step-down circuit 22 includes PMOS transistors (step-down elements) 30-32 connected in series between the input node N20 and the output node N21, the actual number can be adjusted according to actual needs, and the present invention does not take this as a limit. The PMOS transistor 30 has four electrode terminals 301 - 304 , which are gate 301 , drain 302 , source 303 , and base 304 . The drain 302 is coupled to the input node N20. Gate 301 , the source 303 , and the base 304 are coupled to the node N30 . The PMOS transistor 31 has four electrode terminals 311 - 314 , which are gate 311 , drain 312 , source 313 , and base 314 . The drain 312 is coupled to the node N30. The gate 311 , the source 313 , and the base 314 are coupled to the node N31 . The PMOS transistor 32 has four electrode terminals 321 - 324 , which are gate 321 , drain 322 , source 323 , and base 324 . The drain 322 is coupled to the node N31. The gate 311 , the source 313 , and the base 314 are coupled to the output node N21 .

For example, when the electronic circuit 1 is in operation, the voltage tracking circuit 14 receives a voltage VD, such as 44V, through the power terminal T10, and the present invention is not limited thereto. At this time, the PMOS transistors 30-32 are in an off state. Due to the parasitic diodes of the PMOS transistors 30 - 32 , each of the PMOS transistors 30 - 32 has a cross voltage of 0.7V between its drain and source. Therefore, the voltage difference between the input node N20 and the output node N21 of the step-down circuit 22 is 2.1V (0.7Vx3=2.1V). The voltage difference (2.1V) between the input node N20 and the output node N21 is used as the regulation voltage provided by the step-down circuit 22 . At this time, the control voltage V22 on the output node N21 is 41.9V (44V-2.1V=41.9V), so as to realize the step-down operation, that is, the voltage VD is reduced by adjusting the voltage to generate the control voltage V22 at the output node N21 .

FIG. 4 shows the voltage tracking circuit 14 according to another embodiment of the present invention, wherein the step-down circuit 22 has a second architecture. Referring to Fig. 4, the step-down circuit 22 includes diodes (step-down elements) 40-42 connected in series between the input node N20 and the output node N21, the actual number can be adjusted according to actual needs, and the present invention does not take this as a limit. An anode terminal of the diode 40 is coupled to the input node N20, and a cathode terminal thereof is coupled to the node N40. The anode terminal of the diode 41 is coupled to the node N40, and the cathode terminal thereof is coupled to the node N41. The anode terminal of the diode 42 is coupled to the node N41, and the cathode terminal thereof is coupled to the output node N21.

For example, when the electronic circuit 1 is operating, the voltage tracking circuit 14 passes through The power terminal T10 receives a voltage VD, such as 44V, and the present invention is not limited thereto. At this time, each of the diodes 40 - 42 provides a cross voltage of 0.7V between its anode terminal and cathode terminal. Therefore, the voltage difference between the input node N20 and the output node N21 of the step-down circuit 22 is 2.1V (0.7Vx3=2.1V). The voltage difference (2.1V) between the input node N20 and the output node N21 is used as the regulation voltage provided by the step-down circuit 22 . At this time, the control voltage V22 on the output node N21 is 41.9V (44V-2.1V=41.9V), so as to realize the step-down operation, that is, the voltage VD is reduced by adjusting the voltage to generate the control voltage V22 at the output node N21 .

FIG. 5 shows the voltage tracking circuit 14 according to another embodiment of the present invention, wherein the step-down circuit 22 has a third architecture. Referring to Fig. 5, the step-down circuit 22 includes PMOS transistors (step-down elements) 50-52 connected in series between the input node N20 and the output node N21, the actual number can be adjusted according to actual needs, and the present invention does not take this as a guideline limit. The PMOS transistor 50 has four electrode terminals 501 - 504 , which are gate 501 , drain 502 , source 503 , and base 504 . The drain 502 is coupled to the input node N20. The source 503 and the base 504 are coupled to the node N50. The PMOS transistor 51 has four electrode terminals 511 - 514 , which are gate 511 , drain 512 , source 513 , and base 514 . The drain 512 is coupled to the node N50. The source 513 and the base 514 are coupled to the node N51. The PMOS transistor 52 has four electrode terminals 521 - 524 , which are gate 521 , drain 522 , source 523 , and base 524 . The drain 522 is coupled to the node N51. The source 513 and the base 514 are coupled to the output node N21. The gates 501 , 511 , and 521 of the PMOS transistors 50 - 53 are coupled to the output terminal T12 .

For example, when the electronic circuit 1 is in operation, the voltage tracking circuit 14 receives a voltage VD, such as 44V, through the power terminal T10, and the present invention is not limited thereto. At this time, the PMOS transistors 50-52 are in an off state. Due to the presence of PMOS transistors 50~52 As green diodes, each of the PMOS transistors 50-52 has a cross voltage of 0.7V between its drain and source. Therefore, the voltage difference between the input node N20 and the output node N21 of the step-down circuit 22 is 2.1V (0.7Vx3=2.1V). The voltage difference (2.1V) between the input node N20 and the output node N21 is used as the regulation voltage provided by the step-down circuit 22 . At this time, the control voltage V22 on the output node N21 is 41.9V (44V-2.1V=41.9V), so as to realize the step-down operation, that is, the voltage VD is reduced by adjusting the voltage to generate the control voltage V22 at the output node N21 . In this embodiment, the output voltage VTH on the output terminal T12 follows the higher level of the voltage VD and the voltage VS/B, so the gates 501, 511, and 521 of the PMOS transistors 50-53 have The higher voltage enables the PMOS transistors 50-53 to maintain the off state stably.

In some embodiments, when the electronic circuit 1 is in operation, in order to allow the gate voltage of the PMOS transistor 20 in the voltage tracking circuit 14 to rapidly increase towards the voltage VTH, a resistor is coupled to the output terminal of the step-down circuit 22 Between N21 and the ground terminal GND, as shown in Figure 6. Therefore, in each example of the step-down circuit 22 shown in FIGS. 3-5 , the resistor 60 is coupled between the output terminal N21 of the step-down circuit 22 and the ground terminal GND, as shown in FIGS. 7-9 respectively. As in the first structure shown in FIG. 7, the voltage tracking circuit in FIG. 3 further has a resistor 60 coupled between the output terminal N21 of the step-down circuit 22 and the ground terminal GND; as shown in FIG. 8 In the second structure, the voltage tracking circuit in FIG. 4 further has a resistor 60, which is coupled between the output terminal N21 of the step-down circuit 22 and the ground terminal GND; in the third structure shown in FIG. 9, in The voltage tracking circuit in FIG. 5 further has a resistor 60 coupled between the output terminal N21 of the step-down circuit 22 and the ground terminal GND. The operation of the voltage tracking circuit shown in Figures 6-9 is as described above, please refer to the description of Figures 2A-5.

FIG. 10 is a cross-sectional view showing the structure of the NMOS transistor 10 on the high voltage side in FIG. 1 . Referring to FIG. 10, an NMOS transistor 10 is formed on a P-type substrate SUB. The N-type buried layer NBL and the P-type well region 109 are formed in the P-type substrate SUB. The N-type isolated deep well region 100 is formed on the N-type buried layer NBL and interposed between the P-type well regions 109 . The P-type well region 105 is formed in the N-type isolated deep well region 100 . The N-type well region 106 is formed in the P-type well region 105 to serve as the drain region of the NMOS transistor 10 . The contact electrode electrically connected to the N-type well region 106 serves as the drain electrode 102 . The N-type doped region 107 is formed in the P-type well region 105 to serve as the source region of the NMOS transistor 10 . The P-type doped region 108 is formed in the P-type well region 105 to serve as the base region of the NMOS transistor 10 . The contact electrodes electrically connected to the N-type doped region 107 and the P-type doped region 108 respectively serve as the source 103 and the base 104 . Since the source 103 and the base 104 are connected to each other, FIG. 10 only shows a single contact electrode. A gate dielectric layer and a gate layer are formed on the P-type well region 105 , and a contact electrode electrically connected to the gate layer is used as the gate 101 .

According to the structure in Fig. 10, there are several parasitic bipolar transistors, including the parasitic NPN bipolar transistor LNPN formed between the N-type isolated deep well region 100, the P-type well region 105, and the N-type well region 106, forming The parasitic PNP bipolar transistor LPNP between the P-type well area 105, the N-type isolated deep well area 100, and the P-type well area 109 is formed in the N-type well area 106, the P-type well area 105, and the N-type embedded The parasitic NPN bipolar transistor VNPN between the layers NBL, and the parasitic PNP bipolar transistor VPNP formed between the P-type well region 105 , the N-type buried layer NBL, and the P-type substrate SUB.

As shown in FIG. 10 , the N-type isolated deep well region 100 is not connected to the drain 102 . The voltage of the N-type isolated deep well region 100 is independent of the voltage of the drain 102 . According to the operation of the voltage tracking circuit 14, the control voltage VTH generated by it is the higher one of the voltage VD and the voltage VS/B. By applying the control voltage VTH to N-type isolated deep well region 100, to avoid conduction of parasitic diodes, for example, parasitic diodes include NPN bipolar transistor LNPN, parasitic PNP bipolar transistor LPNP, parasitic NPN bipolar transistor VNPN, or parasitic PNP bipolar Transistor VPNP, but the present invention is not limited thereto. In one embodiment, none of the above parasitic diodes are turned on. For example, when the voltage VS/B is greater than the voltage VD, since the voltage tracking circuit 14 generates a control voltage VTH equal to the voltage VS/B, the voltages of the N-type isolated deep well region 100 and the N-type buried layer NBL are close to each other. or equal to. Therefore, the parasitic NPN bipolar transistor VNPN and the parasitic PNP bipolar transistor VPNP are not turned on, which reduces the leakage current through the substrate.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in this art can make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to what is defined in the scope of the attached patent application.

14: Voltage tracking circuit

20,21: PMOS transistor

22: Step-down circuit

201: gate

202: drain

203: source

204: base

211: Gate

212: drain

213: source

214: base

N20: input node

N21: output node

P20, P21: current path

T10, T11: voltage terminal

T12: output terminal

V22: Control voltage

VD: Voltage

VS/B: voltage

Claims (13)

A voltage tracking circuit for tracking one of a first voltage on a first voltage terminal and a second voltage on a second voltage terminal to generate an output voltage, comprising: a first P-type transistor , having a gate, a drain, and a source, wherein the drain of the first P-type transistor is coupled to the first voltage end; a step-down circuit, coupled to the first voltage end and the first voltage end Between the gates of the first P-type transistor, a regulated voltage is provided, wherein the step-down circuit uses the regulated voltage to reduce the first voltage to generate a control voltage, and provides the control voltage to the The gate of the first P-type transistor; and a second P-type transistor having a gate, a drain, and a source, wherein the gate of the second P-type transistor is coupled to the gate The first voltage terminal, and the drain of the second P-type transistor is coupled to the second voltage terminal; wherein, the source of the first P-type transistor and the source of the second P-type transistor An output end of the voltage tracking circuit is coupled, and the output voltage is generated at the output end. The voltage tracking circuit according to claim 1, wherein when the first voltage is greater than or equal to the second voltage, the output voltage is equal to the first voltage through a current path through the first P-type transistor. The voltage tracking circuit according to claim 1, wherein when the first voltage is lower than the second voltage, the output voltage is equal to the second voltage through a current path through the second P-type transistor. The voltage tracking circuit according to claim 1, wherein the step-down circuit includes: an input node, the first voltage terminal; an output node, coupled to the gate of the first P-type transistor; and a plurality of step-down elements , connected in series between the input node and the output node; wherein, the regulated voltage is a voltage difference between the input node and the output node. The voltage tracking circuit according to claim 4 further includes: a resistor coupled between the gate of the first P-type transistor and a ground terminal. The voltage tracking circuit according to claim 4, wherein the plurality of step-down elements include: a third P-type transistor having a drain coupled to the input node and a gate coupled to a first node and a source; a fourth P-type transistor having a drain coupled to the first node, and having a gate and a source coupled to a second node; and a fifth P-type transistor , having a drain coupled to the second node, and having a gate and a source coupled to the output node. The voltage tracking circuit according to claim 4, wherein the plurality of step-down elements include: a first diode having an anode terminal coupled to the input node and a cathode terminal coupled to a first node; a second diode having an anode terminal coupled to the first node and having a cathode terminal coupled to a second node; and A third diode has an anode terminal coupled to the second node and a cathode terminal coupled to the output node. The voltage tracking circuit according to claim 4, wherein the plurality of step-down elements include: a third P-type transistor having a drain coupled to the input node, a source coupled to a first node, and a gate; a fourth P-type transistor with a drain coupled to the first node, a source coupled to a second node, and a gate; and a fifth P-type transistor with A drain coupled to the second node, a source coupled to the output node, and a gate; wherein, the gate of the third P-type transistor, the gate of the fourth P-type transistor The pole and the gate of the fifth P-type transistor are both coupled to the output terminal of the voltage tracking circuit. The voltage tracking circuit according to claim 1, wherein, when the voltage tracking circuit operates, the first voltage is maintained at a fixed value, and the second voltage is a variable voltage. The voltage tracking circuit according to claim 1, wherein the output voltage is applied to an isolated deep well region surrounding a high-voltage side element. An electronic circuit, comprising: a high-voltage side element, having a first electrode terminal and a second electrode terminal, and surrounded by an isolated deep well region; and a voltage tracking circuit, coupled to the first electrode terminal and the second electrode terminal electrode terminals for tracking a first voltage on the first electrode terminal and a second voltage on the second electrode terminal One of them is used to generate an output voltage on an output terminal, and apply the output voltage to the isolated deep well area surrounding the high-voltage side element; wherein, the voltage tracking circuit includes: a first P-type transistor, having A gate, a drain, and a source, wherein the drain of the first P-type transistor is coupled to the first electrode terminal; a step-down circuit is coupled to the first electrode terminal and the first electrode between the gates of a P-type transistor, and provide a regulated voltage, wherein the step-down circuit uses the regulated voltage to reduce the first voltage to generate a control voltage, and provide the control voltage to the first The gate of the P-type transistor; and a second P-type transistor having a gate, a drain, and a source, wherein the gate of the second P-type transistor is coupled to the first electrode terminal, and the drain of the second P-type transistor is coupled to the second electrode terminal; wherein, the source of the first P-type transistor is coupled to the source of the second P-type transistor The output terminal of the voltage tracking circuit. The electronic circuit according to claim 11, wherein when the voltage tracking circuit operates, the first voltage is maintained at a fixed value, and the second voltage is a variable voltage. The electronic circuit of claim 11, wherein the high-voltage side element is an N-type laterally diffused metal oxide semiconductor (LDMOS) transistor, and a gate of the N-type LDMOS transistor An I/O pad of the electronic circuit is coupled with a base.

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