TWI783346B - Micro-electro mechanical system and manufacturing method thereof - Google Patents

Abstract

A micro electro mechanical system (MEMS) includes a circuit substrate comprising electronic circuitry, a support substrate having a recess, a bonding layer disposed between the circuit substrate and the support substrate, through holes passing through the circuit substrate to the opening, a first conductive layer disposed on a front side of the circuit substrate, a second conductive layer disposed on an inner wall of the recess, and a third conductive layer disposed on an inner wall of each of the through holes.

Description

Micro-electro-mechanical system and manufacturing method thereof

Embodiments of the present invention relate to micro-electro-mechanical systems and manufacturing methods thereof.

Microelectromechanical systems (MEMS) devices have recently been developed. MEMS devices include devices fabricated using semiconductor technology to form mechanical and electrical features. MEMS devices are implemented in pressure sensors, microphones, actuators, mirrors, heaters, and/or printer nozzles. While existing apparatus and methods for forming MEMS devices have generally been adequate for their intended purposes, they have not been entirely satisfactory in all respects.

One embodiment of the present invention relates to a micro-electro-mechanical system (MEMS), which includes: a circuit substrate including electronic circuits; a support substrate having a groove; a bonding layer disposed between the circuit substrate and the circuit substrate. Between the support substrates; several through holes, which pass through the circuit substrate to the opening; a first conductive layer, which is placed on a front side of the circuit substrate; a second conductive layer, which is placed in the groove on one of the inner walls; and a third conductive layer placed on one of the inner walls of each of the through holes.

One embodiment of the invention relates to a method of fabricating a microelectromechanical system (MEMS), comprising: forming electronic circuitry over a front side of a first substrate; forming through penetrating into one or more holes in the first substrate; filling the holes with a filling material; thinning a rear side of the first substrate to expose portions of the filled holes; bonding a second substrate with a bonding layer a substrate is bonded to the rear side of the first substrate, the bonding layer is interposed between the second substrate and the rear side of the first substrate; and a groove is formed in the second substrate to expose the first substrate one of the bottom.

One embodiment of the present invention relates to a method of fabricating a microelectromechanical system (MEMS), comprising: forming electronic circuitry over a front side of a first substrate; forming electrodes over the first substrate; forming the Forming one or more holes penetrating into the first substrate at regions other than the electrodes; filling the holes with a filling material; thinning a rear side of the first substrate to expose portions of the filled holes a bonding layer made of silicon oxide bonds a second substrate to the rear side of the first substrate, the bonding layer being interposed between the second substrate and the rear side of the first substrate; forming post electrodes above the electrodes; and forming a groove in the second substrate to expose a bottom of the first substrate.

10: Micro-Electro-Mechanical Systems (MEMS) Devices

10A: MEMS device

10B: MEMS device

10C: MEMS device

10D: MEMS device

20: Circuit board

20': Installation layer

25: Electronic Circuits/Electronic Circuit Systems/Complementary Metal Oxide Semiconductor (CMOS) Circuits

28: Passivation film

30: Support substrate

30': block layer

35: Opening/cavity/groove

40: joint layer

40': oxide layer

50: The first conductive layer

55: Second conductive layer

57: The third conductive layer

60: Through hole

100: electrode

101: electrode

110: passivation layer

120:Through silicon via (TSV) hole

130: the first conductive layer

140: Filling material layer

150: insulation pattern

160: first carrier bonding layer

165: the first carrier substrate

170: bonding layer

180: The first hard mask layer

190: second hard mask layer

200: opening

210: conductive layer/first column electrode

215: Additional conductive layer/second column electrode

220: Mask pattern/photoresist pattern

225: metal pad

230: interlayer dielectric layer

242: first passivation layer

244: Second passivation layer

246: The third passivation layer

250: pad electrode under bump

252: first metal layer/TiW layer

254: Second metal layer/Cu layer

256: The third metal layer/Ni layer

258: The fourth metal layer/Sn layer

260: ball bump

300: second carrier substrate

305: second carrier bonding layer

310: mask pattern

320: second conductive layer

390: cutting road

400: frame

500: electron beam

CR: central area

L1: distance

L2: Distance

L3: Distance

PR: Surrounding area

T1: Thickness

T2: total thickness

The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying figures. It should be emphasized that, in accordance with standard industry practice, various components are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

1A, 1B, 1C and 1D show schematic cross-sectional views of MEMS devices according to embodiments of the invention.

2A, 2B, 2C, 2D, 2E and 2F show schematic cross-sectional views of various stages of a fabrication operation of a MEMS device according to an embodiment of the invention.

3A, 3B, 3C, 3D and 3E show schematic cross-sectional views of various stages of a fabrication operation of a MEMS device according to an embodiment of the invention.

Fig. 4A, Fig. 4B, Fig. 4C and Fig. 4D show that according to one embodiment of the present invention Schematic cross-sectional views of various stages of a fabrication operation of a MEMS device.

5A, 5B and 5C show schematic cross-sectional views of various stages of a fabrication operation of a MEMS device according to an embodiment of the invention.

6A, 6B and 6C show schematic cross-sectional views of various stages of a fabrication operation of a MEMS device according to an embodiment of the invention.

Figure 7A shows a plan view of a MEMS device and Figure 7B shows a cross-sectional view of a pad structure device according to one embodiment of the invention.

Figure 8 shows one use of a MEMS device according to one embodiment of the invention.

9A, 9B, 9C and 9D show schematic cross-sectional views of various stages of a fabrication operation of a MEMS device according to an embodiment of the invention.

It should be appreciated that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and configurations are described below to simplify the present disclosure. Of course, these are examples only and are not meant to be limiting. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on process conditions and/or desired properties of the device. Furthermore, in the following description, forming a first member over or on a second member may include embodiments in which the first member and the second member are formed in direct contact, and may also include embodiments in which a direct contact may be made. An embodiment in which an additional member inserted between the first member and the second member is formed such that the first member and the second member are not in direct contact. Various components may be arbitrarily drawn in different scales for simplicity and clarity.

In addition, for ease of description, spatially relative terms such as "below", "below", "under", "above", "upper" and the like may be used herein to describe the relationship between an element or component and another(s) The relationship of elements or components, as shown in the figure. Except as depicted in the figure Additionally, spatially relative terms are also intended to encompass different orientations of the device in use or operation. A device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly. Additionally, the term "consisting of" may mean "comprising" or "consisting of". In this disclosure, unless otherwise indicated, at least one of A, B and C means "A", "B", "C", "A and B", "A and C", "B and C ” or “A, B and C” and does not mean one from A, one from B and one from C.

A MEMS device according to the present disclosure may be any of the following: an electron beam deflector, an electromagnetic beam deflector, an accelerometer, a gyroscope, a pressure sensor, a microphone, an RF resonator, an RF switch or an ultrasonic sensor.

1A and 1B show schematic cross-sectional views of MEMS devices 10A and 10B according to embodiments of the invention.

In some embodiments, MEMS devices 10A and 10B include a circuit substrate 20 on which is formed an electronic circuit 25 (eg, a transistor comprising a semiconductor field effect transistor, such as a complementary metal-oxide-semiconductor (CMOS) device) and having The substrate 30 is supported at an opening (cavity or groove) 35 for receiving sound, pressure and/or light. In some embodiments, a bonding layer 40 is formed between the circuit substrate 20 and the support substrate 30 . In some embodiments, the bonding layer 40 is a silicon oxide layer. In some embodiments, the circuit substrate 20 includes electronic circuitry 25 formed of electronic circuitry, such as a signal processing circuit and/or an amplifier circuit. In some embodiments, the groove 35 has a rectangular (eg, square) shape in plan view. In some embodiments, at least one of the circuit substrate 20 and the support substrate 30 is made of crystalline silicon. In some embodiments, the bonding layer remains at the bottom of the groove 35 as shown in FIG. 1A , and in other embodiments, as shown in FIG. 1B , the bonding layer is absent at the bottom of the groove 35 .

In addition, in some embodiments, a first conductive layer 50 is formed on the circuit substrate 20, and a second conductive layer 55 is formed on a rear surface of the support substrate 30, as shown in FIG. 1A and FIG. 1B. In some embodiments, as shown in FIG. 1A , bonding layer 40 is in contact with second conductive layer 55 and not in contact with circuit substrate 20 . In other embodiments, the second conductive layer 55 is in contact with the circuit substrate 20 , as shown in FIG. 1B . In some embodiments, the first conductive layer and the second conductive layer include one or more layers of Au, Ti, Cu, Ag and Ni.

In some embodiments, the distance L1 of the size of the groove 35 at the bottom of the circuit substrate 20 is in a range from about 10 mm to about 50 mm, and in other embodiments is in a range from about 15 mm to about 20 mm. . In some embodiments, the distance L2 of the size of the cavity 35 at the bottom of the support substrate 30 is greater than L1 and ranges from about 11 mm to about 52 mm and in other embodiments from about 16 mm to about 22 mm Inside. In some embodiments, the distance L3 (a width of a frame portion) from the edge of the MEMS device to the edge of the groove 35 at the bottom of the circuit substrate 20 is in a range from about 2 μm to about 10 μm, and in others In embodiments, it is within a range from one of about 3 μm to about 5 μm. In some embodiments, thickness T1 of bonding layer 40 is in a range from about 200 nm to about 5 μm, and in other embodiments is in a range from about 500 nm to about 2 μm. In some embodiments, the total thickness T2 of the MEMS device is in a range of from about 300 μm to about 2 mm, and in other embodiments in a range of from about 600 μm to about 800 μm.

1C and ID show schematic cross-sectional views of MEMS devices 10C and 10D according to embodiments of the invention. In some embodiments, MEMS devices 10C and 10D are beam deflectors by which one or more electron or extreme ultraviolet (EUV) beams are deflected by operation of an electronic circuit embedded in the MEMS device.

Similar to MEMS devices 10A and 10B, MEMS devices 10C and 10D include a circuit substrate 20 in which an electronic circuit 25 is formed and have functions for receiving sound, pressure and/or One of the openings (cavities or grooves) 35 of light supports the substrate 30 . In some embodiments, a bonding layer 40 is formed between the circuit substrate 20 and the support substrate 30 . In some embodiments, the bonding layer 40 is a silicon oxide layer. In some embodiments, one or more vias 60 are placed through the circuit substrate 20 and the bonding layer 40 such that the light beam passes through the vias 60 . In some embodiments, vias 60 are arranged in an n×m matrix in a plan view, where n and m are integers of 2 or greater and equal to or less than 128, for example.

In some embodiments, a first conductive layer 50 is formed on a front surface of the circuit substrate 20, and a second conductive layer 55 is formed on a rear surface of the support substrate 30, as shown in FIGS. 1C and 1D . In some embodiments, as shown in FIG. 1C , the bonding layer 40 is in contact with the second conductive layer 55 and not in contact with the circuit substrate 20 . In other embodiments, the second conductive layer 55 is in contact with the circuit substrate 20 , as shown in FIG. 1D . In addition, a third conductive layer 57 is disposed on an inner wall of each of the through holes 60 to connect the first conductive layer 50 and the second conductive layer 55 .

In some embodiments, the circuit substrate 20 includes electronic circuitry 25 formed of electronic circuitry, such as a signal processing circuit and/or an amplifier circuit. In some embodiments, electronic circuitry is coupled to the first conductive layer, the second conductive layer, and/or the third conductive layer to control the potential of the third conductive layer in each of the vias 60 to thereby deflect The beam of the hole 60.

In some embodiments, the groove 35 has a rectangular (eg, square) shape in plan view. In some embodiments, at least one of the circuit substrate 20 and the support substrate 30 is made of crystalline silicon. In some embodiments, the bonding layer remains at the bottom of the groove 35, as shown in Figure 1C, and in other embodiments, as shown in Figure ID, the bonding layer is absent at the bottom of the groove 35.

The dimensions of L1, L2 and L3 of MEMS devices 10C and 10D are the same or similar Dimensions of L1 , L2 and L3 of MEMS devices 10A and 10B.

2A, 2B, 2C, 2D, 2E and 2F show schematic cross-sectional views of various stages of a fabrication operation of a MEMS device according to an embodiment of the invention. It should be appreciated that additional operations may be provided before, during, and after the procedures shown by FIGS. 2A-2F , and that some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations/procedures may be interchanged. The materials, configurations, dimensions, and procedures described with respect to FIGS. 1A-1D are applicable to the following embodiments and detailed descriptions thereof may be omitted.

As shown in FIG. 2A , a CMOS (Complementary Metal Oxide Semiconductor) circuit 25 is formed in a front surface area of the circuit substrate 20 . One or more passivation films 28 are formed over the front surface of the circuit substrate. In some embodiments, one or more passivation films 28 include silicon oxide, silicon nitride, or an organic film. Next, as shown in FIG. 2B , the rear side of the circuit substrate 20 is thinned by a grinding or polishing process. In some embodiments, the remaining thickness of the thinned circuit substrate 20 is in a range from about 100 μm to about 500 μm.

Next, as shown in FIGS. 2C and 2D , the thinned circuit substrate 20 is bonded to a support substrate 30 via a bonding layer 40 . In some embodiments, as shown in FIG. 2C , bonding layer 40 is silicon oxide formed on the surface of support substrate 30 by, for example, a thermal oxidation process or a chemical vapor deposition (CVD) process. In other embodiments, bonding layer 40 is formed on the rear side of circuit substrate 20 by, for example, a CVD process.

Next, the rear side of the support substrate 30 is recessed by using one or more lithography and etching operations. In some embodiments, the etching operation includes plasma dry etching or wet etching. In some embodiments, the wet etch utilizes tetramethylammonium hydroxide (TMAH) or KOH solutions.

In some embodiments, bonding layer 40 acts as an etch stop layer for forming recess 35, as shown in FIG. 2E. In some embodiments, the rear side and the abutment of the support substrate 30 One or more conductive layers are formed on the bonding layer 40 .

In other embodiments, the bonding layer 40 is further etched by one or more dry etch or wet etch operations after the recess etch stops at the bonding layer 40 . In some embodiments, one or more conductive layers are formed on the rear side of the support substrate 30 . In other embodiments, as shown in FIG. 2F , after removal of bonding layer 40 , a portion of the rear side of circuit substrate 20 is etched and one or more conductive layers are then formed.

3A-7B show schematic cross-sectional views of various stages of a fabrication operation of a MEMS device according to an embodiment of the invention. It should be appreciated that additional operations may be provided before, during, and after the procedures shown by FIGS. 3A-7B , and that some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations/procedures may be interchanged. The materials, configurations, dimensions, and procedures described with respect to FIGS. 1A-1D and 2A-2F are applicable to the following embodiments and detailed descriptions thereof may be omitted.

As shown in FIG. 3A , after forming electronic circuitry over a circuit substrate 20 , one or more planar electrodes 100 and 101 are formed and one or more passivation layers 110 are formed. The electrodes 100 and 101 are electrically connected to an electronic circuit formed in the circuit substrate 20 . In some embodiments, the circuit substrate 20 includes a crystalline silicon substrate. In some embodiments, one or more openings are formed over electrode 100 and electrode 101 in one or more passivation layers. In some embodiments, electrode 100 and electrode 101 are made of one or more layers of Cu, Al, Au, Ni, Ag, or other suitable conductive materials. The passivation layer 110 includes silicon nitride, SiON, silicon oxide, aluminum nitride or an organic material.

Next, one or more holes 120 for through-silicon vias (TSVs) are formed in regions other than the electrodes 100 and 101 . TSV holes 120 are formed by one or more lithography and etching operations. In some embodiments, TSV holes 120 are arranged in an n×m matrix in a plan view (see FIG. 7A ), where n and m are integers of 2 or greater and equal to or less than 128, for example. in some real In an embodiment, the depth of the TSVs from the top of the passivation layer 110 ranges from about 20 μm to about 100 μm. In some embodiments, the depth is determined such that the bottom of the TSV hole 120 is exposed after a subsequent thinning procedure is performed on the rear side of the circuit substrate. In some embodiments, the shape of the TSV hole 120 in a plan view is circular or rectangular (eg, square). In some embodiments, the TSV holes 120 are tapered to have an opening larger than one of the bottoms. In some embodiments, a diameter (or a length of a side) of the TSV hole 120 at the opening is in a range from about 100 nm to about 12,000 nm.

Next, a first conductive layer 130 is formed on the electrodes 100 and 101 , above the passivation layer 110 and inside the TSV hole 120 . Next, a filling layer 140 is formed to fill the TSV hole 120, as shown in FIG. 3B. The first conductive layer 130 has the same or similar function as the first conductive layer 50 shown in FIGS. 1A to 1D . In some embodiments, the first conductive layer 130 includes one or more layers of Au, Ti, Cu, Ag and Ni. In certain embodiments, a gold layer formed over a Ti layer is used as the first conductive layer 130 . In some embodiments, the thickness of the Ti layer ranges from about 50 nm to about 500 nm, and in other embodiments from about 80 nm to about 300 nm. In some embodiments, the gold (Au) layer has a thickness in a range from about 10 nm to about 10,000 nm, and in other embodiments in a range from about 150 nm to about 250 nm. In some embodiments, the filling layer 140 includes silicon oxide or any other suitable insulating material. In some embodiments, a blanket layer of filling material is formed over the first conductive layer 130, and then a planarization operation such as a chemical mechanical polishing process or an etch-back process is performed to leave the filling material only in the TSVs. Inside the hole 120, as shown in Figure 3B. In other embodiments, the filling material also remains on a recessed portion of the electrode 100 and the electrode 101 .

Next, as shown in FIG. 3C , the conductive layer 130 is patterned to form one or more openings over the passivation layer 110 near the TSV holes 120 to partially expose the passivation layer. Next, an insulating layer is formed and patterned to form an island-shaped insulating pattern 150 for covering the opening. in some implementations In one example, the insulating pattern 150 includes silicon nitride.

Furthermore, as shown in FIG. 3D , a first carrier bonding layer 160 is formed over the front surface of the circuit substrate 20 on which the conductive layer 130 and the pattern 150 are formed, and then a first carrier substrate 165 is attached. In some embodiments, the first carrier substrate 165 is a glass substrate, a ceramic substrate, a semiconductor substrate or a resin substrate. In some embodiments, the first carrier bonding layer 160 includes an organic material, silicon oxide, or any other suitable material.

Next, the rear side of the circuit substrate 20 is thinned by a grinding or polishing (eg, CMP) operation. In some embodiments, after thinning, circuit substrate 20 has a remaining thickness in the range of from about 20 μm to about 300 μm, and in other embodiments the remaining thickness is in the range of from about 40 μm to about 180 μm . As shown in FIG. 3D , the bottom of the filling material layer 140 filled in the TSV hole 120 is exposed. In other embodiments, the first carrier substrate 165 is attached to the front surface of the circuit substrate 20 after the thinning operation.

In addition, as shown in FIG. 3E , a bonding layer 170 is formed on the thinned rear surface of the circuit substrate 20 . The bonding layer 170 has the same or similar function as the bonding layer 40 shown in FIGS. 1A-2F . In some embodiments, bonding layer 170 includes silicon oxide formed by, for example, a CVD process.

Next, as shown in FIG. 4A , a support substrate 30 is prepared and bonded to the circuit substrate 20 through the bonding layer 170 (oxide fusion bonding). In some embodiments, the support substrate 30 is made of crystalline silicon. After oxide fusion bonding, the first carrier substrate 165 and first carrier bonding layer 160 are removed, as shown in FIG. 4B . As shown in FIG. 4A , bonding layer 170 is connected to fill material layer 140 in TSV hole 120 . In some embodiments, bonding layer 170 and filler material layer 140 are made of the same material.

In other embodiments, the support substrate 30 or the support substrate 30 and the circuit substrate A bonding layer 170 is formed on both. In some embodiments, the thickness of the bonding layer-free support substrate 30 ranges from about 200 μm to about 1.8 mm, and in other embodiments ranges from about 500 μm to about 750 μm.

Next, as shown in FIG. 4C , a first hard mask layer 180 and then a second hard mask layer 190 are formed over the front surface of the circuit substrate 20 . In some embodiments, the first hard mask layer 180 includes silicon oxide and the second hard mask layer 190 includes polysilicon or amorphous silicon. In some embodiments, the silicon oxide hard mask layer 180 is formed by a CVD process, and then a planarization operation such as a CMP operation is performed. Similarly, in some embodiments, polysilicon hard mask layer 190 is formed by chemical vapor deposition (CVD), and then optionally a CMP operation is performed. In some embodiments, the polysilicon hard mask layer 190 has a thickness ranging from about 30 μm to about 70 μm.

Next, the second hard mask layer 190 and the first hard mask layer 180 are patterned by using one or more lithography and etching operations to form one or more openings 200 over the electrodes 100 and 101, as shown in FIG. 4D shown in . In some embodiments, the size of opening 200 is larger than the size of the openings formed in passivation layer 110 over electrode 100 and electrode 101 . Furthermore, in some embodiments, the insulating pattern 150 is partially exposed in the opening 200, as shown in FIG. 4D.

Next, as shown in FIG. 5A , one or more conductive layers 210 (pillar electrodes) are formed in the opening 200 . In some embodiments, the conductive layer comprises gold or gold alloys (eg, AuCu and AuNi) formed by a plating operation (electroplating or electroless plating). In some embodiments, the thickness of the plated conductive layer 210 ranges from about 20 μm to about 50 μm. In some embodiments, the thickness (height) of the plated conductive layer 210 is less than the top of the second hard mask layer 190, as shown in FIG. 5A.

In addition, as shown in FIG. 5B, one or more Part of the electrode 100 and the plating layer 210 above the electrode 101 . In some embodiments, the mask pattern 220 includes a photoresist pattern. Next, an additional conductive layer 215 (column electrode) is formed on the conductive plating layer 210 . In some embodiments, the additional conductive layer 215 is formed by a plating operation (electroplating or electroless plating). In some embodiments, the additional conductive layer 215 is made of the same material as the plated conductive layer 210 and includes gold or a gold alloy (eg, AuCu, AuNi). In other embodiments, the additional conductive layer 215 is made of a material different from the plated conductive layer 210 . Next, the photoresist pattern 220 is removed, as shown in FIG. 5C .

In some embodiments, the thickness of the additional conductive layer 215 ranges from about 10 μm to about 35 μm. In some embodiments, the combined thickness (height) of the plated conductive layer 210 and the additional conductive layer 215 is less than the top of the second hard mask layer 190, as shown in FIG. 5C. In some embodiments, two different thicknesses (heights) of plated conductive layers 210/215 control different circuitry. For example, the higher ones are used to shelter electrons, and the lower ones are used to control the electric field.

Next, as shown in FIG. 6A, a second carrier bonding layer 305 is formed over the front side of the circuit substrate 20, and then a second carrier substrate 300 is attached to the front side of the circuit substrate 20 via the second carrier bonding layer 305. . In some embodiments, the second carrier substrate 300 is a glass substrate, a ceramic substrate, a semiconductor substrate or a resin substrate. In some embodiments, the second carrier bonding layer 305 includes an organic material, silicon oxide, or any other suitable material.

Then, the entire substrate is turned vertically, and then the rear side of the supporting substrate 30 is patterned to form a groove 35 . In some embodiments, recesses 35 are formed by one or more lithography and etching operations using a mask pattern 310 . In some embodiments, the mask pattern 310 is made of a photoresist.

In some embodiments, the etching operation includes plasma dry etching or wet etching. In some embodiments, bonding layer 170 acts as an etch stop layer for forming recess 35 . When a plasma dry etching process is used to form the groove 35, the plasma etching substantially stops at the bonding layer 170, and therefore, plasma damage on the electronic circuits formed in the circuit substrate 20 can be prevented.

In some embodiments, after the recess etch stops at the bonding layer 170, the bonding layer 170 is further etched by one or more dry etch or wet etch operations. In some embodiments, the etching of the bonding layer has a high selectivity relative to the circuit substrate 20 (eg, Si). For example, the etching rate of the bonding layer is 10 times or more that of the circuit substrate 20 . In some embodiments, when the bonding layer 170 is made of silicon oxide, a wet etching process using HF or buffered HF is performed to suppress damage to electronic circuits formed in the circuit substrate 20 . When the filling material layer 140 is made of the same material as the bonding layer 170 (eg, silicon oxide), the filling material layer 140 in the TSV hole 120 is also removed when the bonding layer 170 is removed. When the filling material layer 140 is made of a material other than the bonding layer 170 (eg, silicon nitride), an additional etching operation such as a wet etching operation is performed to remove the filling material layer 140 .

After removing the filling material layer 140 from the TSV hole 120, a second conductive layer 320 is formed inside the groove 35, as shown in FIG. 6B.

In some embodiments, as shown in FIG. 6B , a second conductive layer 320 is formed in contact with the first conductive layer 130 formed on the inner wall of each of the TSV holes 120 . In some embodiments, the second conductive layer 320 is also formed on the inner wall of the TSV hole 120 in which the first conductive layer 130 has been formed. In some embodiments, the second conductive layer 320 is made of the same or different material as the first conductive layer 130 and includes one or more layers of Au, Ti, Cu, Ag and Ni. In certain embodiments, a gold layer formed over a Ti layer is used as the second conductive layer 320 . In some embodiments, the thickness of the Ti layer ranges from about 50 nm to about 200 nm, and in other embodiments ranges from about 80 nm to about 120 nm. In some embodiments, the gold (Au) layer has a thickness ranging from about 10 nm to about 400 nm, and in other embodiments from about 150 nm. to within a range of about 250nm.

In some embodiments, MEMS devices are formed on a Si wafer, and the wafer is diced into individual MEMS devices (wafers) by sawing at dicing streets 390 (a dicing operation). In some embodiments, the cutting operation does not completely cut the supporting second carrier bonding layer 305, as shown in Figure 6B. The individual MEMS devices are released by removing the second carrier bonding layer 305 and thus the second carrier substrate 300 .

In some embodiments, the cutting operation is performed after forming the second conductive layer 320 . In this case, no conductive layer is formed on the sides (cut surfaces) of the MEMS device. In other embodiments, the cutting operation is performed before forming the second conductive layer 320 . In this case, the second conductive layer 320 is also formed at the sides of the MEMS device.

In some embodiments, after removing the second carrier substrate 300 and the second carrier bonding layer 305, the individual MEMS devices are attached on a frame 400, as shown in FIG. 6C. As shown in FIG. 6C , the TSV holes 120 are exposed by removing the second carrier substrate 300 and the second carrier bonding layer 305 so that an electron beam or a light beam can pass through.

FIG. 7A shows a plan view of a MEMS device, and FIG. 7B shows a cross-sectional view of a bonding pad structure at the peripheral region PR. As shown in the plan view of FIG. 7A, the MEMS device has a central region CR and a peripheral region PR surrounding the central region. TSV holes 120 and conductive layers 210/215 are placed in the central region CR. In the peripheral region PR, one or more under-bump electrodes 250 are formed to connect the electronic circuit formed in the circuit substrate 20 to one or more circuits outside the MEMS device. In some embodiments, the peripheral region PR does not overlap the groove 35 in plan view. In other embodiments, the peripheral region PR partially overlaps the groove 35 in plan view.

The under-bump electrode 250 is formed on the front side of the circuit substrate 20 . in some real In an embodiment, the pad electrodes 250 are arranged in a matrix in the peripheral region PR. In some embodiments, a ball bump 260 is placed on each of the under-bump electrodes 250 . In some embodiments, the under-bump electrode 250 is formed prior to the recess etch (as shown in FIG. 6A ). In some embodiments, the under-bump electrode 250 is formed after the support substrate 30 is attached to the circuit substrate 20 via oxide fusion bonding, as shown in FIGS. 4A and 4B .

In some embodiments, the under-bump electrode 250 is formed on a metal pad 225 embedded in the interlayer dielectric layer 230 and composed of the uppermost metal layer of the electronic circuit (such as the 8th metal level to the 12th metal level). level) is formed. In some embodiments, metal pad 225 includes one or more layers of conductive material. In some embodiments, metal pad 225 includes Cu or a Cu alloy.

Furthermore, as shown in FIG. 7B , the under-bump electrode 250 includes multiple layers of conductive material. In some embodiments, the pad electrode 250 includes a first metal layer 252 , a second metal layer 254 , a third metal layer 256 and a fourth metal layer 258 . In some embodiments, the first metal layer is a TiW layer, the second metal layer is a Cu layer, the third metal layer is a Ni layer, and the fourth metal layer is a Sn layer.

In some embodiments, the thickness of TiW layer 252 is in a range from about 50 nm to about 1000 nm, and in other embodiments in a range from about 100 nm to about 500 nm. In some embodiments, Cu layer 254 has a thickness in a range from about 10 nm to about 2000 nm, and in other embodiments in a range from about 500 nm to about 1000 nm. In some embodiments, Ni layer 256 has a thickness in a range from about 1000 nm to about 5000 nm, and in other embodiments in a range from about 2500 nm to about 3500 nm. In some embodiments, the thickness of Sn layer 258 is in a range from about 500 nm to about 4000 nm, and in other embodiments in a range from about 1500 nm to about 2500 nm. The metal layer is formed by CVD, physical vapor deposition (PVD) (which includes sputtering, plating, or any other suitable film forming method) and lithography and etching. One or more engraved operations form.

In some embodiments, the surface of the electronic circuit is covered by one or more passivation layers. In some embodiments, the passivation layer includes a first passivation layer 242 , a second passivation layer 244 and a third passivation layer 246 . The under bump pad electrode 250 is formed in an opening formed in the passivation layer, as shown in FIG. 7B . In some embodiments, the first passivation layer 242 is a SiC layer, the second passivation layer 244 is a silicon oxide layer, and the third passivation layer 246 is a silicon nitride layer.

Figure 8 shows one use of a MEMS device according to one embodiment of the invention. In some embodiments, MEMS device 10 is used in an electron or an electromagnetic lithography. In some embodiments, the electron beam (or EUV line) 500 is input to the MEMS device 10 from the front side of the circuit substrate 20 . The electronic circuit formed in the circuit substrate 20 independently controls the voltage applied to the conductive layer (eg, the first conductive layer 130 ) formed on the inner wall of each of the TSV holes 120 . By adjusting the voltage applied to the conductive layer in the TSV holes 120, a portion of the electron beam 500 passes through one or more of the TSV holes and a portion of the electron beam 500 does not pass through the TSV holes. The portion of the electron beam passing through the TSV aperture is directed to a wafer or a substrate on which a photoresist layer is formed. In some embodiments, the wafer is a semiconductor wafer. In some embodiments, the substrate is used for a light shield, such as a transparent substrate or a reflective substrate. The position of the TSV hole 120 through which the electron beam passes is controlled by controlling the electronic circuitry, and thus a desired shape can be drawn on the photoresist pattern.

In other embodiments, a silicon-on-insulator (SOI) wafer is used. In this case, a fusion bonding procedure is omitted, and the oxide layer of an SOI wafer acts as an etch stop layer in the recess etch. 9A, 9B, 9C and 9D show schematic cross-sectional views of various stages of a fabrication operation of a MEMS device according to an embodiment of the invention. It should be appreciated that additional operations may be provided before, during, and after the procedures shown by FIGS. 9A-9D , and that some of the operations described below may be replaced or eliminated for additional embodiments of the method. do. The order of operations/procedures may be interchanged. The materials, configurations, dimensions, and procedures described with respect to FIGS. 1A-7B are applicable to the following embodiments and detailed descriptions thereof may be omitted.

The SOI substrate includes a device layer (semiconductor layer) 20', an oxide layer 40' and a bulk layer (semiconductor substrate) 30', as shown in FIG. 9A.

As shown in FIG. 9A, a CMOS circuit 25 is formed in a front surface region of the device layer 20'. One or more passivation films 28 are formed over the front surface of device layer 20'. In some embodiments, one or more passivation films 28 include silicon oxide, silicon nitride, or an organic film. In some embodiments, TSV holes 120 filled with a filling material 140 are formed through the device layer 20'. In addition, one or more first conductive layers 50 are formed on the front side of the device layer and in the TSV holes, as shown in Figure 9A.

Next, as shown in FIG. 9B, the rear side of the bulk layer 30' is recessed by using one or more lithography and etching operations. In some embodiments, the etching operation includes plasma dry etching or wet etching. In some embodiments, the wet etch utilizes tetramethylammonium hydroxide (TMAH) or KOH solutions.

In some embodiments, oxide layer 40' acts as an etch stop for forming recess 35, as shown in Figure 9B.

After the recess etch stops at the oxide layer 40', the oxide layer 40' is further etched by one or more dry etch or wet etch operations. During etching of oxide layer 40', fill material layer 140 is also removed from TSV hole 120, as shown in Figure 9C.

In some embodiments, one or more second conductive layers 55 are formed on the rear side of bulk layer 30', as shown in Figure 9D.

In an embodiment of the present invention, a MEMS device is formed by bonding a silicon oxide bonding layer through oxide fusion bonding or using an SOI substrate to bond a circuit substrate and a support substrate. place. The oxide bonding layer (oxide layer) also acts as an etch stop layer for a plasma dry etch when the support substrate is etched to form a recess, and thus protects the electronic circuitry formed in the circuit substrate from being damaged by Damage caused by plasma etching. Since the silicon oxide bonding layer can be removed by a wet etching operation, the removal process of the silicon oxide bonding layer does not cause damage to the electronic circuitry formed in the circuit substrate.

The various embodiments or examples described herein offer several advantages over the prior art, as set forth above. It should be appreciated that not all advantages are necessarily discussed herein, that not all embodiments or examples require a particular advantage, and that other embodiments or examples may provide different advantages.

According to an aspect of the present invention, a micro-electromechanical system (MEMS) includes: a circuit substrate, which includes an electronic circuit system; a support substrate, which has a groove; a bonding layer, which is placed between the circuit substrate and the support Between the substrates; several through holes, which pass through the circuit substrate to the opening; a first conductive layer, which is placed on a front side of the circuit substrate; a second conductive layer, which is placed on the groove on an inner wall; and a third conductive layer disposed on an inner wall of each of the through holes. In one or more of the above and following embodiments, the bonding layer includes silicon oxide. In one or more of the above and following embodiments, no bonding layer is placed in the groove and a bottom of the circuit substrate is in contact with the second conductive layer. In one or more of the above and following embodiments, the circuit substrate includes electrodes having different configurations. In one or more of the above and following embodiments, the electrodes include a first electrode on each of which places a first pillar electrode and each of which places a second electrode on which a second pillar electrode , and a height of the first pillar electrode is different from a height of the second pillar electrode. In one or more of the above and following embodiments, a height difference between the first pillar electrode and the second pillar electrode is in a range from 10 μm to 30 μm. In one or more of the above and following embodiments, in plan view, the circuit substrate includes a central area in which the through holes are provided and a peripheral area surrounding the central area, and has a shape different from the A plurality of under-bump electrodes of the electrode configuration are placed in the peripheral area. In one or more of the above and following embodiments, the peripheral region does not overlap the groove in plan view.

According to another aspect of the invention, in a method of fabricating a microelectromechanical system (MEMS), electronic circuitry is formed over a front side of a first substrate, forming one or more holes, filling the holes with a filling material, thinning a rear side of the first substrate to expose portions of the filled holes, bonding a second substrate to the rear side of the first substrate by a bonding layer , the bonding layer is interposed between the second substrate and the rear side of the first substrate, and a groove is formed in the second substrate to expose a bottom of the first substrate. In one or more of the above and following embodiments, the bonding layer is silicon oxide. In one or more of the above and following embodiments, the bonding layer is formed on the rear side of the first substrate. In one or more of the above and following embodiments, the bonding layer is formed on the second substrate. In one or more of the above and following embodiments, when forming the groove, a portion of the second substrate is etched by plasma dry etching to expose the bonding layer but the first substrate is not etched, and by An etch to etch the bonding layer selectively removes the bonding layer from the first substrate. In one or more of the above and following embodiments, when etching the bonding layer, the fill material is also removed from the holes to thereby form vias. In one or more of the above and following embodiments, a first conductive layer is formed over the front side of the first substrate and on the inner walls of each of the holes, and over an inner wall of the groove A second conductive layer is formed. In one or more of the above and following embodiments, at least one of the first conductive layer and the second conductive layer is a stacked layer of an Au layer on a Ti layer. In one or more of the above and below embodiments, the holes are arranged in a matrix in plan view.

According to another aspect of the invention, in a method of fabricating a microelectromechanical system (MEMS), electronic circuitry is formed over a front side of a first substrate, electrodes are formed over the first substrate, and in addition to forming the Formation of penetration to the second electrode at the region other than One or more holes in a substrate, the holes are filled with a filling material, a rear side of the first substrate is thinned to expose portions of the filled holes, a bonding layer made of silicon oxide connects a first Two substrates are bonded to the rear side of the first substrate, the bonding layer is interposed between the second substrate and the rear side of the first substrate, post electrodes are respectively formed above the electrodes, and on the second substrate A groove is formed in the middle to expose a bottom of the first substrate. In one or more of the above and following embodiments, when forming the groove, a portion of the second substrate is etched by plasma dry etching to expose the bonding layer but the first substrate is not etched, and by Wet etching is used to etch the bonding layer. In one or more of the above and following embodiments, the posts are formed by one or more plating operations.

The features of several embodiments or examples have been summarized above, so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other programs and structures to carry out the same purposes and/or achieve the same purposes as the embodiments or examples introduced herein. Advantages of an embodiment or example. Those skilled in the art should also recognize that such equivalent constructions should not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions and changes herein without departing from the spirit and scope of the present invention.

10C: Micro-Electro-Mechanical Systems (MEMS) Devices

20: Circuit board

25: Electronic Circuits/Electronic Circuit Systems/Complementary Metal Oxide Semiconductor (CMOS) Circuits

30: Support substrate

35: Opening/cavity/groove

40: joint layer

50: The first conductive layer

55: Second conductive layer

57: The third conductive layer

60: Through hole

L1: distance

L2: Distance

L3: Distance

T1: Thickness

T2: total thickness

Claims (10)

A micro-electromechanical system (MEMS), which includes: a circuit substrate, which includes an electronic circuit system; a support substrate, which has a groove; a bonding layer, which is placed between the circuit substrate and the support substrate; several through holes passing through the circuit substrate to openings; a first conductive layer placed on a front side of the circuit substrate; a second conductive layer placed on an inner wall of the groove; and A third conductive layer is disposed on an inner wall of each of the through holes. The MEMS according to claim 1, wherein no bonding layer is placed in the groove and a bottom of the circuit substrate is in contact with the second conductive layer. The MEMS as claimed in claim 1, wherein: the circuit substrate includes electrodes with different configurations, the electrodes include a first electrode on each of them, a first post electrode on each of them, and a first column electrode on each of them The second electrode of the two pillar electrodes, and the height of the first pillar electrode is different from the height of the second pillar electrode. The MEMS of claim 3, wherein: viewed from above, the circuit substrate includes a central area in which the through holes are provided and a peripheral area surrounding the central area, and A plurality of under-bump electrodes having a configuration different from the electrode is placed in the peripheral region. A method of manufacturing a microelectromechanical system (MEMS), comprising: forming electronic circuitry over a front side of a circuit substrate; forming one or more holes penetrating into the circuit substrate; filling the holes with a filling material holes; thinning a rear side of the circuit substrate to expose portions filling the holes; bonding a supporting substrate to the rear side of the circuit substrate by a bonding layer interposed between the supporting substrate and the circuit substrate between the rear sides; forming a groove in the support substrate to expose a bottom of the circuit substrate; forming a first conductive layer above the front side of the circuit substrate and on the inner walls of each of the holes ; and forming a second conductive layer over one of the inner walls of the groove. The method of claim 5, wherein the bonding layer is formed on the support substrate. The method of claim 5, wherein the groove is formed by: etching a part of the supporting substrate by plasma dry etching to expose the bonding layer and not etching the circuit substrate; and etching the bonding by an etching layer, the etching selectively removes the bonding layer from the circuit substrate, and removes the fill material from the holes to thereby form vias. The method of claim 5, wherein the bonding layer is formed on the rear side of the circuit substrate. A method of manufacturing a microelectromechanical system (MEMS), comprising: forming electronic circuitry over a front side of a circuit substrate; forming electrodes over the circuit substrate; forming through-holes at areas other than where the electrodes are formed to one or more holes in the circuit substrate; filling the holes with a filling material; thinning a rear side of the circuit substrate to expose portions of the filled holes; bonding a bonding layer made of silicon oxide to a a supporting substrate is bonded to the rear side of the circuit substrate, the bonding layer is interposed between the supporting substrate and the rear side of the circuit substrate; post electrodes are respectively formed above the electrodes; a groove is formed in the supporting substrate to expose a bottom of the circuit substrate; form a first conductive layer over the front side of the circuit substrate and on the inner walls of each of the holes; and form a second conductive layer over an inner wall of the groove Floor. The method of claim 9, wherein the groove is formed by: etching a part of the support substrate by plasma dry etching to expose the bonding layer and not etching the circuit substrate; and etching the circuit substrate by wet etching bonding layer.

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