TWI783274B - Low distortion triangular wave generator circuit and low distortion triangular wave generation method - Google Patents

Abstract

A low distortion triangular wave generator circuit generates a triangular wave by periodically integrating a charging current and a discharging current towards an integration capacitor during a charging period and a discharging period respectively. Time lengths of the charging period and the discharging period are the same. A common mode related signal related to a common mode characteristic of the triangular wave is generated. An adjusting signal is generated according to a difference between the common mode related signal and a predetermined DC (direct current) level. The adjusting signal adjusts at least one of the charging current and the discharging current with a feedback configuration such that the triangular wave is symmetrical and an average voltage of the triangular wave is equal to a target DC level.

Description

Low-distortion triangular wave generating circuit and method for generating low-distortion triangular wave

The invention relates to a triangular wave generating circuit, in particular to a low-distortion triangular wave generating circuit. The invention also relates to a method of generating a low distortion triangle wave.

Previous cases related to this case include: US9300281B2, US7746130B2, US8044690B2, "A Sub 1-V Constant Gm-C Switched-Capacitor Current Source, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS, VOL.54, NO.3, MARCH 2007", "A Low Area, Switched-Resistor Loop Filter Technique for Fractional-N Synthesizers Applied to a MEMS-based Programmable Oscillator, ISSCC 2010, Session 13.1".

FIG. 1A and FIG. 1B show a triangular wave generating circuit 101 in the prior art, in which two comparators are respectively used to compare the triangular wave signal VTR with the target peak level VH and compare the triangular wave signal VTR with the target valley level VL, and according to the two The comparison result of the comparator controls the charging current and the discharging current, so that in a steady state, the peak value and the valley value of the triangular wave signal VTR can be equal to the target peak level VH and the target valley level VL respectively.

The disadvantage of the triangular wave generating circuit 101 in the prior art is that the period for correcting and controlling the charging current and discharging current is limited to a part of the charging or discharging period. Therefore, the rising slope or falling slope of the triangular wave signal VTR generated by the prior art will vary. turning, thus causing the triangular wave signal VTR to have a higher degree of distortion.

2A-2B show a triangular wave generating circuit 102 in the prior art. This prior art also uses two comparators to compare the triangular wave signal VTR with the target peak level VH and compare the triangular wave signal VTR with the target valley level VL. , and control the charging and discharging time according to the comparison results of the two comparators, so that in a steady state, the peak value and the valley value of the triangular wave signal VTR can be equal to the target peak level VH and the target valley level VL respectively.

The disadvantage of the prior art triangular wave generating circuit 102 is that when the charging current and the falling current are not equal, the rising time and falling time of the triangular wave signal VTR generated by the prior art will also be unequal, thus causing the generated triangular wave signal VTR to be negative. A symmetrical triangle wave also has a high degree of distortion.

Compared with the prior art shown in FIG. 1A and FIG. 2A , the triangular wave signal generated by the present invention has the advantages of single slope and symmetry, and therefore has the advantage of low distortion.

In terms of one of the viewpoints, the present invention provides a low-distortion triangular wave generating circuit, comprising: an integrating circuit for receiving an external clock signal, and the integrating circuit is charged during a switching cycle of the external clock signal and a discharging period, respectively integrating a charging current and a discharging current to an integral capacitor to generate a triangular wave signal, wherein the charging period and the discharging period have the same time length; and an adjustment control circuit for according to the triangular wave signal And generate a common mode correlation signal, wherein the common mode correlation signal is related to the triangular wave signal A common mode characteristic of the common mode, and the adjustment control circuit generates an adjustment signal with gain according to the difference between the common mode related signal and a preset DC level; wherein the adjustment signal is used in a feedback manner to adjust the At least one of the charging current or the discharging current makes the triangular wave signal a symmetrical triangular wave, and the average voltage of the triangular wave signal is equal to a target DC level.

In a preferred embodiment, the regulating control circuit does not regulate the other of the charging current or the discharging current.

In a preferred embodiment, the adjustment control circuit includes: a sampling and holding circuit, which is used to periodically sample and hold the triangular wave signal at a sampling and holding time point in each switching period to generate the common-mode correlation signal and an error amplifier circuit for amplifying the difference between the common-mode correlation signal and the preset DC level to generate the adjustment signal, wherein the relationship between the preset DC level and the target DC level is determined by the sampling The proportional relationship between the maintenance timing and the switching cycle is determined.

In a preferred embodiment, the sample-and-hold circuit uses a phase-difference clock signal to sample and hold the triangular wave signal, wherein the phase difference between the phase-difference clock signal and the switching cycle is 90 degrees, so as to sample and hold a phase of the triangular wave signal The middle value of a rising slope or the middle value of a falling slope generates the common-mode correlation signal; wherein the error amplifier circuit uses the target direct current level as the preset direct current level.

In a preferred embodiment, the low-distortion triangular wave generation circuit is characterized by one of the following: (1) wherein the sample-and-hold circuit uses the external clock signal to sample and hold a peak value of the triangular wave signal, thereby generating the common mode related signal; wherein the error amplifier circuit uses a target peak level of the triangular wave signal as the preset DC level; or (2) wherein the sample hold circuit uses the external clock signal to sample and maintain a triangular wave signal valley, which in turn produces the common-mode phase off signal; wherein the error amplifier circuit uses a target valley level of the triangular wave signal as the preset DC level.

In a preferred embodiment, the sample-and-hold circuit samples and holds the triangular wave signal in an interleaved manner to combine into the common-mode correlation signal.

In a preferred embodiment, the adjustment control circuit includes a filter amplifier circuit, which includes: an error amplifier; and a low-pass filter feedback network, coupled to the error amplifier in a feedback manner, for receiving the A triangular wave signal, wherein the error amplifier and the low-pass filter feedback network use active low-pass filtering to amplify the difference between the triangular wave signal and the preset DC level, and simultaneously obtain the common-mode related signal and The adjustment signal is generated, wherein the error amplifier uses the target DC level as the preset DC level.

In a preferred embodiment, the adjustment control circuit includes: a comparator circuit for comparing the triangular wave signal with a reference signal to generate a pulse width modulation signal; and a filter amplifier circuit, which includes: an error amplifier circuit ; and a low-pass filter feedback network coupled to the error amplifier circuit in a feedback manner to receive the pulse width modulation signal, wherein the error amplifier circuit and the low-pass filter feedback network are active The way of low-pass filtering is to amplify the difference between the PWM signal and the preset DC level, and at the same time obtain the common-mode related signal and generate the adjustment signal, wherein the preset DC level is related to the reference signal, a target peak level of the triangular wave signal, a target valley level of the triangular wave signal, and the amplitude of the PWM signal, wherein the reference signal is between the target peak level and the target valley level between.

In a preferred embodiment, the reference signal corresponds to the target DC level, and the default DC level corresponds to 1/2 of the amplitude of the PWM signal.

In a preferred embodiment, the adjustment control circuit includes: a comparison circuit for comparing the triangular wave signal with the target DC level to generate a pulse width modulation signal; a duty cycle The comparison circuit is used to compare the pulse width modulation signal with the external clock signal, or to compare the pulse width modulation signal with a phase difference clock signal to generate a duty ratio error signal, wherein the phase difference clock signal The phase difference between the signal and the switching period is 90 degrees; and a filter circuit is used to filter the duty cycle error signal to simultaneously obtain the common mode related signal and generate the adjustment signal.

In a preferred embodiment, the filter circuit includes: an error amplifier circuit; and a low-pass filter feedback network coupled to the error amplifier circuit in a feedback manner to receive the duty ratio error signal, The error amplifier circuit and the low-pass filter feedback network amplify the difference between the duty ratio error signal and the preset DC level by means of active low-pass filter, and obtain the common-mode related signal at the same time and generating the regulation signal, wherein the preset DC level corresponds to 1/2 of the amplitude of the duty cycle error signal.

In a preferred embodiment, the duty cycle comparison circuit includes: a logic comparison circuit for comparing the difference between the pulse width modulation signal and the external clock signal, or for comparing the pulse width modulation signal with the The difference of a phase-difference clock signal generates a pull-up signal and a pull-down signal to represent the duty cycle difference of the rising edge and the falling edge respectively; and a switching circuit configured as one of the following: (1) the switching circuit includes An upper switch and a lower switch connected in series between a supply voltage and a ground potential, the upper switch and the lower switch are switched under the control of the pull-up signal and the pull-down signal respectively to generate the duty ratio an error signal, wherein the voltage difference between the supply voltage and the ground potential corresponds to the amplitude of the duty cycle error signal, wherein the filter circuit filters the duty cycle error signal to simultaneously obtain the common mode related signal and generate the or (2) the switching circuit includes an upper side current source and a lower side current source connected in series between a supply voltage and a ground potential, which are switched under the control of the pull-up signal and the pull-down signal respectively, and generates the duty cycle error signal, where the voltage difference between the supply voltage and the ground potential is In response to the amplitude of the duty cycle error signal, the filter circuit integrates and filters the duty cycle error signal to simultaneously obtain the common-mode related signal and generate the adjustment signal.

In a preferred embodiment, the integration circuit includes: the integration capacitor; a variable current circuit for generating one of the charging current or the discharging current according to the adjustment signal; a first fixed current source , used to generate the other of the charging current or the discharging current; and a selection circuit, used to select the charging current or the discharging current according to the external clock signal and integrate the integrating capacitor to generate the triangular wave signal .

In a preferred embodiment, the variable current circuit is configured as one of the following: (1) The variable current circuit includes; a voltage-controlled current source for generating the charge according to the adjustment signal and a transconductance coefficient One of the current or the discharge current; (2) the variable current circuit includes; a voltage-controlled current source for generating a variable current according to the adjustment signal and a transconductance; and a second fixed A current source, wherein the sum or difference of the variable current and the current of the second fixed current source corresponds to one of the charging current or the discharging current; (3) the variable current circuit includes; a third fixed a current source; and a pair of differential transistors receiving and distributing the second fixed current source to each other, wherein one of the pair of differential transistors is biased at a reference voltage, and one of the pair of differential transistors is biased at a reference voltage. The other is controlled by the adjustment signal, wherein the current flowing through the differential transistor pair corresponds to one of the charging current or the discharging current; or (4) the variable current circuit includes; an analog-to-digital conversion device, converting the adjustment signal into a digital switching signal; at least one sub-current source; at least one transfer switch, which is respectively coupled to the at least one sub-current source, wherein the at least one transfer switch receives the digital switching signal to switch accordingly and combining the at least one sub-current source to generate one of the charging current or the discharging current corresponding to the adjustment signal.

In a preferred embodiment, when the variable current circuit is configured as (1), (2) or (3), the selection circuit includes: a main switch for controlling the charging current or the discharging current one of the integrating capacitors; and a bypass switch for, when the one of the charging current or the discharging current is not integrating the integrating capacitor, the one of the charging current or the discharging current One is turned on to a reference potential.

From another point of view, the present invention also provides a method for generating a low-distortion triangular wave, including: a charging current and a discharging current are used for a charging period and a discharging period in a switching cycle of an external clock signal, respectively. Integrating an integrating capacitor to generate a triangular wave signal, wherein the charging period and the discharging period have the same time length; generating a common mode correlation signal according to the triangular wave signal, wherein the common mode correlation signal is related to a common mode characteristic of the triangular wave signal , and generate an adjustment signal with gain according to the difference between the common-mode related signal and a preset DC level; and adjust the charging current or the discharge current according to the adjustment signal in a feedback manner At least one of them makes the triangular wave signal a symmetrical triangular wave, and the average voltage of the triangular wave signal is equal to a target DC level.

In a preferred embodiment, only one of the charging current or the discharging current is adjusted.

In a preferred embodiment, the step of generating the adjustment signal includes: periodically sampling and maintaining the triangular wave signal at a sampling and sustaining time point in each switching cycle to generate the common-mode correlation signal; and The adjustment signal is generated by amplifying the difference between the analog correlation signal and the preset DC level, wherein the relationship between the preset DC level and the target DC level is determined by the proportional relationship between the sampling hold time point and the switching period.

In a preferred embodiment, the step of generating the common-mode correlation signal includes: sampling and maintaining the triangular wave signal with a phase-difference clock signal, wherein the phase difference between the phase-difference clock signal and the switching cycle is 90 degrees to sample Maintain the middle value of a rising slope of the triangular wave signal or an intermediate value of a falling slope to generate the common-mode related signal; wherein the target DC level is used as the preset DC level.

In a preferred embodiment, the method is characterized by one of the following: (1) sampling and maintaining a peak value of the triangular wave signal with the external clock signal, thereby generating the common-mode correlation signal; and using the triangular wave signal a target peak level as the preset DC level; or (2) use the external clock signal to sample and maintain a valley value of the triangular wave signal, thereby generating the common mode related signal; The target valley level is used as the preset DC level.

In a preferred embodiment, in the step of generating the common-mode correlation signal, the triangular wave signal is sampled and maintained in an interleaved manner to be combined into the common-mode correlation signal.

In a preferred embodiment, the step of generating the adjustment signal includes: amplifying the difference between the triangular wave signal and the preset DC level by means of active low-pass filtering, and simultaneously obtaining the common-mode correlation signal and The adjustment signal is generated, wherein the target DC level is used as the preset DC level.

In a preferred embodiment, the step of generating the adjustment signal includes: comparing the triangle wave signal with a reference signal to generate a pulse width modulation signal; amplifying the difference with the preset DC level, and simultaneously obtaining the common-mode correlation signal and generating the adjustment signal, wherein the preset DC level is related to the reference signal, a target peak level of the triangular wave signal, the A target valley level of the triangular wave signal and the amplitude of the PWM signal, wherein the reference signal is between the target peak level and the target valley level.

In a preferred embodiment, the reference signal corresponds to the target DC level, and the default DC level corresponds to 1/2 of the amplitude of the PWM signal.

In a preferred embodiment, the step of generating the adjustment signal includes: comparing the triangular wave signal with the target DC level to generate a pulse width modulation signal; comparing the pulse width modulation signal with the external clock signal, or generating a duty cycle error signal by comparing the pulse width modulated signal with a phase difference clock signal, wherein the phase difference clock signal is 90 degrees out of phase with the switching period; and filtering the duty cycle error signal to simultaneously Obtaining the common-mode correlation signal and generating the adjustment signal.

In a preferred embodiment, the step of filtering the duty cycle error signal includes: amplifying and filtering the difference between the duty cycle error signal and the preset DC level by active low-pass filtering, To obtain the common-mode correlation signal and generate the adjustment signal at the same time, wherein the preset DC level corresponds to 1/2 of the amplitude of the duty cycle error signal.

In the following detailed description by means of specific embodiments, it will be easier to understand the purpose, technical content, characteristics and effects of the present invention.

21, 21A, 21B, 21C: sample and hold circuit

22, 22A, 22B, 22C: error amplifier circuit

23: Filter amplifier circuit

24A, 24B: comparison circuit

25: Duty ratio comparison circuit

26: filter circuit

28,28': filter circuit

100: integrating circuit

101~104,105A: Triangular wave generating circuit

110A~110B, 115A~115D, 116: current circuit

111: Voltage-controlled current source

120: select circuit

130: differential transistor pair

140:digital converter

200: Regulating control circuit

221: Error amplifier

222: Low-pass filter feedback network

231: Error amplifier

232: Low-pass filter feedback network

251: Logic comparison circuit

252A, 252B: switching circuit

261: Error amplifier

262: Low-pass filter feedback network

ADJ, ADJU, ADJD: adjust the signal

CIT: integrating capacitor

ckm: pulse width modulation signal

CLK_e, CLK_eb: external clock signal

CLK_e90, CLK_e90b: phase difference clock signal

Cs1, Cs2: holding capacitor

Dadj: digital switching signal

Derr: duty ratio error signal

DN: pull down signal

Gm: transduction coefficient

Ichg: charging current

Idch: discharge current

Idf: branch current

Ifx1, Ifx2, Ifx3: fixed current sources

Is1~Isx: sub-current source

Ivr: variable current

SAH: common mode related signal

Sd1~Sdx: transfer switch

Sdn: Lower side switch

Sup: upper side switch

SW1: Main switch

SW2: Bypass switch

Tchg: charging period

Tdch: discharge period

Tsw: switching cycle

UP: pull up signal

VCM: target DC level

Vdc: preset DC level

Vdm: common mode related signal

VH: target peak level

VL: target valley level

VP: Peak

Vpp: Amplitude

Vref: reference signal

VTR: triangle wave signal

VV: valley value

Z1, Z2: Feedback components

1A-1B show a prior art triangular wave generation circuit and corresponding operation waveforms.

2A-2B show a prior art triangular wave generation circuit and corresponding operation waveforms.

FIG. 3 shows a schematic diagram of an embodiment of a low-distortion triangular wave generating circuit of the present invention.

FIG. 4 shows a schematic diagram of an embodiment of an adjustment control circuit in the low-distortion triangular wave generating circuit of the present invention.

FIG. 5A shows a schematic diagram of a specific embodiment of a sample-and-hold circuit and an error amplifier circuit in the low-distortion triangular wave generating circuit of the present invention.

FIG. 5B shows an operation waveform diagram corresponding to FIG. 5A.

FIG. 6A shows a schematic diagram of a specific embodiment of a sample-and-hold circuit and an error amplifier circuit in the low-distortion triangular wave generating circuit of the present invention.

FIG. 6B shows an operation waveform diagram corresponding to FIG. 6A.

FIG. 7A shows a schematic diagram of a specific embodiment of a sample-and-hold circuit and an error amplifier circuit in the low-distortion triangular wave generation circuit of the present invention.

FIG. 7B shows an operation waveform diagram corresponding to FIG. 7A.

FIG. 8A shows a schematic diagram of a specific embodiment of the filter amplifier circuit in the low-distortion triangular wave generation circuit of the present invention.

FIG. 8B shows an operation waveform diagram corresponding to FIG. 8A.

FIG. 9A shows a schematic diagram of a specific embodiment of the adjustment control circuit in the low-distortion triangular wave generation circuit of the present invention.

FIG. 9B shows an operation waveform diagram corresponding to FIG. 9A.

FIG. 9C shows a schematic diagram of a specific embodiment of the voltage generating circuit in the low-distortion triangular wave generating circuit of the present invention.

FIG. 10A shows a schematic diagram of a specific embodiment of the adjustment control circuit in the low-distortion triangular wave generation circuit of the present invention.

Fig. 10B shows an operation waveform diagram corresponding to Fig. 10A.

FIG. 11A shows a schematic diagram of a specific embodiment of the adjustment control circuit in the low-distortion triangular wave generation circuit of the present invention.

Fig. 11B shows an operation waveform diagram corresponding to Fig. 11A.

FIG. 12A shows a schematic diagram of a specific embodiment of the duty cycle comparison circuit in the low-distortion triangular wave generating circuit of the present invention.

FIG. 12B shows a schematic diagram of a specific embodiment of the filter circuit in the low-distortion triangular wave generation circuit of the present invention.

FIG. 13 shows a schematic diagram of a specific embodiment of the switching circuit and the filtering circuit in the low-distortion triangular wave generating circuit of the present invention.

14A to 14B show the schematic diagrams of specific embodiments of the integrating circuit in the low-distortion triangular wave generating circuit of the present invention.

15A to 15D show schematic diagrams of specific embodiments of the variable current circuit in the low-distortion triangular wave generating circuit of the present invention.

FIG. 16 shows a schematic diagram of a specific embodiment of a variable current circuit in the low-distortion triangular wave generating circuit of the present invention.

The diagrams in the present invention are all schematic and mainly intended to show the coupling relationship between various circuits and the relationship between various signal waveforms. As for the circuits, signal waveforms and frequencies, they are not drawn to scale.

FIG. 3 shows a block diagram of an embodiment of a low-distortion triangular wave generating circuit (triangular wave generating circuit 103 ) of the present invention. As shown in FIG. 3 , in this embodiment, the triangular wave generation circuit 103 includes an integration circuit 100 and an adjustment control circuit 200 .

The integration circuit 100 is used to receive the external clock signal CLK_e, and during the charging period Tchg and the discharging period Tdch in the switching period Tsw of the external clock signal CLK_e, the integrating circuit 100 uses the charging current Ichg and the discharging current Idch to control the integration circuit 100 respectively. Integral capacitor CIT product The triangular wave signal VTR is generated by dividing, wherein the charging period Tchg and the discharging period Tdch have the same time length. In one embodiment, the charging period Tchg and the discharging period Tdch respectively occupy 50% of the switching period Tsw.

The adjustment control circuit 200 is used to generate a common-mode correlation signal according to the triangular wave signal VTR, wherein the common-mode correlation signal is related to a common-mode characteristic of the triangular wave signal VTR, and the adjustment control circuit 200 is based on the relationship between the common-mode correlation signal and the preset DC level Vdc The difference is used to generate the adjustment signal ADJ with gain.

It should be noted that the above-mentioned "common mode characteristic" refers to the characteristic related to the common mode value of the triangular wave signal. From a point of view, the common mode value of the triangular wave signal is also the low frequency component or DC component of the triangular wave signal. In an embodiment, the "common mode characteristic" may correspond to the common mode value of the triangular wave signal, or the common mode value plus an offset value, or may be a peak value or a valley value.

Please continue to refer to FIG. 3 , the adjustment signal ADJ is used to adjust one of the charging current Ichg or the discharging current Idch in a feedback manner, so that the triangular wave signal VTR is a symmetrical triangular wave, and the average voltage of the triangular wave signal VTR is equal to the target DC level. VCM. In other words, at this time, the absolute values of the charging current Ichg and the discharging current Idch are adjusted to be equal to each other by the adjustment signal ADJ.

From a point of view, when the absolute values of the charging current Ichg and the discharging current Idch are not equal, the integrated triangular wave is The common mode value of the signal VTR will continue to rise or fall. Therefore, when the average voltage of the triangular wave signal VTR is equal to a target DC level VCM, it means that the absolute values of the charging current Ichg and the discharging current Idch are equal. At this time, the triangular wave signal VTR The signal VTR is a symmetrical triangle wave.

Please continue to refer to FIG. 3 , in an embodiment, the integration circuit 100 includes an integration capacitor CIT, current circuits 110A˜ 110B and a selection circuit 120 . In one embodiment, the current circuits 110A˜ 110B are respectively used to provide the charging current Ichg or the discharging current Idch mentioned above. In one embodiment, the selection circuit selects the charging current Ichg or the discharging current Idch to integrate the integrating capacitor CIT according to the external clock signal CLK_e (and its inverted signal: the external clock signal CLK_eb). Specifically, the external clock The pulse signal CLK_eb is used to control the conduction of the charge current Ichg, and the external clock signal CLK_e is used to control the conduction of the discharge current Idch.

In addition, according to the present invention, at least one of the current circuits 110A-110B is variable. Specifically, in one embodiment, at least one of the current circuits 110A-110B is variable. In this case, The integrating circuit 100 controls the current value of the charging current Ichg or the discharging current Idch according to the adjustment signal ADJ. Specifically, the adjustment signal ADJU is used to control the current value of the charging current Ichg, and the adjustment signal ADJD is used to control the current value of the discharge current Idch. .

In one embodiment, according to the present invention, the adjustment control circuit 200 does not adjust the other of the charging current Ichg or the discharge current Idch. One of the above-mentioned charging current Ichg or discharging current Idch, and the other is a fixed current value. Under this configuration, the absolute values of the charging current Ichg and the discharging current Idch are more easily adjusted to be equal, that is, the triangular wave signal The VTR could be more symmetrical.

Certainly, in other embodiments, adjusting the charging current Ichg and the discharging current Idch simultaneously according to the adjustment signal ADJ also complies with the spirit of the present invention.

FIG. 4 shows a schematic diagram of an embodiment of an adjustment control circuit in the low-distortion triangular wave generation circuit (104) of the present invention. In this embodiment, the adjustment control circuit 200 includes a sample hold circuit 21 and an error amplifier circuit 22 . The sample hold circuit 21 is used to periodically switch in each switching period Tsw In the sampling and holding time point, the triangular wave signal VTR is sampled and held to generate the common-mode correlation signal SAH. The error amplifier circuit 22 is used to amplify the difference between the common-mode related signal and the preset DC level Vdc to generate the adjustment signal ADJ, wherein the relationship between the preset DC level Vdc and the target DC level VCM is determined by the sampling and maintaining time point and switching It is determined by the proportional relationship of the cycle Tsw. The feedback elements Z1 and Z2 in the error amplifier circuit 22 can be configured as resistive elements or capacitive elements as required. The specific configuration details of the above-mentioned sample-and-hold circuit 21 are described in detail later.

FIG. 5A shows a schematic diagram of a specific embodiment of a sample-and-hold circuit and an error amplifier circuit in the low-distortion triangular wave generating circuit (105A) of the present invention. FIG. 5B shows an operation waveform diagram corresponding to FIG. 5A. In this embodiment, the sampling and holding circuit 21A uses the phase difference clock signal CLK_e90 to sample and hold the triangular wave signal VTR, wherein the phase difference between the phase difference clock signal CLK_e90 and the switching period Tsw is 90 degrees, so as to sample and hold the middle of the rising slope of the triangular wave signal VTR value or the middle value of the falling slope, thereby generating the aforementioned common-mode related signal. As shown in FIG. 5A and FIG. 5B , in this embodiment, since the intermediate value of the rising slope or the intermediate value of the falling slope of the triangular wave signal VTR is sampled and maintained, the preset DC level Vdc in the error amplifier circuit 22A is configured as Target DC level VCM. In other words, by adjusting at least one of the charging current Ichg or the discharging current Idch, when the middle value of the rising slope or the middle value of the falling slope of the triangular wave signal VTR is adjusted to the target DC level VCM, that is The triangular wave signal VTR can be made into a symmetrical triangular wave, and the average voltage of the triangular wave signal VTR is equal to the target DC level VCM. In one embodiment, the error amplifier circuit 22A includes an error amplifier 221 and a low-pass filter feedback network 222 .

Specifically, in this embodiment, the sample-and-hold circuit 21A includes a sustain capacitor Cs1 and corresponding sampling switches for performing a sample-and-hold operation on the triangular wave signal VTR according to the phase difference clock signals CLK_e90 and CLK_e90b to generate the sample-and-hold signals SAH0 and SAH1 (to Should be in the common mode related signal SAH). In one embodiment, the sample hold circuit 21A further includes a hold capacitor Cs2 and a corresponding sample switch.

In one embodiment, as shown in FIG. 5B , the sample-and-hold circuit 21A samples and holds the triangular wave signal VTR in an interleaved manner to combine into the common-mode correlation signal (SAH). Specifically, the sustain capacitor Cs2 and the corresponding sampling switch sample and sustain the triangular wave signal VTR in an interleaved manner to generate the sample and hold signal SAH1, and then the back-end switch combines the sample and hold signals SAH1 and SAH0 to form a common-mode correlation signal (SAH). .

FIG. 6A shows a schematic diagram of a specific embodiment of a sample-and-hold circuit and an error amplifier circuit in the low-distortion triangular wave generating circuit of the present invention. FIG. 6B shows an operation waveform diagram corresponding to FIG. 6A. In this embodiment, the sample-and-hold circuit 21B uses the external clock signal CLK_e to sample and hold the peak value VP of the triangular wave signal VTR to generate a common-mode correlation signal (SAH). In other words, the common-mode correlation signal SAH in this embodiment corresponds to The peak value VP of the triangular wave signal VTR; as shown in FIG. 6A and FIG. 6B , in this embodiment, the preset DC level Vdc in the error amplifier circuit 22B is configured as the target peak level VH of the triangular wave signal VTR. In other words, by adjusting at least one of the charging current Ichg or the discharging current Idch, when the peak value of the triangular wave signal VTR is adjusted to the target peak level VH, the triangular wave signal VTR can be made into a symmetrical triangle wave, and Make the average voltage of the triangular wave signal VTR equal to the target DC level VCM. In one embodiment, the sampling and holding circuit 21B still has two sets of holding capacitors and corresponding sampling switches, which can offset the interference caused when sampling the triangular wave signal VTR.

FIG. 7A shows a schematic diagram of a specific embodiment of a sample-and-hold circuit and an error amplifier circuit in the low-distortion triangular wave generation circuit of the present invention. FIG. 7B shows an operation waveform diagram corresponding to FIG. 7A. In this embodiment, the sample-and-hold circuit 21C uses the external clock signal CLK_e to sample and hold the valley value VV of the triangular wave signal VTR, thereby generating a common-mode correlation signal (SAH). In other words, in this embodiment The common-mode correlation signal SAH in the corresponding to the valley value VV of the triangular wave signal VTR; as shown in FIG. 7A and FIG. The target valley level VL. In other words, by adjusting at least one of the charging current Ichg or the discharging current Idch, when the valley value VV of the triangle wave signal VTR is adjusted to the target valley level VL, the triangle wave signal VTR can be made symmetrical. Triangular wave, and make the average voltage of the triangular wave signal VTR equal to the target DC level VCM.

FIG. 8A shows a schematic diagram of a specific embodiment of the filter amplifier circuit in the low-distortion triangular wave generation circuit of the present invention. FIG. 8B shows an operation waveform diagram corresponding to FIG. 8A. In this embodiment, as shown in FIG. 8A , the adjustment control circuit 200 includes a filter amplifier circuit 23 . In one embodiment, the filter amplifier circuit 23 includes an error amplifier 231 and a low-pass filter feedback network 232 .

The error amplifier 231 and the low-pass filter feedback network 232 are coupled to each other in a feedback manner to receive the triangular wave signal VTR, wherein the error amplifier 231 and the low-pass filter feedback network 232 are, for example, in the form of an active low-pass filter, Amplify the difference between the triangular wave signal VTR and the preset DC level Vdc, and at the same time obtain the common-mode related signal and generate the adjustment signal ADJ by means of active low-pass filtering, wherein the error amplifier 231 uses the target DC level VCM as the The preset DC level Vdc. In this embodiment, the common-mode related signal may correspond to the voltage Vdm of the negative input terminal of the error amplifier 231 . In other words, by adjusting at least one of the charging current Ichg or the discharging current Idch, when the common-mode related signal Vdm of the triangular wave signal VTR is adjusted to the target DC level VCM, the triangular wave signal VTR can become Symmetrical triangular wave, and make the average voltage of the triangular wave signal VTR equal to the target DC level VCM.

FIG. 9A shows a schematic diagram of a specific embodiment of the adjustment control circuit in the low-distortion triangular wave generation circuit of the present invention. FIG. 9B shows an operation waveform diagram corresponding to FIG. 9A. Figure 9C shows the present A schematic diagram of a specific embodiment of the voltage generating circuit in the low-distortion triangular wave generating circuit of the invention. In this embodiment, the adjustment control circuit 200 includes a comparison circuit 24A and a filter amplifier circuit 23 .

The comparison circuit 24A is used for comparing the triangular wave signal VTR with the reference signal Vref to generate a PWM signal ckm. The filter amplifier circuit 23 is similar to the aforementioned filter amplifier circuit 23, and it is used to receive the pulse width modulation signal ckm, wherein the error amplifier 231 and the low-pass filter feedback network 232 convert the pulse width modulation The difference between the variable signal ckm and the preset DC level Vdc is amplified, and the common-mode related signal (Vdm) is obtained and the adjusted signal ADJ is generated at the same time. In this embodiment, the common-mode related signal may correspond to the voltage of the negative input terminal of the error amplifier 231 (corresponding to Vdm).

In this embodiment, the preset DC level Vdc is related to the reference signal Vref, the target peak level VH of the triangular wave signal VTR, the target valley level VL of the triangular wave signal VTR, and the amplitude of the PWM signal ckm. Please refer to FIG. 9C. Specifically, in one embodiment, as shown in FIG. 9C, the voltage generating circuit 29 obtains a voltage between the target peak level VH and the target valley level VL by using the voltage divider circuit on the left side. The reference signal Vref. In addition, the voltage divider circuit on the right divides the amplitude Vpp of the pulse width modulation signal ckm according to the ratio of the reference signal Vref to the difference between the target peak level VH and the target valley level VL. Generate a preset DC level Vdc. In other words, by adjusting at least one of the charging current Ichg or the discharging current Idch, when the common-mode related signal Vdm of the triangular wave signal VTR is adjusted to the preset DC level Vdc, the triangular wave signal VTR can be adjusted. A symmetrical triangular wave is formed, and the average voltage of the triangular wave signal VTR is equal to the target DC level VCM.

FIG. 10A shows a schematic diagram of a specific embodiment of the adjustment control circuit in the low-distortion triangular wave generation circuit of the present invention. Fig. 10B shows an operation waveform diagram corresponding to Fig. 10A. FIG. 10A and FIG. 10B can be regarded as a specific embodiment of the above-mentioned embodiments in FIG. 9A-FIG. The current level Vdc corresponds to 1/2 of the amplitude of the PWM signal ckm, ie Vpp/2. In other words, in this embodiment, the comparator circuit 24B is used to compare the triangular wave signal VTR with the target DC level VCM to generate the pulse width modulation signal ckm, and at least one of the charging current Ichg or the discharging current Idch is performed as described above. Adjustment, and when the common mode related signal Vdm of the triangular wave signal VTR is adjusted to Vpp/2, the triangular wave signal VTR can be made into a symmetrical triangular wave, and the average voltage of the triangular wave signal VTR is equal to the target DC level VCM.

FIG. 11A shows a schematic diagram of a specific embodiment of the adjustment control circuit in the low-distortion triangular wave generation circuit of the present invention. Fig. 11B shows an operation waveform diagram corresponding to Fig. 11A. In this embodiment, the adjustment control circuit 200 includes a comparison circuit 24B, a duty cycle comparison circuit 25 and a filter circuit 26 .

The comparison circuit 24B is used for comparing the triangular wave signal VTR with the target DC level VCM to generate a PWM signal ckm. The duty cycle comparison circuit 25 is used for comparing the PWM signal ckm with the external clock signal CLK_e, or for comparing the PWM signal ckm with the phase difference clock signal CLK_e90 to generate a duty cycle error signal Derr, wherein The phase difference between the phase difference clock signal CLK_e90 and the switching period Tsw is 90 degrees. The filter circuit 26 is used to filter the duty ratio error signal Derr to simultaneously obtain the common-mode related signal (Vdm) and generate the adjustment signal ADJ.

In this embodiment, the error amplifier 261 of the filter circuit 26 and the low-pass filter feedback network 262 are coupled to each other in a feedback manner to receive the duty cycle error signal Derr, wherein the error amplifier 261 and the low-pass filter feedback network The circuit 262 amplifies the difference between the duty cycle error signal Derr and the preset DC level Vdc by means of active low-pass filtering, and simultaneously obtains the common-mode related signal Vdm and generates an adjustment signal ADJ, wherein the preset DC level Vdc corresponds to 1/2 of the amplitude of the duty ratio error signal Derr, ie Vpp/2. In other words, in this embodiment, by adjusting at least one of the charging current Ichg or the discharging current Idch, when the common-mode value of the duty ratio error signal Derr When Vdm (that is, the common-mode related signal of the triangular wave signal VTR in this embodiment) is adjusted to Vpp/2, the triangular wave signal VTR becomes a symmetrical triangular wave, and the average voltage of the triangular wave signal VTR is equal to the target DC level VCM.

Please refer to FIG. 12A at the same time. FIG. 12A shows a schematic diagram of a specific embodiment of the duty ratio comparator circuit in the low-distortion triangular wave generating circuit of the present invention. In one embodiment, the duty ratio comparison circuit 25 includes a logic comparison circuit 251 and a switching circuit 252A. The logic comparison circuit 251 is used to compare the difference between the PWM signal ckm and the external clock signal CLK_e, or to compare the difference between the PWM signal ckm and the phase difference clock signal CLK_e90 to generate a pull-up signal UP and a pull-down signal DN represents the difference between the duty cycle of the rising edge and the falling edge respectively. In this embodiment, as shown in FIG. 12A , the switching circuit 252A includes an upper switch Sup and a lower switch Sdn connected in series between the supply voltage Vpp and the ground potential, and the upper switch Sup and the lower switch Sdn are respectively received by the pull-up signal UP. Switching with the control of the pull-down signal DN to generate the duty ratio error signal Derr, wherein the voltage difference between the supply voltage Vpp and the ground potential corresponds to the amplitude (ie Vpp) of the duty ratio error signal Derr, wherein the filter circuit 26 will The duty ratio error signal Derr is filtered to simultaneously obtain the common-mode correlation signal and generate the adjustment signal ADJ.

FIG. 12B shows a schematic diagram of another specific embodiment of the filter circuit in the low-distortion triangular wave generation circuit of the present invention. In the above-mentioned embodiment of the adjustment control circuit 200 including the switch circuit 252A, the filter circuit can also replace the aforementioned filter circuit 26 with the passive filter circuit 28 in FIG. Modulus correlation signal and generate adjustment signal ADJ.

FIG. 13 shows a schematic diagram of a specific embodiment of the switching circuit and the filtering circuit in the low-distortion triangular wave generating circuit of the present invention. In this embodiment, the switching circuit 252B includes an upper current source Iup and a lower current source Idn connected in series between the supply voltage Vpp and the ground potential, respectively Switched under the control of the pull-up signal UP and the pull-down signal DN to generate a duty cycle error signal Derr, wherein the voltage difference between the supply voltage Vpp and the ground potential corresponds to the amplitude of the duty cycle error signal Derr, wherein the filter circuit 28 'Integrate and filter the duty ratio error signal Derr to simultaneously obtain the common-mode correlation signal and generate the adjustment signal ADJ.

14A to 14B show the schematic diagrams of specific embodiments of the integrating circuit in the low-distortion triangular wave generating circuit of the present invention. In one embodiment, as shown in FIG. 14A , the integration circuit 100A includes an integration capacitor CIT, a variable current circuit 110A, a fixed current source Ifx1 and a selection circuit 120 . The variable current circuit 110A is used to generate the charging current Ichg according to the adjustment signal ADJ, and the first fixed current source Ifx1 is used to generate the discharging current Idch. The selection circuit 120 is used for selecting the charging current Ichg or the discharging current Idch to integrate the integrating capacitor CIT to generate the triangular wave signal VTR according to the external clock signal CLK_e.

In one embodiment, as shown in FIG. 14B , the integration circuit 100B includes an integration capacitor CIT, a variable current circuit 110B, a fixed current source Ifx2 and a selection circuit 120 . The variable current circuit 110B is used to generate the discharge current Idch according to the adjustment signal ADJ, and the fixed current source Ifx2 is used to generate the charge current Ichg. The selection circuit 120 is used for selecting the charging current Ichg or the discharging current Idch to integrate the integrating capacitor CIT to generate the triangular wave signal VTR according to the external clock signal CLK_e.

15A to 15D show schematic diagrams of specific embodiments of the variable current circuit in the low-distortion triangular wave generating circuit of the present invention.

In one embodiment, as shown in FIG. 15A , the variable current circuit 115A includes a voltage-controlled current source 111, and the voltage-controlled current source 111 is used to generate charging according to the adjustment signal ADJ (ADJU in this embodiment) and the transconductance coefficient Gm. The current Ichg, in other embodiments, the voltage-controlled current source 111 can also be used to generate the discharge current Idch according to the adjustment signal ADJD and the transconductance coefficient Gm.

In one embodiment, as shown in FIG. 15B and FIG. 15C, the variable current circuit (115B, 115C) includes a voltage-controlled current source 111 and a fixed current source Ifx2, which are used to generate a variable current source according to the adjustment signal ADJ and the transconductance coefficient Gm. The variable current Ivr, wherein the sum of the variable current Ivr and the current of the fixed current source Ifx2 (Figure 15B) or the difference between the currents (Figure 15C) corresponds to the charging current Ichg, in other embodiments, the sum of the currents (Figure 15B) or The current difference ( FIG. 15C ) can be used to generate the discharge current Idch according to the adjustment signal ADJD and the transconductance coefficient Gm.

In one embodiment, as shown in FIG. 15D , the variable current circuit 115D includes a fixed current source Ifx3 and a differential transistor pair 130. The transistors M1 and M2 of the differential transistor pair 130 receive and distribute the fixed current source to each other. Ifx3, wherein the transistor M1 of the differential transistor pair is biased at a reference voltage (for example, ground potential), and the transistor M2 of the differential transistor pair is controlled by the adjustment signal ADJ (such as ADJU in FIG. 15D ), which flows through the differential The transistor M2 current of the electrokinetic pair corresponds to the charging current Ichg. Specifically, in this embodiment, charging current Ichg=fixed current source Ifx3−branch current Idf. In other embodiments, the current flowing through one of the differential transistor pair can be used to generate the discharge current Idch according to the adjustment signal ADJD and the conductance coefficient Gm.

Please continue to refer to FIGS. 15A to 15D. In one embodiment, the selection circuit 120 includes a main switch SW1 and a bypass switch SW2. The main switch SW1 is used to control one of the charging current Ichg or the discharging current Idch to the integrating capacitor. CIT integration, the bypass switch SW2 is used to conduct one of the charging current Ichg or the discharging current Idch to the reference potential when one of the charging current Ichg or the discharging current Idch is not integrated to the integrating capacitor CIT, thereby Can reduce the interference caused when switching.

FIG. 16 shows a schematic diagram of a specific embodiment of a variable current circuit in the low-distortion triangular wave generating circuit of the present invention. In one embodiment, as shown in FIG. 16 , the variable current circuit 116 includes an analog-to-digital converter 140, at least one sub-current source (Is1~Isx in the figure, x is a positive integer) and Corresponding to at least one switch (Sd1-Sdx in the figure, x is a positive integer). The analog-to-digital converter 140 converts the adjustment signal ADJ into a digital switching signal Dadj. The at least one sub-current source is correspondingly coupled to the at least one switch, wherein the at least one switch receives the digital switching signal Dadj to switch correspondingly to combine the at least one sub-current source to generate charging corresponding to the adjustment signal ADJ One of the current Ichg or the discharge current Idch.

The present invention has been described above with reference to preferred embodiments, but the above description is only for making those skilled in the art easily understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. The various embodiments described are not limited to single application, and can also be used in combination. For example, two or more embodiments can be used in combination, and some components in one embodiment can also be used to replace another embodiment. corresponding components. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the term "processing or computing according to a certain signal or generating a certain output result" in the present invention is not limited to According to the signal itself, it also includes performing voltage-to-current conversion, current-to-voltage conversion, and/or ratio conversion on the signal when necessary, and then processing or computing the converted signal to generate a certain output result. It can be seen that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combinations, which will not be listed here. Accordingly, the scope of the invention should encompass the above and all other equivalent variations.

100: integrating circuit

105A: Triangular wave generating circuit

21A: Sample hold circuit

22A: Error amplifier circuit

200: Regulating control circuit

221: Error amplifier

222: Low-pass filter feedback network

ADJ: adjust the signal

CLK_e, CLK_eb: external clock signal

CLK_e90, CLK_e90b: phase difference clock signal

Cs1, Cs2: holding capacitor

SAH: common mode related signal

SAH0, SAH1: sample hold signal

VCM: target DC level

Vdc: preset DC level

Vdm: common mode related signal

VTR: triangle wave signal

Z1, Z2: Feedback components

Claims (25)

A low-distortion triangular wave generating circuit, comprising: an integrating circuit for receiving an external clock signal, the integrating circuit uses a charging current for a charging period and a discharging period in a switching cycle of the external clock signal respectively Integrating a discharging current with an integrating capacitor to generate a triangular wave signal, wherein the charging period has the same time length as the discharging period; and an adjustment control circuit for generating a common-mode related signal according to the triangular wave signal, wherein the common The mode-related signal is related to a common-mode characteristic of the triangular wave signal, and the adjustment control circuit generates an adjustment signal in a manner with gain according to the difference between the common-mode correlation signal and a preset DC level; wherein the adjustment signal is The feedback method is used to adjust one of the charging current or the discharging current so that the triangular wave signal is a symmetrical triangular wave, and the average voltage of the triangular wave signal is equal to a target DC level; wherein the integrating circuit includes: the integrating a capacitor; a variable current circuit for generating one of the charging current or the discharging current according to the adjustment signal; a first fixed current source for generating one of the charging current or the discharging current another; and a selection circuit, used to select the charging current or the discharging current to integrate the integral capacitor to generate the triangular wave signal according to the external clock signal. The low-distortion triangular wave generating circuit as described in Claim 1, wherein the variable current circuit is configured as one of the following: (1) The variable current circuit includes; a voltage-controlled current source, which is used to generate the charging current or the discharging current according to the adjustment signal and a transconductance coefficient; (2) The variable current The circuit includes; a voltage-controlled current source, which is used to generate a variable current according to the adjustment signal and a transconductance coefficient; and a second fixed current source, wherein the difference between the variable current and the current of the second fixed current source The sum or difference corresponds to one of the charging current or the discharging current; (3) the variable current circuit includes; a third fixed current source; and a differential transistor pair, receiving and distributing the A third fixed current source, wherein one of the differential transistor pair is biased at a reference voltage, and the other of the differential transistor pair is controlled by the adjustment signal, wherein the differential transistor flows through the differential transistor The corresponding current corresponds to one of the charging current or the discharging current; or (4) the variable current circuit includes; an analog-to-digital converter, which converts the adjustment signal into a digital switching signal; at least one sub Current source; at least one switch, respectively coupled to the at least one sub-current source, wherein the at least one switch receives the digital switching signal to switch correspondingly and combine the at least one sub-current source to generate a current corresponding to the regulation The one of the charging current or the discharging current of the signal. The low-distortion triangular wave generating circuit as described in claim 2, wherein when the variable current circuit is configured as (1), (2) or (3), the selection circuit includes: a main switch for controlling the charging current or one of the discharge currents is integrated with the integrating capacitor; and a bypass switch for either the charging current or the discharging current when the one of the charging current or the discharging current is not integrating the integrating capacitor One of them is turned on to a reference potential. The low-distortion triangular wave generating circuit as described in claim 1, wherein the adjustment control circuit includes: a sampling and holding circuit, which is used to periodically sample and hold the triangular wave signal at a sampling and holding time point in each switching cycle and generating the common-mode correlation signal; and an error amplifier circuit for amplifying the difference between the common-mode correlation signal and the preset DC level to generate the adjustment signal, wherein the preset DC level and the target DC level The accurate relationship is determined by the proportional relationship between the sampling hold time point and the switching period. The low-distortion triangular wave generating circuit as described in claim 4, wherein the sampling and holding circuit uses a phase difference clock signal to sample and hold the triangular wave signal, wherein the phase difference between the phase difference clock signal and the switching period is 90 degrees to sample maintaining an intermediate value of a rising slope or a falling slope of the triangular wave signal to generate the common-mode correlation signal; wherein the error amplifier circuit uses the target DC level as the preset DC level. The low-distortion triangular wave generating circuit as described in claim 4 is characterized in that it is one of the following: (1) wherein the sample hold circuit uses the external clock signal to sample and maintain a peak value of the triangular wave signal, thereby generating the common mode correlation signal; wherein the error amplifier circuit uses a target peak level of the triangular wave signal as the a preset DC level; or (2) wherein the sample hold circuit uses the external clock signal to sample and maintain a valley value of the triangular wave signal, thereby generating the common mode related signal; wherein the error amplifier circuit uses the triangular wave signal A target valley level is used as the preset DC level. The low-distortion triangular wave generating circuit as described in Claim 5, wherein the sample-and-hold circuit samples and holds the triangular wave signal in an interleaved manner to combine into the common-mode correlation signal. The low-distortion triangular wave generation circuit as described in Claim 1, wherein the adjustment control circuit includes a filter amplifier circuit, which includes: an error amplifier; and a low-pass filter feedback network, which is coupled to the error in a feedback manner The amplifier is used to receive the triangular wave signal, wherein the error amplifier and the low-pass filter feedback network use active low-pass filtering to amplify the difference between the triangular wave signal and the preset DC level, and simultaneously obtain The common-mode correlation signal is used to generate the regulation signal, wherein the error amplifier uses the target DC level as the preset DC level. The low-distortion triangular wave generation circuit as described in claim 1, wherein the adjustment control circuit includes: a comparison circuit for comparing the triangular wave signal with a reference signal to generate a pulse width modulation signal; and a filter amplifier circuit, which Including: an error amplification circuit; and A low-pass filter feedback network, coupled to the error amplifier circuit in a feedback manner, for receiving the pulse width modulation signal, wherein the error amplifier circuit and the low-pass filter feedback network are actively low-pass The method of filtering amplifies the difference between the pulse width modulation signal and the preset DC level, and at the same time obtains the common mode related signal and generates the adjustment signal, wherein the preset DC level is related to the reference signal, A target peak level of the triangular wave signal, a target valley level of the triangular wave signal, and the amplitude of the PWM signal, wherein the reference signal is between the target peak level and the target valley level . The low-distortion triangular wave generating circuit as described in Claim 9, wherein the reference signal corresponds to the target DC level, and the preset DC level corresponds to 1/2 of the amplitude of the PWM signal. A low-distortion triangular wave generating circuit, comprising: an integrating circuit for receiving an external clock signal, the integrating circuit uses a charging current for a charging period and a discharging period in a switching cycle of the external clock signal respectively Integrating a discharging current with an integrating capacitor to generate a triangular wave signal, wherein the charging period has the same time length as the discharging period; and an adjustment control circuit for generating a common-mode related signal according to the triangular wave signal, wherein the common The mode-related signal is related to a common-mode characteristic of the triangular wave signal, and the adjustment control circuit generates an adjustment signal in a manner with gain according to the difference between the common-mode correlation signal and a preset DC level; wherein the adjustment signal is The feedback method is used to adjust at least one of the charging current or the discharging current, so that the triangular wave signal is a symmetrical triangular wave, and the average voltage of the triangular wave signal is equal to a target DC level; wherein the adjustment control circuit includes : A comparator circuit for comparing the triangular wave signal with the target DC level to generate a pulse width modulation signal; a duty ratio comparator circuit for comparing the pulse width modulation signal with the external clock signal, or using to generate a duty ratio error signal by comparing the pulse width modulation signal with a phase difference clock signal, wherein the phase difference between the phase difference clock signal and the switching period is 90 degrees; and a filter circuit for the duty ratio The duty ratio error signal is filtered to simultaneously obtain the common mode related signal and generate the adjustment signal; the duty ratio comparison circuit includes: a logic comparison circuit for comparing the difference between the pulse width modulation signal and the external clock signal, Or it is used to compare the difference between the pulse width modulation signal and the phase difference clock signal, and generate a pull-up signal and a pull-down signal to represent the duty cycle difference of the rising edge and the falling edge respectively; and a switching circuit configured as One of the following: (1) The switch circuit includes an upper switch and a lower switch connected in series between a supply voltage and a ground potential, the upper switch and the lower switch are respectively received by the pull-up signal and the pull-down signal Switched by the control of the control to generate the duty cycle error signal, wherein the voltage difference between the supply voltage and the ground potential corresponds to the amplitude of the duty cycle error signal, wherein the filter circuit filters the duty cycle error signal to obtain the common-mode related signal and generate the adjustment signal at the same time; or (2) the switching circuit includes an upper current source and a lower current source connected in series between the supply voltage and the ground potential, which are respectively pulled up by the signal is switched with the control of the pull-down signal to generate the duty cycle error signal, wherein the supply voltage The voltage difference between voltage and the ground potential corresponds to the amplitude of the duty cycle error signal, wherein the filter circuit integrates and filters the duty cycle error signal to simultaneously obtain the common mode related signal and generate the adjustment signal. The low-distortion triangular wave generation circuit as described in claim 11, wherein the filter circuit includes: an error amplifier circuit; and a low-pass filter feedback network, which is coupled to the error amplifier circuit in a feedback manner to receive the Duty ratio error signal, wherein the error amplification circuit and the low-pass filter feedback network amplify the difference between the duty ratio error signal and the preset DC level by means of active low-pass filtering, and at the same time Obtaining the common-mode correlation signal and generating the adjustment signal, wherein the preset DC level corresponds to 1/2 of the amplitude of the duty cycle error signal. The low-distortion triangular wave generation circuit as claimed in claim 11, wherein the adjustment control circuit only adjusts one of the charging current or the discharging current. A method for generating a low-distortion triangular wave, comprising: during a charging period and a discharging period in a switching cycle of an external clock signal, respectively integrating a charging current and a discharging current to an integrating capacitor to generate a triangular wave signal, wherein the charging period has the same time length as the discharging period; a common-mode correlation signal is generated according to the triangular wave signal, wherein the common-mode correlation signal is related to a common-mode characteristic of the triangular wave signal, and according to the common-mode correlation signal and a predetermined Setting the difference of the DC level to generate an adjustment signal with a gain; and adjusting one of the charging current or the discharging current according to the adjustment signal in a feedback manner, so that the triangular wave signal is a symmetrical triangular wave , and the average voltage of the triangular wave signal, etc. At a target DC level, the other of the charge current or the discharge current is a constant current. The method as described in claim 14, wherein the step of adjusting one of the charging current or the discharging current according to the adjustment signal includes one of the following: (1) controlling a (2) controlling a voltage-controlled current source to generate a variable current according to the adjustment signal and a transconductance coefficient; and controlling the adjustable The sum or difference of the variable current and a fixed current is used as the charging current or the one of the discharging current; (3) biasing a differential transistor pair with a fixed current source; and controlling with the adjustment signal One of a pair of differential transistors, and biases the other of the other pair of differential transistors with a reference voltage, wherein the one of the pair of differential transistors controlled by the adjustment signal flows through the One of the currents corresponds to the one of the charging current or the discharging current; or (4) converting the adjustment signal into a digital switching signal; and using the digital switching signal to control at least one switch to switch correspondingly and combine At least one current source is used to generate the one of the charging current or the discharging current corresponding to the adjustment signal. The method as described in claim 14, wherein the step of generating the adjustment signal includes: periodically sampling and maintaining the triangular wave signal at a sampling and holding time point in each switching cycle to generate the common-mode correlation signal; and Amplifying the difference between the common-mode related signal and the preset DC level to generate the adjustment signal, wherein the relationship between the preset DC level and the target DC level is determined by the proportional relationship between the sampling maintenance time point and the switching period And decided. The method as described in claim 16, wherein the step of generating the common-mode correlation signal includes: sampling and maintaining the triangular wave signal with a phase-difference clock signal, wherein the phase difference between the phase-difference clock signal and the switching period is 90 degrees, Sampling and maintaining an intermediate value of a rising slope or a falling slope of the triangular wave signal to generate the common-mode correlation signal; wherein the target DC level is used as the preset DC level. The method as described in claim item 16 is characterized in that one of the following: (1) sampling and maintaining a peak value of the triangular wave signal with the external clock signal, and then generating the common mode correlation signal; and using a peak value of the triangular wave signal The target peak level is used as the preset DC level; or (2) the external clock signal is used to sample and maintain a valley value of the triangular wave signal, thereby generating the common mode related signal; and a target of the triangular wave signal is used The valley level is used as the preset DC level. The method as described in claim 17, wherein in the step of generating the common-mode correlation signal, the triangular wave signal is sampled and maintained in an interleaved manner to be combined into the common-mode correlation signal. The method as described in claim 14, wherein the step of generating the adjustment signal includes: amplifying the difference between the triangular wave signal and the preset DC level by means of active low-pass filtering, and simultaneously obtaining the common-mode correlation signal and generate the adjustment signal, wherein the target DC level is used as the preset DC level. The method as claimed in claim 14, wherein the step of generating the adjustment signal comprises: Comparing the triangular wave signal with a reference signal to generate a pulse width modulation signal; and amplifying the difference between the pulse width modulation signal and the preset DC level by means of active low-pass filtering, and simultaneously obtaining the common mode correlation signal and generating the adjustment signal, wherein the preset DC level is related to the reference signal, a target peak level of the triangular wave signal, a target valley level of the triangular wave signal and the pulse width modulation signal The amplitude of the reference signal is between the target peak level and the target valley level. The method as claimed in claim 21, wherein the reference signal corresponds to the target DC level, and the preset DC level corresponds to 1/2 of the amplitude of the PWM signal. A method for generating a low-distortion triangular wave, comprising: during a charging period and a discharging period in a switching cycle of an external clock signal, respectively integrating a charging current and a discharging current to an integrating capacitor to generate a triangular wave signal, wherein the charging period has the same time length as the discharging period; a common-mode correlation signal is generated according to the triangular wave signal, wherein the common-mode correlation signal is related to a common-mode characteristic of the triangular wave signal, and according to the common-mode correlation signal and a predetermined Setting the difference of the DC level to generate an adjustment signal with a gain; and adjusting at least one of the charging current or the discharging current according to the adjustment signal in a feedback manner, so that the triangular wave signal is Symmetrical triangular wave, and the average voltage of the triangular wave signal is equal to a target DC level; wherein the step of generating the adjustment signal includes: comparing the triangular wave signal with the target DC level to generate a pulse width modulation signal; comparing the pulse width modulation changing the signal with the external clock signal, or comparing the pulse width modulated signal with a phase difference clock signal to generate a duty ratio error signal, wherein the phase difference between the phase difference clock signal and the switching period is 90 degrees; and filtering the duty ratio error signal to simultaneously obtain the common-mode correlation signal and generate the adjustment signal; wherein the step of generating the duty ratio error signal includes: comparing the difference between the pulse width modulation signal and the external clock signal, Or compare the difference between the pulse width modulation signal and the phase difference clock signal, and generate a pull-up signal and a pull-down signal to represent the duty cycle difference of the rising edge and the falling edge respectively; and the following steps (1) or (2 ) in one of: (1) under the control of the pull-up signal and the pull-down signal, respectively switch an upper side switch and a lower side switch connected in series between a supply voltage and a ground potential to generate the duty cycle an error signal, wherein the voltage difference between the supply voltage and the ground potential corresponds to the amplitude of the duty ratio error signal; An upper side current source and a lower side current source between a voltage and the ground potential to generate the duty cycle error signal, wherein the voltage difference between the supply voltage and the ground potential corresponds to the amplitude of the duty cycle error signal . The method as described in claim 23, wherein the step of filtering the duty cycle error signal comprises: amplifying and filtering the difference between the duty cycle error signal and the preset DC level, so as to simultaneously obtain the common mode correlation signal and generate the adjustment signal, wherein the preset DC level corresponds to 1/2 of the amplitude of the duty cycle error signal. The method according to claim 23, wherein one of the charging current or the discharging current is adjusted under the control of the adjustment signal, and the other of the charging current or the discharging current is a fixed current.

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