TWI781807B - Data processing method for afa storage device and the afa storage device utilizing the same - Google Patents

Abstract

An all flash array storage device includes a flash memory array and a micro-processor. The flash memory array includes multiple flash memories. The flash memories correspond to multiple logical aggregation units. Each logical aggregation unit includes multiple stripes. Each stripe includes multiple storage units. The storage units include data units and at least one parity unit. The micro-processor detects a status of the flash memories. In response to a detection result indicating that one of the flash memories has been removed from the flash memory array, the micro-processor sequentially performs a repair operation on the stripes comprised in one or more logical aggregation units that have been written with data. In the repair operation of a stripe, the micro-processor recalculates protection information of the stripe according to content stored in a portion of data units of the stipe and rewrites the recalculated protection information in one or more storage units of the stripe.

Description

Full flash array storage device and data processing method

The invention relates to a data processing method of a full-flash array storage device, especially a data processing method that can efficiently restore the original data protection capability when a disk is lost in the full-flash array storage device.

All Flash Array (AFA for short) is a storage device architecture, and its basic structure is to use several flash memory disks to form a storage array to greatly increase the storage space of the storage device. The full flash array is usually applied to a server on the network side to store a large amount of data from multiple users. In order to prevent one or more flash memory disks in the storage array from being damaged or removed, resulting in data loss in the storage device, the storage device can use a fault-tolerant disk array (Redundant Array of Independent Disks, abbreviated as RAID) ) The error protection mechanism adopted in the technology is used for data protection. In the error protection mechanism adopted by RAID, the storage device can calculate the protection information according to the written data. When it is found that the valid data is lost, the protected information can be used to reversely deduce the content of the lost valid data.

For example, the storage device can calculate M pieces of protection information according to the written data, so that the storage device can have +M protection capability, and the +M means that even when M flash memory disks are damaged or destroyed When removed, the storage device can still use the remaining data to perform data restoration, and deduce the data stored in the damaged or removed M flash memory disks.

However, for a storage device with +M protection capability, when a flash memory disk in the storage array is damaged or removed, the data protection capability will be reduced to +(M-1), and when When the number of damaged or removed flash memory disks is equal to M, the storage device no longer has the data protection capability.

In order to solve the above problems, the storage device can still restore the original data protection ability after the loss of disk (including the above-mentioned flash memory disk is damaged or removed), and at the same time, it is avoided to perform recovery. Due to the introduction of too many write operations related to the original data protection capability, the performance of the storage device is greatly reduced. A novel data processing method is required to effectively protect the flash array storage device when the disk is lost. Efficiently restore the original data protection capabilities.

One purpose of the present invention is to efficiently restore the original data protection capability when the flash array storage device loses a disk.

According to an embodiment of the present invention, a full flash array storage device includes a flash memory array and a microprocessor. The flash memory array includes a plurality of flash memories, and the flash memory corresponds to a plurality of logic aggregation units, each logic aggregation unit includes a plurality of stripes, and each stripe includes a plurality of storage units, and the storage units include a plurality of data for storing data The unit and at least the same unit for storing the protection information. The microprocessor is coupled to the flash memory array for detecting a state of the flash memory, wherein when the microprocessor detects that the operating state of one of the flash memories is abnormal, sequentially Perform a repair operation on the stripes that have been written into one or more logical aggregation units, and: in the repair operation corresponding to a stripe, the microprocessor according to at least a part of the data on the stripe unit stored content, restore a storage data on the stripe or recalculate a protection information corresponding to the stripe; and when the repair operation recalculates the protection information, the microprocessor writes the storage data When the storage data on the stripe is restored by the repair operation, the microprocessor writes the storage data to another one of the stripes.

According to an embodiment of the present invention, a data processing method applicable to a full flash array storage device, wherein the full flash array storage device includes a flash memory array, the flash memory array includes a plurality of flash memories, and the flash memory The memory corresponds to a plurality of logic aggregation units, each logic aggregation unit includes a plurality of stripes, each stripe includes a plurality of storage units, and the storage unit includes a plurality of data units for storing data and at least one homologous unit for storing protection information, data The processing method includes: when an abnormal operation state of one of the flash memories is detected, a repair operation is performed sequentially on the stripes included in one or more logical aggregation units that have written data ; In the repair operation corresponding to a strip, the microprocessor restores a piece of stored data on the strip or recalculates a piece of protection information corresponding to the strip according to the content stored in at least a part of the data units on the strip ; and when the repair operation recalculates the protection information, the microprocessor writes the stored data to the stripe, and when the repair operation restores the stored data on the stripe, the microprocessor will The stored data is written to another of the stripes.

According to an embodiment of the present invention, a full flash array controller includes a memory device and a microprocessor. The microprocessor is coupled to the memory device and a flash memory array, and is used to manage the flash memory array according to the data stored in the memory device, wherein the flash memory array includes a plurality of logic aggregation units, each logic aggregation unit It includes a plurality of stripes, each stripe includes a plurality of storage units, and the storage units include a plurality of data units for storing data and at least one homobit unit for storing protection information. When the microprocessor detects that the operating state of one of the flash memories is abnormal, sequentially perform a repair operation on the stripes included in one or more logical aggregation units that have written data ; In the repair operation corresponding to a strip, the microprocessor restores a piece of stored data on the strip or recalculates a piece of protection information corresponding to the strip according to the content stored in at least a part of the data units on the strip ;as well as

When the repair operation recalculates the protection information, the microprocessor writes the stored data to the stripe, and when the repair operation restores the stored data on the stripe, the microprocessor writes the stored data Data is written to the other of the stripes.

In the following, numerous specific details are described in order to provide a thorough understanding of embodiments of the invention. Those skilled in the art will still understand, however, how to practice the invention without one or more of the specific details or by reliance on other methods, elements, or materials. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the main concepts of the invention.

Reference throughout this specification to "one embodiment," "an embodiment," "an example," or "an example" means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in the present invention In at least one embodiment of the plurality of embodiments. Thus, appearances of the phrases "in one embodiment," "in an embodiment," "in one example," or "in an example" in various places throughout this specification are not necessarily all referring to the same embodiment. or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combination and/or subcombination in one or more embodiments or examples.

In addition, in order to make the purpose, features and advantages of the present invention more comprehensible, specific embodiments of the present invention are listed below and described in detail in conjunction with the accompanying drawings. The purpose is to illustrate the spirit of the present invention rather than to limit the protection scope of the present invention. It should be understood that the following embodiments can be implemented through software, hardware, firmware, or any combination of the above.

The invention relates to a full flash array storage device and a data processing method of the full flash array storage device. According to an embodiment of the present invention, the all-flash array storage device may include a plurality of flash memory disks, each flash memory disk may include at least one flash memory, and the flash memory disks included The memory may form a flash memory array.

FIG. 1 is a schematic view showing the appearance of a full flash array storage device according to an embodiment of the present invention. In the embodiment shown in FIG. 1, the all-flash array storage device 100 may include N flash memory disks, for example, the flash memory disks 110-1~110-N shown in the figure, where N is For a positive integer greater than 1, each flash memory disk includes a flash memory. Therefore, the full flash array storage device 100 may include a flash memory array composed of N flash memories.

When the flash array storage device loses a disk, for example, one of the flash memory disks (for example, flash memory disk 110-n, wherein n is a positive integer) is removed from the full flash array storage device 100, or When the disk is damaged or unrecognizable, the data protection capability of the full flash array storage device 100 will decrease correspondingly because the data stored in the flash memory disk 110-n is lost. In order to restore the lost data and enable the full-flash array storage device 100 to restore the original data protection capability after a disc loss occurs, the full-flash array storage device 100 needs to perform a corresponding repair operation to derive the lost data, and The original data protection capability of the full flash array storage device 100 is restored. In the embodiment of the present invention, with the data processing method proposed by the present invention, the original data protection capability can be efficiently restored with a very small number of write operations.

FIG. 2 is a block diagram showing an example of an all-flash array storage device according to an embodiment of the present invention. According to an embodiment of the present invention, the all-flash array storage device 200 may include an all-flash array controller 210 and a flash memory array 240 formed by flash memories contained in a plurality of flash memory disks. The full flash array controller 210 may include a microprocessor 220 and a memory device 230 . The microprocessor 220 is coupled to the memory device 230 and the flash memory array 240 for managing the flash memory array 240 according to the data stored in the memory device 230 . According to an embodiment of the present invention, the flash memory array 240 may include a plurality of flash memories, and each flash memory may correspond to a flash memory disk, and the microprocessor 220 may continuously detect each flash memory disk. disk or flash memory. For example, the microprocessor 220 can continuously send polling signals to poll the status of the flash disk or the flash memory. When the microprocessor 220 cannot receive a response from the flash memory disk or flash memory within the predetermined time, or the received response shows an abnormal state, or the microprocessor 220 can no longer recognize the flash memory disk or flash memory When the memory is stored, the microprocessor 220 can determine that a disk has been dropped from the full flash array storage device 200 or the flash memory array 240 . Since a disk drop may include many different situations caused by different reasons, and all of these situations will lead to the loss of data stored in this flash memory, therefore, in order to simplify the description, the following paragraphs will be unified as flash memory self-flash The situation in which the memory array 240 is removed is representative of various situations included in disk loss. It will be appreciated that the data processing method proposed by the present invention is not limited to the case where the flash memory is removed, but can be applied to any event that will eventually result in a flash memory array comprising a portion of the flash memory A situation where data is lost and part of the flash memory contained in the flash memory array cannot be used any longer.

FIG. 3 shows the software architecture for managing the flash memory array according to an embodiment of the present invention, and is used to illustrate the addressing operation inside the full flash array storage device. According to one embodiment of the present invention, the microprocessor 220 may include one or more internal memory devices for storing data and program codes required to manage the flash memory array. Wherein, the microprocessor 220 can generate a plurality of modules for managing the flash memory array by executing the program codes, and each module can perform corresponding operations. For example, the software modules generated by the microprocessor 220 by executing the program codes may include a volume management module 310 and a flash array control module 320 . In response to a write command User_Write for writing data corresponding to a Virtual Volume Logic Block Address (VVLBA) into the flash memory array, the volume management module 310 may first write this The virtual volume logical block address VVLBA is converted into another storage pool logical block address (Storage poolLogic Block Address, abbreviated SLBA) used inside the microprocessor 220, and the flash array control module 320 is notified to write the data The storage pool logical block address SLBA. Then, the flash array control module 320 converts the storage pool logical block address SLBA into a disk logical block address (Disk Logical Block Address, DLBA for short) of the flash memory array, and executes the corresponding writing The operation is used to write the received data (that is, the data corresponding to the logical block address SLBA of the storage pool, and also the data corresponding to the aforementioned virtual volume logical block address VVLBA) into the corresponding disk logical area Block address DLBA.

More specifically, in response to a write command User_Write for writing user data DATA_A corresponding to a virtual volume logical block address VVLBA_1 into the flash memory array, the microprocessor 220 of the full flash array controller 210 can Perform address transfer twice, first convert the virtual volume logical block address VVLBA_1 to another internally used storage pool logical block address SLBA_1, and then convert the storage pool logical block address SLBA_1 to the disk logical area block address DLBA_1, and then the microprocessor 220 can issue a write command to one or more flash memory disks to write the data DATA_A into the flash memory array addressed by the disk logic block address DLBA_1 storage unit.

It should be noted that, in the embodiment of the present invention, the aforesaid storage unit is the storage unit in the full flash array storage device, that is, the storage unit viewed by the full flash array controller 210, which is not necessarily equivalent to each flash The physical storage unit inside the memory.

In addition, it should be noted that in the embodiment of the present invention, the size of the "block" in the block address is not necessarily equal to the size of the physical "memory block" included in the flash memory. For example, in one embodiment of the present invention, the "block" in the physical block address or logical block address can be a write unit of 4K bytes (Byte), therefore, a disc The Logical Block Address DLBA is addressable to a storage unit having a size of 4KB in the flash memory array. The size of a physical "memory block" included in the flash memory may depend on the physical configuration of the flash memory.

In addition, it should be noted that since the flash memory array is composed of flash memory contained in a plurality of flash memory disks, each flash memory disk may further include a memory controller for controlling Corresponding flash memory access operations. Therefore, when the memory controller in each flash memory disk writes the received data into the corresponding flash memory according to the received disk logical block address DLBA (or, when the memory controller writes the received data into the corresponding flash memory according to the received When the received logical address reads data from the corresponding flash memory), another redirection operation will be performed to convert the received logical address into one or more addresses that can be addressed to the corresponding flash memory. The physical address of the physical storage unit, the physical address (that is, the physical address viewed by the memory controller in each flash memory disk) is the address that actually corresponds to the physical storage unit.

Continuing from the previous example, when the flash memory disk containing the storage unit of the full flash array storage device pointed to by the disk logical block address DLBA_1 receives a write containing data DATA_A and the disk logical block address DLBA_1, etc. When the command is input, the memory controller of the flash memory disk can further convert the logical block address DLBA_1 of the disk into a physical block address PBA_1 actually used internally, wherein the physical block address PBA_1 refers to the memory block and data page in the flash memory disk that are actually arranged to store the data DATA_A, and the memory controller stores the data DATA_A in the memory block addressed by the physical block address PBA_1 and data page.

According to one embodiment of the present invention, the flash memory array may include a plurality of flash memories, and the flash memories correspond to a plurality of logical aggregation units (Logical Aggregation Unit, abbreviated as LAU), and each logical aggregation unit includes a plurality of stripes ( stripe), each stripe includes a plurality of storage units. The multiple storage units located in the same stripe in the all-flash array storage device can actually be distributed in multiple flash memories, and these storage units can include multiple data units for storing data and at least one data unit for storing protection information. bit (parity) unit.

FIG. 4 is a schematic diagram of a logical aggregation unit according to an embodiment of the present invention. In this example, the full flash array storage device may include a plurality of flash memory disks Drive_1˜Drive_N, wherein N is a positive integer. The flash memory array composed of the flash memories contained in the flash memory disks Drive_1~Drive_N can form/correspond to a plurality of logic aggregation units, such as one of the logic aggregation units LAU framed by a dotted line in the figure. Each logical aggregation unit corresponds to a part of the flash memory disks Drive_1˜Drive_N, for example, a memory space of 64KB.

The right side of Figure 4 shows the data content stored in a logical aggregation unit LAU. Each logical aggregation unit includes a plurality of stripes, such as stripes Stripe_1˜Stripe_K shown in the figure, wherein K is a positive integer. Each stripe includes a plurality of storage units, and the size of a storage unit can be designed to be the size of a write unit (for example, 4KB). The storage units located in the same stripe may respectively correspond to different flash memory disks. The storage unit may include or be further divided into a plurality of data units for storing data (eg, data D1-D32) and a plurality of homobit units for storing protection information (eg, protection information P1-P4 and Q1-Q4).

In the example shown in FIG. 4, N=10, and the flash memory array is designed to have a protection capability of +2. Therefore, as shown in the figure, Stripe_1 may include 10 storage units corresponding to different flash memories, 8 of which may be configured as data units for storing data, and the remaining 2 storage units may be A peer unit configured to store protected information. The microprocessor 220 can calculate the corresponding protection information (for example, protection information P1 and Q1) according to the data content stored in the data unit (for example, the data D1~D8 stored in the data unit of Stripe_1), and store the protection information The co-bit unit stored in this stripe is used to protect the data stored in this stripe. The data stored in the data unit mentioned here is the aforementioned user data.

In addition to storing user data, one or more stripes of a logical aggregation unit LAU can be further used to store the original data (meta data) of the logical aggregation unit LAU, wherein the raw data can at least include the logical aggregation unit LAU Disk to Storage pool (D2S for short) mapping information of multiple stripes. In the example shown in Figure 4, the stripes used to store raw data (for example, stripes Stripe_(K-1) and Stripe_K) can record multiple logical block addresses, such as the logical block shown in the figure Addresses LBA1~LBA16, where a data unit of a stripe used to store raw data can be used to store data stored in a data unit of a stripe used to store user data (for example, stripe Stripe_1) corresponds to Logical block address. That is, the logical block address recorded in a data unit of the strip used to store raw data may be the logical block address corresponding to the data stored in a data unit of the strip used to store user data ( For example, the aforementioned storage pool logical block address (SLBA). In addition, in order to protect the D2S mapping information, the microprocessor 220 can calculate the corresponding protection information (such as , the protection information PM1 and QM1), and store the protection information in the same bit unit of the stripe.

In one embodiment of the present invention, the logical block addresses LBA1~LBA16 may be the aforementioned storage pool logical block addresses SLBA, and the number of stripes used to store raw data in one logical aggregation unit LAU may be Equal to the number of stripes used to store user data.

Referring back to FIG. 2, according to one embodiment of the present invention, when the microprocessor 220 detects that one of the flash memories is removed from the flash memory array 240, the microprocessor 220 can perform a repair operation , so that the flash memory array 240 can restore the predetermined data protection capability. Wherein, the predetermined data protection capability may be the original data protection capability of the flash memory array 240 , that is, the previously set protection capability. For example, assuming that the microprocessor 220 calculates two pieces of corresponding protection information (for example, P1 and Q1 or PM1 and QM1 shown in FIG. The set protection capability of the volume array 240 is +2 protection capability. When the microprocessor 220 detects that one of the flash memories is removed from the flash memory array 240, the protection capability of the flash memory array 240 is reduced to only have a protection capability of +1. Therefore, in the embodiment of the present invention, the microprocessor 220 can perform a repair operation, so that the flash memory array 240 can restore the predetermined data protection capability of +2. It should be noted that, for the sake of brevity, in the embodiment of the present invention, two pieces of protection information and +2 data protection capability are used as an illustration example, but the present invention is not limited thereto. Flash memory arrays can provide different data protection capabilities with different amounts of protection information.

FIG. 5 is a flowchart showing a data processing method of a full flash array storage device according to an embodiment of the present invention. According to an embodiment of the present invention, as described above, in the data processing method of the all-flash array storage device proposed by the present invention, in response to indicating that one of the flash memories is removed from the flash memory array As a result of the detection, the microprocessor 220 can sequentially perform a repair operation on the plurality of stripes included in one or more logic aggregation units that have written data, so that the flash memory array can resume providing predetermined data protection ability.

In the embodiment of the present invention, the repair operation is repeatedly performed on the stripes included in the logical aggregation units that have been written with data, until the repair operations for all the logical aggregation units that have been written with data are completed.

In an embodiment of the present invention, the repair operation performed sequentially on the stripes included in one or more logical aggregation units of the written data may include the following steps:

Step S502: Recalculate the protection information corresponding to the stripe according to the content stored in a part of the data unit of the stripe included in the logical aggregation unit of the data that has been written. It should be noted that, in the embodiment of the present invention, regardless of whether the storage unit corresponding to the removed flash memory in a stripe is a data unit or a parity unit, part of the data used to recalculate the protection information in step S502 One of the units will be less than one of all the data units contained in the stripe.

Step S504: Rewrite the protection information corresponding to the recalculated stripe into one or more of the storage units of the stripe. For example, assuming that the microprocessor 220 wants to enable the flash memory array to provide a data protection capability of +2, the microprocessor 220 can recalculate the two corresponding protection information, and re-write the recalculated protection information into the two storage units to replace their previously stored contents.

Fig. 6 shows an execution example of a repair operation according to an embodiment of the present invention, to illustrate the repair operation when the storage unit corresponding to the removed flash memory in a stripe is a data unit . In this example, one strip can include 10 storage units corresponding to different flash memories, such as storage units 601~610 shown in the figure, where storage units 601~608 are data units for storing data respectively D1-D8, the storage units 609-610 are co-bit units, respectively used to store the protection information P and Q corresponding to the data D1-D8 stored in the stripe.

Assuming that the storage unit 605 corresponding to the removed flash memory in this stripe is a data unit, in the repair operation, the microprocessor 220 can judge whether the data unit 605 stores valid data, if the data unit 605 does not store Valid data, that is, the data D5 is invalid data, then the microprocessor 220 can directly discard the data D5, and according to the information stored in the remaining data units other than the storage unit corresponding to the removed flash memory in this stripe The content recalculates the protection information corresponding to this strip (for example, recalculates the protection information P' and Q' corresponding to this strip according to the data D1~D4 and D6~D8 shown in the figure), and the microprocessor 220 The recalculated protection information can be written into the same bit unit of this stripe to replace the original stored content of the same bit unit (for example, the recalculated protection information P' and Q' are stored in the storage unit 609~ of this stripe 610, used to replace the previous protection information P and Q). It should be noted that, for the microprocessor 220, the recalculated protection information is written into the same disk logical block address DLBA (for example, the addresses of the storage units 609~610), and for the corresponding flash As far as the memory controller in the memory disk is concerned, the recalculated protection information is the update data of the same logical address.

On the other hand, if the data unit 605 still stores valid data, the microprocessor 220 needs to perform data recovery (data recovery) and data transfer operations, and reversely deduce the data stored in the data unit 605 according to the content stored in this strip. data, and move the restored data to other storage units. More specifically, the microprocessor 220 can deduce the valid data stored in the storage unit 605 according to the contents stored in the other storage units in the stripe. After obtaining the valid data stored in the data unit 605 (for example, the data D5 shown in the figure), the microprocessor 220 writes the deduced valid data D5 into a storage unit ( For example, the storage unit 611 shown in the figure), the active logical aggregation unit refers to the logical aggregation unit being configured to receive user data (eg, the data Dh shown in the figure). After the data units (for example, storage units 611~618) in the current logic aggregation unit are full, the microprocessor 220 can calculate two corresponding protection information according to the data content stored in the data unit (for example, in the figure P'' and Q'' as shown) are written into corresponding parity cells (for example, storage cells 619~620).

In addition, the microprocessor 220 according to an address of a data unit (for example, the storage unit 611 shown in the figure) used to store the deduced (restored) valid data in the active logical aggregation unit (for example, the disk logical area block address DLBA) to update a mapping table (for example, a storage pool to disk (Storage pool to Disk, abbreviated as S2D) mapping table) corresponding to the logical address of this valid data (for example, storage pool logic block address SLBA) mapping information. For example, the S2D mapping information corresponding to the storage pool logical block address SLBA of the valid data in the S2D mapping table is modified to the disk logical block address DLBA of the storage unit 611 .

According to one embodiment of the present invention, the microprocessor 220 can establish the above-mentioned S2D mapping table for the flash memory array 240 to record the corresponding disk logical block address for each storage pool logical block address SLBA DLBA, and store this S2D mapping table into the memory device 230, wherein the disk logical block address DLBA corresponding to the logical block address SLBA of a storage pool indicates that the corresponding storage pool logical block address SLBA is stored The disk logical block address DLBA of the data.

The microprocessor 220 can determine whether the data stored in a data unit is valid data by comparing whether the S2D mapping information recorded in the S2D mapping table is consistent with the D2S mapping information recorded in the logic aggregation unit LAU. More specifically, the S2D mapping table may include multiple fields, one field corresponds to a storage pool logical block address SLBA, and the data used to record the storage pool logical block address SLBA is actually stored in the flash Which disk logical block address DLBA of the memory array 240. The number of fields included in the S2D mapping table may be equal to the total number of logical block addresses or storage units viewed by the volume management module 310 and/or the flash array control module 320 .

In addition, as mentioned above, one or more stripes used to store raw data in one logical aggregation unit LAU can record the D2S information of multiple stripes in the logical aggregation unit LAU. When judging whether the data stored in a data unit (for example, data unit DU_a) is valid data, the microprocessor 220 can first check the original data of the data unit recorded in the logical aggregation unit LAU including the data unit, and use To know the D2S mapping information of this data unit, for example, obtain the storage pool logical block address SLBA_a corresponding to this data unit DU_a (that is, know that the data currently stored in this data unit corresponds to the storage pool logical block address SLBA_a). Then, the microprocessor 220 can check the content recorded in the S2D mapping table stored in the memory device 230 corresponding to the storage pool logical block address SLBA_a, so as to obtain the S2D of the storage pool logical block address SLBA_a Mapping information, for example, knowing the disk logical block address DLBA_a currently corresponding to the storage pool logical block address SLBA_a (that is, knowing that the data of the storage pool logical block address SLBA_a is currently stored in the disk logical area Block Address DLBA_a). If the disk logical block address DLBA_a is equal to the disk logical block address of the data unit DU_a, it means that the data stored in the data unit DU_a is valid data. If the disk logical block address DLBA_a is not equal to the disk logical block address of the data unit DU_a, it means that the data of the storage pool logical block address SLBA_a has been updated and stored in other data units, so the data unit DU_a The stored data is no longer valid.

In addition, as mentioned above, in the embodiment of the present invention, for the microprocessor 220, although the aforementioned operation is to rewrite the recalculated protection information P' and Q' to the same disk logical block address DLBA to replace the previous protection information P and Q, but for the memory controller in the corresponding flash memory disk, this operation actually writes the recalculated protection information P' and Q' into a new physical address. In addition, the memory controller can also establish and maintain a corresponding Logical to Physical (L2P) mapping table for the corresponding flash memory, and assign the logical address for the flash memory disk The L2P mapping information (for example, the disk logical block address of the storage units 609~610) is modified to the physical address for actually storing the protection information P' and Q'. With this operation, the previous protection information P and Q can be made invalid.

FIG. 7 shows another implementation example of the repair operation according to an embodiment of the present invention, to illustrate the repair when the storage cells corresponding to the removed flash memory in a stripe are the same bit cells operate. In this example, one band can correspond to 10 storage units of different flash memories, such as the storage units 701~710 shown in the figure, wherein the storage units 701~708 are data units, respectively used to store data D1 ~D8, the storage units 709~710 are co-bit units, respectively used to store the protection information P and Q corresponding to the data D1~D8 stored in this stripe.

Assuming that the storage unit 709 corresponding to the removed flash memory in this stripe is a parity unit, in the repair operation, the microprocessor 220 can select one of the data units from the same stripe, such as but not limited to , select the storage unit 708 closest to the storage unit 709, and recalculate the protection information corresponding to this stripe according to the contents stored in the remaining data units other than the selected data unit in this stripe (for example, according to the The data D1~D7 recalculate the protection information P' and Q' corresponding to this strip, and the microprocessor 220 can write the recalculated protection information into the selected storage unit to replace the original storage unit Content (for example, store the protection information P' in the storage unit 708 to replace the previously stored data D8), and write the recalculated protection information into the same bit unit that has not been removed in this stripe to replace this The content previously stored in the same bit unit (for example, the protected information Q' is stored in the storage unit 710 to replace the previous protected information Q).

In addition, the microprocessor 220 can determine whether the selected storage unit stores valid data. If the data D8 stored in the selected storage unit 708 is invalid, the microprocessor 220 can discard the data D8 directly. If the data D8 stored in the selected storage unit 708 is still valid data, the microprocessor 220 can move (write) the data D8 to a data unit of a current (active) logical aggregation unit (for example, the data unit shown in the figure Shown storage unit 711). After the data units (for example, storage units 711-718) in the current logical aggregation unit are filled, the microprocessor 220 can calculate two corresponding protection information according to the data content stored in the data unit (for example, in the figure P'' and Q'' as shown) are written into corresponding co-bit cells (for example, storage cells 719-720).

In addition, the microprocessor 220 according to a bit of the data unit (for example, the storage unit 711 shown in the figure) used to store the moved valid data (for example, the data D8 shown in the figure) in the active logical aggregation unit address (eg, disk logical block address DLBA) to update mapping information in a mapping table (eg, S2D mapping table) corresponding to a logical address of the valid data (eg, storage pool logical block address SLBA). For example, the S2D mapping information corresponding to the storage pool logical block address SLBA of the valid data in the S2D mapping table is modified to the disk logical block address DLBA of the storage unit 711 .

Similarly, in the embodiment of the present invention, for the microprocessor 220, although the aforementioned operation is to rewrite the recalculated protection information P'' and Q'' to the same disk logical block address DLBA for Replace the previously stored user data and protection information, but for the memory controller in the corresponding flash memory disk, this operation actually writes the recalculated protection information P'' and Q'' respectively A new physical address. The memory controller can further store the L2P mapping information of the logical address (for example, the disk logical block address DLBA of the storage unit 708 and 710) for the flash memory disk in the L2P mapping table maintained internally. It is modified to the physical address of actually storing the protection information P'' and Q''. By doing this, the previously stored user data and protection information can be invalidated.

It should be noted that, in the embodiment of the present invention, regardless of whether the storage unit corresponding to the removed flash memory is a data unit or a parity unit, in the repair operation of one stripe, at most three writes are required operate. For example, in the embodiment shown in FIG. 6, if the data D5 is still valid data, the write operation that needs to be performed in the repair operation includes writing the data D5 into the storage unit 611, and writing the recalculated protection information P' and Q' write operation to memory cells 609 and 610 . On the other hand, when the data D5 is already invalid, only two write operations need to be performed in the repair operation, including the write operation for writing the recalculated protection information P' and Q' into the storage units 609 and 610. Enter operation.

Similarly, in the embodiment shown in FIG. 7, if the data D8 is still valid data, the write operation that needs to be performed in the repair operation includes writing the data D8 into the storage unit 711, and recalculating the protection information P ' and Q' write operation to memory cells 708 and 710 . On the other hand, when the data D8 is invalid data, only two write operations need to be performed in the repair operation, including the write operation for writing the recalculated protection information P' and Q' into the storage units 708 and 710 Enter operation.

In the prior art, in the repair operation of one stripe, at least N write operations need to be performed, where N is the total amount of flash disks or flash memories included in the full flash array storage device. Therefore, when N is a large number, a large number of write operations will cause a large drop in performance of the storage device. Compared with the prior art, in the data processing method of the present invention, only three writing operations need to be performed at most in the repair operation of one strip. In this way, it can effectively solve the problem in the prior art that a large number of writing operations are introduced in order to perform operations related to restoring the original data protection capability, resulting in a significant drop in performance of the storage device.

FIG. 8 shows a detailed flowchart of a data processing method suitable for a full flash array storage device according to an embodiment of the present invention. The data processing method may start from detecting a state in which one of the flash disks is removed, and include the following steps:

Step S802: The microprocessor 220 may select a logical aggregation unit that has written data, and read the original data stored in the logical aggregation unit to obtain the D2S mapping information of the plurality of storage units included in the logical aggregation unit .

Step S804: The microprocessor 220 selects a stripe in the logic aggregation unit. For example, the microprocessor 220 may sequentially select the stripes included in the logical aggregation unit from the first stripe according to the stripe number or index value.

Step S806: The microprocessor 220 can determine whether a storage unit corresponding to the removed flash memory/flash memory disk (or, the removed storage unit for simplified description) in the stripe is a data unit. If not, execute step S808. If yes, execute step S810. It should be noted that the determination of "whether the removed storage unit is a data unit" in step S806 can also be replaced by the determination of "whether the removed storage unit is a same-bit unit". Under this judgment, if yes, step S808 is executed. If not, execute step S810.

Step S808: The microprocessor 220 may select a data unit from the stripe, and determine whether the selected data unit stores valid data. If not, execute step S812. If yes, execute step S814.

Step S810: The microprocessor 220 can determine whether the removed data unit stores valid data. If not, execute step S822. If yes, execute step S826.

Step S812: The microprocessor 220 can read the contents stored in the other data units in the stripe except the selected data unit.

Step S814: The microprocessor 220 can read the contents stored in all the data units in the stripe.

Step S816: The microprocessor 220 can write the content stored in the selected data unit into an active logic aggregation unit.

Step S818: The microprocessor 220 may correspondingly update the S2D mapping table maintained by the microprocessor 220 for the flash memory array 240 according to the write operation in step S816. Update operation as described in Figure 7.

Step S820: The microprocessor 220 may recalculate the protection information corresponding to the stripe according to the contents stored in the data units except the selected data unit in the stripe, and store the recalculated protection information. As mentioned above, when the protection information corresponding to this stripe contains more than one piece of protection information, the protection information can be written into the disk logical block address DLBA of the selected data unit in this stripe and the same bits that have not been removed The disk logical block address DLBA of the unit is used to replace the previously stored content. It is worth noting that the "read content" in the text "recalculate and store the protection information corresponding to this strip according to the read content" in step S820 in the figure refers to the information read in step S812 except the selected The content stored in the other data units other than the data unit, or the stored content in the other data units read in step S814 except the selected data unit.

Step S822: The microprocessor 220 can read the contents stored in the remaining data units in the stripe except the removed storage unit.

Step S824: The microprocessor 220 may recalculate the protection information corresponding to the stripe according to the contents stored in the remaining data units in the stripe except the removed storage unit, and store the recalculated protection information. As mentioned above, when the protection information corresponding to the stripe includes more than one piece of protection information, the protection information can be respectively written into the disk logical block address DLBA of each co-bit unit to replace the previously stored protection information. It is worth noting that the "read content" in the text "recalculate and store the protection information corresponding to this band based on the read content" in step S824 in the figure refers to the unique content in the band obtained in step S822 The content stored in the remaining data units except the removed data unit, or the stored content in the remaining data units in the stripe read in step S826 except the removed data unit.

Step S826: The microprocessor 220 can read the contents stored in the unremoved data units and co-bit units in the stripe.

Step S828: The microprocessor 220 deduces the valid data stored in the removed storage unit according to the read content, and writes the deduced valid data into an active logic aggregation unit.

Step S830: The microprocessor 220 may correspondingly update the S2D mapping table maintained by the microprocessor 220 for the flash memory array 240 according to the write operation in step S828. Update operation as described in Figure 6.

Step S832: The microprocessor 220 may determine whether the currently processed slice is the last slice in the LAU. If yes, it means that the repair operation of all stripes of the currently selected LAU has been completed, and the process goes to step S834. If not, go back to step S804 and select the next unprocessed slice.

Step S834: The microprocessor 220 can determine whether the currently processed LAU is the last LAU whose data has been written into the LAU. If yes, it means that the repair operations corresponding to all LAUs affected by the disk removal have been completed. If not, go back to step S802 and select the next unprocessed LAU.

To sum up, in the data processing method of the present invention, only three writing operations need to be performed at most during the repair operation of each stripe. With the improvement of the present invention, the write operation introduced by performing the repair operation has no relation to the flash disk or the total amount of flash memory included in the all-flash array storage device. In this way, the original data protection capability can be restored very efficiently, and it can effectively solve the problem of the performance of the storage device caused by the introduction of a large number of write operations in order to perform operations related to restoring the original data protection capability in the prior art. The problem fell sharply. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100,200: Full Flash Array Storage 110-1, 110-n, 110-N, Drive_1, Drive_N: Flash memory disk 200: full flash array storage device 210: Full flash array controller 220: Microprocessor 230: memory device 240: Flash memory array 310: volume management module 320:Flash array control module 601,602,603,604,605,606,607,608,609,610,611,612,613,614,615,616,617,618,619,620,701,702,703,704,705,706,707,708,709,710,711,712,713,714,715,716,717,718,719,720:儲存單元 D1~D32, Dh: data DLBA: Disk Logical Block Address P,P’,P’’,P1,P2,P3,P4,PM1,PM2,Q,Q’,Q’’,Q1,Q2,Q3,Q4,QM1,QM2: protection information User_Write: write command LAU: logical aggregation unit LBA1~LBA16: logical block address SLBA: storage pool logical block address Stripe_1,Stripe_K: Stripe VVLBA: Virtual Volume Logical Block Address

FIG. 1 is a schematic view showing the appearance of a full flash array storage device according to an embodiment of the present invention. FIG. 2 is a block diagram showing an example of an all-flash array storage device according to an embodiment of the present invention. FIG. 3 shows a software architecture for managing a flash memory array according to an embodiment of the present invention. FIG. 4 is a schematic diagram of a logical aggregation unit according to an embodiment of the present invention. FIG. 5 is a flowchart showing a data processing method of a full flash array storage device according to an embodiment of the present invention. FIG. 6 shows an example of performing a repair operation according to an embodiment of the present invention. FIG. 7 shows another example of performing repair operations according to an embodiment of the present invention. FIG. 8 shows a detailed flowchart of a data processing method suitable for a full flash array storage device according to an embodiment of the present invention.

200: full flash array storage device

210: Full flash array controller

220: Microprocessor

230: memory device

240: Flash memory array

Claims (15)

A full flash array storage device, comprising: A flash memory array, wherein the flash memory array includes a plurality of flash memories, and the flash memories correspond to a plurality of logic aggregation units, each logic aggregation unit includes a plurality of stripes, and each stripe includes a plurality of storage units comprising a plurality of data units for storing data and at least one homogeneous unit for storing protected information; and a microprocessor, coupled to the flash memory array, for detecting the status of one of the flash memories, wherein when the microprocessor detects the operating status of one of the flash memories In case of abnormality, perform a repair operation on the stripes contained in one or more logical aggregation units of the written data in sequence, and: In the repair operation corresponding to a stripe, the microprocessor restores a piece of stored data on the stripe or recalculates a piece of protection information corresponding to the stripe according to the content stored in at least a part of the data units on the stripe; as well as When the repair operation recalculates the protection information, the microprocessor writes the stored data to the stripe, and when the repair operation restores the stored data on the stripe, the microprocessor writes the stored data Data is written to the other of the stripes. The full flash array storage device as described in item 1 of the scope of the patent application, wherein in the repair operation, when the microprocessor judges that one of the storage units of the flash memory corresponding to the abnormal operating state in the stripe is the same When a bit unit is selected, the microprocessor selects a data unit from the stripe, recalculates the protection information corresponding to the stripe according to the contents stored in other data units in the stripe except the selected data unit, and storing the recalculated protection information in the selected data unit in the stripe, thereby replacing the stored content of the selected data unit. The full flash array storage device as described in item 2 of the scope of the patent application, wherein in the repair operation, the microprocessor further judges whether the selected data unit stores valid data, and when the selected data unit stores valid data data, the microprocessor reads the valid data stored in the selected data unit to write the valid data into a data unit of an active logical aggregation unit, and according to the current logical aggregation unit An address of the data unit updates mapping information corresponding to a logical address of the valid data in a mapping table. The full-flash array storage device as described in item 1 of the patent scope of the application, wherein in the repair operation, when the microprocessor judges that one of the storage units of the flash memory corresponding to the abnormal operating state in the stripe is a data unit, the microprocessor recalculates the protection information corresponding to the stripe according to the stored content in the stripe corresponding to the storage unit of the flash memory in the abnormal operating state and other data units, and storing the recalculated protection information in the peer unit of the stripe, thereby replacing the content stored in the peer unit. The full flash array storage device as described in item 4 of the scope of the patent application, wherein in the repair operation, the microprocessor further judges whether the storage unit corresponding to the flash memory in the stripe is stored valid data, and when the storage unit corresponding to the abnormal operation state of the flash memory stores valid data, the microprocessor reads the contents stored in the remaining storage units in the stripe, and deduces the corresponding The valid data stored in the storage unit of the flash memory in an abnormal operating state, write the deduced valid data into a data unit of an active logical aggregation unit, and according to the current logical aggregation unit The address of the data unit updates the mapping information corresponding to the logical address of the valid data in a mapping table. A data processing method, suitable for an all-flash array storage device, the all-flash array storage device includes a flash memory array, the flash memory array includes a plurality of flash memories, and the flash memories correspond to a plurality of A logical aggregation unit, each logical aggregation unit includes a plurality of stripes, each stripe includes a plurality of storage units, and the storage units include a plurality of data units for storing data and at least one homologous unit for storing protection information, the Data processing methods include: When detecting that the operating state of one of the flash memories is abnormal, sequentially perform a repair operation on the stripes that have been written into one or more logical aggregation units; In the repair operation corresponding to a stripe, the microprocessor restores a piece of stored data on the stripe or recalculates a piece of protection information corresponding to the stripe according to the content stored in at least a part of the data units on the stripe; as well as When the repair operation recalculates the protection information, the microprocessor writes the stored data to the stripe, and when the repair operation restores the stored data on the stripe, the microprocessor writes the stored data Data is written to the other of the stripes. For the data processing method described in item 6 of the scope of the patent application, the steps of performing the restoration operation further include: judging whether a storage unit in the stripe corresponding to an abnormal operation state is the same bit unit; and When the storage unit of the flash memory corresponding to the abnormal operating state in the stripe is the same bit unit, select a data unit from the stripe, according to the remaining data in the stripe other than the selected data unit The content stored in the unit recalculates the protection information corresponding to the strip, and stores the recalculated protection information in the selected data unit, thereby replacing the stored content of the selected data unit. For the data processing method described in item 7 of the scope of the patent application, the steps of performing the restoration operation further include: judging whether the selected data unit stores valid data; and When the selected data unit stores valid data, read the valid data stored in the selected data unit, write the valid data into a data unit of an active logic aggregation unit, and according to the current logic The address of the data unit of the aggregation unit updates the mapping information corresponding to the logical address of the valid data in a mapping table. For the data processing method described in item 6 of the scope of the patent application, the steps of performing the restoration operation further include: judging whether a storage unit of the flash memory corresponding to an abnormal operating state in the stripe is a data unit; and When the storage unit of the flash memory corresponding to the abnormal operating state in the stripe is a data unit, according to the remaining data in the stripe other than the storage unit of the flash memory corresponding to the abnormal operating state The content stored in the unit recalculates the protection information corresponding to the stripe, and stores the recalculated protection information in the same unit of the stripe to replace the content stored in the same unit. For the data processing method described in item 9 of the scope of the patent application, the steps of performing the restoration operation further include: judging whether valid data is stored in the storage unit of the flash memory corresponding to the abnormal operating state in the stripe; and When valid data is stored in the storage unit of the flash memory corresponding to the abnormal operating state, read the contents stored in the remaining storage units in the stripe, and deduce the flash corresponding to the abnormal operating state according to the read content The valid data stored in the storage unit of the flash memory, write the deduced valid data into a data unit of an active logical aggregation unit, and according to an address of the data unit of the active logical aggregation unit Updating mapping information corresponding to a logical address of the valid data in a mapping table. A full flash array controller comprising: a memory device; and a microprocessor coupled to the memory device and a flash memory array for managing the flash memory array according to data stored in the memory device, wherein the flash memory array includes a plurality of logic aggregates Each logical aggregation unit includes a plurality of stripes, each stripe includes a plurality of storage units, and the storage units include a plurality of data units for storing data and at least one homologous unit for storing protection information, and: When the microprocessor detects that the operating state of one of the flash memories is abnormal, sequentially perform a repair operation on the stripes included in one or more logical aggregation units that have written data ; In the repair operation corresponding to a stripe, the microprocessor restores a piece of stored data on the stripe or recalculates a piece of protection information corresponding to the stripe according to the content stored in at least a part of the data units on the stripe; as well as When the repair operation recalculates the protection information, the microprocessor writes the stored data to the stripe, and when the repair operation restores the stored data on the stripe, the microprocessor writes the stored data Data is written to the other of the stripes. The all-flash array controller as described in item 11 of the scope of the patent application, wherein in the repair operation, when the microprocessor judges that one of the storage units of the flash memory corresponding to the abnormal operating state in the stripe is the same When a bit unit is selected, the microprocessor selects a data unit from the stripe, recalculates the protection information corresponding to the stripe according to the contents stored in other data units in the stripe except the selected data unit, and storing the protection information corresponding to the recalculated strip in the selected data unit, thereby replacing the content stored in the selected data unit. The full flash array controller as described in item 12 of the scope of the patent application, wherein in the repair operation, the microprocessor further judges whether the selected data unit stores valid data, and when the selected data unit stores valid data data, the microprocessor reads the valid data stored in the selected data unit to write the valid data into a data unit of an active logical aggregation unit, and according to the current logical aggregation unit An address of the data unit updates mapping information corresponding to a logical address of the valid data in a mapping table. The all-flash array controller as described in item 11 of the scope of the patent application, wherein in the repair operation, when the microprocessor judges that one of the storage units of the flash memory corresponding to the abnormal operation state in the stripe is a data unit, the microprocessor recalculates the protection information corresponding to the stripe according to the contents stored in the other data units in the stripe corresponding to the abnormal operation state of the flash memory except the storage unit, and storing the recalculated protection information in the peer unit of the stripe, thereby replacing the content stored in the peer unit. In the all-flash array controller described in item 14 of the scope of the patent application, in the repair operation, the microprocessor further judges whether the storage unit of the flash memory corresponding to the abnormal operating state in the stripe is stored valid data, and when the storage unit corresponding to the abnormal operation state of the flash memory stores valid data, the microprocessor reads the contents stored in the remaining storage units in the stripe, and deduces the corresponding The effective data stored in the storage unit of the flash memory in an abnormal operating state, writing the deduced effective data into a data unit of an active logical aggregation unit, and according to the active logical aggregation unit The address of the data unit updates the mapping information corresponding to the logical address of the valid data in a mapping table.

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