TWI780967B - Memory device and memory operation method - Google Patents

Abstract

A memory operation method, including the following steps: receiving a write command to find a memory page corresponding to the write command, wherein the memory page includes multiple memory cells; providing a first excitation voltage to the memory cells to maintain a first part of the memory cells at a first threshold voltage range, and adjust a second part of the memory cells to a second threshold voltage range; and providing a second excitation voltage to the second part of the memory cells to adjust a third part of the second part of the memory cells to a third threshold voltage range so that a threshold voltage state of the memory page corresponds to the write command, wherein the first threshold voltage range, the second threshold voltage range, and the third threshold voltage range are different from each other.

Description

Memory device and memory operation method

The present disclosure relates to a memory device and a method of operating the memory, in particular to the technology of programming memory pages according to write commands.

As computers become faster and faster, the requirements for memory speed and stability are getting higher and higher. At the same time, the requirement for data security has gradually become one of the considerations of consumers. In the case of many different market demands, how to improve the memory programming method so that it can not only read and write data efficiently, but also take into account the durability and safety of the memory has become a major issue at present.

The disclosure relates to a memory operation method, comprising the following steps: receiving a write command to find a memory page corresponding to the write command, wherein the memory page includes a plurality of memory cells; applying a first excitation voltage to the memory cell, to maintain the first part of the memory cells in the first threshold voltage range, and adjust the second part of the memory cells to the second threshold voltage range; and apply the The second excitation voltage is used to adjust the third part of the second part of the memory cells to the third threshold voltage range, and the threshold voltage state in the memory page corresponds to the write command, wherein the first valve The value voltage range, the second threshold voltage range and the third threshold voltage range are different from each other.

The disclosure also relates to a memory device including a plurality of memory pages and a processor. The memory pages are classified into a primary memory layer and a secondary memory layer. The priority memory layer includes a plurality of memory groups. Any one of the memory groups consists of at least two adjacent memory page groups. The processor is electrically connected to the memory pages and used for receiving write commands. When the processor performs a write program on one memory page of any one of the memory groups according to the write command, another memory page of any one of the memory groups will be cleared according to the write program. The processor is also used to selectively transfer the data in the memory group to the memory page in the secondary memory layer.

Accordingly, when the processor writes a program to a memory unit, the data stored in the adjacent memory unit can be cleared at the same time, so in addition to improving the space utilization rate of the memory device, the service life can also be improved, and Keep your data safe.

Several embodiments of the present invention will be disclosed in the following figures. For the sake of clarity, many practical details will be described together in the following description. It should be understood, however, that these practical details should not be used to limit the invention. That is, in some embodiments of the present invention, these practical details are unnecessary. In addition, for the sake of simplifying the drawings, some well-known structures and components will be shown in a simple and schematic manner in the drawings.

Herein, when an element is referred to as "connected" or "coupled", it may mean "electrically connected" or "electrically coupled". "Connected" or "coupled" may also be used to indicate that two or more elements cooperate or interact with each other. In addition, although terms such as “first”, “second”, . Unless clearly indicated by the context, the terms do not imply any particular order or sequence, nor are they intended to be limiting of the invention.

The present disclosure relates to a memory device and a memory operation method. As shown in FIG. 1 , in one embodiment, the memory device MR includes a processor 100 and at least one memory block MB (block). The processor 100 is configured to receive a read command, a write command, or a clear command, so as to execute a corresponding read process, write process, and clear process.

In one embodiment, the memory block MB includes a plurality of memory pages P. Each memory page P contains a plurality of memory cells (memory cells). The memory cell can be implemented by a floating gate transistor, and the memory cell will have different threshold voltages according to the amount of charge in the floating gate. Taking a single-level cell (SLC) as an example, the magnitude of the threshold voltage can be used to record one bit of data, such as a digital command of 0 or 1.

In one embodiment, the memory page P can be a kind of multi-level memory cell (multi-level cell, MLC). Through the relative magnitude of the threshold voltage and multiple judging voltage values, each memory cell can be used to record two-bit data (such as 00, 01, 10, 11). In other words, the processor 100 can compare the threshold voltage of each memory cell with a plurality of judging voltage values to confirm the bit data recorded by each memory cell. For example, the data recorded by the memory unit whose threshold voltage is less than the judgment voltage value V1 is “11”, the data recorded by the memory unit whose threshold voltage is greater than the judgment voltage value V1 but less than the judgment voltage value V2 is “10”, and the data recorded by the memory unit whose threshold voltage is greater than the judgment voltage value V2 is “10”. The data recorded by the memory unit with the judgment voltage value V2 but less than the judgment voltage value V3 is “00”, and the data recorded by the memory unit whose threshold voltage is greater than the judgment voltage value V3 is “01”. The aforementioned "determining voltages V1-V3" are used to distinguish memory units with different threshold voltages, so the actual values of the judging voltages V1-V3 can be adjusted according to the actual parameters of the memory device MR. However, the present disclosure is not limited thereto. In other embodiments, the memory page P may also be a triple-level memory (Triple-Level Cell, TLC) for storing three-bit data.

In addition, the memory paging P can be realized by 2D NAND flash memory or 3D NAND flash memory, since those skilled in the art can understand the structure and manufacturing process of memory paging, so no further details are given here.

When the processor 100 reads and writes data, its "sequential access" operation speed will be much higher than the "random access" operation speed. In other words, the speed at which the processor 100 writes data into multiple adjacent memory pages P will be much faster than writing data into multiple memory pages P at random locations. In order to achieve "sequential processing" to improve efficiency, in one embodiment, the processor 100 processes a large amount of data according to various database programming techniques, such as: LSM (Log Structured-Merge Tree) technique. LSM technology can be divided into multiple applications, including LevelDB, RocksDB, Apache AsterixDB, etc.

Here, the LSM technique is briefly described as follows. Please refer to FIG. 1 , the processor 100 classifies the memory pages P into a tree structure (hereinafter referred to as LSM-tree) composed of multiple levels L1, L2˜Ln (levels). The levels L1-Ln are arranged in sequence, and the lower the level, the more memory pages P it contains. When receiving the write command, the processor 100 will preferentially write data into the upper layer. When data has been written in the same level, the processor 100 will compact the data in the same level and transfer them to the next level. For example: transfer the data of the first level L1 to the second level L2.

The LSM technology enables the processor 100 to read data in a "sequential processing" manner, but the transfer of data will cause a "write amplification issue" problem. Too much old data will not only affect data management, but also create doubts about data security.

FIG. 2 is a schematic diagram of two adjacent memory pages P1 and P2 among the plurality of memory pages P in FIG. 1 . As mentioned above, each memory page P1, P2 includes a plurality of memory cells Pc. In each memory page P1/P2, the number of memory cells Pc corresponding to different threshold voltages varies according to the written data. It should be particularly mentioned here that the memory cell Pc shown in FIG. 2 is only a schematic diagram, and does not refer to the actual structure or location. Since those skilled in the art can understand the structures of MLC and TLC, details will not be described here.

In this embodiment, the processor 100 sets at least two adjacent memory pages (eg, P1 and P2 ) as a memory group Px. In other words, all memory pages P are classified into multiple memory groups Px, and each memory group is used to record the same data. The processor's management of memory banks will be described in subsequent paragraphs.

Here, the method for the processor 100 to write data to a single memory bank Px will be described first. Please refer to Figures 1 to 4F, and Figure 3 is the flow chart of the writing program. 4A-4F are schematic diagrams showing changes in the threshold voltage state of the memory page P. FIG.

As shown in Figures 2 and 4A, in step S301, when the processor 100 receives a write command, the processor 100 will find (or select) a write command located in the first level L1 according to the LSM technology. Enter the memory page P1 of the memory group Px of the data. In some embodiments, the threshold voltages of all memory cells Pc in a memory page P1 that has not been written with data (or data has been erased) are lower than the judgment voltage value V1, but the disclosure is not limited thereto.

For the convenience of description, the multiple memory cells Pc having "close threshold voltages (ie, belonging to the same threshold voltage range)" in the same memory page are referred to as "parts". Taking Figure 2 as an example, the memory cell Pc can be roughly divided into four parts according to the threshold voltage, and each part can be used to represent different bit data "11", "10", "00" and "01". Taking FIG. 4A as an example, the "first part" is used to refer to a plurality of memory cells Pc whose threshold voltage is lower than the judgment voltage value V1.

It should be specially mentioned here that the threshold voltage corresponding to each of the two-bit data "11", "10", "00" and "01" is not limited to a fixed value, but can be a " "Threshold voltage range" (that is, different ranges formed by judging the voltage values V1-V3). As shown in Figure 2, the four threshold voltage ranges divided by the judging voltage values V1-V3 respectively correspond to the four parts of the memory cell Pc to represent the four bit data "11", "10", "00" and "01". In addition, in some embodiments, the threshold voltage ranges corresponding to the bit data "11", "10", "00" and "01" do not overlap with each other.

As shown in Figures 2 and 4A-4B, in step S302, the processor 100 applies a first excitation voltage (such as: 10-15 volts) to all the memory cells Pc in the memory page P1, so that the first part 410 The memory cells Pc in the second portion 420 are maintained in the first threshold voltage range, and the memory cells in the second portion 420 are adjusted from the first threshold voltage range to the second threshold voltage range corresponding to bit data "10" (ie, ). Wherein, the second threshold voltage range has a larger threshold voltage than the first threshold voltage range. In addition, the voltage change of the memory page P in Figures 4B-4E is in the programming process, that is, the memory cell Pc has not been programmed yet. Therefore, the aforementioned "the second part 420 corresponds to the second threshold voltage range" It means that most of the second part 420 will fall into the second threshold voltage range, but it does not limit the second part 420 to completely fall into the second threshold voltage range during this process.

Specifically, the memory unit Pc has a control gate, and the processor 100 applies a "one-shot power supply (one-shot)" excitation voltage (such as: the aforementioned first excitation voltage) to the control gate to adjust or and controlling the threshold voltage state in the memory unit Pc. The operating parameters of the excitation voltage are not limited to the above-mentioned values. The principle is similar to programming the memory cell Pc (program operation), but the purpose of the "excitation voltage" here is different from the simple "programming" (will be discussed later paragraph details). Since those skilled in the art can understand the way of applying the excitation voltage, it will not be repeated here.

Due to the imperfection caused by process factors, the activation degree of each memory cell Pc will not be exactly the same. "Activity" is defined as the degree of electronic perturbation in the memory cell. Because the activity of each memory cell Pc is different, when the processor 100 applies the first excitation voltage, the response of each memory cell Pc is also different. As shown in Figures 4A-4B, the memory cell Pc of the second part 420 is more active than the memory cell Pc of the first part 410, so it will be adjusted to correspond to the second part under the influence of the first excitation voltage. Threshold voltage range (bit data "10"). The operating principles of the remaining excitation voltages are also the same, so they will not be repeated in the following text.

As shown in Figures 2 and 4B-4C, in step S303, the processor 100 applies a second excitation voltage to the memory cells Pc in the second part 420, so that the part of the memory cells Pc in the second part 420 (ie, the third part 430 ) is adjusted to correspond to the third threshold voltage range (bit data "00"). The voltage magnitude and/or pulse wave of the second excitation voltage are designed so that the threshold voltages of other memory cells Pc in the second portion 420 do not increase significantly, but remain within the second threshold voltage range. In other words, the memory cells Pc of the third part 430 are only a part of the original memory cells Pc of the second part 420 , not all of them. After step 403 , only the original part 421 of the memory cell Pc corresponding to the second threshold voltage range (bit data "10") remains, and the part 430 of the memory cell Pc is more active than the part 421 . The third threshold voltage range has a larger threshold voltage than the second threshold voltage range.

In step S304, the processor 100 further adjusts the threshold voltages of relatively inactive memory cells Pc among all the memory cells Pc, so that all the memory cells Pc in the memory page P1 can be respectively distributed in multiple threshold voltage ranges Medium (for example: the first threshold voltage range, the second threshold voltage range and the third threshold voltage range). The aforementioned "less active memory cells Pc" are a part of the memory cells Pc whose degree of electronic disturbance is relatively lower than that of other memory cells Pc, or the valves are not changed with the first excitation voltage and the second excitation voltage in the aforementioned steps S301-303. Value voltage memory cell Pc. The adjustment details will be explained in the following paragraphs. In other words, the threshold voltage of the aforementioned "less active memory cell Pc" does not change the original threshold voltage range due to the influence of the first excitation voltage or the second excitation voltage (for example: the first threshold voltage range , bit data "11").

In some embodiments, the processor 100 distributes all the memory cells Pc in the first threshold voltage range, the second threshold voltage range, the third threshold voltage range and the fourth threshold voltage range. The fourth threshold voltage range corresponds to the bit data “01”, and the fourth threshold voltage range has a larger threshold voltage than the third threshold voltage range.

The waveform diagrams shown in FIGS. 4A-4F are only for illustration. In practice, when the processor 100 distributes memory cells Pc in various threshold voltage ranges, the number of memory cells Pc corresponding to each threshold voltage range will decrease. Depends on the write command. In other words, the overall threshold voltage state of the memory page P will correspond to the write command.

The method of adjusting the threshold voltage of the relatively inactive memory cell Pc (herein referred to as “low active cell”) among all the memory cells Pc is described as follows. The processor 100 can apply the third activation voltage to all or part of the memory cells Pc in the memory page P1, so that the threshold voltage of the low active cells can be moved to the third threshold voltage range (bit data "00") ) or the fourth threshold voltage range (bit data "01"). The excitation voltage (for example: the third excitation voltage) of the low active unit is adjusted to be greater than the first excitation voltage and the second excitation voltage.

Specifically, as shown in Figures 4C and 4D, when the processor 100 has passed the first excitation voltage and the second excitation voltage, the more active memory cells Pc are distributed to correspond to the second threshold voltage range (bit data After "10") and the third threshold voltage range (bit data "00"), the processor 100 may further apply a third excitation to the memory cell Pc having the first threshold voltage range (bit data "11") Voltage. At this time, the memory cell Pc (that is, the part in Figure 4C) that originally had the first threshold voltage range (bit data "11") and originally had the second threshold voltage range (bit data "10") 410 and part 421 ) of the low-active cells (ie, part 440 ) are affected by the third excitation voltage, causing their voltage to rise. After excitation, the memory cell Pc with the first threshold voltage range (bit data "11") and the second threshold voltage range (bit data "10") changes as shown in parts 411 and 422 of FIG. 4D Show.

Next, as shown in Figures 4D and 4E, the processor 100 can further apply a fourth excitation voltage to these low-active cells (part 440 of Figure 4D), so that the voltages of relatively less active cells among these low-active cells As the fourth activation voltage rises, the portions 450, 460 shown in FIG. 4E are formed, wherein the portion 460 of the memory cell Pc is more active than the portion 450. Likewise, the fourth excitation voltage is greater than the first excitation voltage and the second excitation voltage.

Continuing from the above, since the third excitation voltage/fourth excitation voltage will also affect the voltage of the active cells (such as: parts 411, 422, 430) when adjusting the voltage of the low active cells, the threshold voltage of these active cells Therefore, the threshold voltage state of the memory page P1 can be fine-tuned by applying excitation voltages to different memory cells Pc multiple times.

For example, if the part 422 of the memory cell Pc does not completely correspond to the second threshold voltage range, an activation voltage can be applied to the right part (such as: part 430, 450), so that the part 422 goes toward Adjust right. Similarly, when the third excitation voltage is applied to the memory cell Pc to form the portion 422, since the threshold voltage of the subsequent portion 422 will also be affected by the fourth excitation voltage, the fourth excitation voltage can be estimated in advance. Influenced by , the voltage value of the adjustment part 422 when the third excitation voltage is formed.

The final adjusted threshold voltage state is shown in Figure 4F. The memory page P1 will contain memory cells Pc with different threshold voltage ranges, and the number of memory cells Pc in each part will be based on the actual data of the write command. rather different.

Please refer to FIG. 2 , while the memory page P1 is being written according to the above steps, since the memory page P2 is adjacent to the memory page P1, when the processor 100 applies an excitation voltage to the memory page P1 (for example: the first excitation voltage to the fourth excitation voltage), the excitation voltage will also affect the adjacent memory page P2, so that the threshold voltage states of the plurality of memory cells Pc in the memory page P2 will be affected. Such a change can be regarded as destroying the data originally written in the memory page P2, like performing a clearing operation on the data in the memory page P2. As mentioned above, the memory page P1 and the memory page P2 belong to the same memory group Px. In other words, different memory pages in the same memory group Px record data (value) written at different times. In some embodiments, different memory pages P in the same memory group Px respectively record a piece of data at different time points The latest and previous versions of . Therefore, when the processor 100 writes new data into the memory page P1, the old data originally stored in the memory page P2 will be destroyed and cleared due to the influence of the excitation voltage. Accordingly, it can be ensured that too much historical data will not be retained in the memory device MR, thereby ensuring the data security of the user.

The write procedure shown in the foregoing embodiments can utilize the disturbance characteristics of the memory unit Pc to destroy the data of the adjacent memory unit Pc while performing the write procedure on one memory unit Pc. In other words, the processor 100 does not need to additionally clear the adjacent memory cells Pc or the entire memory block MB, thus ensuring data security and improving service life without affecting operating efficiency.

Please refer to FIG. 1 , which describes the overall data management method of the memory device MR. In some embodiments, in addition to being classified into multiple levels L1-Ln, these memory pages P (or levels L1-Ln) can be further classified into the priority memory layer LA or the secondary memory layer LB. . For example, the first level L1 and the second level L2 belong to the priority memory layer LA, and the nth level Ln belongs to the secondary memory layer LB. The number of layers included in the priority memory layer can be set or adjusted according to requirements (for example: the first to fifth layers belong to the priority memory layer LA), and are not limited to those shown in Figure 1.

Continuing from the above, in the priority memory layer LA, adjacent memory pages P are set as the same memory group Px. As shown in FIG. 2, two adjacent memory pages P1 and P2 belong to the same memory group Px, or four adjacent memory pages P belong to the same memory group Px. The memory groups Px in the priority memory layer LA are arranged in the levels L1˜Ln according to the “time for writing program”.

The processor 100 is electrically connected to the memory page P, and regards the primary memory layer LA as a block for storing hot data, and the secondary memory layer LB as a block for storing cold data. "Hot data" refers to data that is read and written frequently, and "cold data" refers to data that is read and written relatively infrequently. When receiving a write command, the processor 100 will regard the data as hot data, and write it into a memory page (such as: P1). At this time, another adjacent memory page (for example: P2) in the memory group Px will be cleared according to the excitation voltage in the writing process.

The processor 100 is also configured to selectively transfer the data in the memory group Px to the memory pages P in the secondary memory layer LB. The timing of the transfer may be when all the memory groups Px of the same level have completed the writing process. The processor 100 is used to transfer the data in the same level to the next level, or transfer the data in the same level from the primary memory layer LA to the secondary memory layer LB (ie, the aforementioned LSM technology).

For example, if the memory device MR sets "the fifth level and below" as the secondary memory level, then when the memory groups Px in the fourth level are all written with data and ready to be transferred to the fifth level , the processor 100 marks the data in the fourth level as "cold data".

The secondary memory layer LB does not need to set a plurality of adjacent memory pages P as a set of memory groups. In other words, only one memory page P is used in the secondary memory layer LB to store a single piece of data, and there is no need to store the historical version of the data, thus saving storage space and avoiding the security problem of data leakage.

As above, when the processor 100 wants to transfer the data of a memory page P in the memory group Px to the secondary memory layer LB, the processor 100 will transfer the data of the memory page P to the memory in the secondary memory layer LB. The page P is written into the program (such as copying), and at the same time, the processor 100 will also clear all the memory pages in the memory group Px (such as: P1, P2 in Figure 2), so as to delete the data stored in the memory group Px .

On the other hand, when the processor 100 receives a new write command, and the target of the write command corresponds to one of the memory pages P of the secondary memory layer LB, the processor 100 will transfer this data from the "cold Data" was relabeled as "Hot Data". At this point, the processor 100 will select one of the memory groups Px from the priority memory layer LA, and perform the writing process on a memory page in the memory group Px. After completing the writing process, the processor 100 clears the memory page P in the secondary memory layer LB corresponding to the writing command, so as to delete the stored data.

In some embodiments, when the memory device MR receives the write command, it will simultaneously store the "address (adress)" and "data (value)". The address is used to record the actual location of the memory unit Pc, and the data is the actual stored content. Since the amount of data is much larger than the address, the storage of the address does not cause obvious problems or burdens to the memory management. In other words, the processor 100 can store and manage "data" according to the method of the above-mentioned embodiments, but the method of storing "address" can use the existing traditional technology.

In some embodiments, the memory device MR also has a management with wear leveling technique. Please refer to Figures 1 and 5 together, wherein Figure 5 is a schematic diagram of a memory block in a memory device according to the disclosure. The memory device MR includes a plurality of memory blocks MB1, MB2. Each memory block MB1, MB2 includes a plurality of memory pages P, and respectively corresponds to the primary memory layer LA or the secondary memory layer LB. When the data needs to be completely cleared, the processor 100 can execute a clearing program on the memory blocks MB1 and MB2, so as to clear all the data on one memory block at the same time. Since those skilled in the art can understand the operation of the clearing program, it will not be repeated here.

In some embodiments, the memory device MR further includes a priority layer management table CP1 and a secondary layer management table CP2. The priority layer management table CP1 respectively includes a plurality of counting fields Ca~Cd, and each counting field Ca~Cd corresponds to a memory block in the priority memory layer LA respectively, and is used to record that the memory block has been cleared. times. Similarly, the secondary layer management table CP2 includes a plurality of counting fields Ce~Ch, each counting field Ce~Ch respectively corresponds to a memory block in the secondary memory layer LB, and is used to record the memory block being The number of times the cleanup procedure has been executed. For example, the count field Ca is used to record the number of times the memory block MB1 has been cleared (for example: 5100 times), and the count field Ce is used to record the number of times the memory block MB2 has been cleared (for example: 300 times).

The counting fields Ca to Cf in the priority layer management table CP1 and the secondary layer management table CP2 are arranged according to the "number of clearing procedures". For example, the value recorded in the counting field Ca is the largest in the priority layer management table CP1, and the value recorded in the counting field Cd is the smallest in the priority layer management table CP1. Similarly, the value recorded in the counting field Ce is the largest in the secondary layer management table CP2, and the value recorded in the counting field Cf is the smallest in the secondary layer management table CP2.

Continuing from the above, the processor 100 is configured to execute the clearing procedure according to the priority layer management table CP1 and the secondary layer management table CP2. For example, the processor 100 will preferentially perform the clearing procedure on memory blocks that have been cleared less frequently, so as to ensure that the clearing times of each memory block will not vary too much.

In addition, the processor 100 is also used to selectively re-associate any one of these memory blocks to the priority memory layer LA according to the count fields Ca˜Cf in the priority layer management table CP1 and the secondary layer management table CP2 or the secondary memory layer LB to effectively manage the service life of the memory device MR. In some embodiments, when the value of any count field Ca in the priority layer management table CP1 is greater than a threshold value (eg: 5000), the processor 100 will change the count field Ca to the secondary layer In the management table CP2, at the same time, the counting field with the lowest value in the secondary layer management table CP2 (for example: the counting field Cf) is changed to be set in the priority layer management table CP1. Taking Fig. 5 as an example, the counting field Ca is moved to the secondary layer management table CP2, and the counting field Cf is moved to the priority layer management table CP1. Accordingly, the problem of premature damage caused by partial memory blocks being cleared many times can be avoided.

By managing memory blocks according to the priority layer management table CP1 and the secondary layer management table CP2, the space utilization (enhance space utilization) of the memory device MR can be improved, and the wear-out of the memory unit Pc can be improved. And durability issues (improve endurance).

Various components, method steps or technical features in the above-mentioned embodiments can be combined with each other, and are not limited by the order of description in words or presentation in drawings in the present disclosure.

Although the content of this disclosure has been disclosed above in terms of implementation, it is not intended to limit the content of this disclosure. Anyone who is skilled in this art can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, this disclosure The scope of protection of the content shall be defined by the scope of the attached patent application.

MR: memory device MB: memory block MB1-MB2: memory blocks L1-Ln: Stratum LA: priority memory layer LB: secondary memory layer Px: memory group Pc: memory unit P: memory paging P1-P2: memory paging V1-V4: threshold voltage range 100: Processor 410: part 411: part 420: part 421: part 422: part 430: part 440: part 450: part 460: part CP1: priority layer management table CP2: Secondary layer management table Ca-Cf: count field S301-S304: Steps

FIG. 1 is a schematic diagram of a memory device according to some embodiments of the present disclosure. FIG. 2 is a schematic diagram of two adjacent memory pages according to some embodiments of the present disclosure. FIG. 3 is a flowchart of a memory operation method according to some embodiments of the present disclosure. FIGS. 4A-4F are schematic diagrams showing changes in threshold voltage states according to some embodiments of the present disclosure. FIG. 5 is a schematic diagram of a management method of memory blocks according to some embodiments of the present disclosure.

Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

S301-S304: Steps

Claims (10)

A memory manipulation method, comprising: receiving a write command to find a memory page corresponding to the write command, wherein the memory page includes a plurality of memory cells; applying a first excitation voltage to the memory cells to maintain a first portion of the memory cells within a first threshold voltage range and adjust a second portion of the memory cells to a first threshold voltage range two threshold voltage ranges; and applying a second excitation voltage to the second portion of the memory cells to adjust a third portion of the second portion of the memory cells to a third threshold voltage range, and the memory page One of the threshold voltage states corresponds to the write command, wherein the first threshold voltage range, the second threshold voltage range and the third threshold voltage range are different from each other. The memory operation method as claimed in claim 1, wherein the third threshold voltage range has a larger threshold voltage than the second threshold voltage range, and the second threshold voltage range is larger than the first threshold voltage The range has a larger threshold voltage, and the first threshold voltage range, the second threshold voltage range and the third threshold voltage range are used to correspond to a plurality of different bit data. The memory operation method as described in claim 1, further comprising: Through the first excitation voltage or the second excitation voltage, data in another memory page adjacent to the memory page is deleted. The memory operation method as described in claim 1, wherein the method of making the threshold voltage state in the memory page correspond to the write command further includes: adjusting multiple threshold voltages of a plurality of low active cells in the memory cells, so that the memory cells are at least distributed in the first threshold voltage range, the second threshold voltage range, and the third threshold voltage range and a fourth threshold voltage range, wherein the electronic perturbation degree of the low active cells is lower than that of the other memory cells. The memory operation method as described in claim 1, wherein the method for adjusting the threshold voltages of the low active units includes: A third excitation voltage is applied to the memory page, wherein the third excitation voltage is greater than the first excitation voltage and the second excitation voltage. A memory device comprising: A plurality of memory pages, the memory pages are classified into a priority memory layer and a secondary memory layer, wherein the priority memory layer includes a plurality of memory groups, any one of the memory groups is composed of at least two adjacent composed of memory pages; and A processor, electrically connected to the memory pages, and used to receive a write command, wherein when the processor executes a memory page on any one of the memory groups according to the write command When writing a program, another memory page of any one of the memory groups will be cleared according to the write program; the processor is also used to selectively transfer the data in the memory group to the secondary In a memory page in the memory layer. The memory device as described in claim 6, wherein any one of the memory pages includes a plurality of memory units, and the processor is used to control the voltage of the memory units so that the memory units are at least distributed in a first valve value voltage range, a second threshold voltage range, a third threshold voltage range and a fourth threshold voltage range, and a threshold voltage state of any one of the memory pages corresponds to the write command. The memory device as described in claim 6, wherein the memory groups of the priority memory layer are arranged according to the time when the writing process is performed, so as to be divided into multiple levels, when the memory groups of the same level have all performed the writing process When writing programs, the processor is used to transfer the data in the same layer to the next layer, or transfer the data in the same layer from the primary memory layer to the secondary memory layer. The memory device as claimed in claim 8, wherein when the processor selectively transfers the data in the memory group to the memory page in the secondary memory layer, the processor is also used to delete the memory Data for all those memory pages in the group. The memory device as described in claim 6, further comprising: a plurality of memory blocks, the memory pages are included in the memory blocks, and correspond to the priority memory layer or the secondary memory layer, wherein the processor is used according to a priority layer management table and a secondary layer management table, Perform a clearing process on any one of the memory blocks, the priority level management table and the secondary level management table are used to record the number of times the memory blocks perform the clearing process, and the processor is used to perform the clearing process according to the priority level The management table and the secondary layer management table selectively re-associate any one of the memory blocks with the primary memory layer or the secondary memory layer.

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