TWI780967B - Memory device and memory operation method - Google Patents

Memory device and memory operation method Download PDF

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TWI780967B
TWI780967B TW110140054A TW110140054A TWI780967B TW I780967 B TWI780967 B TW I780967B TW 110140054 A TW110140054 A TW 110140054A TW 110140054 A TW110140054 A TW 110140054A TW I780967 B TWI780967 B TW I780967B
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memory
threshold voltage
voltage range
layer
data
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TW202318202A (en
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王韋程
李永駿
何書因
何建忠
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旺宏電子股份有限公司
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Abstract

A memory operation method, including the following steps: receiving a write command to find a memory page corresponding to the write command, wherein the memory page includes multiple memory cells; providing a first excitation voltage to the memory cells to maintain a first part of the memory cells at a first threshold voltage range, and adjust a second part of the memory cells to a second threshold voltage range; and providing a second excitation voltage to the second part of the memory cells to adjust a third part of the second part of the memory cells to a third threshold voltage range so that a threshold voltage state of the memory page corresponds to the write command, wherein the first threshold voltage range, the second threshold voltage range, and the third threshold voltage range are different from each other.

Description

記憶體裝置及記憶體操作方法Memory device and memory operation method

本揭示內容關於一種記憶體裝置及記憶體操作方法,特別是根據寫入指令對記體分頁編程之技術。The present disclosure relates to a memory device and a method of operating the memory, in particular to the technology of programming memory pages according to write commands.

隨著電腦速度越來越快,對於記憶體的速度以及穩定性的要求越來越高。同時,對於資料安全的要求也逐漸成為消費者的考量之一。在有眾多不同市場需求的情況下,如何改良記憶體的編程方式,使其不僅能有效率地讀寫資料,且兼顧記憶體的耐用性與安全性,即成為當前的一大課題。As computers become faster and faster, the requirements for memory speed and stability are getting higher and higher. At the same time, the requirement for data security has gradually become one of the considerations of consumers. In the case of many different market demands, how to improve the memory programming method so that it can not only read and write data efficiently, but also take into account the durability and safety of the memory has become a major issue at present.

本揭示內容係關於一種記憶體操作方法,包含下列步驟:接收寫入指令,以找出對應於寫入指令的記憶分頁,其中記憶分頁包含複數個記憶單元;對記憶單元施加第一激發電壓,以將該些記憶單元的第一部份維持於第一閥值電壓範圍,且將該些記憶單元的第二部份調整至第二閥值電壓範圍;以及對記憶單元的第二部份施加第二激發電壓,以將該些記憶單元的第二部份中的第三部份調整至第三閥值電壓範圍,且記憶分頁內之閥值電壓狀態對應於寫入指令,其中第一閥值電壓範圍、第二閥值電壓範圍及第三閥值電壓範圍互不相同。The disclosure relates to a memory operation method, comprising the following steps: receiving a write command to find a memory page corresponding to the write command, wherein the memory page includes a plurality of memory cells; applying a first excitation voltage to the memory cell, to maintain the first part of the memory cells in the first threshold voltage range, and adjust the second part of the memory cells to the second threshold voltage range; and apply the The second excitation voltage is used to adjust the third part of the second part of the memory cells to the third threshold voltage range, and the threshold voltage state in the memory page corresponds to the write command, wherein the first valve The value voltage range, the second threshold voltage range and the third threshold voltage range are different from each other.

本揭示內容還關於一種記憶體裝置,包含複數個記憶分頁及處理器。該些記憶分頁被分類於優先記憶層及次要記憶層。優先記憶層包含複數個記憶組。記憶組中的任一者由至少二個相鄰之該些記憶分頁組。處理器電性連接於該些記憶分頁,且用以接收寫入指令。當處理器根據寫入指令,對該些記憶組之任一者的其中一個記憶分頁進行寫入程序時,該些記憶組之任一者的另一個記憶分頁將根據寫入程序而被清除。處理器還用以選擇性地將記憶組中的資料轉移至次要記憶層中之記憶分頁中。The disclosure also relates to a memory device including a plurality of memory pages and a processor. The memory pages are classified into a primary memory layer and a secondary memory layer. The priority memory layer includes a plurality of memory groups. Any one of the memory groups consists of at least two adjacent memory page groups. The processor is electrically connected to the memory pages and used for receiving write commands. When the processor performs a write program on one memory page of any one of the memory groups according to the write command, another memory page of any one of the memory groups will be cleared according to the write program. The processor is also used to selectively transfer the data in the memory group to the memory page in the secondary memory layer.

據此,由於處理器對一個記憶單元進行寫入程序時,可一併清除相鄰之記憶單元所儲存的數據,故除能提昇記憶體裝置的空間利用率外,還可改善使用壽命,並確保資料安全。Accordingly, when the processor writes a program to a memory unit, the data stored in the adjacent memory unit can be cleared at the same time, so in addition to improving the space utilization rate of the memory device, the service life can also be improved, and Keep your data safe.

以下將以圖式揭露本發明之複數個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本發明。也就是說,在本發明部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。Several embodiments of the present invention will be disclosed in the following figures. For the sake of clarity, many practical details will be described together in the following description. It should be understood, however, that these practical details should not be used to limit the invention. That is, in some embodiments of the present invention, these practical details are unnecessary. In addition, for the sake of simplifying the drawings, some well-known structures and components will be shown in a simple and schematic manner in the drawings.

於本文中,當一元件被稱為「連接」或「耦接」時,可指「電性連接」或「電性耦接」。「連接」或「耦接」亦可用以表示二或多個元件間相互搭配操作或互動。此外,雖然本文中使用「第一」、「第二」、…等用語描述不同元件,該用語僅是用以區別以相同技術用語描述的元件或操作。除非上下文清楚指明,否則該用語並非特別指稱或暗示次序或順位,亦非用以限定本發明。Herein, when an element is referred to as "connected" or "coupled", it may mean "electrically connected" or "electrically coupled". "Connected" or "coupled" may also be used to indicate that two or more elements cooperate or interact with each other. In addition, although terms such as “first”, “second”, . Unless clearly indicated by the context, the terms do not imply any particular order or sequence, nor are they intended to be limiting of the invention.

本揭示內容關於一種記憶體裝置及記憶體操作方法,如第1圖所示,在一實施例中,記憶體裝置MR包含處理器100及至少一個記憶區塊MB(block)。處理器100用以接收讀取指令、寫入指令或清除指令,以執行對應的讀取程序、寫入程序及清除程序。The present disclosure relates to a memory device and a memory operation method. As shown in FIG. 1 , in one embodiment, the memory device MR includes a processor 100 and at least one memory block MB (block). The processor 100 is configured to receive a read command, a write command, or a clear command, so as to execute a corresponding read process, write process, and clear process.

在一實施例中,記憶區塊MB包含多個記憶分頁P。每個記憶分頁P中包含多個記憶單元(memory cell)。記憶單元可由浮柵電晶體實現,且根據浮柵中的電荷量多寡,記憶單元會具有不同的閥值電壓。以單階記憶單元(single-level cell,SLC)為例,閥值電壓的大小可用以紀錄一個位元的資料,如0或1的數位指令。In one embodiment, the memory block MB includes a plurality of memory pages P. Each memory page P contains a plurality of memory cells (memory cells). The memory cell can be implemented by a floating gate transistor, and the memory cell will have different threshold voltages according to the amount of charge in the floating gate. Taking a single-level cell (SLC) as an example, the magnitude of the threshold voltage can be used to record one bit of data, such as a digital command of 0 or 1.

在一實施例中,記憶分頁P可為一種多階記憶單元(multi-level cell,MLC)。透過閥值電壓與多個判斷電壓值的相對大小,每個記憶單元可用於記錄兩位元的資料(twobit data,如00、01、10、11)。換言之,處理器100可將每個記憶單元的閥值電壓與多個判斷電壓值相比對,以確認每個記憶單元紀錄的位元資料為何。例如,閥值電壓小於判斷電壓值V1的記憶單元記錄的資料為「11」,閥值電壓大於判斷電壓值V1但小於判斷電壓值V2的記憶單元記錄的資料為「10」,閥值電壓大於判斷電壓值V2但小於判斷電壓值V3的記憶單元記錄的資料為「00」,閥值電壓大於判斷電壓值V3的記憶單元記錄的資料為「01」。前述之「判斷電壓值V1~V3」係用以區分不同閥值電壓的記憶單元,故判斷電壓值V1~V3的實際數值可依照記憶體裝置MR的實際參數調整。然而,本揭示內容並不以此為限。在其他實施例中,記憶分頁P亦可為三階記憶體(Triple-Level Cell,TLC),用以儲存三位元的資料。In one embodiment, the memory page P can be a kind of multi-level memory cell (multi-level cell, MLC). Through the relative magnitude of the threshold voltage and multiple judging voltage values, each memory cell can be used to record two-bit data (such as 00, 01, 10, 11). In other words, the processor 100 can compare the threshold voltage of each memory cell with a plurality of judging voltage values to confirm the bit data recorded by each memory cell. For example, the data recorded by the memory unit whose threshold voltage is less than the judgment voltage value V1 is “11”, the data recorded by the memory unit whose threshold voltage is greater than the judgment voltage value V1 but less than the judgment voltage value V2 is “10”, and the data recorded by the memory unit whose threshold voltage is greater than the judgment voltage value V2 is “10”. The data recorded by the memory unit with the judgment voltage value V2 but less than the judgment voltage value V3 is “00”, and the data recorded by the memory unit whose threshold voltage is greater than the judgment voltage value V3 is “01”. The aforementioned "determining voltages V1-V3" are used to distinguish memory units with different threshold voltages, so the actual values of the judging voltages V1-V3 can be adjusted according to the actual parameters of the memory device MR. However, the present disclosure is not limited thereto. In other embodiments, the memory page P may also be a triple-level memory (Triple-Level Cell, TLC) for storing three-bit data.

此外,記憶分頁P可由2D NAND快閃記憶體或3D NAND快閃記憶體實現,由於本領域人士能理解記憶分頁的結構與製程,故在此不另贅述。In addition, the memory paging P can be realized by 2D NAND flash memory or 3D NAND flash memory, since those skilled in the art can understand the structure and manufacturing process of memory paging, so no further details are given here.

處理器100在讀寫資料時,其「順序處理(sequential access)」的運算速度會遠高於「隨機處理」的運算速度。換言之,處理器100將數據寫入多個相鄰的記憶分頁P的速度,將會遠快於把數據寫入多個隨機位置的記憶分頁P。為了實現「順序處理」以提昇效率,在一實施例中,處理器100依照多種資料庫編程技術來處理大量的數據,例如:LSM ( Log Structured-Merge Tree)技術。LSM技術又可分為多種應用,包含LevelDB、RocksDB、Apache AsterixDB等。When the processor 100 reads and writes data, its "sequential access" operation speed will be much higher than the "random access" operation speed. In other words, the speed at which the processor 100 writes data into multiple adjacent memory pages P will be much faster than writing data into multiple memory pages P at random locations. In order to achieve "sequential processing" to improve efficiency, in one embodiment, the processor 100 processes a large amount of data according to various database programming techniques, such as: LSM (Log Structured-Merge Tree) technique. LSM technology can be divided into multiple applications, including LevelDB, RocksDB, Apache AsterixDB, etc.

在此概要性地說明LSM技術如後。請參閱第1圖所示,處理器100將記憶體分頁P分類為由多個階層L1、L2~Ln(level)組成的樹狀結構(以下簡稱為LSM-tree)。該些階層L1~Ln依序排列,且越靠後的階層,其包含的記憶分頁P越多。在接收到寫入指令時,處理器100會優先將數據寫入上面的階層。當同一個階層皆已寫入數據時,處理器100將會把同一階層的數據整合(compact),並統一轉移至下一個階層。例如:將第一階層L1的資料轉移至第二階層L2。Here, the LSM technique is briefly described as follows. Please refer to FIG. 1 , the processor 100 classifies the memory pages P into a tree structure (hereinafter referred to as LSM-tree) composed of multiple levels L1, L2˜Ln (levels). The levels L1-Ln are arranged in sequence, and the lower the level, the more memory pages P it contains. When receiving the write command, the processor 100 will preferentially write data into the upper layer. When data has been written in the same level, the processor 100 will compact the data in the same level and transfer them to the next level. For example: transfer the data of the first level L1 to the second level L2.

LSM技術可使處理器100以「順序處理」的方式讀取資料,但資料的轉移會造成「寫入放大(write amplification issue)」問題。過多的舊資料除了會影響資料管理外,同時也會形成資料安全上的疑慮。The LSM technology enables the processor 100 to read data in a "sequential processing" manner, but the transfer of data will cause a "write amplification issue" problem. Too much old data will not only affect data management, but also create doubts about data security.

第2圖為第1圖的多個記憶體分頁P中兩個相鄰之記憶分頁P1、P2的示意圖。如前所述,每個記憶分頁P1、P2包含複數個記憶單元Pc。每個記憶分頁P1/P2中,對應於不同閥值電壓的記憶單元Pc之數量會根據寫入數據而有所不同。在此要特別一提者,第2圖所示之記憶單元Pc僅為示意圖,並非指實際的結構或位置。由於本領域人士能理解MLC、TLC之結構,故在此不另贅述。FIG. 2 is a schematic diagram of two adjacent memory pages P1 and P2 among the plurality of memory pages P in FIG. 1 . As mentioned above, each memory page P1, P2 includes a plurality of memory cells Pc. In each memory page P1/P2, the number of memory cells Pc corresponding to different threshold voltages varies according to the written data. It should be particularly mentioned here that the memory cell Pc shown in FIG. 2 is only a schematic diagram, and does not refer to the actual structure or location. Since those skilled in the art can understand the structures of MLC and TLC, details will not be described here.

在本實施例中,處理器100將至少兩個相鄰的記憶分頁(如:P1、P2)設為一個記憶組Px。換言之,所有的記憶分頁P會被分類成多個記憶組Px,且每一個記憶組用以紀錄同一個資料。處理器對於記憶組的管理將於後續段落中說明。In this embodiment, the processor 100 sets at least two adjacent memory pages (eg, P1 and P2 ) as a memory group Px. In other words, all memory pages P are classified into multiple memory groups Px, and each memory group is used to record the same data. The processor's management of memory banks will be described in subsequent paragraphs.

在此先說明處理器100針對單一個記憶組Px,寫入資料的方法。請搭配參閱第1~4F圖所示,其中第3圖為寫入程序的流程圖。第4A~4F圖則為記憶分頁P的閥值電壓狀態的變化示意圖。Here, the method for the processor 100 to write data to a single memory bank Px will be described first. Please refer to Figures 1 to 4F, and Figure 3 is the flow chart of the writing program. 4A-4F are schematic diagrams showing changes in the threshold voltage state of the memory page P. FIG.

如第2及4A圖所示,在步驟S301中,當處理器100接收到寫入指令時,處理器100將根據LSM技術,找出(或挑選出)位於第一階層L1中一個可被寫入數據之記憶組Px的記憶分頁P1。在部份實施例中,一個未被寫入數據(或數據已被清除)的記憶分頁P1內的所有記憶單元Pc的閾值電壓小於判斷電壓值V1,但本揭示內容並不以此為限。As shown in Figures 2 and 4A, in step S301, when the processor 100 receives a write command, the processor 100 will find (or select) a write command located in the first level L1 according to the LSM technology. Enter the memory page P1 of the memory group Px of the data. In some embodiments, the threshold voltages of all memory cells Pc in a memory page P1 that has not been written with data (or data has been erased) are lower than the judgment voltage value V1, but the disclosure is not limited thereto.

為便於說明,在此將同一個記憶分頁中具有「相近閥值電壓(即,屬於同一個閥值電壓範圍內)」的多個記憶單元Pc以「部份」稱呼。以第2圖為例,記憶單元Pc可根據閥值電壓的大小被約略分為四個部份,每一個部份可用以代表不同的位元資料「11」、「10」、「00」和「01」。以第4A圖為例,「第一部份」用以稱呼閥值電壓小於判斷電壓值V1的多個記憶單元Pc。For the convenience of description, the multiple memory cells Pc having "close threshold voltages (ie, belonging to the same threshold voltage range)" in the same memory page are referred to as "parts". Taking Figure 2 as an example, the memory cell Pc can be roughly divided into four parts according to the threshold voltage, and each part can be used to represent different bit data "11", "10", "00" and "01". Taking FIG. 4A as an example, the "first part" is used to refer to a plurality of memory cells Pc whose threshold voltage is lower than the judgment voltage value V1.

在此要特別一提者,二位元之資料「11」、「10」、「00」和「01」每一者所對應的閥值電壓並不限定為一固定值,而可為一個「閥值電壓範圍」(即,判斷電壓值V1~V3所形成的不同範圍)。如第2圖所示,判斷電壓值V1~V3所劃分出的四個閥值電壓範圍分別對應於記憶單元Pc的四個部份,以代表四個位元資料「11」、「10」、「00」和「01」。此外,在部份實施例中,位元資料「11」、「10」、「00」和「01」所對應之閥值電壓範圍互不重疊。It should be specially mentioned here that the threshold voltage corresponding to each of the two-bit data "11", "10", "00" and "01" is not limited to a fixed value, but can be a " "Threshold voltage range" (that is, different ranges formed by judging the voltage values V1-V3). As shown in Figure 2, the four threshold voltage ranges divided by the judging voltage values V1-V3 respectively correspond to the four parts of the memory cell Pc to represent the four bit data "11", "10", "00" and "01". In addition, in some embodiments, the threshold voltage ranges corresponding to the bit data "11", "10", "00" and "01" do not overlap with each other.

如第2及4A~4B圖所示,在步驟S302中,處理器100對記憶分頁P1中所有的記憶單元Pc施加第一激發電壓(如:10~15伏特),以使第一部份410的記憶單元Pc維持於第一閥值電壓範圍,且第二部份420的記憶單元從第一閥值電壓範圍被調整至對應於位元資料「10」之第二閥值電壓範圍(即,)。其中,第二閥值電壓範圍比第一閥值電壓範圍具有更大的閥值電壓。此外,第4B~4E圖記憶分頁P處於寫入程序時的電壓變化,亦即,記憶單元Pc還未被寫入完成,因此,前述「第二部份420對應於第二閥值電壓範圍」係指大部分之第二部份420會落入第二閥值電壓範圍,但並非限制第二部份420在此過程中完全地落入第二閥值電壓範圍。As shown in Figures 2 and 4A-4B, in step S302, the processor 100 applies a first excitation voltage (such as: 10-15 volts) to all the memory cells Pc in the memory page P1, so that the first part 410 The memory cells Pc in the second portion 420 are maintained in the first threshold voltage range, and the memory cells in the second portion 420 are adjusted from the first threshold voltage range to the second threshold voltage range corresponding to bit data "10" (ie, ). Wherein, the second threshold voltage range has a larger threshold voltage than the first threshold voltage range. In addition, the voltage change of the memory page P in Figures 4B-4E is in the programming process, that is, the memory cell Pc has not been programmed yet. Therefore, the aforementioned "the second part 420 corresponds to the second threshold voltage range" It means that most of the second part 420 will fall into the second threshold voltage range, but it does not limit the second part 420 to completely fall into the second threshold voltage range during this process.

具體而言,記憶單元Pc具有控制閘(control gate),處理器100會對控制閘施加「一次性供電(one-shot)」的激發電壓(如:前述之第一激發電壓),以調整或控制記憶單元Pc中的閥值電壓狀態。激發電壓的操作參數並不以前述舉例的數值為限,其原理類似於對記憶單元Pc進行編程(program operation),但此處「激發電壓」之目的與單純的「編程」不同(將於後續段落詳述)。由於本領域人士能理解激發電壓的施加方式,故在此不另贅述。Specifically, the memory unit Pc has a control gate, and the processor 100 applies a "one-shot power supply (one-shot)" excitation voltage (such as: the aforementioned first excitation voltage) to the control gate to adjust or and controlling the threshold voltage state in the memory unit Pc. The operating parameters of the excitation voltage are not limited to the above-mentioned values. The principle is similar to programming the memory cell Pc (program operation), but the purpose of the "excitation voltage" here is different from the simple "programming" (will be discussed later paragraph details). Since those skilled in the art can understand the way of applying the excitation voltage, it will not be repeated here.

因為製程因素造成的不理想,每個記憶單元Pc的活躍程度不會完全相同。「活躍」之定義為記憶單元中電子擾動程度的多寡。因為每個記憶單元Pc的活躍程度不同,因此當處理器100施加第一激發電壓時,每個記憶單元Pc的反應亦有所差異。如第4A~4B圖所示,第二部份420的記憶單元Pc係較第一部份410的記憶單元Pc為活躍,因此會隨著第一激發電壓的影響而被調整至對應於第二閥值電壓範圍(位元資料「10」)。後續其餘激發電壓之操作原理亦同,故後文不再複述。Due to the imperfection caused by process factors, the activation degree of each memory cell Pc will not be exactly the same. "Activity" is defined as the degree of electronic perturbation in the memory cell. Because the activity of each memory cell Pc is different, when the processor 100 applies the first excitation voltage, the response of each memory cell Pc is also different. As shown in Figures 4A-4B, the memory cell Pc of the second part 420 is more active than the memory cell Pc of the first part 410, so it will be adjusted to correspond to the second part under the influence of the first excitation voltage. Threshold voltage range (bit data "10"). The operating principles of the remaining excitation voltages are also the same, so they will not be repeated in the following text.

如第2及4B~4C圖所示,在步驟S303中,處理器100對第二部份420的記憶單元Pc施加第二激發電壓,以將原本第二部份420中的部份記憶單元Pc(即,第三部份430)的閥值電壓調整至對應於第三閥值電壓範圍(位元資料「00」)。第二激發電壓的電壓大小及/或脈波設計為使得原本第二部份420中其他部份記憶單元Pc的閥值電壓值未明顯提昇,而保持於第二閥值電壓範圍。換言之,第三部份430的記憶單元Pc僅為原先第二部份420之記憶單元Pc的其中一部份,而非全部。經過步驟403後,對應於第二閥值電壓範圍(位元資料「10」)的記憶單元Pc只剩下原先的一部分421,記憶單元Pc的部份430相對部份421更活躍。第三閥值電壓範圍比第二閥值電壓範圍具有更大的閥值電壓。As shown in Figures 2 and 4B-4C, in step S303, the processor 100 applies a second excitation voltage to the memory cells Pc in the second part 420, so that the part of the memory cells Pc in the second part 420 (ie, the third part 430 ) is adjusted to correspond to the third threshold voltage range (bit data "00"). The voltage magnitude and/or pulse wave of the second excitation voltage are designed so that the threshold voltages of other memory cells Pc in the second portion 420 do not increase significantly, but remain within the second threshold voltage range. In other words, the memory cells Pc of the third part 430 are only a part of the original memory cells Pc of the second part 420 , not all of them. After step 403 , only the original part 421 of the memory cell Pc corresponding to the second threshold voltage range (bit data "10") remains, and the part 430 of the memory cell Pc is more active than the part 421 . The third threshold voltage range has a larger threshold voltage than the second threshold voltage range.

在步驟S304中,處理器100會進一步調整所有記憶單元Pc中相對較不活躍的記憶單元Pc之閥值電壓,以使記憶分頁P1中的所有記憶單元Pc能分別分佈於多個閥值電壓範圍中(如:第一閥值電壓範圍、第二閥值電壓範圍及第三閥值電壓範圍)。前述「較不活躍的記憶單元Pc」為電子擾動程度相對低於其他記憶單元Pc的一部分記憶單元Pc,或者為前述步驟S301~303中並未隨著第一激發電壓、第二激發電壓改變閥值電壓的記憶單元Pc。調整細節將於後續段落說明。換言之,前述「較不活躍的記憶單元Pc」的閥值電壓並未因為第一激發電壓或第二激發電壓的影響,而改變原先所位於的閥值電壓範圍(如:第一閥值電壓範圍,位元資料「11」)。In step S304, the processor 100 further adjusts the threshold voltages of relatively inactive memory cells Pc among all the memory cells Pc, so that all the memory cells Pc in the memory page P1 can be respectively distributed in multiple threshold voltage ranges Medium (for example: the first threshold voltage range, the second threshold voltage range and the third threshold voltage range). The aforementioned "less active memory cells Pc" are a part of the memory cells Pc whose degree of electronic disturbance is relatively lower than that of other memory cells Pc, or the valves are not changed with the first excitation voltage and the second excitation voltage in the aforementioned steps S301-303. Value voltage memory cell Pc. The adjustment details will be explained in the following paragraphs. In other words, the threshold voltage of the aforementioned "less active memory cell Pc" does not change the original threshold voltage range due to the influence of the first excitation voltage or the second excitation voltage (for example: the first threshold voltage range , bit data "11").

在部份實施例中,處理器100會將所有記憶單元Pc分佈於第一閥值電壓範圍、第二閥值電壓範圍、第三閥值電壓範圍及第四閥值電壓範圍中。第四閥值電壓範圍對應於位元資料「01」,且第四閥值電壓範圍比第三閥值電壓範圍具有更大的閥值電壓。In some embodiments, the processor 100 distributes all the memory cells Pc in the first threshold voltage range, the second threshold voltage range, the third threshold voltage range and the fourth threshold voltage range. The fourth threshold voltage range corresponds to the bit data “01”, and the fourth threshold voltage range has a larger threshold voltage than the third threshold voltage range.

第4A~4F圖所示的波形圖僅為示意,在實作上,當處理器100將記憶單元Pc分佈於各個閥值電壓範圍時,對應於每個閥值電壓範圍的記憶單元Pc數量會取決於寫入指令。換言之,記憶分頁P整體形成的閥值電壓狀態將對應於寫入指令。The waveform diagrams shown in FIGS. 4A-4F are only for illustration. In practice, when the processor 100 distributes memory cells Pc in various threshold voltage ranges, the number of memory cells Pc corresponding to each threshold voltage range will decrease. Depends on the write command. In other words, the overall threshold voltage state of the memory page P will correspond to the write command.

在此說明調整所有記憶單元Pc中相對較不活躍的記憶單元Pc(在此稱為「低活躍單元」)之閥值電壓的方法如後。處理器100可對記憶分頁P1中的所有或部份之記憶單元Pc施加第三激發電壓,以使低活躍單元的閥值電壓能被移動至第三閥值電壓範圍(位元資料「00」)或第四閥值電壓範圍(位元資料「01」)。調整低活躍單元的激發電壓(如:第三激發電壓)係大於第一激發電壓及第二激發電壓。The method of adjusting the threshold voltage of the relatively inactive memory cell Pc (herein referred to as “low active cell”) among all the memory cells Pc is described as follows. The processor 100 can apply the third activation voltage to all or part of the memory cells Pc in the memory page P1, so that the threshold voltage of the low active cells can be moved to the third threshold voltage range (bit data "00") ) or the fourth threshold voltage range (bit data "01"). The excitation voltage (for example: the third excitation voltage) of the low active unit is adjusted to be greater than the first excitation voltage and the second excitation voltage.

具體而言,如第4C及4D圖所示,當處理器100已透過第一激發電壓及第二激發電壓,使較為活躍之記憶單元Pc分佈至對應於第二閥值電壓範圍(位元資料「10」)及第三閥值電壓範圍(位元資料「00」)之後,處理器100可進一步對具有第一閥值電壓範圍(位元資料「11」)的記憶單元Pc施加第三激發電壓。此時,原先具有第一閥值電壓範圍(位元資料「11」)及原先具有第二閥值電壓範圍(位元資料「10」)的記憶單元Pc(即,第4C圖中之部份410與部份421)中的低活躍單元(即,部份440)會受到第三激發電壓的影響,使其電壓上升。經過激發後,具有第一閥值電壓範圍(位元資料「11」)及第二閥值電壓範圍(位元資料「10」)的記憶單元Pc變化如第4D圖之部份411及422所示。Specifically, as shown in Figures 4C and 4D, when the processor 100 has passed the first excitation voltage and the second excitation voltage, the more active memory cells Pc are distributed to correspond to the second threshold voltage range (bit data After "10") and the third threshold voltage range (bit data "00"), the processor 100 may further apply a third excitation to the memory cell Pc having the first threshold voltage range (bit data "11") Voltage. At this time, the memory cell Pc (that is, the part in Figure 4C) that originally had the first threshold voltage range (bit data "11") and originally had the second threshold voltage range (bit data "10") 410 and part 421 ) of the low-active cells (ie, part 440 ) are affected by the third excitation voltage, causing their voltage to rise. After excitation, the memory cell Pc with the first threshold voltage range (bit data "11") and the second threshold voltage range (bit data "10") changes as shown in parts 411 and 422 of FIG. 4D Show.

接著,如第4D及4E圖所示,處理器100可對這些低活躍單元(第4D圖之部份440)進一步施加第四激發電壓,使這些低活躍單元中相對更不活躍的單元的電壓隨著第四激發電壓而上升,形成第4E圖所示之部份450、460,其中記憶單元Pc的部份460相對部份450更活躍。同樣地,第四激發電壓大於第一激發電壓及第二激發電壓。Next, as shown in Figures 4D and 4E, the processor 100 can further apply a fourth excitation voltage to these low-active cells (part 440 of Figure 4D), so that the voltages of relatively less active cells among these low-active cells As the fourth activation voltage rises, the portions 450, 460 shown in FIG. 4E are formed, wherein the portion 460 of the memory cell Pc is more active than the portion 450. Likewise, the fourth excitation voltage is greater than the first excitation voltage and the second excitation voltage.

承上,由於在調整低活躍單元的電壓時,第三激發電壓/第四激發電壓同樣會影響到活躍單元(如:部份411、422、430)的電壓,使得這些活躍單元的閥值電壓會略為提昇或降低,因此,可透過對不同的記憶單元Pc多次施加激發電壓,以微調記憶分頁P1的閥值電壓狀態。Continuing from the above, since the third excitation voltage/fourth excitation voltage will also affect the voltage of the active cells (such as: parts 411, 422, 430) when adjusting the voltage of the low active cells, the threshold voltage of these active cells Therefore, the threshold voltage state of the memory page P1 can be fine-tuned by applying excitation voltages to different memory cells Pc multiple times.

舉例而言,若記憶單元Pc的部份422並未完全對應於第二閥值電壓範圍,則可以針對右方部份(如:部份430、450)施加激發電壓,以使部份422往右調整。同理,在對記憶單元Pc施加第三激發電壓以形成部份422時,由於後續部份422的閥值電壓還會受到第四激發電壓的影響而變動,因此可事先預估第四激發電壓的影響,調整部份422隨著第三激發電壓形成時的電壓值。For example, if the part 422 of the memory cell Pc does not completely correspond to the second threshold voltage range, an activation voltage can be applied to the right part (such as: part 430, 450), so that the part 422 goes toward Adjust right. Similarly, when the third excitation voltage is applied to the memory cell Pc to form the portion 422, since the threshold voltage of the subsequent portion 422 will also be affected by the fourth excitation voltage, the fourth excitation voltage can be estimated in advance. Influenced by , the voltage value of the adjustment part 422 when the third excitation voltage is formed.

最後調整後的閥值電壓狀態如第4F圖所示,記憶分頁P1中會包含不同的閥值電壓範圍的記憶單元Pc,且每個部份的記憶單元Pc數量會根據寫入命令的實際數據而有所不同。The final adjusted threshold voltage state is shown in Figure 4F. The memory page P1 will contain memory cells Pc with different threshold voltage ranges, and the number of memory cells Pc in each part will be based on the actual data of the write command. rather different.

請參閱第2圖所示,根據前述步驟對記憶分頁P1進行寫入程序的同時,由於記憶分頁P2鄰近記憶分頁P1,因此,當處理器100對記憶分頁P1施加激發電壓(如:第一激發電壓~第四激發電壓)時,激發電壓同樣會影響到相鄰之記憶分頁P2,使得記憶分頁P2內的多個記憶單元Pc的閥值電壓狀態受到影響。此種變化可視為破壞了記憶分頁P2內原先寫入的數據,如同對記憶分頁P2中的數據執行清除動作。如前所述,記憶分頁P1及記憶分頁P2屬於同一記憶組Px。換言之,同一個記憶組Px中不同的記憶分頁記錄的是不同時刻寫入的數據(value),在一些實施例中,同一記憶組Px中的不同記憶分頁P分別記錄了一筆數據在不同時間點的最新版本及歷史版本。因此,當處理器100將新的數據寫入記憶分頁P1時,記憶分頁P2中原先儲存的舊數據會隨著激發電壓的影響而被破壞、清除。據此,即可確保記憶體裝置MR中不會留存過多的歷史資料,而確保了使用者的資料安全。Please refer to FIG. 2 , while the memory page P1 is being written according to the above steps, since the memory page P2 is adjacent to the memory page P1, when the processor 100 applies an excitation voltage to the memory page P1 (for example: the first excitation voltage to the fourth excitation voltage), the excitation voltage will also affect the adjacent memory page P2, so that the threshold voltage states of the plurality of memory cells Pc in the memory page P2 will be affected. Such a change can be regarded as destroying the data originally written in the memory page P2, like performing a clearing operation on the data in the memory page P2. As mentioned above, the memory page P1 and the memory page P2 belong to the same memory group Px. In other words, different memory pages in the same memory group Px record data (value) written at different times. In some embodiments, different memory pages P in the same memory group Px respectively record a piece of data at different time points The latest and previous versions of . Therefore, when the processor 100 writes new data into the memory page P1, the old data originally stored in the memory page P2 will be destroyed and cleared due to the influence of the excitation voltage. Accordingly, it can be ensured that too much historical data will not be retained in the memory device MR, thereby ensuring the data security of the user.

前述實施例所示的寫入程序,係可利用記憶單元Pc的干擾特性(disturb characteristics),以在對一個記憶單元Pc進行寫入程序的同時,破壞相鄰記憶單元Pc的數據。換言之,處理器100無須額外針對相鄰之記憶單元Pc或整個記憶區塊MB進行清除程序,因此可在不影響運作效率的情況下,確保資料安全,並改善使用壽命。The write procedure shown in the foregoing embodiments can utilize the disturbance characteristics of the memory unit Pc to destroy the data of the adjacent memory unit Pc while performing the write procedure on one memory unit Pc. In other words, the processor 100 does not need to additionally clear the adjacent memory cells Pc or the entire memory block MB, thus ensuring data security and improving service life without affecting operating efficiency.

請參閱第1圖所示,在此說明記憶體裝置MR的整體數據管理方式。在部份實施例中,記憶分頁P除了被分類於多個階層L1~Ln外,該些記憶分頁P(或階層L1~Ln)還可進一步被分類於優先記憶層LA或次要記憶層LB。舉例而言,第一階層L1及第二階層L2屬於優先記憶層LA,第n階層Ln屬於次要記憶層LB。優先記憶層所包含的階層數量可依照需求設定或調整(如:第一~第五層屬於優先記憶層LA),並不以第1圖所示之為限。Please refer to FIG. 1 , which describes the overall data management method of the memory device MR. In some embodiments, in addition to being classified into multiple levels L1-Ln, these memory pages P (or levels L1-Ln) can be further classified into the priority memory layer LA or the secondary memory layer LB. . For example, the first level L1 and the second level L2 belong to the priority memory layer LA, and the nth level Ln belongs to the secondary memory layer LB. The number of layers included in the priority memory layer can be set or adjusted according to requirements (for example: the first to fifth layers belong to the priority memory layer LA), and are not limited to those shown in Figure 1.

承上,在優先記憶層LA中,相鄰的記憶分頁P會被設定為同一組記憶組Px。如第2圖所示,相鄰的兩個記憶分頁P1、P2為同一記憶組Px,或者相鄰之四個記憶分頁P為同一記憶組Px。優先記憶層LA中的記憶組Px會根據「進行寫入程序的時間」排列於該些階層L1~Ln中。Continuing from the above, in the priority memory layer LA, adjacent memory pages P are set as the same memory group Px. As shown in FIG. 2, two adjacent memory pages P1 and P2 belong to the same memory group Px, or four adjacent memory pages P belong to the same memory group Px. The memory groups Px in the priority memory layer LA are arranged in the levels L1˜Ln according to the “time for writing program”.

處理器100電性連接於記憶分頁P,且將優先記憶層LA視為儲存熱資料(Hot data)的區塊,次要記憶層LB則為儲存冷資料(Cold data)的區塊。「熱資料」為讀寫較為頻繁的數據,「冷資料」則為讀寫相對較不頻繁的數據。當收到寫入指令時,處理器100會將數據視為熱資料,並寫入優先記憶層LA中最高階層(如:第一階層L1)的其中一個記憶組Px的記憶分頁裡(如:P1)。此時,記憶組Px內的另一個相鄰之記憶分頁(如:P2)會隨著寫入程序中的激發電壓而被清除。The processor 100 is electrically connected to the memory page P, and regards the primary memory layer LA as a block for storing hot data, and the secondary memory layer LB as a block for storing cold data. "Hot data" refers to data that is read and written frequently, and "cold data" refers to data that is read and written relatively infrequently. When receiving a write command, the processor 100 will regard the data as hot data, and write it into a memory page (such as: P1). At this time, another adjacent memory page (for example: P2) in the memory group Px will be cleared according to the excitation voltage in the writing process.

處理器100還用以選擇性地將記憶組Px中的數據轉移至次要記憶層LB中的記憶分頁P中。轉移的時機可為同一階層的所有記憶組Px皆已完成寫入程序的時候。處理器100用以將同一階層內的數據轉移至下一階層,或者將同一階層內的數據從該優先記憶層LA轉移至次要記憶層LB(即,前述之LSM技術)。The processor 100 is also configured to selectively transfer the data in the memory group Px to the memory pages P in the secondary memory layer LB. The timing of the transfer may be when all the memory groups Px of the same level have completed the writing process. The processor 100 is used to transfer the data in the same level to the next level, or transfer the data in the same level from the primary memory layer LA to the secondary memory layer LB (ie, the aforementioned LSM technology).

舉例而言,若記憶體裝置MR將「第五階層及以下的階層」設定為次要記憶層,則當第四階層中之記憶組Px都被寫入數據,準備被轉移至第五階層時,處理器100會將第四階層中的數據標記為「冷資料」。For example, if the memory device MR sets "the fifth level and below" as the secondary memory level, then when the memory groups Px in the fourth level are all written with data and ready to be transferred to the fifth level , the processor 100 marks the data in the fourth level as "cold data".

次要記憶層LB並無須將多個相鄰的記憶分頁P設為一組記憶組。換言之,次要記憶層LB中只使用一個記憶分頁P來儲存單一筆數據,無須儲存該數據的歷史版本,因此較為節省儲存空間,同時亦可避免數據洩漏的安全問題。The secondary memory layer LB does not need to set a plurality of adjacent memory pages P as a set of memory groups. In other words, only one memory page P is used in the secondary memory layer LB to store a single piece of data, and there is no need to store the historical version of the data, thus saving storage space and avoiding the security problem of data leakage.

承上,當處理器100要將記憶組Px中的一個記憶分頁P的數據轉移至次要記憶層LB時,處理器100會根據該記憶分頁P的數據,對次要記憶層LB中的記憶分頁P進行寫入程序(如:複製),同時,處理器100還會對記憶組Px中的所有記憶分頁(如:第2圖之P1、P2)進行清除,以刪除記憶組Px儲存的數據。As above, when the processor 100 wants to transfer the data of a memory page P in the memory group Px to the secondary memory layer LB, the processor 100 will transfer the data of the memory page P to the memory in the secondary memory layer LB. The page P is written into the program (such as copying), and at the same time, the processor 100 will also clear all the memory pages in the memory group Px (such as: P1, P2 in Figure 2), so as to delete the data stored in the memory group Px .

另一方面,當處理器100接收到新的一筆寫入指令,且該寫入指令的目標對應於次要記憶層LB的其中一個記憶分頁P時,處理器100會將這筆數據由「冷資料」改標記為「熱資料」。此時,處理器100將從優先記憶層LA選擇其中一個記憶組Px,並針對記憶組Px中的一個記憶分頁進行該寫入程序。完成寫入程序後,處理器100會清除對應於寫入指令的次要記憶層LB中的記憶分頁P,以刪除其儲存之數據。On the other hand, when the processor 100 receives a new write command, and the target of the write command corresponds to one of the memory pages P of the secondary memory layer LB, the processor 100 will transfer this data from the "cold Data" was relabeled as "Hot Data". At this point, the processor 100 will select one of the memory groups Px from the priority memory layer LA, and perform the writing process on a memory page in the memory group Px. After completing the writing process, the processor 100 clears the memory page P in the secondary memory layer LB corresponding to the writing command, so as to delete the stored data.

在部份實施例中,記憶體裝置MR接收到寫入指令時,會同時儲存「位址(adress)」與「數據(value)」。其中位址用以紀錄記憶單元Pc的實際位置,數據則才是真正儲存的內容。由於數據的資料量遠大於位址,因此位址的儲存並不會對記憶體管理造成明顯的問題或負擔。換言之,處理器100可根據前述實施例之方式儲存及管理「數據」,但儲存「位址」的方式則可使用現有的傳統技術。In some embodiments, when the memory device MR receives the write command, it will simultaneously store the "address (adress)" and "data (value)". The address is used to record the actual location of the memory unit Pc, and the data is the actual stored content. Since the amount of data is much larger than the address, the storage of the address does not cause obvious problems or burdens to the memory management. In other words, the processor 100 can store and manage "data" according to the method of the above-mentioned embodiments, but the method of storing "address" can use the existing traditional technology.

在部份實施例中,記憶體裝置MR還具有損耗平均管理(management with wear leveling technique)之技術。請搭配參閱第1及5圖,其中第5圖為根據本揭示內容之記憶體裝置中的記憶區塊示意圖。記憶體裝置MR包含多個記憶區塊MB1、MB2。每個記憶區塊MB1、MB2皆包含多個記憶分頁P,且分別對應於優先記憶層LA或次要記憶層LB。在需要完整清除數據時,處理器100可對記憶區塊MB1、MB2執行清除程序,以同時清除一個記憶區塊上的所有數據。由於本領域人士能理解清除程序的運作方式,故在此不另贅述。In some embodiments, the memory device MR also has a management with wear leveling technique. Please refer to Figures 1 and 5 together, wherein Figure 5 is a schematic diagram of a memory block in a memory device according to the disclosure. The memory device MR includes a plurality of memory blocks MB1, MB2. Each memory block MB1, MB2 includes a plurality of memory pages P, and respectively corresponds to the primary memory layer LA or the secondary memory layer LB. When the data needs to be completely cleared, the processor 100 can execute a clearing program on the memory blocks MB1 and MB2, so as to clear all the data on one memory block at the same time. Since those skilled in the art can understand the operation of the clearing program, it will not be repeated here.

在部份實施例中,記憶體裝置MR內還包含優先層管理表CP1及次要層管理表CP2。優先層管理表CP1別包含多個計數欄位Ca~Cd,每一個計數欄位Ca~Cd分別對應於優先記憶層LA中的一個記憶區塊,且用以紀錄記憶區塊被執行過清除程序的次數。相似地,次要層管理表CP2包含多個計數欄位Ce~Ch,每一個計數欄位Ce~Ch分別對應於次要記憶層LB中的一個記憶區塊,且用以紀錄記憶區塊被執行過清除程序的次數。舉例而言,計數欄位Ca用以紀錄記憶區塊MB1被清除過的次數(如:5100次),計數欄位Ce用以紀錄記憶區塊MB2被清除過的次數(如:300次)。In some embodiments, the memory device MR further includes a priority layer management table CP1 and a secondary layer management table CP2. The priority layer management table CP1 respectively includes a plurality of counting fields Ca~Cd, and each counting field Ca~Cd corresponds to a memory block in the priority memory layer LA respectively, and is used to record that the memory block has been cleared. times. Similarly, the secondary layer management table CP2 includes a plurality of counting fields Ce~Ch, each counting field Ce~Ch respectively corresponds to a memory block in the secondary memory layer LB, and is used to record the memory block being The number of times the cleanup procedure has been executed. For example, the count field Ca is used to record the number of times the memory block MB1 has been cleared (for example: 5100 times), and the count field Ce is used to record the number of times the memory block MB2 has been cleared (for example: 300 times).

優先層管理表CP1及次要層管理表CP2中的計數欄位Ca~Cf依照「清除程序的次數」排列。例如計數欄位Ca紀錄的數值為優先層管理表CP1中最大、計數欄位Cd紀錄的數值為優先層管理表CP1最小。同理,計數欄位Ce紀錄的數值為次要層管理表CP2中最大、計數欄位Cf紀錄的數值為次要層管理表CP2最小。The counting fields Ca to Cf in the priority layer management table CP1 and the secondary layer management table CP2 are arranged according to the "number of clearing procedures". For example, the value recorded in the counting field Ca is the largest in the priority layer management table CP1, and the value recorded in the counting field Cd is the smallest in the priority layer management table CP1. Similarly, the value recorded in the counting field Ce is the largest in the secondary layer management table CP2, and the value recorded in the counting field Cf is the smallest in the secondary layer management table CP2.

承上,處理器100用以根據優先層管理表CP1及次要層管理表CP2來執行清除程序。例如:處理器100會優先針對被清除次數較少的記憶區塊進行清除程序,以確保每個記憶區塊的清除次數不會差異過大。Continuing from the above, the processor 100 is configured to execute the clearing procedure according to the priority layer management table CP1 and the secondary layer management table CP2. For example, the processor 100 will preferentially perform the clearing procedure on memory blocks that have been cleared less frequently, so as to ensure that the clearing times of each memory block will not vary too much.

此外,處理器100還用以根據優先層管理表CP1及次要層管理表CP2中的計數欄位Ca~Cf,選擇性地將該些記憶區塊之任一者重新對應至優先記憶層LA或次要記憶層LB,以有效管理記憶體裝置MR的使用壽命。在部份實施例中,當優先層管理表CP1中的任一個計數欄位Ca的值大於門檻值(如:5000)時,處理器100會將該計數欄位Ca改為設定至次要層管理表CP2內,同時,將次要層管理表CP2中具有最低值的計數欄位(如:計數欄位Cf)改為設定至優先層管理表CP1中。以第5圖為例,即為將計數欄位Ca移動至次要層管理表CP2、且將計數欄位Cf移動至優先層管理表CP1。據此,即可避免部份記憶區塊被清除過多次,導致提前損壞的問題。In addition, the processor 100 is also used to selectively re-associate any one of these memory blocks to the priority memory layer LA according to the count fields Ca˜Cf in the priority layer management table CP1 and the secondary layer management table CP2 or the secondary memory layer LB to effectively manage the service life of the memory device MR. In some embodiments, when the value of any count field Ca in the priority layer management table CP1 is greater than a threshold value (eg: 5000), the processor 100 will change the count field Ca to the secondary layer In the management table CP2, at the same time, the counting field with the lowest value in the secondary layer management table CP2 (for example: the counting field Cf) is changed to be set in the priority layer management table CP1. Taking Fig. 5 as an example, the counting field Ca is moved to the secondary layer management table CP2, and the counting field Cf is moved to the priority layer management table CP1. Accordingly, the problem of premature damage caused by partial memory blocks being cleared many times can be avoided.

藉由根據優先層管理表CP1及次要層管理表CP2來管理記憶區塊,將可提昇記憶體裝置MR之空間利用率(enhance space utilization),並改善記憶單元Pc的(wear-out )耗損及耐用性問題(improve endurance)。By managing memory blocks according to the priority layer management table CP1 and the secondary layer management table CP2, the space utilization (enhance space utilization) of the memory device MR can be improved, and the wear-out of the memory unit Pc can be improved. And durability issues (improve endurance).

前述各實施例中的各項元件、方法步驟或技術特徵,係可相互結合,而不以本揭示內容中的文字描述順序或圖式呈現順序為限。Various components, method steps or technical features in the above-mentioned embodiments can be combined with each other, and are not limited by the order of description in words or presentation in drawings in the present disclosure.

雖然本揭示內容已以實施方式揭露如上,然其並非用以限定本揭示內容,任何熟習此技藝者,在不脫離本揭示內容之精神和範圍內,當可作各種更動與潤飾,因此本揭示內容之保護範圍當視後附之申請專利範圍所界定者為準。Although the content of this disclosure has been disclosed above in terms of implementation, it is not intended to limit the content of this disclosure. Anyone who is skilled in this art can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, this disclosure The scope of protection of the content shall be defined by the scope of the attached patent application.

MR:記憶體裝置 MB:記憶區塊 MB1-MB2:記憶區塊 L1-Ln:階層 LA:優先記憶層 LB:次要記憶層 Px:記憶組 Pc:記憶單元 P:記憶分頁 P1-P2:記憶分頁 V1-V4:閥值電壓範圍 100:處理器 410:部份 411:部份 420:部份 421:部份 422:部份 430:部份 440:部份 450:部份 460:部份 CP1:優先層管理表 CP2:次要層管理表 Ca-Cf:計數欄位 S301-S304:步驟MR: memory device MB: memory block MB1-MB2: memory blocks L1-Ln: Stratum LA: priority memory layer LB: secondary memory layer Px: memory group Pc: memory unit P: memory paging P1-P2: memory paging V1-V4: threshold voltage range 100: Processor 410: part 411: part 420: part 421: part 422: part 430: part 440: part 450: part 460: part CP1: priority layer management table CP2: Secondary layer management table Ca-Cf: count field S301-S304: Steps

第1圖為根據本揭示內容之部份實施例之記憶體裝置的示意圖。 第2圖為根據本揭示內容之部份實施例之兩個相鄰之記憶分頁的示意圖。 第3圖為根據本揭示內容之部份實施例之記憶體操作方法的流程圖。 第4A~4F圖為根據本揭示內容之部份實施例中閥值電壓狀態的變化示意圖。 第5圖為根據本揭示內容之部份實施例之記憶區塊的管理方式示意圖。 FIG. 1 is a schematic diagram of a memory device according to some embodiments of the present disclosure. FIG. 2 is a schematic diagram of two adjacent memory pages according to some embodiments of the present disclosure. FIG. 3 is a flowchart of a memory operation method according to some embodiments of the present disclosure. FIGS. 4A-4F are schematic diagrams showing changes in threshold voltage states according to some embodiments of the present disclosure. FIG. 5 is a schematic diagram of a management method of memory blocks according to some embodiments of the present disclosure.

國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none

S301-S304:步驟 S301-S304: Steps

Claims (10)

一種記憶體操作方法,包含: 接收一寫入指令,以找出對應於該寫入指令的一記憶分頁,其中該記憶分頁包含複數個記憶單元; 對該些記憶單元施加一第一激發電壓,以將該些記憶單元的一第一部份維持於一第一閥值電壓範圍,且將該些記憶單元的一第二部份調整至一第二閥值電壓範圍;以及 對該些記憶單元的該第二部份施加一第二激發電壓,以將該些記憶單元的該第二部份中的一第三部份調整至第三閥值電壓範圍,且該記憶分頁內之一閥值電壓狀態對應於該寫入指令,其中該第一閥值電壓範圍、該第二閥值電壓範圍及該第三閥值電壓範圍互不相同。 A memory manipulation method, comprising: receiving a write command to find a memory page corresponding to the write command, wherein the memory page includes a plurality of memory cells; applying a first excitation voltage to the memory cells to maintain a first portion of the memory cells within a first threshold voltage range and adjust a second portion of the memory cells to a first threshold voltage range two threshold voltage ranges; and applying a second excitation voltage to the second portion of the memory cells to adjust a third portion of the second portion of the memory cells to a third threshold voltage range, and the memory page One of the threshold voltage states corresponds to the write command, wherein the first threshold voltage range, the second threshold voltage range and the third threshold voltage range are different from each other. 如請求項1所述之記憶體操作方法,其中該第三閥值電壓範圍比該第二閥值電壓範圍具有更大的閥值電壓,該第二閥值電壓範圍比該第一閥值電壓範圍具有更大的閥值電壓,且該第一閥值電壓範圍、該第二閥值電壓範圍及該第三閥值電壓範圍用以對應複數個不同的位元資料。The memory operation method as claimed in claim 1, wherein the third threshold voltage range has a larger threshold voltage than the second threshold voltage range, and the second threshold voltage range is larger than the first threshold voltage The range has a larger threshold voltage, and the first threshold voltage range, the second threshold voltage range and the third threshold voltage range are used to correspond to a plurality of different bit data. 如請求項1所述之記憶體操作方法,還包含: 透過該第一激發電壓或該第二激發電壓,刪除相鄰於該記憶分頁之另一個記憶分頁內的數據。 The memory operation method as described in claim 1, further comprising: Through the first excitation voltage or the second excitation voltage, data in another memory page adjacent to the memory page is deleted. 如請求項1所述之記憶體操作方法,其中使該記憶分頁內之該閥值電壓狀態對應於該寫入指令的方法還包含: 調整該些記憶單元中之複數個低活躍單元的複數個閥值電壓,以使該些記憶單元至少分佈於該第一閥值電壓範圍、該第二閥值電壓範圍、該第三閥值電壓範圍及一第四閥值電壓範圍,其中該些低活躍單元的電子擾動程度低於其他的該些記憶單元。 The memory operation method as described in claim 1, wherein the method of making the threshold voltage state in the memory page correspond to the write command further includes: adjusting multiple threshold voltages of a plurality of low active cells in the memory cells, so that the memory cells are at least distributed in the first threshold voltage range, the second threshold voltage range, and the third threshold voltage range and a fourth threshold voltage range, wherein the electronic perturbation degree of the low active cells is lower than that of the other memory cells. 如請求項1所述之記憶體操作方法,其中調整該些低活躍單元的該些閥值電壓的方法包含: 對該記憶分頁施加一第三激發電壓,其中該第三激發電壓大於該第一激發電壓及該第二激發電壓。 The memory operation method as described in claim 1, wherein the method for adjusting the threshold voltages of the low active units includes: A third excitation voltage is applied to the memory page, wherein the third excitation voltage is greater than the first excitation voltage and the second excitation voltage. 一種記憶體裝置,包含: 複數個記憶分頁,該些記憶分頁被分類於一優先記憶層及一次要記憶層,其中該優先記憶層包含複數個記憶組,該些記憶組中的任一者由至少二個相鄰之該些記憶分頁組成;以及 一處理器,電性連接於該些記憶分頁,且用以接收一寫入指令,其中當該處理器根據該寫入指令,對該些記憶組之任一者的其中一個該記憶分頁進行一寫入程序時,該些記憶組之任一者的另一個該記憶分頁將根據該寫入程序而被清除;該處理器還用以選擇性地將該記憶組中的數據轉移至該次要記憶層中的一記憶分頁中。 A memory device comprising: A plurality of memory pages, the memory pages are classified into a priority memory layer and a secondary memory layer, wherein the priority memory layer includes a plurality of memory groups, any one of the memory groups is composed of at least two adjacent composed of memory pages; and A processor, electrically connected to the memory pages, and used to receive a write command, wherein when the processor executes a memory page on any one of the memory groups according to the write command When writing a program, another memory page of any one of the memory groups will be cleared according to the write program; the processor is also used to selectively transfer the data in the memory group to the secondary In a memory page in the memory layer. 如請求項6所述之記憶體裝置,其中該些記憶分頁的任一者包含複數個記憶單元,該處理器用以控制該些記憶單元的電壓,使該些記憶單元至少分佈於一第一閥值電壓範圍、一第二閥值電壓範圍、一第三閥值電壓範圍及一第四閥值電壓範圍,且該記憶分頁的任一者之一閥值電壓狀態對應於該寫入指令。The memory device as described in claim 6, wherein any one of the memory pages includes a plurality of memory units, and the processor is used to control the voltage of the memory units so that the memory units are at least distributed in a first valve value voltage range, a second threshold voltage range, a third threshold voltage range and a fourth threshold voltage range, and a threshold voltage state of any one of the memory pages corresponds to the write command. 如請求項6所述之記憶體裝置,其中該優先記憶層之該些記憶組係依照進行該寫入程序的時間排列,以分成複數個階層,當同一階層的該些記憶組皆進行過該寫入程序時,該處理器用以將該同一階層內的數據轉移至下一階層,或者將該同一階層內的數據從該優先記憶層轉移至該次要記憶層。The memory device as described in claim 6, wherein the memory groups of the priority memory layer are arranged according to the time when the writing process is performed, so as to be divided into multiple levels, when the memory groups of the same level have all performed the writing process When writing programs, the processor is used to transfer the data in the same layer to the next layer, or transfer the data in the same layer from the primary memory layer to the secondary memory layer. 如請求項8所述之記憶體裝置,其中當該處理器選擇性地將該記憶組中的數據轉移至該次要記憶層中之該記憶分頁中時,該處理器還用以刪除該記憶組中所有該些記憶分頁之數據。The memory device as claimed in claim 8, wherein when the processor selectively transfers the data in the memory group to the memory page in the secondary memory layer, the processor is also used to delete the memory Data for all those memory pages in the group. 如請求項6所述之記憶體裝置,還包含: 複數個記憶區塊,該些記憶分頁包含於該些記憶區塊中,且對應於該優先記憶層或次要記憶層,其中該處理器用以根據一優先層管理表及一次要層管理表,對該些記憶區塊之任一者進行一清除程序,該優先層管理表及該次要層管理表用以紀錄該些記憶區塊進行該清除程序的次數,該處理器用以根據該優先層管理表及該次要層管理表,選擇性地將該些記憶區塊之任一者重新對應至該優先記憶層或該次要記憶層。 The memory device as described in claim 6, further comprising: a plurality of memory blocks, the memory pages are included in the memory blocks, and correspond to the priority memory layer or the secondary memory layer, wherein the processor is used according to a priority layer management table and a secondary layer management table, Perform a clearing process on any one of the memory blocks, the priority level management table and the secondary level management table are used to record the number of times the memory blocks perform the clearing process, and the processor is used to perform the clearing process according to the priority level The management table and the secondary layer management table selectively re-associate any one of the memory blocks with the primary memory layer or the secondary memory layer.
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