TWI780521B - Electronic device and multiplexing method of spatial - Google Patents

Abstract

An electronic device includes a memory, a processor and function hardware. The memory includes a queue. The processor is configured to write at least one processing command into at least one target area of the queue. The function hardware is configured to read the at least one processing command from the at least one target area. The function hardware generates at least one completion message after executing the at least one processing command, and write the at least one completion message into the at least one target area. The at least one completion message correspond to the at least one processing command.

Description

Electronic device and space multiplexing method

This case is about the utilization technology of storage space, especially an electronic device and space multiplexing method that can improve storage utilization.

During system operation, the processor can dispatch various functional hardware through the bus to perform relevant calculations and data processing, so as to complete the entire system function. Generally speaking, the processor will issue execution tasks to the functional hardware by processing instructions, and the functional hardware will feed back to the processor through a completion message after executing the task.

Traditionally, two independent storage spaces need to be configured in the system to store processing instructions and completion messages respectively, thus occupying a lot of storage space.

This case provides an electronic device. In one embodiment, the electronic device includes a memory, a processor and functional hardware. Memory contains queues. The processor is used for storing at least one processing instruction in at least one target area of the queue. The functional hardware is used for reading at least one processing instruction from the target area. The functional hardware generates at least one completion message after executing at least one processing instruction, and writes at least one completion message into at least one target area, wherein the at least one completion message corresponds to the at least one processing instruction.

This case provides a space multiplexing method. In one embodiment, the spatial multiplexer The method includes: determining the size of at least one target area according to at least one processing instruction, wherein the at least one target area is located in a memory queue; writing the at least one processing instruction to the memory queue At least one target area; read the at least one processing command from the at least one target area; generate at least one completion message after executing the at least one processing command; write the at least one completion message into the at least one target area; and from the at least one target area The at least one completion message is read from at least one target area.

The detailed features and advantages of this case are described in detail below in the implementation mode. The content is enough to make any person familiar with the related art understand the technical content of this case and implement it according to the content disclosed in this specification. Those who are familiar with the related art can easily understand the purpose and advantages related to this case.

100: Electronic device

110: memory

120: Processor

130: Functional hardware

140: busbar

150:Scratch file

A1: status bar

A2: storage column

C1-C4: Processing instructions

C41-C42: Subprocessing instructions

D31-D32: false instruction

D41: Fake news

M1-M4: Completion message

M31-M33: Sub completion message

PC1: Instruction write indicator

PC2: Instruction read indicator

PM1: message writing indicator

PM2: Message reading indicator

Q1: Queue

Q11-Q1n: storage block

T1-T4: target area

S01-S06: Steps

FIG. 1 is a schematic block diagram of an embodiment of the electronic device of the present invention.

Fig. 2 is a schematic flow chart of an embodiment of the spatial multiplexing method in this case.

FIG. 3 is a schematic diagram of an embodiment of multiplexing spaces in queues for processing instructions and completion messages.

FIG. 4 is a schematic diagram of an embodiment of the queue in an initial state.

FIG. 5 is a schematic diagram after writing at least one processing instruction into at least one target area of the queue.

FIG. 6 is a schematic diagram of reading at least one processing instruction from the queue in FIG. 5 .

FIG. 7 is a schematic diagram after writing at least one completion message into the queue of FIG. 5 .

FIG. 8 is a schematic diagram of reading at least one completion message from the queue in FIG. 7 .

FIG. 9 is a schematic diagram of writing at least one processing instruction into the queue of FIG. 8 .

FIG. 10 is a schematic diagram after writing at least one completion message into the queue of FIG. 9 .

FIG. 11 is a schematic diagram of reading at least one completion message from the queue in FIG. 10 .

In order to make the above-mentioned purpose, features and advantages of the embodiments of the present case more comprehensible, a detailed description is given below in conjunction with the accompanying drawings.

Referring to FIG. 1 , the electronic device 100 includes a memory 110 , a processor 120 and functional hardware 130 , and the memory 110 is coupled to the processor 120 and the functional hardware 130 . Wherein, each number is not limited thereto, and one is used as an example for the convenience of description. In some embodiments, the processor 120 and the functional hardware 130 are respectively coupled to the memory 110 through a bus (BUS) 140 .

The memory 110 includes a queue Q1, and the queue Q1 may include a plurality of storage blocks Q11-Q1n in series. In some embodiments, n is a positive integer greater than 1, and the size of n (that is, the size of the queue Q1 ) can be preset by the processor 120 . However, the size of the queue Q1 is not fixed from then on. After setting, the processor 120 can dynamically adjust it according to its access to the queue Q1, so as to effectively use the space of the memory 110 . In some implementation aspects, the memory 110 may be, for example but not limited to, static random access memory (SRAM), dynamic random access memory (DRAM) or flash memory.

The processor 120 can be used to generate the processing instruction C1 and write the processing instruction C1 into the queue Q1 of the memory 110 through the bus 140 . The functional hardware 130 can obtain and execute the processing instruction C1 from the queue Q1 through the bus 140 . After executing the processing command C1 , the functional hardware 130 can generate a completion message M1 according to the execution result, and write the completion message M1 into the queue Q1 of the memory 110 . Wherein, the completion message M1 corresponds to the processing instruction C1. In particular, the electronic device 100 of any embodiment of the present application can implement the spatial multiplexing of any embodiment method to improve the storage utilization of the memory 110 .

In some implementations, the processor 120 can utilize a system-on-chip (SoC), a central processing unit (CPU), a microcontroller (MCU), an embedded controller (Embedded Controller), an application-specific integrated circuit (ASIC) , application processor (AP) or any other suitable electronic components. In addition, the functional hardware 130 can be various hardware components, such as but not limited to a display card, a network card, a sound card, and the like.

1 to 3, in one embodiment of the spatial multiplexing method, after the processor 120 of the electronic device 100 generates the processing command C1, it can write the processing command C1 into the target area T1 of the queue Q1 ( Step S01). Wherein, the target area T1 includes at least one of the plurality of storage blocks Q11 - Q1n, and the number of storage blocks covered by the target area T1 can be determined by the processor 120 . The functional hardware 130 of the electronic device 100 can read the processing command C1 from the target area T1 (step S02 ) to execute the processing command C1 , and generate a completion message M1 after executing the processing command C1 (step S03 ). Afterwards, the functional hardware 130 writes the completion message M1 back into the target area T1 of the queue Q1 (step S04 ). In this way, the processing instruction C1 and the completion message M1 can reuse the same storage space (ie, the target area T1 ), thereby improving storage utilization. In addition, the processor 120 may further read the completion message M1 from the target area T1 (step S05 ), so as to know the execution status of the processing instruction C1 according to the completion message M1 , such as execution success, failure, error, etc.

The processor 120 can be further used to generate complex processing instructions C1-C4. Therefore, in an embodiment of step S01 , the processor 120 may write the plurality of processing instructions C1 - C4 into the plurality of target areas T1 - T4 of the queue Q1 . Wherein, each processing instruction C1-C4 may correspond to one of the plurality of target areas T1-T4. For example, the processor 120 can plan the corresponding target areas T1-T4 in the queue Q1 according to the processing instructions C1-C4 respectively, and write the processing instructions C1-C4 into to target zone T1-T4. For example, the processor 120 may sequentially write the processing instructions C1-C4 into the target areas T1-T4 respectively. Here, the target areas T1-T4 can be connected sequentially. For example, the target area T1 covers the storage block Q11, the target area T2 covers the storage block Q12 and is connected in series after the target area T1, and the target area T3 covers the storage blocks Q13- Q15 is serially connected after the target area T2, and the target area T4 covers the storage blocks Q16-Q17 and is serially connected after the target area T3. Wherein, the number of storage blocks covered by each target area T1-T4 may be different, and the decision on the number of storage blocks covered by each target area T1-T4 will be explained in detail later.

Correspondingly, in one embodiment of step S02 to step S04 , the functional hardware 130 can read the processing instructions C1 - C4 from the target areas T1 - T4 to execute the processing instructions C1 - C4 respectively. After executing the processing instructions C1-C4 respectively, the functional hardware 130 can generate corresponding completion messages M1-M4 respectively, and store the completion messages M1-M4 back into corresponding target areas T1-T4 respectively. For example, the functional hardware 130 generates a completion message M1 after executing the processing instruction C1, and stores the completion message M1 back into the target area T1, so as to reuse the storage space used by the processing instruction C1 (ie, the target area T1) . By analogy to the processing instruction C4 in this order, the functional hardware 130 generates a completion message M4 after executing the processing instruction C4, and stores the completion message M4 back into the target area T4 to reuse the storage space used by the processing instruction C4 ( Namely the target zone T4). Correspondingly, in one embodiment of step S05, the processor 120 can read the completion messages M1-M4 from the target area T1-T4, so as to know the execution status of each processing instruction C1-C4 according to each completion message M1-M4 .

It should be noted that this application does not limit that the steps S02 to S04 need to be executed after the entire execution of the step S01 is completed. Even if the processor 120 is still storing another processing instruction in the target area of the queue Q1 (that is, step S01 is still being executed), as long as there are still unused commands in the queue Q1 With the executed processing instructions, the functional hardware 130 can execute steps S02 to S04. For example, the processing instruction C1 is already stored in the target area T1 of the queue Q1, and the processor 120 continues to write the processing instruction C2 into the target area T2. At this time, the functional hardware 130 can start to execute steps S02 to S04, That is, the functional hardware 130 can fetch and execute the processing instruction C1 from the target area T1 , and store the completion message M1 generated after the execution into the target area T1 . Similarly, in step S05, as long as there is a completion message in the queue Q1, the processor 120 can retrieve the completion message from the queue Q1. Furthermore, the processor 120 may wait until the number of completion messages stored in the queue Q1 has accumulated to a certain amount before starting to execute step S05.

In addition, this case does not limit the functional hardware 130 to fetch all processing instructions currently stored in the queue Q1 in step S02 . For example, the processing instructions C1-C4 are already stored in the target areas T1-T4 of the queue Q1, and the functional hardware 130 can only fetch and execute the processing instructions C1-C2 in the target areas T1-T2 to generate completion messages respectively M1-M2. And after storing the completed messages M1-M2 back into the target areas T1-T2 respectively, the functional hardware 130 fetches the processing instructions C3-C4 in the target areas T3-T4 for execution. Wherein, the number of instructions that the functional hardware 130 can execute at one time depends on its processing capability.

In some embodiments, the processor 120 predetermines the size of the completion messages M1-M4 according to the processing instructions C1-C4. Specifically, the processor 120 can know the size of each processing instruction C1-C4 when generating each processing instruction C1-C4. Moreover, the processor 120 can know in advance the sizes of the corresponding completion messages M1-M4 at that time according to the processing instructions C1-C4. For example, the processor 120 can know the sizes of the corresponding completion messages M1-M4 according to the instruction types of the processing instructions C1-C4. In addition, the size ratio between the processing instructions of each instruction type and the corresponding completion message can be agreed in advance, for example, through program declaration Wait.

In order to make each completion message M1-M4 return to the place where the corresponding processing instructions C1-C4 have been stored in the queue Q1, and not overwrite other processing instructions, therefore, before step S01, according to at least one processing instruction (in advance ) determines the size of at least one target area, wherein the at least one target area is located in a queue of a memory. Specifically, the processor 120 can further use the larger of the size of each processing instruction C1-C4 and the size of each corresponding completion message M1-M4 (the size of the completion message M1-M4 determined in advance) as each target area The size of T1-T4, or when the size of each processing instruction C1-C4 is equal to the size of each corresponding completion message M1-M4, use the size of each processing instruction C1-C4 as the size of each target area T1-T4 (step S06).

For example, assuming that the processor 120 knows that when the processing instruction C1 is stored in the queue Q1, it needs to occupy a storage block and the corresponding completion message M1 also needs to occupy a storage block. The size of the message M1, the processor 120 can process the size of the instruction C1 as the size of the target area T1, and the planned target area T1 includes a storage block Q11. For another example, assume that the processor 120 needs to occupy one storage block when the processing instruction C3 is stored in the queue Q1 and the corresponding completion message M3 needs to occupy three storage blocks. At this time, since the completion message M3 is the larger one, the processor 120 The size of the message M3 can be completed as the size of the target area T3, and the planned target area T3 includes three storage blocks Q13-Q15. Wherein, as shown in FIG. 3 , the completion message M3 can be divided into three sub-completion messages M31 - M33 , and the processor 120 respectively writes them into the storage blocks Q13 - Q15 when writing. For another example, assume that the processor 120 needs to occupy two storage blocks when the processing instruction C4 is stored in the queue Q1 and the corresponding completion message M4 needs to occupy one storage block. At this time, since the processing instruction C4 is the larger one, the processor 120 Can be dealt with The size of the processing instruction C4 is used as the size of the target area T4, and the planned target area T4 includes two storage blocks Q16-Q17. Wherein, as shown in FIG. 3 , the processing instruction C4 can be divided into two sub-processing instructions C41-C42, which are respectively written into the storage blocks Q16-Q17 when writing.

In some embodiments of step S01, when the size of the completion message is larger than the size of the processing instruction, the size of the target area will also be larger than the size of the processing instruction. At this time, the processor 120 writes the at least one processing instruction and at least one dummy (dummy) instruction in the target area T3. In some embodiments, in addition to writing the processing instructions in the target area, the processor 120 writes dummy instructions in the target area except for the processing instructions. For example, as shown in FIG. 3 , the processor 120 may write the processing instruction C3 into the storage block Q13 of the target area T3, and write the dummy instructions D31-D32 into the storage blocks Q14-Q15 of the target area T3.

In some embodiments of step S03 and step S04, when the size of the processing instruction is greater than the size of the completion message, the size of the target area will also be greater than the size of the completion message. At this time, the functional hardware 130 will not only generate the completion message, but also A dummy message can be generated, and the functional hardware 130 writes the at least one completion message and at least one dummy message in the target area T4. In some embodiments, in addition to writing the completion message in the target area, the functional hardware 130 writes a dummy message in a space other than the completion message in the target area. For example, the functional hardware 130 can generate a completion message M4 and a false message D41, and as shown in FIG. storage block Q17.

An embodiment of the aforementioned dummy (dummy) command or/and dummy message can be written into a fixed value (for example: all 0, or all 1), also can only reserve the write space, without writing Enter any value.

In some embodiments, the electronic device 100 may further include a register file 150 , and the register file 150 may be coupled to the processor 120 and the functional hardware 130 through the bus 140 . In some implementation aspects, the register file 150 can be implemented by using an array of multiple registers, such as but not limited to using SRAM.

Referring to FIG. 1 to FIG. 11 , the register file 150 may include a command write pointer PC1 , a command read pointer PC2 , a message write pointer PM1 and a message read pointer PM2 . The command writing pointer PC1 is used to indicate the storage position of the latest processing command in the queue Q1. The command read pointer PC2 is used to indicate the read position of the latest processing command read from the queue Q1. The message writing indicator PM1 is used to indicate the storage position of the latest completed message in the queue Q1. Moreover, the message reading indicator PM2 is used to indicate the reading position of the latest complete message read from the queue Q1. Here, the command writing pointer PC1 , the command reading pointer PC2 , the message writing pointer PM1 and the message reading pointer PM2 can all indicate the initial position of the queue Q1 in the initial state, as shown in FIG. 4 .

In some embodiments, after the processor 120 writes at least one of the plurality of processing instructions C1-C4 to at least one of the plurality of target areas T1-T4 in step S01, it can access the register file 150 through the bus 140, Write to pointer PC1 with an update command. For example, as shown in FIG. 5, the processor 120 can access the register file 150 after writing the processing instructions C1-C3 to the target area T1-T3, and update the command write pointer PC1 from the initial position to the target area T3 The location of the storage block Q15.

After the functional hardware 130 reads at least one of the plurality of processing instructions C1-C4 from at least one of the plurality of target areas T1-T4 in step S02, the temporary storage can be accessed through the bus 140 The device file 150 reads the pointer PC2 with an update command. For example, as shown in FIG. 6, the functional hardware 130 can access the register file 150 after reading the processing instructions C1-C2 from the target area T1-T2, and update the instruction read pointer PC2 from the initial position to the target The location of storage block Q12 in region T2. After the functional hardware 130 writes at least one of the plurality of completion messages M1-M4 to at least one of the plurality of target areas T1-T4 in step S04, it can access the register file 150 through the bus 140 to update the information written Indicator PM1. For example, as shown in FIG. 7 , the functional hardware 130 can access the register file 150 after writing the completion message M1-M2 to the target area T1-T2, and update the message writing pointer PM1 from the initial position to the target area The location of storage block Q12 of T2. After the processor 120 reads at least one of the plurality of completion messages M1-M4 from at least one of the plurality of target areas T1-T4 in step S05, it can access the register file 150 through the bus 140 to update the message read pointer PM2. For example, as shown in FIG. 8 , the processor 120 can access the register file 150 after reading the completed messages M1-M2 from the target area T1-T2, and update the message read pointer PM2 from the initial position to the target area T2 The location of the storage block Q12.

In some embodiments of step S01, the processor 120 may first access the register file 150 to obtain a new command write pointer PC1, and write at least one of the plurality of processing instructions C1-C4 according to the command write pointer PC1 The instruction is written into at least one target area behind the sequence pointed by the pointer PC1. For example, when it is obtained that the instruction writing pointer PC1 points to the location of the storage block Q15 of the target area T3 (as shown in FIG. 8 ), the processor 120 can write the processing instruction C4 into the location of the instruction writing pointer PC1. Point to the target area T4 behind the sequence, and update the command write pointer PC1 to the location of the storage block Q17 of the target area T4 after writing, as shown in FIG. 9 .

In some embodiments of step S02, the functional hardware 130 can first access the register file 150 to obtain the new command write pointer PC1 and the new command read pointer PC2, and according to The command write pointer PC1 and the command read pointer PC2 read at least one processing instruction from the next sequential target area pointed by the command read pointer PC2 to the target area pointed by the command write pointer PC1. For example, when the instruction write pointer PC1 points to the location of the storage block Q17 of the target area T4 and the instruction read pointer PC2 points to the location of the storage block Q12 of the target area T2 (an implementation as shown in FIG. 9 ), the function hard The bank 130 can read the processing instruction C3 located in the target area T3 from the next target area pointed by the instruction read pointer PC2, that is, the target area T3, to the target area T4 pointed by the instruction write pointer PC1, and update the instruction Read the pointer PC2 to the location of the storage block Q15 of the target area T3. In addition, in some embodiments, the functional hardware 130 can further calculate how many processing instructions are still to be executed according to the instruction writing index PC1 and the instruction reading index PC2.

In some implementations, the functional hardware 130 can analyze the processing instruction C3 after reading the processing instruction C3, such as but not limited to knowing the length of the processing instruction C3 through the header in the processing instruction C3, Then it is determined that the following dummy instructions D31-D32 are false and no processing is required, for example but not limited to not reading the dummy instructions D31-D32 and directly updating the instruction read pointer PC2 to the location of the storage block Q15 of the target area T3.

In some embodiments of step S03, after analyzing the processing instruction C3, the functional hardware 130 can know the proportional relationship between the processing instruction C3 and the completion message M3 through, for example but not limited to, the header in the processing instruction C3, and then After the processing command C3 is executed, a completion message M3 with a corresponding proportion is generated. For example, if the relationship between the processing command C3 and the completion message M3 is 1:3, the functional hardware 130 will generate the completion message M3 which can be divided into three sub-completion messages M31-M33.

In some embodiments of step S04, the functional hardware 130 can first access the register file 150 to obtain a new message writing indicator PM1, and write at least one of the plurality of completion messages M1-M4 according to the message writing indicator PM1 After the sequence indicated by the message writing indicator PM1 at least one target area of . For example, when the message writing pointer PM1 points to the location of the storage block Q12 of the target area T2, the functional hardware 130 can write the completion message M3 into the target area T3 located behind the sequence indicated by the message writing pointer PM1, and The message writing pointer PM1 is updated to the location of the storage block Q15 in the target area T3, as shown in FIG. 10 .

In some embodiments of step S05, the processor 120 may first access the register file 150 to obtain the new message write pointer PM1 and the new message read pointer PM2, and then write the message according to the message write pointer PM1 and the message read pointer PM2 reads at least one completed message from the next target area pointed by the message read pointer PM2 to the target area pointed by the message write pointer PM1. For example, when the message write pointer PM1 points to the position of the storage block Q15 of the target area T3 and the message read pointer PM2 points to the position of the storage block Q12 of the target area T2 (an implementation as shown in FIG. 10 ), the message read The target area next to the point of the index PM2 is the target area T3, which is the same as the target area pointed to by the message writing index PM1, so the processor 120 can read the completion message M3 from the target area T3 at this time, and Update the message reading pointer PM2 to the location of the storage block Q15 in the target area T3, as shown in FIG. 11 . In addition, in some embodiments, the processor 120 can further calculate how many completed messages to be processed according to the message writing indicator PM1 and the message reading indicator PM2.

In some implementations, the processor 120 can read the completion message M4 after reading the completion message M4, and then know that the subsequent false message D41 is false without processing, for example but not limited to not reading the false message D41 Or read the dummy message D41 but not execute it, and directly update the message read pointer PM2 to the location of the storage block Q17 of the target area T4.

In some embodiments, the functional hardware 130 can access the register file 150 to obtain the new message write pointer PM1 and the new message read pointer PM2, and write the message according to the message The index PM1 and the message reading index PM2 calculate how many completion messages are still waiting to be processed, and then judge whether to interrupt the notification processor 120 to process these completion messages based on this.

In some embodiments, each target area T1-T4 may include a status column A1 and a storage column A2. Wherein, the status column A1 can be used to indicate that what is stored in the storage column A2 is an instruction or a message. When the processor 120 writes the processing instructions C1-C4 to the target areas T1-T4 in step S01, each processing instruction C1-C4 can be written into the storage column A2 of each target area T1-T4, and written into a first A value in the status column A1 of each target zone T1-T4. When the functional hardware 130 writes the completion messages M1-M4 to the target areas T1-T4 in step S04, each completion message M1-M4 can be written in the storage column A2 of each target area T1-T4, and write a first The binary value is in the status column A1 of each target area T1-T4. Wherein, the second value is different from the first value. In some implementation aspects, the first value may be but not limited to 1, and the second value may be but not limited to 0.

In some embodiments, each storage block Q11-Q1n can be divided into the aforementioned status column A1 and storage column A2. The processor 120 can write the processing instruction into the storage column A2 of the storage block, and write the first value into the status column A1 of the storage block. The functional hardware 130 can write the completion message into the storage column A2 of the storage block, and write the second value into the status column A1 of the storage block. In particular, even if a dummy command is written, for example, a dummy command D31-D32 is written to the storage column A2 of the storage block Q14-Q15, the processor 120 will also write the first value into the status column A1 of the storage block Q14-Q15 . Even if a false message is written, for example, a false message D41 is written into the storage column A2 of the storage block Q17, the functional hardware 130 will also write the second value into the status column A1 of the storage block Q17.

In some embodiments, the functional hardware 130 can parse the processing instructions C1-C4 obtained from the queue Q1 through the parsing circuit. In addition, the number of functional hardware 130 in the electronic device 100 may be multiple, and the processing instructions C1-C4 stored in the same queue Q1 may be used To be executed by multiple functional hardware 130 . At this time, the functional hardware 130 can first analyze the processing instruction obtained from the queue Q1 through the analysis circuit, and then distribute the processing instruction to the corresponding functional hardware 130 for execution. In some implementations, the analysis circuit may be included in the functional hardware 130 , or independently configured and coupled to the functional hardware 130 and the memory 110 .

To sum up, the electronic device and the space multiplexing method of the embodiment of the present case write the processing instruction into the target area of the queue of the memory, and return the completion message corresponding to the aforementioned processing instruction to the same target In the area, the processing instruction and the corresponding completion message can reuse the storage space in the same queue, thereby improving the storage utilization rate of the memory.

Although the technical content of this case has been disclosed above with the preferred embodiment, it is not used to limit this case. Anyone who is familiar with this technology and makes some changes and modifications without departing from the spirit of this case should be included in the scope of this case. Therefore, the protection scope of this case should be defined by the scope of the attached patent application.

100: Electronic device

110: memory

120: Processor

130: Functional hardware

140: busbar

150:Scratch file

C1: Processing instructions

M1: Completion message

Q1: Queue

Q11-Q1n: storage block

Claims (12)

An electronic device comprising: a memory including a queue; a processor for writing at least one processing instruction to at least one target area of the queue; and A functional hardware for reading the at least one processing command from the target area, the functional hardware generates at least one completion message after executing the at least one processing command and writes the at least one completion message into the at least one The target area, wherein the at least one completion message corresponds to the at least one processing instruction. The electronic device as claimed in claim 1, wherein the processor further reads the at least one completion message from the at least one target area. The electronic device as described in claim 2 further includes a register file, the register file includes a command write pointer, a command read pointer, a message write pointer and a message read pointer; Wherein, the processor updates the instruction write pointer after storing the at least one processing instruction in the at least one target area; Wherein, the functional hardware updates the command read indicator after reading the at least one processing command from the at least one target area; Wherein, the functional hardware updates the message writing indicator after writing the at least one completion message to the at least one target area; and Wherein, the processor updates the message reading indicator after reading the at least one completion message from the at least one target area. The electronic device according to any one of claims 1 to 3, wherein the processor predetermines the size of the completion message according to the at least one processing instruction, and the processor predetermines the size of the completion message according to the at least one processing instruction size and The size of the completion message determines the size of the target area. The electronic device as described in claim 4, wherein when the size of the at least one target area is larger than the size of the at least one processing instruction, the processor writes the at least one processing instruction and at least one dummy instruction in the target Area. The electronic device as described in claim 4, wherein when the size of the at least one target area is greater than the size of the at least one completion message, the functional hardware writes the at least one completion message and at least one dummy message in the at least one completion message in the target area. The electronic device as described in claim 4, wherein the at least one target area includes a status column and a storage column, wherein the processor writes the at least one processing instruction in the storage column, and writes a first value in the storage column In the status column, the functional hardware writes the at least one completion message in the storage column, and writes a second value in the status column. A method for spatial multiplexing, comprising: Determine the size of at least one target area according to at least one processing instruction, wherein the at least one target area is located in a queue of a memory; writing the at least one processing instruction to the at least one target area; reading the at least one processing instruction from the at least one target area; generating at least one completion message after executing the at least one processing instruction; writing the at least one completion message into the at least one target area; and The at least one completion message is read from the at least one target area. The spatial multiplexing method as described in claim item 8, comprising: After writing the at least one processing command into the at least one target area, updating a command write pointer in a register file; after reading the at least one processing command from the at least one target area, updating a command read pointer in the register file; updating a message write pointer in the register file after writing the at least one completion message to the at least one target area; and After reading the at least one completion message from the at least one target area, updating a message read indicator in the register file. The space multiplexing method as described in claim 8, wherein when the size of the completion message is larger than the size of the processing instruction, writing the at least one processing instruction to the at least one object in the queue of the memory The step of area is writing the at least one processing instruction and a dummy instruction into the at least one target area. The space multiplexing method as described in claim 8, wherein when the size of the processing instruction is larger than the size of the completion message, the step of writing the at least one completion message into the at least one target area is writing the at least one completion message A message and a dummy message are sent to the at least one target area. The space multiplexing method as described in claim 8, wherein the target area includes a status column and a storage column, and the step of writing the at least one processing command to the at least one target area in the queue of the memory is writing the at least one processing instruction in the storage column and writing a first value in the status column, the step of writing the at least one completion message in the target area is writing the at least one completion message in the storage column, And write a second value in the status column.

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