TWI780481B - Configurable memory die capacitance - Google Patents

Abstract

Methods, systems, and devices for configurable memory die capacitance are described. A memory device may include a capacitive component, which may include one or more capacitors and associated switching components. The capacitive component may be coupled with an input/output (I/O) pad and an associated input buffer, and the one or more capacitors of the capacitive component may be selectively couplable with the I/O pad via the switching components. Switching components may be activated individually, in coordination, or not at all, such that one, multiple, or none of the capacitors may be coupled with the I/O pad. The capacitive component, I/O pad, and input buffer may be included in a same die of the memory device. In some cases, a configuration of the capacitive component may be based on signaling received from a host device.

Description

Configurable memory die capacitance

The following relates generally to a system including at least one memory device, and more particularly to configurable memory die capacitance.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Store information by programming different states of a memory device. For example, binary devices most often store one of two states, often represented by a logical one or a logical zero. In other devices, more than two states may be stored. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of a device may write or program state in a memory device.

Various types of memory devices exist, including magnetic hard drives, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM) , Magnetic RAM (MRAM), Resistive RAM (RRAM), Flash Memory, Phase Change Memory (PCM), and others. Memory devices can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices, such as DRAM, may lose their stored state when disconnected from an external power source.

Some systems may include one or more memory devices coupled to a host device, where the memory devices may provide data storage or other memory capabilities to the host device. Under some conditions, the communication between the host device and the associated memory device can experience interference or noise, which can degrade the performance of the system.

A memory device can be configured to exchange signals with a host device, and under some circumstances, the signals exchanged between the memory device and the host device can experience interference (eg, noise, crosstalk, and the like). For example, due to reflections between the memory device and the host device, or due to associations with other memory devices that may also be coupled to the host device (e.g., via a bus common to the memory device) Interference may occur from other signals or reflections or due to other causes known to those of ordinary skill in the art.

In some cases, increasing the slew rate (e.g., shortening rise and fall times) of signaling between the host device and one or more memory devices may provide or be associated with various benefits, such as those associated with higher speeds (e.g., higher frequency ) signaling the associated increased data rate. Increasing the slew rate, however, can increase the amount of interference within the system (eg, due to higher frequency harmonics and increased capacitive crosstalk, or other reasons known to those of ordinary skill in the art). Additionally or alternatively, increasing the slew rate may reduce the voltage margin for interpreting signals at the memory device (eg, with respect to the data window used to decode signaling, which may also be referred to as the eye window). In some cases, reducing the slew rate of signals as transmitted by the host device to one or more memory devices may be undesirable or not supported by the host device.

However, by including configurable (eg, adjustable, tunable) capacitance at the memory device, as described herein, signal reflections and other sources of interference as observed by the memory device can be mitigated. Configurable capacitance can be included in the memory die within the memory device (e.g., can be configured on-die capacitance), which avoids the need for capacitors external to the device that could cause layout or other space issues, and have other benefits. The configurable capacitance at the memory device can be configured to have a capacitance that mitigates reflections and other sources of interference due to, for example, signal reflections associated with other memory devices via a common A bus (eg, using a leap bus topology), such as a common command/address (CA) bus, couples the memory device and the host device.

For example, a memory device may include a configurable capacitive element whose capacitance may be adjustable (tunable) for adjustment or configuration and inclusion in a memory die The capacitance associated with the I/O pad. The capacitive components may include one or more capacitors and one or more associated switching components such as transistors. The switching component may be associated with one or more respective capacitors, and one or more capacitors of the capacitive component and the I/O pad may be selectively coupled via the switching component. For example, one or more switching components may activate or switch on (close) and couple one or more capacitors with a conductive path between the I/O pad and the input buffer. The switching components may be activated individually or in concert, or not at all, such that any one or more of the capacitors may be coupled to the I/O pads, or none of the capacitors may be coupled to the I/O pads. The capacitive component is operable to adjust or configure capacitance associated with an I/O pad (eg, the input capacitance of a memory die of a memory device). In some cases, a capacitive component may be coupled to an I/O pad and an associated input buffer included in the die (e.g., a capacitive component may be coupled to a conductive line between an I/O pad and an input buffer. catch).

The memory device can identify a target configuration for the configurable capacitive element. For example, a host device may signal a memory device to indicate a target capacitance or related configuration information for a capacitive component. The memory device can receive signaling from the host device and can configure the capacitive element based on the indicated target capacitance or configuration information. For example, a controller associated with a memory device may activate or deactivate one or more switching elements based on the indicated target capacitance or configuration information. The adjusted capacitance of the I/O pad can adjust (eg, reduce) the slew rate associated with the signal received at the memory device and can reduce the noise generated by the reflected signal, which can increase the decoding of the memory device from the host The accuracy and reliability of the signal received by the device, among other benefits. Among other implementations, this enhanced accuracy and reliability of signaling may provide safety and other benefits in automotive or other safety-critical deployments.

Features of the present invention are initially described in the context of a memory system and memory die as described with reference to FIGS. 1 and 2 . Features of the present invention are described in the context of circuit diagrams, system topologies, memory device configurations, and program flows as described with reference to FIGS. 3-6. These and other features of the present invention are further illustrated by and described with reference to apparatus diagrams and flow diagrams relating to configurable memory die capacitors, as shown with reference to FIGS. 7-11. describe.

1 illustrates an example of a system 100 utilizing one or more memory devices according to examples as disclosed herein. The system 100 may include an external memory controller 105 , a memory device 110 , and a plurality of channels 115 coupling the external memory controller 105 and the memory device 110 . The system 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110 .

System 100 may include part of an electronic device, such as a computing device, mobile computing device, wireless device, or graphics processing device. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, laptop, tablet, smartphone, cellular phone, wearable device, Internet connected device, or the like. Memory device 110 may be a component of a system configured to store data for one or more other components of system 100 .

At least part of system 100 may be an example of a host device. Such a host device may be an example of a device that uses memory to execute a program, such as a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop, tablet computer, smartphone, cellular phone, Wearable devices, Internet-connected devices, some other stationary or portable electronic devices, vehicles, vehicle controllers, or the like. In some cases, a host device may refer to hardware, firmware, software, or a combination thereof that implements the functions of the external memory controller 105 . In some cases, external memory controller 105 may be referred to as a host or a host device. In some examples, system 100 is a graphics card.

In some cases, memory device 110 may be a stand-alone device or component configured to communicate with other components of system 100 and provide physical memory addresses/space for potential use or reference by system 100 . In some examples, memory device 110 may be configurable to work with at least one or a plurality of different types of system 100 . Signaling between components of system 100 and memory device 110 may be operable to support modulation schemes for modulating signals, different pin designs for communicating signals, relative communication between system 100 and memory device 110 Different packaging, clock signaling and synchronization between the system 100 and the memory device 110 , timing conventions, and/or other factors.

Memory device 110 may be configured to store data for components of system 100 . In some cases, memory device 110 may act as a controlled device to system 100 (eg, respond to and execute commands provided by system 100 via external memory controller 105 ). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. Memory device 110 may include two or more memory dies 160 (eg, memory chips) to support a desired or specified capacity for data storage. A memory device 110 that includes two or more memory dies may be referred to as a multi-die memory or package (also known as a multi-die memory or package).

System 100 may further include a processor 120 , a basic input/output system (BIOS) component 125 , one or more peripheral components 130 and an input/output (I/O) controller 135 . Components of system 100 may communicate electronically with each other using bus 140 .

Processor 120 may be configured to control at least a portion of system 100 . Processor 120 may be a general purpose processor, digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, A discrete hardware component, or it may be a combination of these types of components. In such cases, processor 120 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose graphics processing unit (GPGPU), or a system-on-a-chip (SoC), among other examples.

BIOS component 125 may be a software component including BIOS operating as firmware that can initialize and execute various hardware components of system 100 . BIOS component 125 may also manage data flow between processor 120 and various components of system 100 (eg, peripheral components 130, I/O controller 135, etc.). BIOS component 125 may include programs or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

Peripheral component 130 may be any input device or output device that may be integrated into or with system 100, or an interface for such a device. Examples may include disk controllers, sound controllers, graphics controllers, Ethernet controllers, modems, Universal Serial Bus (USB) controllers, serial or parallel ports, or such as peripheral component interconnect (PCI ) or a peripheral card slot for a dedicated graphics port. The peripheral component 130 may be other components understood by those skilled in the art as peripheral devices.

The I/O controller 135 can manage data communication between the processor 120 and the peripheral components 130 , the input device 145 or the output device 150 . The I/O controller 135 can manage peripheral devices that are not integrated into or integrated with the system 100 . In some cases, I/O controller 135 may represent a physical connection or port to external peripheral components.

Input 145 may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or components thereof. This may include a user interface or an interface with or between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130 or may be managed by I/O controller 135 .

Output 150 may represent a device or signal external to system 100 configured to receive an output from system 100 or any of its components. Examples of output 150 may include a display, audio speakers, another processor on a printed device or printed circuit board, among others. In some cases, output 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130 or may be managed by I/O controller 135 .

The components of system 100 may consist of general or special purpose circuitry designed to perform their functions. This may include various circuit elements such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements configured to perform the functions described herein. In some examples, conductive lines can be coupled to system components or can be coupled to subcomponents within system components. For example, some conductive lines may include printed circuit board (PCB) traces or other conductive interconnects configured to carry signals between system components. As another example, some of the conductive lines may include bond wires or other conductive interconnects configured to carry signals between the memory die and another component of the device or system 100 . As another example, some conductive lines may include electrodes or other interconnects configured to carry signals within the memory die (eg, from one component fabricated on the die to another component fabricated on the die). even pieces.

The memory device 110 may include a device memory controller 155 and one or more memory die 160 . Each memory die 160 may include a local memory controller 165 (eg, local memory controller 165-a, local memory controller 165-b, and/or local memory controller 165- N ) and a memory array 170 (such as memory array 170-a, memory array 170-b and/or memory array 170- N ). Memory array 170 may be a collection (eg, a grid) of memory cells, where each memory cell is configured to store at least one bit of digital data. Features of memory array 170 and/or memory cells are described in more detail with reference to FIG. 2 . The memory die 160 may have one or more properties (eg, capacitance) that may be based on one or more elements of the memory die 160 (eg, access lines, memory cells, circuitry, etc.).

Memory device 110 may be an example of a two-dimensional (2D) array of memory cells or may be an example of a three-dimensional (3D) array of memory cells. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more than two memory dies 160 (eg, memory die 160-a, memory die 160 -b and/or any number of memory die 160- N ). In a 3D memory device, a plurality of memory die 160- N may be stacked on top of each other or next to each other. In some cases, memory die 160- N in a 3D memory device may be referred to as a mesa, level, layer or die. A 3D memory device may include any number of stacked memory die 160- N (eg, up to two, up to three, up to four, up to five, up to six, up to seven, up to eight). This can increase the number of memory cells that can be located on a substrate compared to a single 2D memory device, which in turn can reduce production costs or increase the performance of the memory array, or both. In a 3D memory device, different platforms may share at least one common access line such that some platforms may share at least one of word lines, bit lines and/or plate lines.

Device memory controller 155 may include circuitry or components configured to control the operation of memory device 110 . Thus, device memory controller 155 may include hardware, firmware, and software that enable memory device 110 to execute commands and may be configured to receive, transmit, or execute commands, data, or control information related to memory device 110 . Device memory controller 155 may be configured to communicate with external memory controller 105 , one or more memory die 160 , or processor 120 . In some cases, memory device 110 may receive data and/or commands from external memory controller 105 . For example, memory device 110 may receive a write command instructing memory device 110 to store certain data on behalf of a component of system 100 (such as processor 120), or to instruct memory device 110 to store certain data on a memory die Certain data in 160 provides read commands to components of system 100 such as processor 120 . In some cases, device memory controller 155 may combine with local memory controller 165 of memory die 160 to control the operation of memory device 110 as described herein. Examples of components included in the device memory controller 155 and/or the local memory controller 165 may include: receivers for demodulating signals received from the external memory controller 105, for modulating and transmitting The signal goes to a decoder, logic, decoder, amplifier, filter or the like of the external memory controller 105.

A local memory controller 165 (eg, local to the memory die 160 ) can be configured to control the operation of the memory die 160 . Also, the local memory controller 165 can be configured to communicate (eg, receive and transmit data and/or commands) with the device memory controller 155 . Local memory controller 165 may support device memory controller 155 to control the operation of memory device 110 as described herein. In some cases, memory device 110 does not include device memory controller 155, and local memory controller 165 or external memory controller 105 may perform various functions described herein. Thus, the local memory controller 165 may be configured to communicate with the device memory controller 155 , to communicate with other local memory controllers 165 , or to communicate directly with the external memory controller 105 or the processor 120 .

External memory controller 105 may be configured to enable communication of information, data, and/or commands between components of system 100 (eg, processor 120 ) and memory device 110 . The external memory controller 105 can act as a link between the components of the system 100 and the memory device 110 such that the components of the system 100 do not need to know the details of the operation of the memory device. Components of system 100 may present requests (eg, read commands or write commands) to external memory controller 105 that external memory controller 105 fulfills. External memory controller 105 may translate or translate communications exchanged between components of system 100 and memory device 110 . In some cases, external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

In some cases, external memory controller 105 or other components of system 100 , or the functions described herein, may be implemented by processor 120 . For example, external memory controller 105 may be hardware, firmware, or software implemented by processor 120 or other components of system 100, or some combination thereof. Although external memory controller 105 is depicted as being external to memory device 110 , in some cases external memory controller 105 or its functions described herein may be implemented by memory device 110 . For example, external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by device memory controller 155 or one or more local memory controllers 165 . In some cases, external memory controller 105 may be distributed across processor 120 and memory device 110 such that portions of external memory controller 105 are implemented by processor 120 and other portions by device memory controller 155 or local memory controller 165 for implementation. Likewise, in some cases, one or more of the functions ascribed herein to device memory controller 155 or local memory controller 165 may in some cases be performed by external memory controller 105 (either separate from processor 120 or included in the processor 120) to execute.

Components of system 100 may exchange information with memory device 110 using plurality of channels 115 . In some examples, the channels 115 enable communication between the external memory controller 105 and the memory device 110 . Each channel 115 may include one or more signal paths or transmission media (eg, conductors) between terminals associated with components of system 100 . For example, channel 115 may include a first terminal that includes one or more pins at external memory controller 105 and one or more pins at memory device 110 . A pin may be an example of, and generally refers to, any type of conductive input or output point of a device of system 100 (such as a ball grid array (BGA) ball), and a pin may be Configured to act as part of a channel.

In some cases, a pin may be part of the signal path of channel 115 . Additional signal paths may be coupled to terminals of channels used to route signals within components of system 100 . For example, memory device 110 may include various components that route signals from terminals of channel 115 to memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory memory array 170) (eg, signal paths within the memory device 110 or components thereof, such as within the memory die 160).

Channel 115 (and associated signal paths and terminals) may be dedicated to conveying particular types of information. In some cases, channel 115 may be a collective channel and thus may include a plurality of individual channels. For example, the data channel 190 may be x4 (eg, including four signal paths), x8 (eg, including eight signal paths), x16 (eg, including sixteen signal paths), and so on. Signals communicated on these lanes may use a double data rate (DDR) timing scheme. For example, some symbols of a signal may be registered on the rising edge of the clock signal and other symbols of the signal may be registered on the falling edge of the clock signal. Signals communicated on the channel may use single data rate (SDR) signaling. For example, one symbol of the signal may be buffered for each clock cycle.

In some cases, channel 115 may include one or more CA channels 186 . CA channel 186 may be configured to communicate commands between external memory controller 105 and memory device 110, including control information (eg, address information) associated with the commands. For example, CA channel 186 may include a read command with the address of the desired data. In some cases, CA channel 186 may be buffered on rising clock signal edges and/or falling clock signal edges. In some cases, CA channel 186 may include any number of signal paths (eg, eight or nine signal paths) to decode address and command data.

In some cases, channels 115 may include one or more clock signal (CK) channels 188 . CK channel 188 may be configured to communicate one or more common clock signals between external memory controller 105 and memory device 110 . Each clock signal can be configured to oscillate between a high state and a low state and coordinate the actions of the external memory controller 105 and the memory device 110 . In some cases, the clock signal may be a differential output (eg, CK_t signal and CK_c signal) and the signal path of CK channel 188 may be configured accordingly. In some cases, the clock signal may be single-ended. CK channel 188 may include any number of signal paths. In some cases, clock signal CK (eg, CK_t signal and CK_c signal) may provide a timing reference for command and address operations of memory device 110 or for other system-wide operations of memory device 110 . The clock signal CK may thus be variously referred to as a control clock signal CK, a command clock signal CK or a system clock signal CK. The system clock signal CK can be generated by the system clock, and the system clock can include one or more hardware components (such as oscillators, crystals, logic gates, transistors, or the like).

In some cases, lanes 115 may include one or more data (DQ) lanes 190 . Data channel 190 may be configured to communicate data and/or control information between external memory controller 105 and memory device 110 . For example, data channel 190 may convey information to be written to memory device 110 (eg, bi-directional) or information to be read from memory device 110 .

In some cases, channel 115 may include one or more other channels 192 that may be dedicated to other purposes. These other channels 192 may include any number of signal paths.

In some cases, other channels 192 may include one or more write clock signal (WCK) channels. Although the "W" in WCK can nominally represent "write", the write clock signal WCK (such as the WCK_t signal and the WCK_c signal) can provide a timing reference commonly used for access operations of the memory device 110 (such as timing reference for both read and write operations). Therefore, the write clock signal WCK can also be referred to as the data clock signal WCK. The WCK channel can be configured to communicate a common data clock signal between the external memory controller 105 and the memory device 110 . The data clock signal can be configured to coordinate access operations (eg, write operations or read operations) between the external memory controller 105 and the memory device 110 . In some cases, the write clock signal can be a differential output (eg, WCK_t signal and WCK_c signal) and the signal path of the WCK channel can be configured accordingly. A WCK channel may include any number of signal paths. The data clock signal WCK can be generated by a data clock, and the data clock can include one or more hardware components (such as oscillators, crystals, logic gates, transistors, or the like).

In some cases, other channels 192 may include one or more error detection code (EDC) channels. EDC channels can be configured to communicate error detection signals, such as checksums, to improve system reliability. An EDC channel may include any number of signal paths.

Channel 115 can couple external memory controller 105 to memory device 110 using a variety of different architectures. Examples of various architectures may include bus bars, point-to-point connections, crossbar switches, high density interposers such as silicon interposers, or channels formed in an organic substrate, or some combination thereof. For example, in some cases, a signal path may at least partially include a high density interposer, such as a silicon interposer or a glass interposer.

Memory device 110 may be configured to communicate (eg, transmit and receive signals) with a host device. In some cases, memory device 110 may experience interference or noise when receiving signals from a host device. Signals from the host device may be reflected from components of memory device 110 or from one or more adjacent memory devices 110, for example. The reflected signal can combine with the signal from the host device to the memory device 110 and can cause constructive and/or destructive interference. The disturbance experienced at the memory device 110 may depend on the signal slew rate, the system configuration or topology (e.g., a bus topology such as for the CA or DQ bus), the circuitry or other components of the memory device 110, or its analogues.

The signal communicated on channel 115 may be modulated using a number of different modulation schemes. In some cases, a binary sign (or binary level) modulation scheme may be used to modulate the signals communicated between the external memory controller 105 and the memory device 110 . A binary symbol modulation scheme may be an example of an M-ary modulation scheme, where M equals two. Each symbol of the binary symbol modulation scheme can be configured to represent a bit of digital data (eg, a symbol can represent a logic 1 or a logic 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return-to-zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and /or other.

In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate the signals communicated between the external memory controller 105 and the memory device 110 . A multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to three. Each symbol of a multi-symbol modulation scheme can be configured to represent more than one bit of digital data (eg, a symbol can represent a logical 00, a logical 01, a logical 10, or a logical 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM3, PAM4, PAM8, etc., Quadrature Amplitude Modulation (QAM), Quadrature Phase Shift Keying (QPSK), and/or others. A multi-symbol signal, such as a PAM3 signal or a PAM4 signal, may be a signal modulated using a modulation scheme comprising at least three levels to encode more than one bit of information per symbol. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or high-order modulation schemes and symbols.

As described herein, memory device 110 can be configured to transmit signals to and receive signals from a host device (e.g., external memory controller 105) and, in some cases, to receive signals from the host device. Experience interference or noise. For example, signals from a host device may have high slew rates, which may contribute to increased noise levels (eg, via signal reflections on neighboring memory devices). In some cases, the capacitance of one or more neighboring memory devices 110 (not shown) may at least partially cause signal reflections. The host device can be configured to reduce the noise experienced by the memory device 110 by indicating a target capacitance or related configuration information associated with a configurable capacitive component of the memory device 110 . The memory device 110 is operable to adjust or configure the capacitance associated with the configurable capacitive element and thus the I/O pads of the memory device 110 to which the configurable capacitive element can be coupled . In some cases, a configurable capacitive component may include one or more capacitors and may selectively couple the one or more capacitors to an I/O pad to one or more associated switching components (such as electrical crystal). In some cases, the configured capacitance of the configurable capacitive element can reduce the slew rate of signaling from the host device to the memory device 110 (e.g., the slew rate at the memory device 110), and the reduced slew rate The rate reduces signal reflections and associated noise.

FIG. 2 illustrates an example of a memory die 200 according to examples as disclosed herein. Memory die 200 may be an example of memory die 160 described with reference to FIG. 1 . In some cases, memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 can include one or more memory cells 205 that can be programmed to store one or more different logic states. Each memory cell 205 may be programmable to store two or more states. For example, memory cell 205 can be configured to store one bit of information (eg, a logical zero or a logical one) at a time. In some cases, a single memory cell 205 (eg, a multi-level memory cell) can be configured to store more than one bit of information at a time (eg, logical 00, logical 01, logical 10, or logical 11).

Memory cell 205 may store a charge representing a programmable state in a capacitor. DRAM architectures may include capacitors that include dielectric material to store charges representing programmable states. In other memory architectures, other storage devices and components are possible. For example, non-linear (eg, ferroelectric) dielectric materials may be used.

Operations such as reading and writing can be performed on memory cell 205 by activating or selecting access lines such as word lines 210 and/or bit lines 215 . In some cases, the digit lines 215 may also be referred to as bit lines. References to access lines, word lines and bit lines, or the like, are interchangeable without loss of understanding or operation. Activating or selecting wordline 210 or digitline 215 may include applying a voltage to the respective line.

Memory die 200 may include access lines (eg, word lines 210 and bit lines 215 ) arranged in a grid-like pattern. Memory cell 205 may be located at the intersection of word line 210 and bit line 215 . A single memory cell 205 can be accessed at the intersection of wordline 210 and bitline 215 by biasing (eg, applying a voltage to) wordline 210 or bitline 215 .

Access to memory cell 205 can be controlled via column decoder 220 or row decoder 225 . For example, column decoder 220 may receive a column address from local memory controller 260 and activate word line 210 based on the received column address. The row decoder 225 can receive a row address from the local memory controller 260 and can activate the bit line 215 based on the received row address. For example, memory die 200 may include a number of word lines 210 labeled WL_1 through WL_M, and a number of digit lines 215 labeled DL_1 through DL_N, where M and N depend on the size of the memory array. Therefore, memory cell 205 can be accessed at their intersections by enabling word lines 210 and bit lines 215 , such as WL_1 and DL_3 . In a two-dimensional or three-dimensional configuration, the intersection of the word line 210 and the digit line 215 may be referred to as the address of the memory cell 205 .

Memory cell 205 may include logic storage components such as capacitor 230 and switching component 235 . Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A first node of capacitor 230 may be coupled to switching component 235 and a second node of capacitor 230 may be coupled to voltage source 240 . In some cases, voltage source 240 may be a cell plate reference voltage, such as Vpl, or may be a ground, such as Vss. In some cases, voltage source 240 may be an instance of a boardline coupled with a boardline driver. Switching component 235 may be an example of a transistor or any other type of switching device that selectively establishes or deestablishes electronic communication between two components.

Selecting or deselecting the memory cell 205 can be realized by activating or deactivating the switching component 235 . Capacitor 230 may be in electronic communication with digit line 215 using switching component 235 . For example, capacitor 230 may be isolated from digit line 215 when switching component 235 is deactivated, and capacitor 230 may be coupled to digit line 215 when switching component 235 is enabled. In some cases, switching element 235 is a transistor and its operation can be controlled by applying a voltage to the gate of the transistor, where the voltage difference between the gate of the transistor and the source of the transistor can be greater or less than the threshold of the transistor. limit voltage. In some cases, the switching element 235 can be a p-type transistor or an n-type transistor. The word line 210 can be in electronic communication with the gate of the switching element 235 and the switching element 235 can be activated/deactivated based on the voltage applied to the word line 210 .

The word line 210 may be a conductive line in electronic communication with the memory cell 205 for performing access operations on the memory cell 205 . In some architectures, the word line 210 can be in electronic communication with the gate of the switching element 235 of the memory cell 205 and can be configured to control the switching element 235 of the memory cell. In some architectures, the word line 210 may be in electronic communication with the node of the capacitor of the memory cell 205 and the memory cell 205 may not include switching elements.

The digit line 215 can be a conductive line connecting the memory cell 205 and the sensing element 245 . In some architectures, memory cells 205 and digit lines 215 may be selectively coupled during portions of access operations. For example, word line 210 and switching element 235 of memory cell 205 can be configured to couple and/or isolate capacitor 230 of memory cell 205 from bit line 215 . In some architectures, memory cells 205 may be in electronic communication (eg, constant) with a digit line 215 .

The sensing component 245 can be configured to detect the state (eg, charge) stored on the capacitor 230 of the memory cell 205 and determine the logic state of the memory cell 205 based on the stored state. In some cases, the charge stored by memory cell 205 may be very small. Therefore, the sensing element 245 may include one or more sense amplifiers to amplify the signal output by the memory cell 205 . The sense amplifier can detect small changes in charge of digit line 215 during a read operation and can generate a signal corresponding to logic state 0 or logic state 1 based on the detected charge. During a read operation, the capacitor 230 of the memory cell 205 may output a signal (eg, discharge a charge) to its corresponding digit line 215 . This signal can cause the voltage on digit line 215 to change. The sensing component 245 can be configured to compare the signal received across the digit line 215 from the memory cell 205 to a reference signal 250 (eg, a reference voltage). The sensing component 245 can determine the stored state of the memory cell 205 based on the comparison. For example, in binary signaling, if the digit line 215 has a higher voltage than the reference signal 250, the sensing element 245 can determine that the stored state of the memory cell 205 is a logic 1, and if the digit line 215 has At a voltage lower than the reference signal 250, the sensing element 245 can determine that the stored state of the memory cell 205 is a logic 0. The sensing element 245 may include various transistors or amplifiers to detect and amplify the difference of signal signals. The detected logic state of memory cell 205 may be provided as an output of sensing component 245 (eg, to input/output 255 ), and may be sent to another component of memory device 110 including memory die 200 ( Such as the device memory controller 155) indicates the detected logic state (eg, directly or using the local memory controller 260).

The local memory controller 260 can control the operation of the memory cell 205 through various components such as the column decoder 220 , the row decoder 225 and the sensing component 245 . Local memory controller 260 may be an example of local memory controller 165 described with reference to FIG. 1 . In some cases, one or more of column decoder 220 , row decoder 225 , and sensing element 245 may be co-located with local memory controller 260 . The local memory controller 260 can be configured to receive commands and/or data from the external memory controller 105 (or the device memory controller 155 described with reference to FIG. Memory die 200 uses information, performs one or more operations on memory die 200, and communicates data from memory die 200 to external memory controller 105 (or device memory controller 155). The local memory controller 260 can generate column and row address signals to activate the target word line 210 and the target bit line 215 . The local memory controller 260 can also generate and control various voltages or currents used during the operation of the memory die 200 . In general, the amplitude, shape, or duration of the applied voltage or current discussed herein may be adjusted or varied, and may be different for the various operations discussed in operating memory die 200 .

The local memory controller 260 (or another controller included in the memory device) can configure one or more components associated with the memory die 200 . For example, the controller may enable or disable one or more switching elements of the configurable capacitive elements of the memory die 200 based on a target capacitance or related configuration information, which may be determined by Indicated to or otherwise recognized or determined by a memory device.

In some cases, the local memory controller 260 may be configured to perform a write operation (eg, a program operation) on one or more memory cells 205 of the memory die 200 . During a write operation, memory cells 205 of memory die 200 may be programmed to store a desired logic state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 260 can identify the target memory cell 205 for the write operation. The local memory controller 260 can identify the target word line 210 and the target bit line 215 in electronic communication with the target memory cell 205 (eg, the address of the target memory cell 205 ). The local memory controller 260 can activate the target word line 210 and the target bit line 215 (for example, apply a voltage to the word line 210 or the bit line 215 ) to access the target memory cell 205 . The local memory controller 260 may apply a specific signal (such as a voltage) to the digit line 215 during a write operation to store a specific state (such as a charge) in the capacitor 230 of the memory cell 205, the specific state (such as charge) may indicate a desired logic state.

In some cases, the local memory controller 260 can be configured to perform a read operation (eg, a sense operation) on one or more memory cells 205 of the memory die 200 . During a read operation, the logic state stored in memory cells 205 of memory die 200 may be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. The local memory controller 260 can identify the target memory cell 205 for the read operation. The local memory controller 260 can identify the target word line 210 and the target bit line 215 in electronic communication with the target memory cell 205 (eg, the address of the target memory cell 205 ). The local memory controller 260 can activate the target word line 210 and the target bit line 215 (for example, apply a voltage to the word line 210 or the bit line 215 ) to access the target memory cell 205 . The target memory cell 205 can send a signal to the sense component 245 in response to biasing the access line. The sensing component 245 can amplify the signal. The local memory controller 260 can activate a sensing element 245 (eg, a latch sensing element) and thereby compare the signal received from the memory cell 205 with the reference signal 250 . Based on the comparison, the sensing component 245 can determine the logic state stored on the memory cell 205 . Local memory controller 260 may communicate the logic state stored on memory cell 205 to external memory controller 105 (or device memory controller 155) as part of a read operation.

In some memory architectures, accessing the memory cell 205 can degrade or destroy the logical state stored in the memory cell 205 . For example, a read operation performed in a DRAM architecture may partially or completely discharge a capacitor of a target memory cell. The local memory controller 260 can perform a rewrite operation or a refresh operation to restore the memory cells to their original logic state. The local memory controller 260 can rewrite the logic state to the target memory cell after the read operation. In some cases, a rewrite operation may be considered part of a read operation. Additionally, activating a single access line, such as word line 210, can disturb the state stored in some of the memory cells that are in electronic communication with that access line. Therefore, a rewrite operation or a refresh operation may be performed on one or more memory cells that may not have been accessed yet.

Memory die 200 may be configured to transmit signals to and receive signals from a host device, and in some cases may experience interference or noise when receiving signals from a host device. For example, signals from a host device may have higher slew rates, which may result in higher noise levels (eg, via signal reflections on neighboring memory devices). In some cases, the capacitance of one or more adjacent memory dies 200 may at least partially cause signal reflections. The host device can be configured to reduce the noise experienced by the memory die 200 by indicating a target capacitance or configuration associated with the capacitive components of the memory die 200 . The capacitive component is operable to adjust or configure the capacitance associated with the I/O pads of the memory die 200, and may include one or more capacitors and may connect the one or more capacitors to the I/O pads. The pads are selectively coupled to one or more associated switching components (eg, transistors). In some cases, the capacitance dictated by the target capacitance or configuration of the capacitive component may reduce the slew rate of signaling from the host device to the memory die 200 (e.g., the slew rate at the memory die 200), and reduce Small slew rates reduce signal reflections and associated noise.

3 illustrates an example of a circuit 300 supporting configurable memory die capacitance according to examples as disclosed herein. In some examples, circuit 300 may represent a portion of a memory device, which may include memory die 200 as described with reference to FIG. 2 . For example, the circuit represented by circuit 300 may include I/O pad 305 . I/O pads 305 may be coupled with bond wires or other interconnects, which may in turn couple I/O pads 305 with, for example, pins of a memory device. Although described as a "pad," the scope and disclosure herein is not limited to any particular physical dimensions of I/O pad 305 . Rather, an I/O pad, such as the example of I/O pad 305, may refer to any conductive structure configured to receive or transmit signals external to the memory die that includes the I/O pad.

The circuit represented by circuit 300 may also include one or more conductive paths 330 (eg, traces, wires (such as bond wires), conductive lines/layers, etc.) and an input buffer 310 . The conductive path 330 may be an example of the conductive lines described with reference to FIGS. 1 and 2 . The circuit illustrated in circuit 300 can be configured to adjust or configure the capacitance of a memory die (eg, by adjusting or configuring the capacitance of I/O pad 305).

For example, the circuit illustrated by circuit 300 may include one or more capacitive components 315 , wherein capacitive component 315 is operable to adjust (eg, configure) the capacitance associated with I/O pad 305 . Capacitive components 315 may include a capacitor 320 (eg, capacitor 320-a) and an associated switching component 325 (eg, switching component 325-a). In some examples, the capacitive components may include multiple capacitors 320 (such as capacitors 320-a, 320-b, and 320-c) and multiple switching components (such as switching components 325-a, 325-b, and 325-c) . Switching components 325 , such as transistors, may be associated with one or more respective capacitors 320 . For example, switching component 325-a may be associated with capacitor 320-a, switching component 325-b may be associated with capacitor 320-b, and so on.

Capacitive component 315 may be coupled to I/O pad 305 , and thus one or more capacitors 320 of capacitive component 315 may be selectively coupled to I/O pad 305 via switching component 325 . In some cases, the capacitive component 315 may also be coupled to the input buffer 310 , and thus one or more capacitors 320 of the capacitive component 315 may be selectively coupled to the input buffer 310 via the switching component 325 . For example, one or more switching components 325 can activate or switch on (close) one or more capacitors 320 and connect one or more capacitors 320 to the conductive path between I/O pad 305 and input buffer 310 330 coupling. Switching components 325 may be activated individually or in concert, or not at all, such that any one or more of capacitors 320 may be coupled to I/O pad 305, or none of capacitors 320 may be coupled to I/O pad Pad 305 is coupled. Because capacitive component 315 can be coupled with I/O pad 305, capacitive component 315 is operable to adjust or configure the capacitance associated with I/O pad 305 (eg, the input capacitance of a memory die). As described above, switching component 325 of capacitive component 315 is operable to couple a plurality (eg, one, multiple, or none) of capacitors 320 of capacitive component 315 with I/O pad 305 . The host device or memory device associated with the memory die may indicate the number of capacitors 320 coupled to the I/O pad 305 to adjust or configure the capacitance associated with the I/O pad 305 .

In some cases, the host device may indicate a target capacitance for one or more capacitive elements 315 or an indication for the configuration of one or more capacitive elements 315 (such as an indication of coupling to I/O pad 305 The signaling of the number of capacitors 320) is transmitted to the memory device. In a first example, the signaling from the host device may instruct the memory device to store target capacitance or related configuration information for one or more capacitive elements 315 in one or more mode registers of the memory device device. In some cases, the mode register may include additional memory dedicated to storing the state of one or more capacitive elements 315 , such as the state of switching element 325 associated with one or more capacitive elements 315 . For example, the mode register may store information (eg, one or more logical values) indicating the number of switching elements 325 to be closed or activated. Additionally or alternatively, the mode register may store one or more logical values as a dot map, where each bit of the dot map may correspond to a switching element 325 of the capacitive element 315 . Thus, each bit of the bitmap may indicate whether the corresponding switching element 325 is to be activated (closed) or deactivated (opened) (eg, by indicating a logic 0 or a logic 1).

Accordingly, the memory device may store target capacitance or related configuration information for one or more capacitive elements 315 in the mode register, and may use the stored target capacitance or related configuration information to configure the one or more capacitive elements 315. One or more capacitive elements 315 (eg, by activating and/or deactivating switching elements 325 ) and thereby adjust the capacitance associated with the memory die (eg, the capacitance associated with I/O pad 305 ). For example, whenever the memory device is powered on, the memory device (eg, the memory device's controller) may access the mode register and configure the one or more capacitive elements 315 accordingly.

In a second example, signaling from the host device may indicate or command a target capacitance or configuration for one or more capacitive elements 315 (e.g., not specify to a memory device to store associated information in one or more modes in the scratchpad). Thus, the memory device may configure one or more capacitive elements 315 in response to the signaling (eg, by directly activating and/or deactivating the switching element 325 in response to the signaling). The memory device may adjust the capacitive element without storing information associated with the received indication to (and later reading information from) one or more mode registers. In some cases, the memory device may maintain the indicated target capacitance or configuration for one or more capacitive components 315 until a new signaling is received from the host device indicating a new target capacitance or new configuration. In some cases, the memory device may store the target capacitance or configuration for one or more capacitive elements 315 in the mode register when powered down if no new signaling has been received.

The target capacitance or configuration for one or more capacitive elements 315 may be based on signal slew rate, memory die capacitance (eg, parasitic capacitance of capacitive element 315 or other capacitance in addition to parasitic capacitance), signal noise (such as reflection noise) or one or more of the like, or any combination thereof. In one example, a target capacitance or configuration for one or more capacitive components 315 can support a target slew rate. Similarly, the target capacitance or configuration for one or more capacitive elements 315 can be configured to reduce the noise level of the signal between the host device and the memory device (e.g., reflections from adjacent memory devices). noise). The target capacitance or configuration for one or more capacitive components 315 may also be based on the parasitic capacitance of one or more components of the memory die (e.g., PMOS transistors and/or NMOS transistors of I/O buffer 310 the gate capacitance). For example, the target capacitance or configuration can be based on the parasitic capacitance of the memory die such that the capacitance of the capacitive element 315 together with the parasitic capacitance can be equal to the target total capacitance. The target total capacitance may be based on target slew rate or signal noise, as described above, and may additionally be based on memory device and/or host device simulation results or measurements.

The target memory die capacitance or configuration for one or more capacitive elements 315 may also be based on the placement of the memory device, the placement of one or more associated (coupled) memory devices, or the placement of the memory device. Placement of one or more memory dies. For example, placement of a memory device or one or more associated memory dies may affect one or more parasitic capacitances (eg, and associated noise) associated with the memory device, or may affect one or more Other signaling parameters. Thus, a target memory die capacitance or configuration for one or more capacitive components may be based on the capacitive or conductive capacitance introduced by the placement of the memory device or one or more associated memory devices and die. letter effect. Additionally or alternatively, the target memory die capacitance or configuration may be based on signal routing and communication structures between the host device and the memory device. In some cases, each memory die of a memory device may have a different target capacitance or a different configuration (eg, based on placement and/or routing) for the associated capacitive component 315 . Each memory device coupled with the host device may also have a different target capacitance or a different configuration for the associated capacitive component 315 .

For example, each memory device may be based on the location or placement of the memory device and/or on signal routing (e.g., relative to the host device or termination impedance, such as in terms of the signal path length between the memory device and the host device ( such as bus length) or termination impedance) to have a target capacitance for capacitive component 315 . In one example, the host device may be coupled to two or more memory devices, with a second memory device closer to the host device than a memory device further away from the host device than a first memory device. A memory device may have a higher target capacitance (eg, based on the associated configuration) for capacitive component 315 (eg, an additional 2 picofarads (pF)). Additionally or alternatively, the bus that couples the host to two or more memory devices may include impedances (eg, termination impedances such as termination resistors (RTT)) that can attenuate or eliminate some transmission noise. Thus, a first memory device that is further away from impedance may have a higher target capacitance for capacitive component 315 (eg, based on the associated configuration) than a memory device that is closer in impedance than the first memory device.

In one example, a memory die (e.g., a memory device including a memory die) can be configured to communicate (e.g., transmit and receive signals) with a host device, and can experience disturbances when receiving signals from the host device or noise. For example, a signal from a host device (such as a CA signal) may have smaller rise and/or fall times (higher slew rates), which may result (for example, via signal reflections) at higher Noise level. In some cases, the capacitance of one or more adjacent memory dies may at least partially cause signal reflections (eg, due to printed circuit board (PCB) discontinuities). The host device can be configured to reduce the noise experienced by the memory die by indicating a target capacitance or configuration to the capacitive element 315 of the memory die (e.g., by activating and/or deactivating the switching element 325) . In some cases, the capacitance dictated by the target capacitance or configuration of capacitive component 315 may reduce the slew rate of signaling from the host device to the memory die (e.g., the slew rate at the memory die), and reduce The fast slew rate reduces signal reflections and associated noise.

The host device may signal the memory die to indicate a target capacitance or configuration of capacitive element 315 (eg, including an indication of whether to use a mode register). The memory die can receive signaling from the host device and can configure the capacitive component 315 based on the indicated target capacitance or configuration. For example, a controller associated with a memory die may activate or deactivate one or more switching elements 325 according to an indicated target capacitance or configuration. The switching element 325 can couple or decouple one or more associated capacitors 320 from the I/O pad 305 of the memory die, and thus can change the capacitance of the capacitive element 315 and the I/O pad 305 . The adjusted capacitance of the I/O pad 305 can adjust (eg, reduce) the slew rate associated with the signal received at the memory die and can reduce noise generated by the reflected signal, which can increase the accuracy of the memory device. Spend.

4 illustrates an example of a bus topology 400 for a memory device supporting configurable memory die capacitance, according to examples as disclosed herein. In some examples, one or more memory devices 405 may be coupled to a host device 410 (eg, a system-on-chip (SoC)) using a bus topology 400 . Each memory device 405 may include a memory die, which may be an example of the memory die described with reference to FIGS. 2 and 3 . In some cases, memory device 405 may include one memory die, and in other cases, memory device may include multiple memory dies. The memory die may include I/O pads, which may be examples of the I/O pads described with reference to FIG. 3 . The connections represented by busbar topology 400 may also include one or more conductive paths (e.g., traces, wires, conductive lines/layers, etc.), which may be signal paths or signal paths as described with reference to FIG. An example of a conductive thread. The devices illustrated in bus topology 400 can be configured to adjust or configure the capacitance of a memory die (eg, by adjusting or configuring the capacitance of an associated I/O pad).

For example, each memory device illustrated by bus topology 400 may include one or more capacitive elements, where a capacitive element may be an example of capacitive element 315 described with reference to FIG. 3 . Each capacitive element can be selectively coupled with an associated I/O pad (e.g., via one or more switching elements of the capacitive element) in order to adjust or configure the capacitance of the I/O pad (e.g., to a target capacitance ). In some cases, the target capacitance of a memory die or associated I/O pad may be based on the configuration or topology of one or more memory devices 405 relative to each other and/or relative to host device 410 (eg, may be based on characteristics of the bus topology 400).

In one example, the plurality of memory devices 405 can be coupled to the host device 410-a in a leap topology via one or more lines 415, 420, and/or 425, wherein the plurality of memory devices 405 can be coupled via The common trunk line 415-a and respective branch lines 425 are coupled to the host device 410-a, wherein each branch line 425 couples the memory device 405 to the common trunk line 415-a. A relay line 415-a (such as a relay PCB trace) can couple the host device 410-a with the memory device 405, and the length of the relay line 415-a can depend on the distance between the host device 410-a and the memory device 405. distance. In some cases, trunk line 415 - a may be the longest line coupling host device 410 - a with memory device 405 . Traces 420-a, 420-b, 420-c, 420-d, and 420-e may couple stub lines 425 for memory device 405 to one another and, in some cases, may represent stub lines 425 between PCB traces. The length associated with trace 420 may be based on the package size of memory device 405 . The branch lines 425-a, 425-b, 425-c, 425-d, and 425-e may respectively represent from the trunk line 415-a or the respective traces 420 to the memory devices 405-a, 405-b, 405-c , 405-d and 405-e the PCB traces of the pins (eg, corresponding to balls of a ball grid array (BGA)). In some cases, branch line 425 may be shorter than trace line 420 or trunk line 415-a.

In some examples, lines 415, 420, and 425 may represent lines used for CA bus routing, and in some cases multiple signals (eg, 20 signals) may be carried on each line (eg, in FIG. 4 Each line illustrated may correspond to a group of parallel lines). Lines 415, 420, and 425 may represent one or more connections between host device 410-a and memory device 405, where one pin or pad on host device 410-a may be connected to more than one pin in memory device 405. Pins or pads on one are coupled. For example, a pin on the host device 410 - a can be coupled to a pin on each memory device 405 .

Host device 410 may be coupled with multiple memory devices 405 to achieve one or more benefits. For example, the host device 410 can be coupled with multiple memory devices 405 (e.g., four or five memory devices 405) to increase, for example, throughput, bandwidth, and memory density as an automotive ADAS ( ADAS), artificial intelligence (AI) applications, or other applications. In some cases, signals from host device 410 (e.g., CA signals) to memory device 405 may have small rise and/or fall times, which may cause higher level noise to be reflected from adjacent memory devices 405 . In some cases, the noise level at the memory device 405, which may affect the voltage margin associated with the data window used to interpret the signalling, may drop below the input level of the memory device 405 and may cause Timing error at memory device 405 . In some cases, a termination impedance (eg, RTT 430) can absorb or attenuate reflected noise, and thus, memory devices 405 (eg, memory devices 405-a and/or 405-b) positioned farther from RTT 430 can More reflection noise from nearby memory devices 405 is experienced.

Thus, memory device 405 or one or more dies of memory device 405 may be configured with a capacitive element operable to adjust or configure the memory die associated with the capacitive element. Capacitance (such as the capacitance of the I/O pad of the memory die). Capacitive components can reduce noise (eg, reflection noise) at the associated memory device 405 by adjusting the capacitance of one or more memory dies of the memory device 405 . For example, host device 410 may be configured to reduce noise experienced by one or more memory devices 405 by indicating a target capacitance or configuration for capacitive components of memory device 405 . In some cases, the resulting capacitance of the capacitive element (i.e., the capacitance of the capacitive element as adjusted (tuned, configured) by the memory device 405 based on the indication) may decrease from the host device 410 to the memory device. The slew rate of the signal at 405, such as the slew rate at memory device 405, and a reduced slew rate can reduce signal reflections and associated noise.

For example, memory devices farther away from RTT 430 (such as memory devices 405-a and/or 405-b) and memory devices 405 closer to RTT 430 (such as memory devices 405-c and/or 405- d) Can have a higher target capacitance for capacitive components than can be (eg based on associated configuration). Additionally or alternatively, memory devices closer to host device 410 (such as memory devices 405-a and/or 405-b) and memory devices 405 farther away from host device 410 (such as memory devices 405-c and/or or 405-d) may have a higher target capacitance for the capacitive component than (eg, based on the associated configuration).

Host device 410 may signal memory device 405 to indicate a target capacitance or configuration of a capacitive element (e.g., an indication of configuration information, including configuration information, for memory device 405 to store in a mode register). one or more commands). Memory device 405 can receive signals from host device 410 and can configure capacitive components based on the indicated target capacitance or configuration. For example, a controller associated with memory device 405 may activate (close) or deactivate (open) one or more switching components of the capacitive component according to the indicated target capacitance or configuration. When activated, the switching element can couple one or more associated capacitors to the I/O pads of the memory die of the memory device 405, which can change the capacitance of the I/O pads and the memory die ( such as memory die input capacitance). The adjusted capacitance of the I/O pads can configure (set) (e.g., reduce) the slew rate associated with signals received at the memory die and at the memory device 405, and can reduce generation by reflected signals noise. Reducing noise can improve performance at memory device 405, for example, by increasing signal accuracy and voltage margin.

5 illustrates an example of a memory device configuration 500 supporting configurable memory die capacitance according to examples as disclosed herein. In some examples, the memory device configuration 500 can be or include a memory device 505 that includes a plurality of memory dies 510, where the memory dies 510 can be as described with reference to FIGS. 2-4 An example of a memory die and memory device 505 may be an example of the memory device described with reference to FIGS. 3 and 4 . The memory die 510 may include an I/O pad, which may be an example of the I/O pad described with reference to FIGS. 3 and 4 . Memory device 505 may include one or more conductive paths 515 (e.g., traces, wires, conductive lines/layers, etc.), which may be conductive lines or conductive paths as described with reference to FIGS. 2 and 3 instance of . The memory device 505 is operable to adjust (tune, set, configure) the capacitance of one or more memory die 510 (eg, by adjusting or configuring the capacitance of an associated I/O pad).

For example, memory die 510 of memory device 505 may include one or more capacitive elements, where the capacitive elements may be examples of the capacitive elements described with reference to FIGS. 3 and 4 . Each capacitive element can be selectively coupled with an associated I/O pad (e.g., via one or more switching elements of the capacitive element) in order to adjust or configure the capacitance of the I/O pad (e.g., to a target capacitance ). In some cases, the target capacitance of memory die 510 or associated I/O pads may be based on the configuration or topology of one or more memory die 510 relative to each other and/or relative to memory device 505 One or more properties. Additionally or alternatively, the target capacitance of the memory die 510 or associated I/O pads may be based on a configuration or topology of the memory device 505 relative to one or more other memory devices 505 and/or the host device. or multiple features (eg, bus topology for coupling the host device to one or more memory devices 505).

In one example, the memory device 505 can include a host device that can couple the memory device 505 to one or more other memory devices 505 and/or a host device (eg, via one or more traces or other interconnects, Pins 520 (eg, BGA balls, electrodes, pins, pads, etc.) such as described with reference to the example of FIG. 4 . The pin 520 can be coupled to one or more conductive paths 515 of the memory device 505 , wherein the one or more conductive paths 515 can couple the pin to one or more memory die 510 . For example, conductive paths 515 may couple pins 520 to one or more I/O pads corresponding to one or more memory dies 510 . Additionally or alternatively, the conductive path 515 may couple two or more than two memory dies 510 . For example, the conductive path 515 can couple two I/O pads of two corresponding memory dies 510 .

In some cases, the signals from the host device (eg, CA signals) to the memory device 505 may have smaller rise and/or fall times (eg, higher slew rates), which may cause higher levels of noise from adjacent The memory device 505 reflects. Noise levels at the memory device 505 (which may be referred to as or may affect voltage margins or other signaling windows) can be reduced below threshold levels for the memory device 505 (e.g., based on reliability threshold) and may cause timing errors or other adverse effects at the memory device 505.

Thus, one or more dies 510 of the memory device 505 can be configured with capacitive components that can be used to adjust or configure the capacitance of the corresponding memory die 510 (eg, I/O of the memory die 510). O pad capacitance). Additionally or alternatively, the capacitive components of one memory die 510 may be used to adjust or configure the capacitance of one or more other memory dies 510 (e.g., splitting the input between one or more other memory dies 510 capacitor, coupled with one or more other memory die 510). For example, the capacitive components of memory die 510-a are operable to adjust or configure memory dies 510-a and 510-b or memory dies 510-a, 510-b, and 510-c. Capacitor (eg, the capacitive element can be (eg, selectively) coupled to the I/O pins of the memory die 510-b and/or 510-c). The one or more capacitive elements are operable to reduce noise (eg, reflection noise) at the memory device 505 by adjusting the capacitance of one or more memory dies 510 of the memory device 505 . For example, a host device can be configured to reduce the noise experienced by the memory device 505 by indicating a target capacitance or configuration for a capacitive component of one or more memory dies 510 of the memory device 505. News. In some cases, the resulting capacitance associated with the capacitive element (i.e., the capacitance of the capacitive element as adjusted (tuned, configured) by the memory device 505 based on the indication) may decrease from the host device to the memory The slew rate of the signal of the body device 505, such as the slew rate at the memory device 505, and the reduced slew rate can reduce signal reflections and associated noise.

In some cases, the host device may signal the memory device 505 to indicate a target capacitance or configuration of one or more capacitive components (e.g., for configuration information stored by the memory device 505 in a mode register). instructions, one or more commands containing configuration information). The memory device 505 can receive a signal from the host device and can configure one or more capacitive components based on the indicated target capacitance or configuration. For example, a controller associated with memory device 505 may activate (close) or deactivate (open) one or more switching components of the capacitive component according to the indicated target capacitance or configuration. When activated, the switching component can couple one or more associated capacitors to one or more I/O pads of one or more memory dies 510 of memory device 505, which can change the one or more I/O pads and the capacitance (eg, input capacitance) of the one or more memory dies 510 . The adjusted capacitance of one or more I/O pads may configure (set) (e.g., reduce) the slew rate associated with signals received at one or more memory die 510 and at memory device 505 , and can reduce the noise generated by the reflected signal. Reducing noise can improve device performance by increasing signaling accuracy and margins, such as voltage margins.

6 illustrates an example of a process flow 600 for supporting configurable memory die capacitance according to examples as disclosed herein. In some examples, program flow 600 may be implemented by memory device 605 and a host device, which may be examples of the memory device and host device described with reference to FIGS. 3-5 . Memory device 605 may include one or more memory dies with one or more corresponding I/O pads, and memory device 605 may be operable to adjust or configure the capacitance of one or more memory dies ( For example by adjusting or configuring the capacitance of the associated I/O pad). For example, the host device 610 may instruct the memory device 605 to configure or adjust the capacitance of one or more memory dies.

In the following description of program flow 600, operations between memory device 605 and host device 610 may be transmitted in a different order than shown, or operations performed by host device 610 or memory device 605 may be in a different order or Execute at different times. Certain operations may also be omitted from program flow 600 , or other operations may be added to program flow 600 . Although host device 610 and memory device 605 are shown as performing the operations of program flow 600, some aspects of some operations may also be performed by another device.

At 615, host device 610 may identify the capacitive components of memory device 605 based on the target capacitance associated with the I/O pads of memory device 605 (e.g., associated with a memory die of memory device 605). target configuration. In some cases, host device 610 may determine based on a target capacitance associated with one or more I/O pads of memory device 605 (e.g., associated with one or more memory dies of memory device 605). A target configuration for one or more capacitive components of memory device 605 is identified. The target capacitance may be based on the location of the memory device 605 relative to the host device 610 or relative to one or more impedances associated with a bus bar coupling the host device 610 and the memory device 605 .

The host device can also identify a second target configuration of a second capacitive component of the second memory device based on a second target capacitance associated with a second I/O pad of the second memory device. The second target capacitance may be different from the target capacitance and may be based on the second memory device relative to the host device 610 or relative to the bus bar coupling the host device 610 and the second memory device (e.g., coupling the host device 610, memory The location of one or more impedances associated with device 605 and the bus bar of the second memory device).

At 620, host device 610 may transmit configuration information to memory device 605 based on identifying the target configuration. The host device 610 may also transmit second configuration information indicating the second target configuration to the second memory device based on identifying the second target configuration. In some examples, the configuration information (eg, or second configuration information) may include a target configuration of a capacitive element of memory device 605 (eg, or second memory device). Additionally or alternatively, the configuration information may include a target capacitance for a capacitive component of memory device 605 (eg, or a second memory device). In some cases, the configuration information may include an indication of the configuration information stored in the mode register by the memory device 605 or one or more commands including the configuration information.

At 625, the memory device 605 can configure the capacitance of the I/O pads of the memory device 605 based on the configuration information. For example, as described with reference to FIGS. or multiple I/O pads. In some cases, the memory device 605 can configure the capacitance of the I/O pads by configuring the capacitive elements (eg, according to a target configuration or target capacitance). For example, a controller associated with the memory device 605 can activate (close) or deactivate (open) the capacitive component or one or more switching components based on the configuration information. In some examples, memory device 605 may store the received configuration information to one or more mode registers of memory device 605 and may be based on storing the configuration information to one or more mode registers Configure capacitive components.

In some cases, memory device 605 may identify a target configuration for one or more capacitive components of memory device 605 based on a target capacitance associated with one or more I/O pads of memory device 605 . Thus, the memory device can configure the capacitance of the I/O pads of the memory device 605 based on the identified configuration.

At 630 , under some conditions, memory device 605 may transmit an indication of the capacitance of the configured I/O pads to host device 610 .

At 635, host device 610 may transmit signaling to memory device 605 via the I/O pads (eg, after transmitting the configuration information and after memory device 605 has configured the capacitance of the I/O pads). In some cases, the signaled slew rate (eg, the signaled slew rate at memory device 605 ) may be based on configuration information (eg, based on the configuration of one or more capacitive components of memory device 605 ). For example, the slew rate of signals from host device 610 to memory device 605 may be adjusted (eg, reduced) based on the capacitance of a capacitive element adjusted (tuned, configured), as indicated by memory device 605 .

In some examples, the slew rate can be reduced by the configuration of one or more capacitive elements, and the lower slew rate can reduce reflection noise at the memory device 605 . Noise reduction at the memory device 605 can improve device performance by increasing signaling accuracy and thereby reducing latency and improving reliability.

7 shows a block diagram 700 of a memory device 705 supporting configurable memory die capacitance according to examples as disclosed herein. Memory device 705 may be an example of aspects of a memory device as described with reference to FIGS. 3-6 . The memory device 705 may include a configuration information receiving component 710 , a capacitor configuration component 715 and a signal receiving component 720 . Each of these modules can communicate with each other directly or indirectly (eg, via one or more bus bars).

The configuration information receiving component 710 can receive, at the memory device, configuration information associated with a target capacitance of an I/O pad of the memory device. In some cases, the configuration information indicates the configuration of the capacitive component.

The capacitance configuration component 715 can configure the capacitance of the I/O pads at the memory device based on the configuration information. In some examples, configuring the capacitance of the I/O pad includes configuring a capacitive element. In some examples, the capacitive configuration component 715 can store the configuration information in one or more mode registers. In some examples, capacitive configuration component 715 may configure capacitive components based on storing configuration information to one or more mode registers. In some examples, capacitance configuration component 715 can transmit an indication of the configured capacitance of the I/O pad to the host device after configuring the capacitance of the I/O pad. In some cases, memory devices include capacitive elements having adjustable capacitance and coupled to I/O pads.

The signal receiving component 720 can receive signaling from the host device via the I/O pad after configuring the capacitance of the I/O pad.

8 shows a block diagram 800 of a host device 805 supporting configurable memory die capacitance according to examples as disclosed herein. Host device 805 may be an example of aspects of a host device as described with reference to FIGS. 3-6 . The host device 805 can include a capacitive configuration component 810 , a configuration information transmission component 815 and a signal transmission component 820 . Each of these modules can communicate with each other directly or indirectly (eg, via one or more bus bars).

Capacitive configuration component 810 can identify a target configuration for a capacitive component of a memory device based on a target capacitance associated with an I/O pad of the memory device. In some examples, capacitive configuration element 810 may identify a second capacitive element of the second memory device based on a second target capacitance associated with a second I/O pad of the second memory device. A target configuration, where the second target capacitance may be different from the target capacitance.

The configuration information transfer component 815 can transfer configuration information indicative of the target configuration to the memory device based on identifying the target configuration. In some examples, the configuration information transmitting component 815 can transmit the second configuration information indicative of the second target configuration to the second memory device based on identifying the second target configuration.

The signal transmission component 820 can transmit the signal to the memory device through the I/O pad after transmitting the configuration information. In some cases, the signaled slew rate is based on configuration information.

9 shows a flowchart illustrating one or more methods 900 of supporting configurable memory die capacitances in accordance with aspects of the present invention. The operations of method 900 may be implemented by a memory device or components thereof as described herein. For example, the operations of method 900 may be performed by a memory device as described with reference to FIG. 7 . In some examples, a memory device can execute a set of instructions to control functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may employ special purpose hardware to perform aspects of the described functions.

At 905, the memory device can receive at the memory device configuration information associated with a target capacitance of an I/O pad of the memory device. The operation of 905 may be performed according to the methods described herein. In some examples, aspects of the operation of 905 may be performed by a configuration information receiving component as described with reference to FIG. 7 .

At 910, the memory device can configure the capacitance of the I/O pad at the memory device based on the configuration information. The operation of 910 may be performed according to methods described herein. In some examples, aspects of the operation of 910 may be performed by capacitively configured components as described with reference to FIG. 7 .

At 915, the memory device may receive signaling from the host device via the I/O pad after configuring the capacitance of the I/O pad. The operation of 915 may be performed according to methods described herein. In some examples, aspects of the operation of 915 may be performed by signal receiving components as described with reference to FIG. 7 .

In some examples, an apparatus as described herein may perform one or more methods, such as method 900 . The apparatus may include means for receiving, at the memory device, configuration information associated with a target capacitance of an I/O pad of the memory device, configuring the I/O pad at the memory device based on the configuration information Capacitance and receive a signaled feature, component or instruction (eg, a non-transitory computer-readable medium storing instructions executable by a processor) from a host device via the I/O pad after configuring the capacitance of the I/O pad. In some examples of method 900 and apparatus described herein, a memory device may include a capacitive element having an adjustable capacitance coupled to an I/O pad, and configuring the capacitance of the I/O pad may include setting The capacitive device can be configured, and the configuration information can indicate the configuration of the capacitive device.

Method 900 and some examples of the apparatus described herein may further include storing configuration information to one or more mode registers and configuring based on storing configuration information to one or more mode registers An operation, feature, component or instruction of a capacitive component. Some examples of the method 900 and apparatus described herein may further include operations for transmitting an indication of the configurable capacitance of the I/O pad to the host device after the configuration of the capacitance of the I/O pad, features , component or directive.

FIG. 10 shows a flowchart illustrating one or more methods 1000 of supporting configurable memory die capacitance in accordance with aspects of the present invention. The operations of method 1000 may be implemented by a memory device or components thereof as described herein. For example, the operations of method 1000 may be performed by a memory device as described with reference to FIG. 7 . In some examples, a memory device can execute a set of instructions to control functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may employ special purpose hardware to perform aspects of the described functions.

At 1005, the memory device can receive, at the memory device, configuration information associated with a target capacitance of an I/O pad of the memory device. The operation of 1005 may be performed according to the methods described herein. In some examples, aspects of the operation of 1005 may be performed by a configuration information receiving component as described with reference to FIG. 7 .

At 1010, the memory device may configure the capacitance of the I/O pad at the memory device based on the configuration information. The operations of 1010 may be performed according to methods described herein. In some examples, aspects of the operation of 1010 may be performed by capacitively configured components as described with reference to FIG. 7 .

At 1015, the memory device may store configuration information to one or more mode registers. The operation of 1015 may be performed according to the methods described herein. In some examples, aspects of the operation of 1015 may be performed by capacitively configured components as described with reference to FIG. 7 .

At 1020, the memory device can configure the capacitive device based on storing configuration information to one or more mode registers. The operation of 1020 may be performed according to the methods described herein. In some examples, aspects of the operation of 1020 may be performed by capacitively configured components as described with reference to FIG. 7 .

At 1025, the memory device may receive signaling from the host device via the I/O pad after configuring the capacitance of the I/O pad. The operation of 1025 may be performed according to the methods described herein. In some examples, aspects of the operation of 1025 may be performed by a signal receiving component as described with reference to FIG. 7 .

11 shows a flowchart illustrating one or more methods 1100 of supporting configurable memory die capacitance in accordance with aspects of the present invention. The operations of method 1100 may be implemented by a host device or components thereof as described herein. For example, the operations of method 1100 may be performed by a host device as described with reference to FIG. 8 . In some examples, a host device can execute a set of instructions to control functional elements of the host device to perform the described functions. Additionally or alternatively, the host device may use special purpose hardware to perform aspects of the described functions.

At 1105, the host device can identify a target configuration of capacitive components of the memory device based on the target capacitance associated with the I/O pads of the memory device. The operation of 1105 may be performed according to the methods described herein. In some examples, the aspect of operation of 1105 may be performed by a capacitive component configuration as described with reference to FIG. 8 .

At 1110, the host device may transmit configuration information indicative of the target configuration to the memory device based on identifying the target configuration. The operations of 1110 may be performed according to methods described herein. In some examples, aspects of the operation of 1110 may be performed by configuring information transfer components as described with reference to FIG. 8 .

At 1115, the host device may transmit signaling to the memory device via the I/O pad after transmitting the configuration information. The operation of 1115 may be performed according to methods described herein. In some examples, aspects of the operation of 1115 may be performed by signaling components as described with reference to FIG. 8 .

In some examples, an apparatus as described herein may perform one or more methods, such as method 1100 . The apparatus may include for identifying a target configuration of a capacitive component of a memory device based on a target capacitance associated with an I/O pad of the memory device, a configuration that will indicate the target configuration based on identifying the target configuration A feature, component, or instruction (such as a non-transitory computer-readable medium that stores instructions executable by a processor) that transmits information to a memory device and, after transmitting configuration information, signals to the memory device via an I/O pad ). In some examples of the method 1100 and apparatus described herein, the signaled slew rate can be based on configuration information.

It should be noted that the methods described herein are possible implementations, and that operations and steps may be reconfigured or otherwise modified, and that other implementations are possible. Additionally, portions from two or more of these methods may be combined.

Describe a device. The device may include a memory die including: an I/O pad; an input buffer included in the memory die, the input buffer coupled to the I/O pad and having an adjustable capacitance and including a capacitive element in the memory die, the capacitive element is coupled with the I/O pad.

In some examples, the capacitive component includes a capacitor and a switching component operable to selectively couple the capacitor with the I/O pad. In some examples, the capacitive element includes a set of capacitors and a set of switching elements, each respective switching element of the set operable to selectively couple a respective capacitor of the set to the I/O pad catch. Some examples of the apparatus may include: a mode register operable to store one or more logical values; and a controller operable to cause the apparatus to configure the capacitor based on the one or more logical values A capacitive element may have one of a set of capacitances supported by the capacitive element.

In some examples, the capacitive component includes a set of switching components, and the one or more logical values indicate a quantity of the set of switching components for closing the controller. In some examples, the capacitive element includes a set of switching elements; and the one or more logical values include a bitmap, each bit of the bitmap indicates whether the controller can turn on or turn off the set of switching elements One of them switches components individually.

Some examples of the apparatus may include a controller coupled to the capacitive component and operable to configure the data received via the I/O pad based on configuring the adjustable capacitance of the capacitive component. One slew rate of one signal.

Some examples of the device may include a second memory die including a second I/O pad and a second capacitive element having a second adjustable capacitance And coupled with the second I/O pad.

Describe a system. The system may include a memory device and a host device coupled to the memory device. The memory device may include a memory die including an I/O pad and a capacitive element having an adjustable capacitance coupled to the I/O pad. The host device is operable to provide configuration information to the memory device, and the memory device is operable to configure the adjustable capacitance of the capacitive element based on the configuration information.

In some examples, the capacitive element of the memory device includes one or more capacitors and one or more switching elements, wherein each of the one or more switching elements is operable to switch the one or more A respective one of the capacitors is selectively coupled to the I/O pad. In some examples, the host device is operable to provide the configuration information based on issuing a command to the memory device indicating the configuration information. In some examples, a slew rate of a signal transmitted from the host device to the memory device is based on the adjustable capacitance of the capacitive element.

Some examples of the memory device may include a mode register, wherein the memory device is operable to configure the adjustable of the capacitive element based on one or more logic values stored in the mode register capacitance. In some examples, the host device is operable to provide the configuration information based on transmitting an indication of the one or more logical values to the memory device, and the memory device is operable to transmit an indication of the one or more logical values to the memory device based on the indication. or multiple logical values are stored in the mode register.

Some examples of the memory device may include an input buffer coupled to the I/O pad. Some examples of the memory device may include one or more additional memory die, each including a respective I/O pad. In some examples, the memory device is operable to couple the capacitive element to the respective I/O pad of at least one of the one or more additional memory dies. Some examples of the system may include one or more additional memory devices each including a respective memory die including a respective I/O pad and a respective capacitive element . In some examples, the respective capacitive element can have a respective adjustable capacitance and can be coupled with the respective I/O pad. In some examples, the single I/O pad of the host device and the separate I/O pads of each of the one or more additional memory devices comprising the I/O pad of the memory device A plurality of I/O pads of the pad are coupled.

In some examples of the system, the capacitive component of the memory device can be configured to have a first capacitance and be included in one of the second memory devices of the one or more additional memory devices The second capacitive component can be configured to have a second capacitance. In some examples, the memory device may be closer to the host device than the second memory device and the first capacitance may be greater than the second capacitance. In some examples of the system, the system can further include a terminating impedance for a bus coupled with the host device, the memory device, and the second memory device, wherein the memory device can be compared to the second memory device The second memory device is further away from the terminal impedance, and wherein the first capacitance can be larger than the second capacitance.

The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some of the figures may illustrate the signal as a single signal; however, one of ordinary skill in the art will understand that the signal may represent a bus of signals, where the bus may be of various bit widths.

The terms "electronically communicate," "conductive contact," "connect" and "couple" may refer to a relationship between components that enables the flow of signals between components. Components are considered to be in electronic communication with each other (or to be in conductive contact or connected to or coupled to each other) if there is any conductive path between the components that can at any time support the flow of signals between the components. At any given time, a conductive path between components that are in electronic communication with each other (or are in conductive contact with each other or connected or coupled to each other) can be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between connected components may be a direct conductive path between components, or the conductive path between connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some cases, signal flow between connected components may be interrupted for a period of time, eg, using one or more intermediate components such as switches or transistors.

The term "coupled" refers to the transition from an open circuit relationship between components in which signals are not currently capable of being communicated between components via conductive paths to a closed circuit relationship between components in which signals can be communicated between components via conductive paths. Move condition. When a component such as a controller couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that previously did not permit signal flow.

The term "isolation" refers to a relationship between components in which signals are not currently able to flow between those components. If there is an open circuit between components, the components are isolated from each other. For example, two components separated by a switch positioned between the components are isolated from each other when the switch is open. When the controller isolates two components, the controller effects a change that prevents signals from flowing between the components using conductive paths that previously permitted signal flow.

As used herein, the term "layer" refers to a layer or sheet of a geometric structure. Each layer can have three dimensions (eg, height, width, and depth) and can cover at least a portion of the surface. For example, a layer can be a three-dimensional structure, where two dimensions are greater than the third, such as a film. Layers may comprise different elements, components and/or materials. In some cases, a layer may consist of two or more sub-layers. In some of the accompanying figures, two dimensions of a three-dimensional layer are depicted for purposes of illustration.

As used herein, the term "electrode" may refer to an electrical conductor, and in some cases may serve as an electrical contact to a memory cell or other component of a memory array. The electrodes may include traces, wires, conductive lines, conductive layers, or the like that provide conductive paths between elements or components of the memory array.

Devices including memory arrays discussed herein can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled through doping with various chemistries including but not limited to phosphorous, boron or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other means of doping.

A switching element or transistor as discussed herein may represent a field effect transistor (FET) and includes a three terminal device including a source, a drain and a gate. The terminals can be connected to other electronic components via conductive materials such as metals. The source and drain can be conductive and can include heavily doped (eg, altered) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (ie, most of the carrier is a signal), the FET may be referred to as an n-type FET. If the channel is p-type (ie, most of the carrier is a hole), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. A transistor can be "turned on" or "activated" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the gate of the transistor. A transistor can be "turned off" or "deactivated" when a voltage less than the threshold voltage of the transistor is applied to the gate of the transistor.

The description set forth herein in conjunction with the drawings describes example configurations and does not represent all examples that may be implemented or that are within the scope of the claimed claims. As used herein, the term "exemplary" means "serving as an example, instance, or illustration," and does not mean "preferred" or "over other examples." The detailed description includes specific details to provide an understanding of the described technology. However, such techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

In the drawings, similar components or features may have the same reference label. Further, various components of the same type can be distinguished by following the reference label by a dash and a second label that distinguishes among similar components. If only a first reference label is used in the specification, the description applies to any of similar components having the same first reference label independently of the second reference label.

The various illustrative blocks and modules described in connection with the invention herein may use a general purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or designed Implemented or performed in any combination that performs the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (eg, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, functions described can be implemented using software executed by a processor, hardware, firmware, hardwiring or combinations of any of these. Features implementing functions may also be physically located at various locations, including being distributed such that portions of functions are performed at different physical locations. Also, as used herein (including in claims), "or" is used in lists of items (for example, beginning with phrases such as "at least one of" or "one or more of" list of items) indicates an inclusive list such that, for example, a list of at least one of A, B or C means A or B or C or AB or AC or BC or ABC (that is, A and B and C). Furthermore, as used herein, the phrase "based on" should not be taken as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the invention. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a general purpose or special purpose computer. By way of example and not limitation, non-transitory computer readable media may include RAM, ROM, Electrically Erasable Programmable Read Only Memory (EEPROM), Compact Disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage device, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer or general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable Wire, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, Optical discs reproduce data optically by means of lasers. Combinations of the above are also included within the scope of computer-readable media.

The description herein is provided to enable any person skilled in the art to make or use the invention. Various modifications to this invention will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other changes without departing from the scope of the invention. Thus, the invention is not to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

100: System 105: External Memory Controller 110: Memory Device 115: Channel 120: Processor 125: Basic Input/Output System (BIOS) Components 130: Peripheral Components 135: Input/Output (I/O) Controller 140 : bus bar 145: input device/input 150: output device/output 155: device memory controller 160-a: memory die 160-b: memory die 160- N : memory die 165-a: Local memory controller 165-b: local memory controller 165- N : local memory controller 170-a: memory array 170-b: memory array 170- N : memory array 186: command /Address (CA) channel 188: clock signal (CK) channel 190: data (DQ) channel 192: other channels 200: memory grain 205: memory cell 210: word line 215: digital line 220: row Decoder 225: row decoder 230: capacitor 235: switching component 240: voltage source 245: sensing component 250: reference signal 255: input/output 260: local memory controller 300: circuit 305: input/output (I /0) pad 310: input buffer 315: capacitive component 320-a: capacitor 320-b: capacitor 320-c: capacitor 325-a: switching component 325-b: switching component 325-c: switching component 330: Conductive path 400: busbar topology 405-a: memory device 405-b: memory device 405-c: memory device 405-d: memory device 405-e: memory device 410-a: host device 415 -a: common trunk 420-a:trace 420-b:trace 420-c:trace 420-d:trace 420-e:trace 425-a:branch line 425-b:branch line 425-c : branch line 425-d: branch line 425-e: branch line 430: terminal resistor (RTT) 500: memory device configuration 505: memory device 510-a: memory crystal grain 510-b: memory crystal grain Grain 510-c: memory die 515: conductive path 520: pin 600: program flow 605: memory device 610: host device 615: operation 620: operation 625: operation 630: operation 635: operation 700: block diagram 705 : memory device 710: configuration information receiving component 715: capacitor configuration component 720: signal receiving component 800: block diagram 805: host device 810: capacitive configuration component 815: configuration information transmission component 820: signal transmission component 900 :method 905:op 910:op 915:op 1000:method 1005:op 1010:op 1015:op 1020:op 1025:op 1100:method 1105:op 1110:op 1115:op DL _1: Digit line DL_2: Digit line DL_3: Digit line DL_N: Digit line Vpl: Cell plate reference voltage WL_1: Word line WL_2: Word line WL_M: Word line

1 illustrates an example of a system supporting configurable memory die capacitance according to examples as disclosed herein.

2 illustrates an example of a memory die supporting configurable memory die capacitance according to examples as disclosed herein.

3 illustrates an example of a circuit supporting configurable memory die capacitance according to examples as disclosed herein.

4 illustrates an example of a bus topology to support configurable memory die capacitance according to examples as disclosed herein.

5 illustrates an example of a memory device configuration supporting configurable memory die capacitance according to examples as disclosed herein.

6 illustrates an example of a program flow to support configurable memory die capacitance according to examples as disclosed herein.

7 shows a block diagram of a memory device supporting configurable memory die capacitance according to aspects of the present invention.

8 shows a block diagram of a host device supporting configurable memory die capacitors according to aspects of the invention.

9-11 show flowcharts illustrating one or more methods of supporting configurable memory die capacitance according to examples as disclosed herein.

300: circuit

305: Input/Output (I/O) Pad

310: input buffer

315: capacitive components

320-a: Capacitor

320-b: Capacitor

320-c: Capacitor

325-a: Toggle component

325-b: Toggle components

325-c: Toggle Components

330: Conductive path

Claims (29)

A memory device comprising: a memory die including: an input/output (I/O) pad; an input buffer included in the memory die, the input buffer a device coupled with the I/O pad; and a capacitive element having an adjustable capacitance and included in the memory die, the capacitive element coupled with the I/O pad. The memory device of claim 1, wherein the capacitive element comprises a capacitor and a switching element operable to selectively couple the capacitor to the I/O pad. The memory device as claimed in claim 1, wherein the capacitive element includes a plurality of capacitors and a plurality of switching elements, each individual switching element in the plurality of switching elements is operable to individually separate one of the plurality of capacitors A capacitor is selectively coupled to the I/O pad. The memory device of claim 1, further comprising: a mode register operable to store one or more logic values; and a controller operable to cause the device to be based at least in part on the one or more logical values Logical values configure the capacitive element to have one of a plurality of capacitances supported by the capacitive element. Such as the memory device of claim 4, wherein: The capacitive element includes a plurality of switching elements; and the one or more logical values indicate a quantity of one of the plurality of switching elements for closing the controller. The memory device as claimed in claim 4, wherein: the capacitive element includes a plurality of switching elements; and the one or more logic values include a bitmap, and each bit of the bitmap indicates whether the controller is turned on or One of the plurality of switching components is closed respectively. The memory device of claim 1, further comprising: a controller coupled to the capacitive element and operable to configure the adjustable capacitance via the I based at least in part on configuring the adjustable capacitance of the capacitive element The slew rate of a signal received by the /O pad. The memory device of claim 1, further comprising: a second memory die comprising a second I/O pad and a second capacitive element, the second capacitive element has a second The capacitance is adjusted and coupled with the second I/O pad. A memory system comprising: a memory device comprising: a memory die comprising an input/output (I/O) pad; and a capacitive element having an adjustable capacitor and coupled with the I/O pad; and a host device coupled with the memory device, wherein: The host device is operable to provide configuration information to the memory device; and the memory device is operable to configure the adjustable capacitance of the capacitive element based at least in part on the configuration information. As the memory system of claim 9, wherein the capacitive element of the memory device includes one or more capacitors and one or more switching elements, each of the one or more switching elements is operable to the A respective one of the one or more capacitors is selectively coupled to the I/O pad. The memory system of claim 9, wherein the host device is operable to provide the configuration information based at least in part on issuing a command to the memory device indicating the configuration information. The memory system of claim 9, wherein the memory device further comprises a mode register, and wherein the memory device is operable based at least in part on one or more logical values stored in the mode register to configure the adjustable capacitance of the capacitive component. The memory system of claim 12, wherein: the host device is operable to provide the configuration information based at least in part on transmitting an indication of the one or more logical values to the memory device; and the memory device is operable to store the one or more logical values in the mode register based at least in part on the indication. The memory system according to claim 9, wherein the memory device further comprises an input buffer coupled to the I/O pad. The memory system of claim 9, wherein the memory device further comprises one or more additional memory dies, and each of the one or more additional memory dies comprises a respective I/O pad. The memory system of claim 15, wherein the memory device is operable to couple the capacitive element to the respective I/O pad of at least one of the one or more additional memory dies. As the memory system of claim 9, it further comprises: one or more additional memory devices, each of which includes a respective memory die, the respective memory die includes a respective I/O pad and A respective capacitive element having a respective adjustable capacitance coupled to the respective I/O pad. The memory system of claim 17, wherein: the capacitive component of the memory device is configured to have a first capacitance; and one of the one or more additional memory devices includes a second memory device A second capacitive component of is configured to have a second capacitance. The memory system of claim 18, wherein: the memory device is closer to the host device than the second memory device; and the first capacitance is greater than the second capacitance. The memory system of claim 18, further comprising: a pool for coupling with the host device, the memory device, and the second memory device A terminal impedance of the current bank, wherein the memory device is farther from the terminal impedance than the second memory device, and wherein the first capacitance is greater than the second capacitance. The memory system of claim 17, wherein a single I/O pad of the host device is connected to each of the I/O pad including the memory device and the one or more additional memory devices A plurality of I/O pads of the respective I/O pads are coupled. The memory system of claim 9, wherein a slew rate of a signal transmitted from the host device to the memory device is based at least in part on the adjustable capacitance of the capacitive element. A method for memory operations, comprising: receiving, at a memory device, configuration information associated with a target capacitance of an input/output (I/O) pad of the memory device; configuring a capacitance of the I/O pad based at least in part on the configuration information at the host device; and receiving a signal from a host device via the I/O pad after configuring the capacitance of the I/O pad letter. The method of claim 23, wherein: the memory device includes a capacitive element having an adjustable capacitance coupled to the I/O pad; configuring the capacitance of the I/O pad includes configuring the a capacitive component; and the configuration information indicates a configuration of the capacitive component. The method of claim 24, further comprising: storing the configuration information to one or more mode registers; and configuring at least in part based on storing the configuration information to the one or more mode registers state the capacitive component. The method of claim 23, further comprising: transmitting an indication that the capacitance of the I/O pad has been configured to the host device after configuring the capacitance of the I/O pad. A method for memory operations comprising: identifying a capacitive component of a memory device based at least in part on a target capacitance associated with an input/output (I/O) pad of the memory device a target configuration; based at least in part on identifying the target configuration, transmitting configuration information indicative of the target configuration to the memory device; and transmitting the transmitted configuration information via the I/O pad after transmitting the configuration information The message is transferred to the memory device. The method of claim 27, further comprising: identifying a second memory device based at least in part on a second target capacitance associated with a second input/output (I/O) pad of the second memory device A second target configuration of a second capacitive component of the bulk device, wherein the second target capacitance is different from the target capacitance; and based at least in part on identifying the second target configuration will indicate the second target configuration The second configuration information is transmitted to the second memory device. The method of claim 27, wherein the signaling of a slew rate is based at least in part on the configuration information.

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