TWI780481B - Configurable memory die capacitance - Google Patents

Configurable memory die capacitance Download PDF

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TWI780481B
TWI780481B TW109131002A TW109131002A TWI780481B TW I780481 B TWI780481 B TW I780481B TW 109131002 A TW109131002 A TW 109131002A TW 109131002 A TW109131002 A TW 109131002A TW I780481 B TWI780481 B TW I780481B
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memory
memory device
capacitance
pad
capacitive
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TW202211229A (en
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程景偉
張成
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美商美光科技公司
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Abstract

Methods, systems, and devices for configurable memory die capacitance are described. A memory device may include a capacitive component, which may include one or more capacitors and associated switching components. The capacitive component may be coupled with an input/output (I/O) pad and an associated input buffer, and the one or more capacitors of the capacitive component may be selectively couplable with the I/O pad via the switching components. Switching components may be activated individually, in coordination, or not at all, such that one, multiple, or none of the capacitors may be coupled with the I/O pad. The capacitive component, I/O pad, and input buffer may be included in a same die of the memory device. In some cases, a configuration of the capacitive component may be based on signaling received from a host device.

Description

可組態之記憶體晶粒電容Configurable memory die capacitance

下文大體而言係關於一種包括至少一個記憶體裝置之系統,且更特定言之,係關於可組態之記憶體晶粒電容。The following relates generally to a system including at least one memory device, and more particularly to configurable memory die capacitance.

記憶體裝置廣泛地用於在諸如電腦、無線通信裝置、攝影機、數位顯示器及其類似者之各種電子裝置中儲存資訊。藉由程式化記憶體裝置之不同狀態來儲存資訊。舉例而言,二進位裝置最常儲存兩個狀態中之一者,常常由邏輯1或邏輯0表示。在其他裝置中,可儲存多於兩個狀態。為了存取所儲存資訊,裝置之組件可讀取或感測記憶體裝置中之至少一個所儲存狀態。為了儲存資訊,裝置之組件可在記憶體裝置中寫入或程式化狀態。Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Store information by programming different states of a memory device. For example, binary devices most often store one of two states, often represented by a logical one or a logical zero. In other devices, more than two states may be stored. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of a device may write or program state in a memory device.

存在各種類型之記憶體裝置,包括磁性硬碟機、隨機存取記憶體(RAM)、唯讀記憶體(ROM)、動態RAM (DRAM)、同步動態RAM (SDRAM)、鐵電RAM (FeRAM)、磁性RAM (MRAM)、電阻式RAM (RRAM)、快閃記憶體、相變記憶體(PCM)及其他者。記憶體裝置可為揮發性的或非揮發性的。即使在不存在外部電源的情況下,非揮發性記憶體,例如FeRAM亦可維持其所儲存邏輯狀態歷時擴展之時間段。揮發性記憶體裝置,例如DRAM,在與外部電源斷開連接時可能丟失其所儲存狀態。Various types of memory devices exist, including magnetic hard drives, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM) , Magnetic RAM (MRAM), Resistive RAM (RRAM), Flash Memory, Phase Change Memory (PCM), and others. Memory devices can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices, such as DRAM, may lose their stored state when disconnected from an external power source.

一些系統可包括與主機裝置耦接之一或多個記憶體裝置,其中該等記憶體裝置可向主機裝置提供資料儲存或其他記憶體能力。在一些狀況下,主機裝置與關聯記憶體裝置之間的傳信可經歷干擾或雜訊,此可使系統之效能降級。Some systems may include one or more memory devices coupled to a host device, where the memory devices may provide data storage or other memory capabilities to the host device. Under some conditions, the communication between the host device and the associated memory device can experience interference or noise, which can degrade the performance of the system.

記憶體裝置可經組態以與主機裝置交換信號,且在一些狀況下,在記憶體裝置與主機裝置之間交換之信號可經歷干擾(例如雜訊、串擾及其類似者)。舉例而言,歸因於記憶體裝置與主機裝置之間的反射,或歸因於與亦可與主機裝置耦接(例如經由與記憶體裝置共同之匯流排)之其他記憶體裝置相關聯的其他信號或反射或歸因於一般熟習此項技術者可瞭解的其他原因,可出現干擾。A memory device can be configured to exchange signals with a host device, and under some circumstances, the signals exchanged between the memory device and the host device can experience interference (eg, noise, crosstalk, and the like). For example, due to reflections between the memory device and the host device, or due to associations with other memory devices that may also be coupled to the host device (e.g., via a bus common to the memory device) Interference may occur from other signals or reflections or due to other causes known to those of ordinary skill in the art.

在一些狀況下,增加主機裝置與一或多個記憶體裝置之間的傳信之轉換速率(例如縮短上升及下降時間)可提供各種益處或與之相關,諸如與較高速度(例如較高頻率)傳信相關聯的增加之資料速率。然而,增加轉換速率可增加系統內之干擾量(例如歸因於較高頻率諧波及增加之電容性串擾,或一般熟習此項技術者可瞭解的其他原因)。另外或替代地,增加轉換速率可減低用於在記憶體裝置處解譯信號之電壓裕度(例如關於用於解碼傳信之資料窗,其亦可被稱作眼睛窗)。在一些狀況下,減小如由主機裝置傳輸至一或多個記憶體裝置之信號之轉換速率可為非所要的或不被主機裝置所支援。In some cases, increasing the slew rate (e.g., shortening rise and fall times) of signaling between the host device and one or more memory devices may provide or be associated with various benefits, such as those associated with higher speeds (e.g., higher frequency ) signaling the associated increased data rate. Increasing the slew rate, however, can increase the amount of interference within the system (eg, due to higher frequency harmonics and increased capacitive crosstalk, or other reasons known to those of ordinary skill in the art). Additionally or alternatively, increasing the slew rate may reduce the voltage margin for interpreting signals at the memory device (eg, with respect to the data window used to decode signaling, which may also be referred to as the eye window). In some cases, reducing the slew rate of signals as transmitted by the host device to one or more memory devices may be undesirable or not supported by the host device.

然而,如本文中所描述,藉由在記憶體裝置處包括可組態(例如可調整、可調諧)電容,可減輕如由記憶體裝置觀測到的信號反射及其他干擾源。可組態之電容可包括於記憶體裝置內之記憶體晶粒中(例如可組態於晶粒電容上),此可避免可能造成佈局或其他空間問題的對裝置外部之電容器之需求,以及具有其他益處。記憶體裝置處之可組態之電容可經組態為具有一電容,該電容減輕由於例如與其他記憶體裝置相關聯之信號反射引起的反射及其他干擾源,該等其他記憶體裝置經由共同匯流排(例如使用飛躍式匯流排拓樸) (諸如共同命令/位址(CA)匯流排)與該記憶體裝置及主機裝置耦接。However, by including configurable (eg, adjustable, tunable) capacitance at the memory device, as described herein, signal reflections and other sources of interference as observed by the memory device can be mitigated. Configurable capacitance can be included in the memory die within the memory device (e.g., can be configured on-die capacitance), which avoids the need for capacitors external to the device that could cause layout or other space issues, and have other benefits. The configurable capacitance at the memory device can be configured to have a capacitance that mitigates reflections and other sources of interference due to, for example, signal reflections associated with other memory devices via a common A bus (eg, using a leap bus topology), such as a common command/address (CA) bus, couples the memory device and the host device.

舉例而言,記憶體裝置可包含可組態之電容性組件,該可組態之電容性組件之電容可為可調整的(可調諧的)以便調整或組態與包括於記憶體晶粒中之I/O襯墊相關聯之電容。該電容性組件可包括一或多個電容器及一或多個關聯切換組件(例如電晶體)。切換組件可與一或多個各別電容器相關聯,且電容性組件之一或多個電容器與I/O襯墊可經由切換組件可選擇性地耦接。舉例而言,一或多個切換組件可啟動或接通(閉合)一或多個電容器且將一或多個電容器與I/O襯墊與輸入緩衝器之間的導電路徑耦接。切換組件可個別地或協同地啟動或根本不被啟動,使得電容器中之任一或多者可與I/O襯墊耦接,或電容器中無一者可與I/O襯墊耦接。電容性組件可操作以調整或組態與I/O襯墊相關聯之電容(例如記憶體裝置之記憶體晶粒之輸入電容)。在一些狀況下,電容性組件可與I/O襯墊及包括於晶粒中之關聯輸入緩衝器耦接(例如電容性組件可與I/O襯墊與輸入緩衝器之間的導電線耦接)。For example, a memory device may include a configurable capacitive element whose capacitance may be adjustable (tunable) for adjustment or configuration and inclusion in a memory die The capacitance associated with the I/O pad. The capacitive components may include one or more capacitors and one or more associated switching components such as transistors. The switching component may be associated with one or more respective capacitors, and one or more capacitors of the capacitive component and the I/O pad may be selectively coupled via the switching component. For example, one or more switching components may activate or switch on (close) and couple one or more capacitors with a conductive path between the I/O pad and the input buffer. The switching components may be activated individually or in concert, or not at all, such that any one or more of the capacitors may be coupled to the I/O pads, or none of the capacitors may be coupled to the I/O pads. The capacitive component is operable to adjust or configure capacitance associated with an I/O pad (eg, the input capacitance of a memory die of a memory device). In some cases, a capacitive component may be coupled to an I/O pad and an associated input buffer included in the die (e.g., a capacitive component may be coupled to a conductive line between an I/O pad and an input buffer. catch).

記憶體裝置可識別用於可組態之電容性組件之目標組態。舉例而言,主機裝置可向記憶體裝置傳信以指示用於電容性組件之目標電容或相關組態資訊。記憶體裝置可自主機裝置接收傳信且可基於所指示之目標電容或組態資訊來組態電容性組件。舉例而言,與記憶體裝置相關聯之控制器可根據所指示之目標電容或組態資訊來啟動或解除啟動一或多個切換組件。I/O襯墊之經調整電容可調整(例如減低)與在記憶體裝置處所接收之信號相關聯的轉換速率且可減少由經反射信號產生之雜訊,此可增加記憶體裝置解碼自主機裝置接收之信號之準確度及可靠性,以及具有其他益處。在其他實施當中,傳信之此增強之準確度及可靠性可在汽車或其他安全決定性部署中提供安全及其他益處。The memory device can identify a target configuration for the configurable capacitive element. For example, a host device may signal a memory device to indicate a target capacitance or related configuration information for a capacitive component. The memory device can receive signaling from the host device and can configure the capacitive element based on the indicated target capacitance or configuration information. For example, a controller associated with a memory device may activate or deactivate one or more switching elements based on the indicated target capacitance or configuration information. The adjusted capacitance of the I/O pad can adjust (eg, reduce) the slew rate associated with the signal received at the memory device and can reduce the noise generated by the reflected signal, which can increase the decoding of the memory device from the host The accuracy and reliability of the signal received by the device, among other benefits. Among other implementations, this enhanced accuracy and reliability of signaling may provide safety and other benefits in automotive or other safety-critical deployments.

本發明之特徵最初在如參看圖1及圖2所描述之記憶體系統及記憶體晶粒之內容背景中加以描述。本發明之特徵在如參看圖3至圖6所描述之電路圖、系統拓樸、記憶體裝置組態及程序流程之內容背景中加以描述。本發明之此等及其他特徵係由與可組態之記憶體晶粒電容相關的設備圖解及流程圖加以進一步說明且參看該等設備圖解及流程圖加以描述,如參看圖7至圖11所描述。Features of the present invention are initially described in the context of a memory system and memory die as described with reference to FIGS. 1 and 2 . Features of the present invention are described in the context of circuit diagrams, system topologies, memory device configurations, and program flows as described with reference to FIGS. 3-6. These and other features of the present invention are further illustrated by and described with reference to apparatus diagrams and flow diagrams relating to configurable memory die capacitors, as shown with reference to FIGS. 7-11. describe.

1 說明根據如本文中所揭示之實例的利用一或多個記憶體裝置之系統100的實例。系統100可包括外部記憶體控制器105、記憶體裝置110,及將外部記憶體控制器105與記憶體裝置110耦接之複數個通道115。系統100可包括一或多個記憶體裝置,但為了易於描述,該一或多個記憶體裝置可被描述為單一記憶體裝置110。 1 illustrates an example of a system 100 utilizing one or more memory devices according to examples as disclosed herein. The system 100 may include an external memory controller 105 , a memory device 110 , and a plurality of channels 115 coupling the external memory controller 105 and the memory device 110 . The system 100 may include one or more memory devices, but for ease of description, the one or more memory devices may be described as a single memory device 110 .

系統100可包括電子裝置之部分,諸如計算裝置、行動計算裝置、無線裝置或圖形處理裝置。系統100可為攜帶型電子裝置之實例。系統100可為電腦、膝上型電腦、平板電腦、智慧型電話、蜂巢式電話、可穿戴式裝置、網際網路連接裝置或其類似者之實例。記憶體裝置110可為經組態以儲存用於系統100之一或多個其他組件之資料的系統之組件。System 100 may include part of an electronic device, such as a computing device, mobile computing device, wireless device, or graphics processing device. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, laptop, tablet, smartphone, cellular phone, wearable device, Internet connected device, or the like. Memory device 110 may be a component of a system configured to store data for one or more other components of system 100 .

系統100之至少部分可為主機裝置之實例。此主機裝置可為使用記憶體以執行程序之裝置的實例,諸如計算裝置、行動計算裝置、無線裝置、圖形處理裝置、電腦、膝上型電腦、平板電腦、智慧型電話、蜂巢式電話、可穿戴式裝置、網際網路連接裝置、一些其他靜止或攜帶型電子裝置、車輛、車輛控制器或其類似者。在一些狀況下,主機裝置可指實施外部記憶體控制器105之功能的硬體、韌體、軟體或其組合。在一些狀況下,外部記憶體控制器105可被稱作主機或主機裝置。在一些實例中,系統100係圖形卡。At least part of system 100 may be an example of a host device. Such a host device may be an example of a device that uses memory to execute a program, such as a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop, tablet computer, smartphone, cellular phone, Wearable devices, Internet-connected devices, some other stationary or portable electronic devices, vehicles, vehicle controllers, or the like. In some cases, a host device may refer to hardware, firmware, software, or a combination thereof that implements the functions of the external memory controller 105 . In some cases, external memory controller 105 may be referred to as a host or a host device. In some examples, system 100 is a graphics card.

在一些狀況下,記憶體裝置110可為經組態以與系統100之其他組件通信且提供實體記憶體位址/空間以供系統100潛在地使用或參考的獨立裝置或組件。在一些實例中,記憶體裝置110可為可組態的以與至少一個或複數個不同類型之系統100一起工作。系統100與記憶體裝置110之組件之間的傳信可為可操作的以支援用以調變信號之調變方案、用於傳達信號之不同接腳設計、系統100及記憶體裝置110之相異封裝、系統100與記憶體裝置110之間的時脈傳信及同步、時序約定及/或其他因素。In some cases, memory device 110 may be a stand-alone device or component configured to communicate with other components of system 100 and provide physical memory addresses/space for potential use or reference by system 100 . In some examples, memory device 110 may be configurable to work with at least one or a plurality of different types of system 100 . Signaling between components of system 100 and memory device 110 may be operable to support modulation schemes for modulating signals, different pin designs for communicating signals, relative communication between system 100 and memory device 110 Different packaging, clock signaling and synchronization between the system 100 and the memory device 110 , timing conventions, and/or other factors.

記憶體裝置110可經組態以儲存用於系統100之組件之資料。在一些狀況下,記憶體裝置110可充當至系統100之受控型裝置(例如回應並執行由系統100經由外部記憶體控制器105提供之命令)。此類命令可包括用於存取操作之存取命令,諸如用於寫入操作之寫入命令、用於讀取操作之讀取命令、用於再新操作之再新命令,或其他命令。記憶體裝置110可包括用以支援用於資料儲存之所要或指定容量之兩個或多於兩個記憶體晶粒160 (例如記憶體晶片)。包括兩個或多於兩個記憶體晶粒之記憶體裝置110可被稱作多晶粒記憶體或封裝(亦被稱作多晶片記憶體或封裝)。Memory device 110 may be configured to store data for components of system 100 . In some cases, memory device 110 may act as a controlled device to system 100 (eg, respond to and execute commands provided by system 100 via external memory controller 105 ). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. Memory device 110 may include two or more memory dies 160 (eg, memory chips) to support a desired or specified capacity for data storage. A memory device 110 that includes two or more memory dies may be referred to as a multi-die memory or package (also known as a multi-die memory or package).

系統100可進一步包括一處理器120、一基本輸入/輸出系統(BIOS)組件125、一或多個周邊組件130及一輸入/輸出(I/O)控制器135。系統100之組件可使用匯流排140彼此電子通信。System 100 may further include a processor 120 , a basic input/output system (BIOS) component 125 , one or more peripheral components 130 and an input/output (I/O) controller 135 . Components of system 100 may communicate electronically with each other using bus 140 .

處理器120可經組態以控制系統100之至少部分。處理器120可為通用處理器、數位信號處理器(DSP)、特殊應用積體電路(ASIC)、場可程式化閘陣列(FPGA)或其他可程式化邏輯裝置、離散閘或電晶體邏輯、離散硬體組件,或其可為此等類型之組件的組合。在此類狀況下,處理器120可為中央處理單元(CPU)、圖形處理單元(GPU)、通用圖形處理單元(GPGPU)或系統單晶片(SoC)之實例,以及其他實例。Processor 120 may be configured to control at least a portion of system 100 . Processor 120 may be a general purpose processor, digital signal processor (DSP), application specific integrated circuit (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, A discrete hardware component, or it may be a combination of these types of components. In such cases, processor 120 may be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general purpose graphics processing unit (GPGPU), or a system-on-a-chip (SoC), among other examples.

BIOS組件125可為包括作為韌體而操作之BIOS的軟體組件,其可初始化且執行系統100之各種硬體組件。BIOS組件125亦可管理處理器120與系統100之各種組件(例如周邊組件130、I/O控制器135等)之間的資料流。BIOS組件125可包括儲存於唯讀記憶體(ROM)、快閃記憶體或任何其他非揮發性記憶體中之程式或軟體。BIOS component 125 may be a software component including BIOS operating as firmware that can initialize and execute various hardware components of system 100 . BIOS component 125 may also manage data flow between processor 120 and various components of system 100 (eg, peripheral components 130, I/O controller 135, etc.). BIOS component 125 may include programs or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

周邊組件130可為可整合至系統100中或與系統100整合的任何輸入裝置或輸出裝置,或用於此類裝置之介面。實例可包括磁碟控制器、聲音控制器、圖形控制器、乙太網路控制器、數據機、通用串列匯流排(USB)控制器、串聯或平行埠,或諸如周邊組件互連(PCI)或專門圖形埠之周邊卡槽。周邊組件130可為由熟習此項技術者理解為周邊裝置之其他組件。Peripheral component 130 may be any input device or output device that may be integrated into or with system 100, or an interface for such a device. Examples may include disk controllers, sound controllers, graphics controllers, Ethernet controllers, modems, Universal Serial Bus (USB) controllers, serial or parallel ports, or such as peripheral component interconnect (PCI ) or a peripheral card slot for a dedicated graphics port. The peripheral component 130 may be other components understood by those skilled in the art as peripheral devices.

I/O控制器135可管理處理器120與周邊組件130、輸入裝置145或輸出裝置150之間的資料通信。I/O控制器135可管理並不整合至系統100中或與系統100整合的周邊裝置。在一些狀況下,I/O控制器135可表示至外部周邊組件之實體連接或埠。The I/O controller 135 can manage data communication between the processor 120 and the peripheral components 130 , the input device 145 or the output device 150 . The I/O controller 135 can manage peripheral devices that are not integrated into or integrated with the system 100 . In some cases, I/O controller 135 may represent a physical connection or port to external peripheral components.

輸入145可表示在系統100外部的將資訊、信號或資料提供至系統100或其組件的裝置或信號。此可包括使用者介面或與其他裝置的或在其他裝置之間的介面。在一些狀況下,輸入145可為經由一或多個周邊組件130與系統100介接的周邊裝置或可由I/O控制器135管理。Input 145 may represent a device or signal external to system 100 that provides information, signals, or data to system 100 or components thereof. This may include a user interface or an interface with or between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130 or may be managed by I/O controller 135 .

輸出150可表示在系統100外部的經組態以自系統100或其組件中之任一者接收輸出的裝置或信號。輸出150之實例可包括顯示器、音訊揚聲器、印刷裝置或印刷電路板上之另一處理器,等等。在一些狀況下,輸出150可為經由一或多個周邊組件130與系統100介接的周邊裝置或可由I/O控制器135管理。Output 150 may represent a device or signal external to system 100 configured to receive an output from system 100 or any of its components. Examples of output 150 may include a display, audio speakers, another processor on a printed device or printed circuit board, among others. In some cases, output 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130 or may be managed by I/O controller 135 .

系統100之組件可由經設計為進行其功能之通用或專用電路系統組成。此可包括各種電路元件,例如導電線、電晶體、電容器、電感器、電阻器、放大器、或經組態以進行本文中所描述之功能的其他主動或被動元件。在一些實例中,導電線可與系統組件耦接或可與系統組件內之子組件耦接。舉例而言,一些導電線可包含經組態以在系統組件之間攜載信號之印刷電路板(PCB)跡線或其他導電互連件。作為另一實例,一些導電線可包含經組態以在記憶體晶粒與裝置或系統100之另一組件之間攜載信號的接合線或其他導電互連件。作為另一實例,一些導電線可包含經組態以在記憶體晶粒內(例如自晶粒上所製造之一個組件至晶粒上所製造之另一組件)攜載信號之電極或其他互連件。The components of system 100 may consist of general or special purpose circuitry designed to perform their functions. This may include various circuit elements such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements configured to perform the functions described herein. In some examples, conductive lines can be coupled to system components or can be coupled to subcomponents within system components. For example, some conductive lines may include printed circuit board (PCB) traces or other conductive interconnects configured to carry signals between system components. As another example, some of the conductive lines may include bond wires or other conductive interconnects configured to carry signals between the memory die and another component of the device or system 100 . As another example, some conductive lines may include electrodes or other interconnects configured to carry signals within the memory die (eg, from one component fabricated on the die to another component fabricated on the die). even pieces.

記憶體裝置110可包括一裝置記憶體控制器155及一或多個記憶體晶粒160。每一記憶體晶粒160可包括一本端記憶體控制器165 (例如本端記憶體控制器165-a、本端記憶體控制器165-b及/或本端記憶體控制器165-N )及一記憶體陣列170 (例如記憶體陣列170-a、記憶體陣列170-b及/或記憶體陣列170-N )。記憶體陣列170可為記憶體胞元之集合(例如柵格),其中每一記憶體胞元經組態以儲存數位資料之至少一個位元。記憶體陣列170及/或記憶體胞元之特徵係參看圖2更詳細地加以描述。記憶體晶粒160可具有可基於記憶體晶粒160之一或多個元件(例如存取線、記憶體胞元、電路系統等)之一或多個屬性(例如電容)。The memory device 110 may include a device memory controller 155 and one or more memory die 160 . Each memory die 160 may include a local memory controller 165 (eg, local memory controller 165-a, local memory controller 165-b, and/or local memory controller 165- N ) and a memory array 170 (such as memory array 170-a, memory array 170-b and/or memory array 170- N ). Memory array 170 may be a collection (eg, a grid) of memory cells, where each memory cell is configured to store at least one bit of digital data. Features of memory array 170 and/or memory cells are described in more detail with reference to FIG. 2 . The memory die 160 may have one or more properties (eg, capacitance) that may be based on one or more elements of the memory die 160 (eg, access lines, memory cells, circuitry, etc.).

記憶體裝置110可為記憶體胞元之二維(2D)陣列之實例或可為記憶體胞元之三維(3D)陣列之實例。舉例而言,2D記憶體裝置可包括單一記憶體晶粒160。3D記憶體裝置可包括兩個或多於兩個記憶體晶粒160 (例如記憶體晶粒160-a、記憶體晶粒160-b及/或任何數量之記憶體晶粒160-N )。在3D記憶體裝置中,複數個記憶體晶粒160-N 可堆疊於彼此之頂部上或彼此緊鄰地堆疊。在一些狀況下,3D記憶體裝置中之記憶體晶粒160-N 可被稱作平台、層級、層或晶粒。3D記憶體裝置可包括任何數量之堆疊記憶體晶粒160-N (例如高達兩個、高達三個、高達四個、高達五個、高達六個、高達七個、高達八個)。此與單一2D記憶體裝置相比可增加可定位於基板上之記憶體胞元之數量,此繼而可降低生產成本或增加記憶體陣列之效能,或兩者兼具。在某3D記憶體裝置中,不同的平台可共用至少一個共同存取線使得一些平台可共用字線、數位線及/或板線中之至少一者。Memory device 110 may be an example of a two-dimensional (2D) array of memory cells or may be an example of a three-dimensional (3D) array of memory cells. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more than two memory dies 160 (eg, memory die 160-a, memory die 160 -b and/or any number of memory die 160- N ). In a 3D memory device, a plurality of memory die 160- N may be stacked on top of each other or next to each other. In some cases, memory die 160- N in a 3D memory device may be referred to as a mesa, level, layer or die. A 3D memory device may include any number of stacked memory die 160- N (eg, up to two, up to three, up to four, up to five, up to six, up to seven, up to eight). This can increase the number of memory cells that can be located on a substrate compared to a single 2D memory device, which in turn can reduce production costs or increase the performance of the memory array, or both. In a 3D memory device, different platforms may share at least one common access line such that some platforms may share at least one of word lines, bit lines and/or plate lines.

裝置記憶體控制器155可包括經組態以控制記憶體裝置110之操作之電路或組件。因而,裝置記憶體控制器155可包括使記憶體裝置110能夠執行命令且可經組態以接收、傳輸或執行與記憶體裝置110有關之命令、資料或控制資訊的硬體、韌體及軟體。裝置記憶體控制器155可經組態以與外部記憶體控制器105、一或多個記憶體晶粒160或處理器120通信。在一些狀況下,記憶體裝置110可自外部記憶體控制器105接收資料及/或命令。舉例而言,記憶體裝置110可接收指示記憶體裝置110將代表系統100之組件(例如處理器120)儲存某些資料之寫入命令,或指示記憶體裝置110將把儲存於記憶體晶粒160中之某些資料提供至系統100之組件(例如處理器120)之讀取命令。在一些狀況下,裝置記憶體控制器155可結合記憶體晶粒160之本端記憶體控制器165來控制本文中所描述之記憶體裝置110之操作。裝置記憶體控制器155及/或本端記憶體控制器165中所包括之組件之實例可包括:用於解調自外部記憶體控制器105接收之信號之接收器、用於調變及傳輸信號至外部記憶體控制器105之解碼器、邏輯、解碼器、放大器、濾波器或其類似者。Device memory controller 155 may include circuitry or components configured to control the operation of memory device 110 . Thus, device memory controller 155 may include hardware, firmware, and software that enable memory device 110 to execute commands and may be configured to receive, transmit, or execute commands, data, or control information related to memory device 110 . Device memory controller 155 may be configured to communicate with external memory controller 105 , one or more memory die 160 , or processor 120 . In some cases, memory device 110 may receive data and/or commands from external memory controller 105 . For example, memory device 110 may receive a write command instructing memory device 110 to store certain data on behalf of a component of system 100 (such as processor 120), or to instruct memory device 110 to store certain data on a memory die Certain data in 160 provides read commands to components of system 100 such as processor 120 . In some cases, device memory controller 155 may combine with local memory controller 165 of memory die 160 to control the operation of memory device 110 as described herein. Examples of components included in the device memory controller 155 and/or the local memory controller 165 may include: receivers for demodulating signals received from the external memory controller 105, for modulating and transmitting The signal goes to a decoder, logic, decoder, amplifier, filter or the like of the external memory controller 105.

本端記憶體控制器165 (例如在記憶體晶粒160本端)可經組態以控制記憶體晶粒160之操作。又,本端記憶體控制器165可經組態以與裝置記憶體控制器155通信(例如接收及傳輸資料及/或命令)。本端記憶體控制器165可支援裝置記憶體控制器155以控制如本文所描述之記憶體裝置110之操作。在一些狀況下,記憶體裝置110並不包括裝置記憶體控制器155,且本端記憶體控制器165或外部記憶體控制器105可執行本文中所描述之各種功能。因而,本端記憶體控制器165可經組態以與裝置記憶體控制器155通信、與其他本端記憶體控制器165通信,或直接與外部記憶體控制器105或處理器120通信。A local memory controller 165 (eg, local to the memory die 160 ) can be configured to control the operation of the memory die 160 . Also, the local memory controller 165 can be configured to communicate (eg, receive and transmit data and/or commands) with the device memory controller 155 . Local memory controller 165 may support device memory controller 155 to control the operation of memory device 110 as described herein. In some cases, memory device 110 does not include device memory controller 155, and local memory controller 165 or external memory controller 105 may perform various functions described herein. Thus, the local memory controller 165 may be configured to communicate with the device memory controller 155 , to communicate with other local memory controllers 165 , or to communicate directly with the external memory controller 105 or the processor 120 .

外部記憶體控制器105可經組態以使能夠在系統100之組件(例如處理器120)與記憶體裝置110之間傳達資訊、資料及/或命令。外部記憶體控制器105可充當系統100之組件與記憶體裝置110之間的聯絡者使得系統100之組件可無需知曉記憶體裝置之操作的細節。系統100之組件可向外部記憶體控制器105呈現外部記憶體控制器105滿足的請求(例如讀取命令或寫入命令)。外部記憶體控制器105可轉換或轉譯在系統100之組件與記憶體裝置110之間所交換之通信。在一些狀況下,外部記憶體控制器105可包括產生共同(源)系統時脈信號之系統時脈。在一些狀況下,外部記憶體控制器105可包括產生共同(源)資料時脈信號之共同資料時脈。External memory controller 105 may be configured to enable communication of information, data, and/or commands between components of system 100 (eg, processor 120 ) and memory device 110 . The external memory controller 105 can act as a link between the components of the system 100 and the memory device 110 such that the components of the system 100 do not need to know the details of the operation of the memory device. Components of system 100 may present requests (eg, read commands or write commands) to external memory controller 105 that external memory controller 105 fulfills. External memory controller 105 may translate or translate communications exchanged between components of system 100 and memory device 110 . In some cases, external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

在一些狀況下,外部記憶體控制器105或系統100之其他組件,或其在本文中所描述之功能可由處理器120實施。舉例而言,外部記憶體控制器105可為由處理器120或系統100之其他組件實施之硬體、韌體或軟體或其某一組合。雖然外部記憶體控制器105被描繪為在記憶體裝置110之外部,但在一些狀況下,外部記憶體控制器105或其在本文中所描述之功能可由記憶體裝置110實施。舉例而言,外部記憶體控制器105可為由裝置記憶體控制器155或一或多個本端記憶體控制器165實施之硬體、韌體、或軟體或其某一組合。在一些狀況下,外部記憶體控制器105可橫越處理器120及記憶體裝置110而分佈,使得外部記憶體控制器105之部分係由處理器120實施且其他部分係由裝置記憶體控制器155或本端記憶體控制器165實施。同樣地,在一些狀況下,本文中歸屬於裝置記憶體控制器155或本端記憶體控制器165之一或多個功能在一些狀況下可由外部記憶體控制器105(與處理器120分離或包括於處理器120中)執行。In some cases, external memory controller 105 or other components of system 100 , or the functions described herein, may be implemented by processor 120 . For example, external memory controller 105 may be hardware, firmware, or software implemented by processor 120 or other components of system 100, or some combination thereof. Although external memory controller 105 is depicted as being external to memory device 110 , in some cases external memory controller 105 or its functions described herein may be implemented by memory device 110 . For example, external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by device memory controller 155 or one or more local memory controllers 165 . In some cases, external memory controller 105 may be distributed across processor 120 and memory device 110 such that portions of external memory controller 105 are implemented by processor 120 and other portions by device memory controller 155 or local memory controller 165 for implementation. Likewise, in some cases, one or more of the functions ascribed herein to device memory controller 155 or local memory controller 165 may in some cases be performed by external memory controller 105 (either separate from processor 120 or included in the processor 120) to execute.

系統100之組件可使用複數個通道115與記憶體裝置110交換資訊。在一些實例中,該等通道115可實現外部記憶體控制器105與記憶體裝置110之間的通信。每一通道115可包括在與系統100之組件相關聯之端子之間的一或多個信號路徑或傳輸媒體(例如導體)。舉例而言,通道115可包括第一端子,該第一端子包括外部記憶體控制器105處之一或多個接腳及記憶體裝置110處之一或多個接腳。接腳可為系統100之裝置之任何類型之導電輸入或輸出點的實例且一般係指該任何類型之導電輸入或輸出點(例如球狀柵格陣列(BGA)之球),且接腳可經組態為充當通道之部分。Components of system 100 may exchange information with memory device 110 using plurality of channels 115 . In some examples, the channels 115 enable communication between the external memory controller 105 and the memory device 110 . Each channel 115 may include one or more signal paths or transmission media (eg, conductors) between terminals associated with components of system 100 . For example, channel 115 may include a first terminal that includes one or more pins at external memory controller 105 and one or more pins at memory device 110 . A pin may be an example of, and generally refers to, any type of conductive input or output point of a device of system 100 (such as a ball grid array (BGA) ball), and a pin may be Configured to act as part of a channel.

在一些狀況下,接腳可為通道115之信號路徑之部分。額外信號路徑可與用於在系統100之組件內路由信號之通道之端子耦合。舉例而言,記憶體裝置110可包括將信號自通道115之端子路由至記憶體裝置110之各種組件(例如裝置記憶體控制器155、記憶體晶粒160、本端記憶體控制器165、記憶體陣列170)之信號路徑(例如在記憶體裝置110或其組件內部(諸如在記憶體晶粒160內部)之信號路徑)。In some cases, a pin may be part of the signal path of channel 115 . Additional signal paths may be coupled to terminals of channels used to route signals within components of system 100 . For example, memory device 110 may include various components that route signals from terminals of channel 115 to memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory memory array 170) (eg, signal paths within the memory device 110 or components thereof, such as within the memory die 160).

通道115 (及關聯信號路徑及端子)可專用於傳達特定類型之資訊。在一些狀況下,通道115可為聚集通道且因此可包括多個個別通道。舉例而言,資料通道190可為x4 (例如包括四個信號路徑)、x8 (例如包括八個信號路徑)、x16 (例如包括十六個信號路徑)等等。在該等通道上傳達之信號可使用雙資料速率(DDR)時序方案。舉例而言,一信號之一些符號可暫存於時脈信號之上升邊緣上且該信號之其他符號可暫存於時脈信號之下降邊緣上。在通道上傳達之信號可使用單資料速率(SDR)傳信。舉例而言,可針對每一時脈循環暫存信號之一個符號。Channel 115 (and associated signal paths and terminals) may be dedicated to conveying particular types of information. In some cases, channel 115 may be a collective channel and thus may include a plurality of individual channels. For example, the data channel 190 may be x4 (eg, including four signal paths), x8 (eg, including eight signal paths), x16 (eg, including sixteen signal paths), and so on. Signals communicated on these lanes may use a double data rate (DDR) timing scheme. For example, some symbols of a signal may be registered on the rising edge of the clock signal and other symbols of the signal may be registered on the falling edge of the clock signal. Signals communicated on the channel may use single data rate (SDR) signaling. For example, one symbol of the signal may be buffered for each clock cycle.

在一些狀況下,通道115可包括一或多個CA通道186。CA通道186可經組態以在外部記憶體控制器105與記憶體裝置110之間傳達命令,包括與命令相關聯之控制資訊(例如位址資訊)。舉例而言,CA通道186可包括具有所要資料之位址之讀取命令。在一些狀況下,CA通道186可被暫存於上升時脈信號邊緣及/或下降時脈信號邊緣上。在一些狀況下,CA通道186可包括用以解碼位址及命令資料之任何數量的信號路徑(例如八個或九個信號路徑)。In some cases, channel 115 may include one or more CA channels 186 . CA channel 186 may be configured to communicate commands between external memory controller 105 and memory device 110, including control information (eg, address information) associated with the commands. For example, CA channel 186 may include a read command with the address of the desired data. In some cases, CA channel 186 may be buffered on rising clock signal edges and/or falling clock signal edges. In some cases, CA channel 186 may include any number of signal paths (eg, eight or nine signal paths) to decode address and command data.

在一些狀況下,通道115可包括一或多個時脈信號(CK)通道188。CK通道188可經組態以在外部記憶體控制器105與記憶體裝置110之間傳達一或多個共同時脈信號。每一時脈信號可經組態以在高狀態與低狀態之間振盪且協調外部記憶體控制器105及記憶體裝置110之動作。在一些狀況下,時脈信號可為差動輸出(例如CK_t信號及CK_c信號)且CK通道188之信號路徑可相應地經組態。在一些狀況下,時脈信號可為單端的。CK通道188可包括任何數量之信號路徑。在一些狀況下,時脈信號CK (例如CK_t信號及CK_c信號)可向用於記憶體裝置110之命令及定址操作或用於記憶體裝置110之其他全系統範圍操作提供時序參考。時脈信號CK因此可被不同地稱作控制時脈信號CK、命令時脈信號CK或系統時脈信號CK。系統時脈信號CK可由系統時脈產生,系統時脈可包括一或多個硬體組件(例如振盪器、晶體、邏輯閘、電晶體或其類似者)。In some cases, channels 115 may include one or more clock signal (CK) channels 188 . CK channel 188 may be configured to communicate one or more common clock signals between external memory controller 105 and memory device 110 . Each clock signal can be configured to oscillate between a high state and a low state and coordinate the actions of the external memory controller 105 and the memory device 110 . In some cases, the clock signal may be a differential output (eg, CK_t signal and CK_c signal) and the signal path of CK channel 188 may be configured accordingly. In some cases, the clock signal may be single-ended. CK channel 188 may include any number of signal paths. In some cases, clock signal CK (eg, CK_t signal and CK_c signal) may provide a timing reference for command and address operations of memory device 110 or for other system-wide operations of memory device 110 . The clock signal CK may thus be variously referred to as a control clock signal CK, a command clock signal CK or a system clock signal CK. The system clock signal CK can be generated by the system clock, and the system clock can include one or more hardware components (such as oscillators, crystals, logic gates, transistors, or the like).

在一些狀況下,通道115可包括一或多個資料(DQ)通道190。資料通道190可經組態以在外部記憶體控制器105與記憶體裝置110之間傳達資料及/或控制資訊。舉例而言,資料通道190可傳達待寫入至記憶體裝置110之資訊(例如雙向的)或自記憶體裝置110讀取之資訊。In some cases, lanes 115 may include one or more data (DQ) lanes 190 . Data channel 190 may be configured to communicate data and/or control information between external memory controller 105 and memory device 110 . For example, data channel 190 may convey information to be written to memory device 110 (eg, bi-directional) or information to be read from memory device 110 .

在一些狀況下,通道115可包括可專用於其他目的之一或多個其他通道192。此等其他通道192可包括任何數量之信號路徑。In some cases, channel 115 may include one or more other channels 192 that may be dedicated to other purposes. These other channels 192 may include any number of signal paths.

在一些狀況下,其他通道192可包括一或多個寫入時脈信號(WCK)通道。雖然WCK中之「W」可標稱地表示「寫入」,但寫入時脈信號WCK  (例如WCK_t信號及WCK_c信號)可提供通常用於記憶體裝置110之存取操作之時序參考(例如用於讀取及寫入操作兩者之時序參考)。因此,寫入時脈信號WCK亦可被稱作資料時脈信號WCK。WCK通道可經組態以在外部記憶體控制器105與記憶體裝置110之間傳達共同資料時脈信號。資料時脈信號可經組態以協調外部記憶體控制器105及記憶體裝置110之存取操作(例如寫入操作或讀取操作)。在一些狀況下,寫入時脈信號可為差動輸出(例如WCK_t信號及WCK_c信號)且WCK通道之信號路徑可相應地經組態。WCK通道可包括任何數量之信號路徑。資料時脈信號WCK可由資料時脈產生,資料時脈可包括一或多個硬體組件(例如振盪器、晶體、邏輯閘、電晶體或其類似者)。In some cases, other channels 192 may include one or more write clock signal (WCK) channels. Although the "W" in WCK can nominally represent "write", the write clock signal WCK (such as the WCK_t signal and the WCK_c signal) can provide a timing reference commonly used for access operations of the memory device 110 (such as timing reference for both read and write operations). Therefore, the write clock signal WCK can also be referred to as the data clock signal WCK. The WCK channel can be configured to communicate a common data clock signal between the external memory controller 105 and the memory device 110 . The data clock signal can be configured to coordinate access operations (eg, write operations or read operations) between the external memory controller 105 and the memory device 110 . In some cases, the write clock signal can be a differential output (eg, WCK_t signal and WCK_c signal) and the signal path of the WCK channel can be configured accordingly. A WCK channel may include any number of signal paths. The data clock signal WCK can be generated by a data clock, and the data clock can include one or more hardware components (such as oscillators, crystals, logic gates, transistors, or the like).

在一些狀況下,其他通道192可包括一或多個誤差偵測碼(EDC)通道。EDC通道可經組態以傳達誤差偵測信號,諸如總和檢查碼,以改良系統可靠性。EDC通道可包括任何數量之信號路徑。In some cases, other channels 192 may include one or more error detection code (EDC) channels. EDC channels can be configured to communicate error detection signals, such as checksums, to improve system reliability. An EDC channel may include any number of signal paths.

通道115可使用多種不同架構將外部記憶體控制器105與記憶體裝置110耦接。各種架構之實例可包括匯流排、點對點連接、交叉開關、高密度中介層(諸如矽中介層)或形成於有機基板中之通道或其某一組合。舉例而言,在一些狀況下,信號路徑可至少部分地包括高密度中介層,諸如矽中介層或玻璃中介層。Channel 115 can couple external memory controller 105 to memory device 110 using a variety of different architectures. Examples of various architectures may include bus bars, point-to-point connections, crossbar switches, high density interposers such as silicon interposers, or channels formed in an organic substrate, or some combination thereof. For example, in some cases, a signal path may at least partially include a high density interposer, such as a silicon interposer or a glass interposer.

記憶體裝置110可經組態以與主機裝置通信(例如傳輸及接收信號)。在一些狀況下,記憶體裝置110可在自主機裝置接收信號時經歷干擾或雜訊。舉例而言,來自主機裝置之信號可自記憶體裝置110之組件或自一或多個相鄰記憶體裝置110反射。經反射信號可與自主機裝置至記憶體裝置110之信號組合且可造成建設性及/或破壞性干擾。在記憶體裝置110處所經歷之干擾可取決於信號轉換速率、系統組態或拓樸(例如諸如用於CA或DQ匯流排之匯流排拓樸)、電路系統或記憶體裝置110之其他組件或其類似者。Memory device 110 may be configured to communicate (eg, transmit and receive signals) with a host device. In some cases, memory device 110 may experience interference or noise when receiving signals from a host device. Signals from the host device may be reflected from components of memory device 110 or from one or more adjacent memory devices 110, for example. The reflected signal can combine with the signal from the host device to the memory device 110 and can cause constructive and/or destructive interference. The disturbance experienced at the memory device 110 may depend on the signal slew rate, the system configuration or topology (e.g., a bus topology such as for the CA or DQ bus), the circuitry or other components of the memory device 110, or its analogues.

可使用多種不同的調變方案來調變在通道115上傳達之信號。在一些狀況下,可使用二進位符號(或二進位位階)調變方案以調變在外部記憶體控制器105與記憶體裝置110之間傳達之信號。二進位符號調變方案可為M進位調變方案之實例,其中M等於二。二進位符號調變方案之每一符號可經組態以表示數位資料之一個位元(例如,符號可表示邏輯1或邏輯0)。二進位符號調變方案之實例包括但不限於不歸零(NRZ)、單極編碼、雙極編碼、曼徹斯特(Manchester)編碼、具有兩個符號(例如PAM2)之脈衝振幅調變(PAM)及/或其他者。The signal communicated on channel 115 may be modulated using a number of different modulation schemes. In some cases, a binary sign (or binary level) modulation scheme may be used to modulate the signals communicated between the external memory controller 105 and the memory device 110 . A binary symbol modulation scheme may be an example of an M-ary modulation scheme, where M equals two. Each symbol of the binary symbol modulation scheme can be configured to represent a bit of digital data (eg, a symbol can represent a logic 1 or a logic 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return-to-zero (NRZ), unipolar encoding, bipolar encoding, Manchester encoding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and /or other.

在一些狀況下,可使用多符號(或多位階)調變方案以調變在外部記憶體控制器105與記憶體裝置110之間傳達之信號。多符號調變方案可為M進位調變方案之實例,其中M大於或等於三。多符號調變方案之每一符號可經組態以表示數位資料之多於一個位元(例如,符號可表示邏輯00、邏輯01、邏輯10或邏輯11)。多符號調變方案之實例包括但不限於PAM3、PAM4、PAM8等、正交振幅調變(QAM)、正交相移鍵控(QPSK)及/或其他者。多符號信號(例如PAM3信號或PAM4信號)可為使用包括至少三個位階以每符號編碼多於一個位元資訊的調變方案所調變的信號。多符號調變方案及符號可替代地被稱作非二進位、多位元、或高階調變方案及符號。In some cases, a multi-symbol (or multi-level) modulation scheme may be used to modulate the signals communicated between the external memory controller 105 and the memory device 110 . A multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to three. Each symbol of a multi-symbol modulation scheme can be configured to represent more than one bit of digital data (eg, a symbol can represent a logical 00, a logical 01, a logical 10, or a logical 11). Examples of multi-symbol modulation schemes include, but are not limited to, PAM3, PAM4, PAM8, etc., Quadrature Amplitude Modulation (QAM), Quadrature Phase Shift Keying (QPSK), and/or others. A multi-symbol signal, such as a PAM3 signal or a PAM4 signal, may be a signal modulated using a modulation scheme comprising at least three levels to encode more than one bit of information per symbol. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or high-order modulation schemes and symbols.

如本文中所描述,記憶體裝置110可經組態以將信號傳輸至主機裝置(例如外部記憶體控制器105)及自主機裝置接收信號,且在一些狀況下可在自主機裝置接收信號時經歷干擾或雜訊。舉例而言,來自主機裝置之信號可具有高轉換速率,此可促成雜訊位準增加(例如經由在相鄰記憶體裝置上之信號反射)。在一些狀況下,一或多個相鄰記憶體裝置110 (未圖示)之電容可至少部分地造成信號反射。主機裝置可經組態以藉由指示與記憶體裝置110之可組態之電容性組件相關聯的目標電容或相關組態資訊而減少由記憶體裝置110經歷之雜訊。記憶體裝置110可操作以調整或組態與可組態之電容性組件相關聯且因此與可組態之電容性組件可耦接至之記憶體裝置110之I/O襯墊相關聯的電容。在一些狀況下,可組態之電容性組件可包括一或多個電容器及可將該一或多個電容器與I/O襯墊選擇性地耦接之一或多個關聯切換組件(例如電晶體)。在一些狀況下,可組態之電容性組件之經組態電容可減小自主機裝置至記憶體裝置110之傳信之轉換速率(例如記憶體裝置110處之轉換速率),且減小之轉換速率可減少信號反射及關聯雜訊。As described herein, memory device 110 can be configured to transmit signals to and receive signals from a host device (e.g., external memory controller 105) and, in some cases, to receive signals from the host device. Experience interference or noise. For example, signals from a host device may have high slew rates, which may contribute to increased noise levels (eg, via signal reflections on neighboring memory devices). In some cases, the capacitance of one or more neighboring memory devices 110 (not shown) may at least partially cause signal reflections. The host device can be configured to reduce the noise experienced by the memory device 110 by indicating a target capacitance or related configuration information associated with a configurable capacitive component of the memory device 110 . The memory device 110 is operable to adjust or configure the capacitance associated with the configurable capacitive element and thus the I/O pads of the memory device 110 to which the configurable capacitive element can be coupled . In some cases, a configurable capacitive component may include one or more capacitors and may selectively couple the one or more capacitors to an I/O pad to one or more associated switching components (such as electrical crystal). In some cases, the configured capacitance of the configurable capacitive element can reduce the slew rate of signaling from the host device to the memory device 110 (e.g., the slew rate at the memory device 110), and the reduced slew rate The rate reduces signal reflections and associated noise.

2 說明根據如本文中所揭示之實例的記憶體晶粒200之實例。記憶體晶粒200可為參看圖1所描述之記憶體晶粒160之實例。在一些狀況下,記憶體晶粒200可被稱作記憶體晶片、記憶體裝置或電子記憶體設備。記憶體晶粒200可包括可程式化以儲存不同邏輯狀態之一或多個記憶體胞元205。每一記憶體胞元205可為可程式化的以儲存兩個或多於兩個狀態。舉例而言,記憶體胞元205可經組態以一次儲存一個位元資訊(例如邏輯0或邏輯1)。在一些狀況下,單一記憶體胞元205 (例如多位階記憶體胞元)可經組態以一次儲存多於一個位元資訊(例如邏輯00、邏輯01、邏輯10或邏輯11)。 FIG. 2 illustrates an example of a memory die 200 according to examples as disclosed herein. Memory die 200 may be an example of memory die 160 described with reference to FIG. 1 . In some cases, memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 can include one or more memory cells 205 that can be programmed to store one or more different logic states. Each memory cell 205 may be programmable to store two or more states. For example, memory cell 205 can be configured to store one bit of information (eg, a logical zero or a logical one) at a time. In some cases, a single memory cell 205 (eg, a multi-level memory cell) can be configured to store more than one bit of information at a time (eg, logical 00, logical 01, logical 10, or logical 11).

記憶體胞元205可將表示可程式化狀態之電荷儲存於電容器中。DRAM架構可包括包括介電材料以儲存表示可程式化狀態之電荷的電容器。在其他記憶體架構中,其他儲存裝置及組件係可能的。舉例而言,可使用非線性(例如鐵電)介電材料。Memory cell 205 may store a charge representing a programmable state in a capacitor. DRAM architectures may include capacitors that include dielectric material to store charges representing programmable states. In other memory architectures, other storage devices and components are possible. For example, non-linear (eg, ferroelectric) dielectric materials may be used.

可藉由啟動或選擇諸如字線210及/或數位線215之存取線而對記憶體胞元205執行諸如讀取及寫入之操作。在一些狀況下,數位線215亦可被稱作位元線。對存取線、字線及數位線或其類似物之參考係可互換的,而不會損失理解或操作。啟動或選擇字線210或數位線215可包括將電壓施加至各別線。Operations such as reading and writing can be performed on memory cell 205 by activating or selecting access lines such as word lines 210 and/or bit lines 215 . In some cases, the digit lines 215 may also be referred to as bit lines. References to access lines, word lines and bit lines, or the like, are interchangeable without loss of understanding or operation. Activating or selecting wordline 210 or digitline 215 may include applying a voltage to the respective line.

記憶體晶粒200可包括以柵格狀圖案配置之存取線(例如字線210及數位線215)。記憶體胞元205可定位於字線210與數位線215之交叉點處。藉由使字線210及數位線215偏置(例如將電壓施加至字線210或數位線215),可在其交叉點處存取單一記憶體胞元205。Memory die 200 may include access lines (eg, word lines 210 and bit lines 215 ) arranged in a grid-like pattern. Memory cell 205 may be located at the intersection of word line 210 and bit line 215 . A single memory cell 205 can be accessed at the intersection of wordline 210 and bitline 215 by biasing (eg, applying a voltage to) wordline 210 or bitline 215 .

可經由列解碼器220或行解碼器225控制存取記憶體胞元205。舉例而言,列解碼器220可自本端記憶體控制器260接收列位址且基於所接收之列位址啟動字線210。行解碼器225可自本端記憶體控制器260接收行位址且可基於所接收之行位址啟動數位線215。舉例而言,記憶體晶粒200可包括標記為WL_1至WL_M之多條字線210,及標記為DL_1至DL_N之多條數位線215,其中M及N取決於記憶體陣列之大小。因此,藉由啟動字線210及數位線215,例如WL_1及DL_3,可在其交叉點處存取記憶體胞元205。在二維或三維組態中,字線210與數位線215之交叉點可被稱作記憶體胞元205之位址。Access to memory cell 205 can be controlled via column decoder 220 or row decoder 225 . For example, column decoder 220 may receive a column address from local memory controller 260 and activate word line 210 based on the received column address. The row decoder 225 can receive a row address from the local memory controller 260 and can activate the bit line 215 based on the received row address. For example, memory die 200 may include a number of word lines 210 labeled WL_1 through WL_M, and a number of digit lines 215 labeled DL_1 through DL_N, where M and N depend on the size of the memory array. Therefore, memory cell 205 can be accessed at their intersections by enabling word lines 210 and bit lines 215 , such as WL_1 and DL_3 . In a two-dimensional or three-dimensional configuration, the intersection of the word line 210 and the digit line 215 may be referred to as the address of the memory cell 205 .

記憶體胞元205可包括邏輯儲存組件,諸如電容器230及切換組件235。電容器230可為介電電容器或鐵電電容器之實例。電容器230之第一節點可與切換組件235耦接且電容器230之第二節點可與電壓源240耦接。在一些狀況下,電壓源240可為胞元板參考電壓,諸如Vpl,或可接地,諸如Vss。在一些狀況下,電壓源240可為與板線驅動器耦接之板線之實例。切換組件235可為電晶體或在兩個組件之間選擇性地建立或解除建立電子通信之任何其他類型之開關裝置的實例。Memory cell 205 may include logic storage components such as capacitor 230 and switching component 235 . Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A first node of capacitor 230 may be coupled to switching component 235 and a second node of capacitor 230 may be coupled to voltage source 240 . In some cases, voltage source 240 may be a cell plate reference voltage, such as Vpl, or may be a ground, such as Vss. In some cases, voltage source 240 may be an instance of a boardline coupled with a boardline driver. Switching component 235 may be an example of a transistor or any other type of switching device that selectively establishes or deestablishes electronic communication between two components.

選擇或取消選擇記憶體胞元205可藉由啟動或解除啟動切換組件235來實現。電容器230可使用切換組件235與數位線215電子通信。舉例而言,當解除啟動切換組件235時,電容器230可與數位線215隔離,且當啟動切換組件235時,電容器230可與數位線215耦接。在一些狀況下,切換組件235為電晶體且其操作可藉由將電壓施加至電晶體閘極來控制,其中電晶體閘極與電晶體源之間的電壓差可大於或小於電晶體之臨限電壓。在一些狀況下,切換組件235可為p型電晶體或n型電晶體。字線210可與切換組件235之閘極電子通信且可基於經施加至字線210之電壓而啟動/解除啟動切換組件235。Selecting or deselecting the memory cell 205 can be realized by activating or deactivating the switching component 235 . Capacitor 230 may be in electronic communication with digit line 215 using switching component 235 . For example, capacitor 230 may be isolated from digit line 215 when switching component 235 is deactivated, and capacitor 230 may be coupled to digit line 215 when switching component 235 is enabled. In some cases, switching element 235 is a transistor and its operation can be controlled by applying a voltage to the gate of the transistor, where the voltage difference between the gate of the transistor and the source of the transistor can be greater or less than the threshold of the transistor. limit voltage. In some cases, the switching element 235 can be a p-type transistor or an n-type transistor. The word line 210 can be in electronic communication with the gate of the switching element 235 and the switching element 235 can be activated/deactivated based on the voltage applied to the word line 210 .

字線210可為與記憶體胞元205電子通信的用以對記憶體胞元205執行存取操作的導電線。在一些架構中,字線210可與記憶體胞元205之切換組件235之閘極電子通信且可經組態以控制該記憶體胞元之該切換組件235。在一些架構中,字線210可與記憶體胞元205之電容器之節點電子通信且記憶體胞元205可不包括切換組件。The word line 210 may be a conductive line in electronic communication with the memory cell 205 for performing access operations on the memory cell 205 . In some architectures, the word line 210 can be in electronic communication with the gate of the switching element 235 of the memory cell 205 and can be configured to control the switching element 235 of the memory cell. In some architectures, the word line 210 may be in electronic communication with the node of the capacitor of the memory cell 205 and the memory cell 205 may not include switching elements.

數位線215可為將記憶體胞元205與感測組件245連接的導電線。在一些架構中,記憶體胞元205與數位線215可在存取操作之部分期間選擇性地耦接。舉例而言,字線210及記憶體胞元205之切換組件235可經組態以將記憶體胞元205之電容器230與數位線215耦接及/或隔離。在一些架構中,記憶體胞元205可與數位線215電子通信(例如恆定)。The digit line 215 can be a conductive line connecting the memory cell 205 and the sensing element 245 . In some architectures, memory cells 205 and digit lines 215 may be selectively coupled during portions of access operations. For example, word line 210 and switching element 235 of memory cell 205 can be configured to couple and/or isolate capacitor 230 of memory cell 205 from bit line 215 . In some architectures, memory cells 205 may be in electronic communication (eg, constant) with a digit line 215 .

感測組件245可經組態以偵測儲存於記憶體胞元205之電容器230上之狀態(例如電荷)且基於所儲存狀態判定記憶體胞元205之邏輯狀態。在一些狀況下,由記憶體胞元205儲存之電荷可能極小。因而,感測組件245可包括一或多個感測放大器以放大由記憶體胞元205輸出之信號。感測放大器可在讀取操作期間偵測到數位線215之電荷之小的改變且可基於偵測到之電荷產生對應於邏輯狀態0或邏輯狀態1之信號。在讀取操作期間,記憶體胞元205之電容器230可輸出信號(例如使電荷放電)至其對應數位線215。該信號可導致數位線215之電壓改變。感測組件245可經組態以將橫越數位線215自記憶體胞元205接收到之信號與參考信號250 (例如參考電壓)進行比較。感測組件245可基於該比較判定記憶體胞元205之所儲存狀態。舉例而言,在二進位傳信中,若數位線215具有比參考信號250高的電壓,則感測組件245可判定記憶體胞元205之所儲存狀態為邏輯1,且若數位線215具有比參考信號250低的電壓,則感測組件245可判定記憶體胞元205之所儲存狀態為邏輯0。感測組件245可包括各種電晶體或放大器,以偵測及放大信號信號之差異。記憶體胞元205之所偵測之邏輯狀態可被提供為感測組件245之輸出(例如至輸入/輸出255),且可向包括記憶體晶粒200之記憶體裝置110之另一組件(諸如裝置記憶體控制器155)指示所偵測之邏輯狀態(例如直接地或使用本端記憶體控制器260)。The sensing component 245 can be configured to detect the state (eg, charge) stored on the capacitor 230 of the memory cell 205 and determine the logic state of the memory cell 205 based on the stored state. In some cases, the charge stored by memory cell 205 may be very small. Therefore, the sensing element 245 may include one or more sense amplifiers to amplify the signal output by the memory cell 205 . The sense amplifier can detect small changes in charge of digit line 215 during a read operation and can generate a signal corresponding to logic state 0 or logic state 1 based on the detected charge. During a read operation, the capacitor 230 of the memory cell 205 may output a signal (eg, discharge a charge) to its corresponding digit line 215 . This signal can cause the voltage on digit line 215 to change. The sensing component 245 can be configured to compare the signal received across the digit line 215 from the memory cell 205 to a reference signal 250 (eg, a reference voltage). The sensing component 245 can determine the stored state of the memory cell 205 based on the comparison. For example, in binary signaling, if the digit line 215 has a higher voltage than the reference signal 250, the sensing element 245 can determine that the stored state of the memory cell 205 is a logic 1, and if the digit line 215 has At a voltage lower than the reference signal 250, the sensing element 245 can determine that the stored state of the memory cell 205 is a logic 0. The sensing element 245 may include various transistors or amplifiers to detect and amplify the difference of signal signals. The detected logic state of memory cell 205 may be provided as an output of sensing component 245 (eg, to input/output 255 ), and may be sent to another component of memory device 110 including memory die 200 ( Such as the device memory controller 155) indicates the detected logic state (eg, directly or using the local memory controller 260).

本端記憶體控制器260可經由各種組件(例如列解碼器220、行解碼器225及感測組件245)控制記憶體胞元205之操作。本端記憶體控制器260可為參看圖1所描述之本端記憶體控制器165的實例。在一些狀況下,列解碼器220、行解碼器225及感測組件245中之一或多者可與本端記憶體控制器260共置。本端記憶體控制器260可經組態以自外部記憶體控制器105(或參考圖1所描述之裝置記憶體控制器155)接收命令及/或資料、將命令及/或資料轉譯成可由記憶體晶粒200使用之資訊、對記憶體晶粒200執行一或多個操作,且回應於執行一或多個操作而將資料自記憶體晶粒200傳達至外部記憶體控制器105 (或裝置記憶體控制器155)。本端記憶體控制器260可產生列及行位址信號以啟動目標字線210及目標數位線215。本端記憶體控制器260亦可產生及控制在記憶體晶粒200之操作期間使用之各種電壓或電流。大體而言,本文所論述的所施加電壓或電流之振幅、形狀或持續時間可進行調整或變化,且可針對操作記憶體晶粒200時所論述的各種操作而不同。The local memory controller 260 can control the operation of the memory cell 205 through various components such as the column decoder 220 , the row decoder 225 and the sensing component 245 . Local memory controller 260 may be an example of local memory controller 165 described with reference to FIG. 1 . In some cases, one or more of column decoder 220 , row decoder 225 , and sensing element 245 may be co-located with local memory controller 260 . The local memory controller 260 can be configured to receive commands and/or data from the external memory controller 105 (or the device memory controller 155 described with reference to FIG. Memory die 200 uses information, performs one or more operations on memory die 200, and communicates data from memory die 200 to external memory controller 105 (or device memory controller 155). The local memory controller 260 can generate column and row address signals to activate the target word line 210 and the target bit line 215 . The local memory controller 260 can also generate and control various voltages or currents used during the operation of the memory die 200 . In general, the amplitude, shape, or duration of the applied voltage or current discussed herein may be adjusted or varied, and may be different for the various operations discussed in operating memory die 200 .

本端記憶體控制器260 (或包括於記憶體裝置中之另一控制器)可組態與記憶體晶粒200相關聯之一或多個組件。舉例而言,控制器可基於目標電容或相關組態資訊啟動或解除啟動記憶體晶粒200之可組態之電容性組件之一或多個切換組件,該目標電容或相關組態資訊可被指示給記憶體裝置或由記憶體裝置以其他方式識別或判定。The local memory controller 260 (or another controller included in the memory device) can configure one or more components associated with the memory die 200 . For example, the controller may enable or disable one or more switching elements of the configurable capacitive elements of the memory die 200 based on a target capacitance or related configuration information, which may be determined by Indicated to or otherwise recognized or determined by a memory device.

在一些狀況下,本端記憶體控制器260可經組態以對記憶體晶粒200之一或多個記憶體胞元205執行寫入操作(例如程式化操作)。在寫入操作期間,記憶體晶粒200之記憶體胞元205可經程式化以儲存所要邏輯狀態。在一些狀況下,複數個記憶體胞元205可在單一寫入操作期間經程式化。本端記憶體控制器260可識別執行寫入操作所針對的目標記憶體胞元205。本端記憶體控制器260可識別與目標記憶體胞元205電子通信之目標字線210及目標數位線215 (例如目標記憶體胞元205之位址)。本端記憶體控制器260可啟動目標字線210及目標數位線215 (例如將電壓施加至字線210或數位線215),以存取目標記憶體胞元205。本端記憶體控制器260可在寫入操作期間將特定信號(例如電壓)施加至數位線215以將特定狀態(例如電荷)儲存於記憶體胞元205之電容器230中,該特定狀態(例如電荷)可指示所要邏輯狀態。In some cases, the local memory controller 260 may be configured to perform a write operation (eg, a program operation) on one or more memory cells 205 of the memory die 200 . During a write operation, memory cells 205 of memory die 200 may be programmed to store a desired logic state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 260 can identify the target memory cell 205 for the write operation. The local memory controller 260 can identify the target word line 210 and the target bit line 215 in electronic communication with the target memory cell 205 (eg, the address of the target memory cell 205 ). The local memory controller 260 can activate the target word line 210 and the target bit line 215 (for example, apply a voltage to the word line 210 or the bit line 215 ) to access the target memory cell 205 . The local memory controller 260 may apply a specific signal (such as a voltage) to the digit line 215 during a write operation to store a specific state (such as a charge) in the capacitor 230 of the memory cell 205, the specific state (such as charge) may indicate a desired logic state.

在一些狀況下,本端記憶體控制器260可經組態以對記憶體晶粒200之一或多個記憶體胞元205執行讀取操作(例如感測操作)。在讀取操作期間,可判定儲存於記憶體晶粒200之記憶體胞元205中之邏輯狀態。在一些狀況下,可在單個讀取操作期間感測複數個記憶體胞元205。本端記憶體控制器260可識別執行讀取操作所針對的目標記憶體胞元205。本端記憶體控制器260可識別與目標記憶體胞元205電子通信之目標字線210及目標數位線215 (例如目標記憶體胞元205之位址)。本端記憶體控制器260可啟動目標字線210及目標數位線215 (例如將電壓施加至字線210或數位線215),以存取目標記憶體胞元205。目標記憶體胞元205可回應於使存取線偏置而將信號傳送至感測組件245。感測組件245可放大該信號。本端記憶體控制器260可激發感測組件245 (例如鎖存感測組件)且藉此比較自記憶體胞元205接收之信號與參考信號250。基於該比較,感測組件245可判定儲存於記憶體胞元205上之邏輯狀態。本端記憶體控制器260可將儲存於記憶體胞元205上之邏輯狀態傳達至外部記憶體控制器105 (或裝置記憶體控制器155)作為讀取操作之部分。In some cases, the local memory controller 260 can be configured to perform a read operation (eg, a sense operation) on one or more memory cells 205 of the memory die 200 . During a read operation, the logic state stored in memory cells 205 of memory die 200 may be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. The local memory controller 260 can identify the target memory cell 205 for the read operation. The local memory controller 260 can identify the target word line 210 and the target bit line 215 in electronic communication with the target memory cell 205 (eg, the address of the target memory cell 205 ). The local memory controller 260 can activate the target word line 210 and the target bit line 215 (for example, apply a voltage to the word line 210 or the bit line 215 ) to access the target memory cell 205 . The target memory cell 205 can send a signal to the sense component 245 in response to biasing the access line. The sensing component 245 can amplify the signal. The local memory controller 260 can activate a sensing element 245 (eg, a latch sensing element) and thereby compare the signal received from the memory cell 205 with the reference signal 250 . Based on the comparison, the sensing component 245 can determine the logic state stored on the memory cell 205 . Local memory controller 260 may communicate the logic state stored on memory cell 205 to external memory controller 105 (or device memory controller 155) as part of a read operation.

在一些記憶體架構中,存取記憶體胞元205可降級或毀壞儲存於記憶體胞元205中之邏輯狀態。舉例而言,在DRAM架構中執行之讀取操作可使目標記憶體胞元之電容器部分或完全地放電。本端記憶體控制器260可執行重新寫入操作或再新操作以使記憶體胞元恢復至其原始邏輯狀態。本端記憶體控制器260可在讀取操作之後將邏輯狀態重新寫入至目標記憶體胞元。在一些狀況下,重新寫入操作可被認為係讀取操作之部分。另外,啟動諸如字線210之單一存取線可干擾與彼存取線電子通信之一些記憶體胞元中所儲存之狀態。因此,可對可尚未存取之一或多個記憶體胞元執行重新寫入操作或再新操作。In some memory architectures, accessing the memory cell 205 can degrade or destroy the logical state stored in the memory cell 205 . For example, a read operation performed in a DRAM architecture may partially or completely discharge a capacitor of a target memory cell. The local memory controller 260 can perform a rewrite operation or a refresh operation to restore the memory cells to their original logic state. The local memory controller 260 can rewrite the logic state to the target memory cell after the read operation. In some cases, a rewrite operation may be considered part of a read operation. Additionally, activating a single access line, such as word line 210, can disturb the state stored in some of the memory cells that are in electronic communication with that access line. Therefore, a rewrite operation or a refresh operation may be performed on one or more memory cells that may not have been accessed yet.

記憶體晶粒200可經組態以將信號傳輸至主機裝置及自主機裝置接收信號,且在一些狀況下,當自主機裝置接收信號時可經歷干擾或雜訊。舉例而言,來自主機裝置之信號可具有較高轉換速率,此可導致較高雜訊位準(例如經由相鄰記憶體裝置上之信號反射)。在一些狀況下,一或多個相鄰記憶體晶粒200之電容可至少部分地造成信號反射。主機裝置可經組態以藉由指示與記憶體晶粒200之電容性組件相關聯的目標電容或組態而減少由記憶體晶粒200經歷之雜訊。電容性組件可操作以調整或組態與記憶體晶粒200之I/O襯墊相關聯之電容,且可包括一或多個電容器及可將該一或多個電容器與該I/O襯墊選擇性地耦接之一或多個關聯切換組件(例如電晶體)。在一些狀況下,由電容性組件之目標電容或組態指示之電容可減小自主機裝置至記憶體晶粒200之傳信之轉換速率(例如記憶體晶粒200處之轉換速率),且減小之轉換速率可減少信號反射及關聯雜訊。Memory die 200 may be configured to transmit signals to and receive signals from a host device, and in some cases may experience interference or noise when receiving signals from a host device. For example, signals from a host device may have higher slew rates, which may result in higher noise levels (eg, via signal reflections on neighboring memory devices). In some cases, the capacitance of one or more adjacent memory dies 200 may at least partially cause signal reflections. The host device can be configured to reduce the noise experienced by the memory die 200 by indicating a target capacitance or configuration associated with the capacitive components of the memory die 200 . The capacitive component is operable to adjust or configure the capacitance associated with the I/O pads of the memory die 200, and may include one or more capacitors and may connect the one or more capacitors to the I/O pads. The pads are selectively coupled to one or more associated switching components (eg, transistors). In some cases, the capacitance dictated by the target capacitance or configuration of the capacitive component may reduce the slew rate of signaling from the host device to the memory die 200 (e.g., the slew rate at the memory die 200), and reduce Small slew rates reduce signal reflections and associated noise.

3 說明根據如本文中所揭示之實例的支援可組態之記憶體晶粒電容之電路300的實例。在一些實例中,電路300可表示記憶體裝置之一部分,其中記憶體裝置可包括如參看圖2所描述之記憶體晶粒200。舉例而言,由電路300表示之電路可包括I/O襯墊305。I/O襯墊305可與接合線或其他互連件耦接,該接合線或其他互連件可繼而將I/O襯墊305與例如記憶體裝置之接腳耦接。儘管被描述為「襯墊」,但本文中之申請專利範圍及揭露內容不限於I/O襯墊305之任何特定實體外觀尺寸。實情為,I/O襯墊(諸如I/O襯墊305之實例)可指經組態以在包括I/O襯墊之記憶體晶粒外部接收或傳輸信號的任何導電結構。 3 illustrates an example of a circuit 300 supporting configurable memory die capacitance according to examples as disclosed herein. In some examples, circuit 300 may represent a portion of a memory device, which may include memory die 200 as described with reference to FIG. 2 . For example, the circuit represented by circuit 300 may include I/O pad 305 . I/O pads 305 may be coupled with bond wires or other interconnects, which may in turn couple I/O pads 305 with, for example, pins of a memory device. Although described as a "pad," the scope and disclosure herein is not limited to any particular physical dimensions of I/O pad 305 . Rather, an I/O pad, such as the example of I/O pad 305, may refer to any conductive structure configured to receive or transmit signals external to the memory die that includes the I/O pad.

由電路300表示之電路亦可包括一或多個導電路徑330 (例如跡線、電線(諸如接合線)、導電線/層等)及一輸入緩衝器310。導電路徑330可為參考圖1及圖2所描述之導電線之實例。電路300中所說明之電路可經組態以調整或組態記憶體晶粒之電容(例如藉由調整或組態I/O襯墊305之電容)。The circuit represented by circuit 300 may also include one or more conductive paths 330 (eg, traces, wires (such as bond wires), conductive lines/layers, etc.) and an input buffer 310 . The conductive path 330 may be an example of the conductive lines described with reference to FIGS. 1 and 2 . The circuit illustrated in circuit 300 can be configured to adjust or configure the capacitance of a memory die (eg, by adjusting or configuring the capacitance of I/O pad 305).

舉例而言,由電路300所說明之電路可包括一或多個電容性組件315,其中電容性組件315可操作以調整(例如組態)與I/O襯墊305相關聯之電容。電容性組件315可包括電容器320 (例如電容器320-a)及關聯切換組件325 (例如切換組件325-a)。在一些實例中,電容性組件可包括多個電容器320 (例如電容器320-a、320-b及320-c)及多個切換組件(例如切換組件325-a、325-b及325-c)。切換組件325 (例如電晶體)可與一或多個各別電容器320相關聯。舉例而言,切換組件325-a可與電容器320-a相關聯,切換組件325-b可與電容器320-b相關聯,等等。For example, the circuit illustrated by circuit 300 may include one or more capacitive components 315 , wherein capacitive component 315 is operable to adjust (eg, configure) the capacitance associated with I/O pad 305 . Capacitive components 315 may include a capacitor 320 (eg, capacitor 320-a) and an associated switching component 325 (eg, switching component 325-a). In some examples, the capacitive components may include multiple capacitors 320 (such as capacitors 320-a, 320-b, and 320-c) and multiple switching components (such as switching components 325-a, 325-b, and 325-c) . Switching components 325 , such as transistors, may be associated with one or more respective capacitors 320 . For example, switching component 325-a may be associated with capacitor 320-a, switching component 325-b may be associated with capacitor 320-b, and so on.

電容性組件315可與I/O襯墊305耦接,且因此電容性組件315之一或多個電容器320與I/O襯墊305可經由切換組件325可選擇性地耦接。在一些狀況下,電容性組件315亦可與輸入緩衝器310耦接,且因此電容性組件315之一或多個電容器320與輸入緩衝器310可經由切換組件325可選擇性地耦接。舉例而言,一或多個切換組件325可啟動或接通(閉合)一或多個電容器320且將一或多個電容器320與I/O襯墊305與輸入緩衝器310之間的導電路徑330耦接。切換組件325可個別地或協同地啟動或根本不被啟動,使得電容器320中之任一或多者可與I/O襯墊305耦接,或電容器320中無一者可與I/O襯墊305耦接。因為電容性組件315可與I/O襯墊305耦接,所以電容性組件315可操作以調整或組態與I/O襯墊305相關聯之電容(例如記憶體晶粒之輸入電容)。如上文所描述,電容性組件315之切換組件325可操作以將電容性組件315之多個(例如一個、多個或無)電容器320與I/O襯墊305耦接。與記憶體晶粒相關聯之主機裝置或記憶體裝置可指示與I/O襯墊305耦接以調整或組態與I/O襯墊305相關聯之電容的電容器320之數目。Capacitive component 315 may be coupled to I/O pad 305 , and thus one or more capacitors 320 of capacitive component 315 may be selectively coupled to I/O pad 305 via switching component 325 . In some cases, the capacitive component 315 may also be coupled to the input buffer 310 , and thus one or more capacitors 320 of the capacitive component 315 may be selectively coupled to the input buffer 310 via the switching component 325 . For example, one or more switching components 325 can activate or switch on (close) one or more capacitors 320 and connect one or more capacitors 320 to the conductive path between I/O pad 305 and input buffer 310 330 coupling. Switching components 325 may be activated individually or in concert, or not at all, such that any one or more of capacitors 320 may be coupled to I/O pad 305, or none of capacitors 320 may be coupled to I/O pad Pad 305 is coupled. Because capacitive component 315 can be coupled with I/O pad 305, capacitive component 315 is operable to adjust or configure the capacitance associated with I/O pad 305 (eg, the input capacitance of a memory die). As described above, switching component 325 of capacitive component 315 is operable to couple a plurality (eg, one, multiple, or none) of capacitors 320 of capacitive component 315 with I/O pad 305 . The host device or memory device associated with the memory die may indicate the number of capacitors 320 coupled to the I/O pad 305 to adjust or configure the capacitance associated with the I/O pad 305 .

在一些狀況下,主機裝置可將指示用於一或多個電容性組件315之目標電容或指示用於一或多個電容性組件315之組態(例如指示與I/O襯墊305耦接之電容器320之數目)之傳信傳輸至記憶體裝置。在第一實例中,來自主機裝置之傳信可向記憶體裝置指示將用於一或多個電容性組件315之目標電容或相關組態資訊儲存於記憶體裝置之一或多個模式暫存器中。在一些狀況下,模式暫存器可包括專用於儲存一或多個電容性組件315之狀態(例如與一或多個電容性組件315相關聯之切換組件325之狀態)之額外記憶體。舉例而言,模式暫存器可儲存指示待閉合或啟動之切換組件325之數目的資訊(例如一或多個邏輯值)。另外或替代地,模式暫存器可將一或多個邏輯值儲存為點陣圖,其中該點陣圖之每一位元可對應於電容性組件315之一切換組件325。因而,點陣圖之每一位元可指示是要啟動(閉合)抑或解除啟動(斷開)對應切換組件325 (例如藉由指示邏輯0或邏輯1)。In some cases, the host device may indicate a target capacitance for one or more capacitive elements 315 or an indication for the configuration of one or more capacitive elements 315 (such as an indication of coupling to I/O pad 305 The signaling of the number of capacitors 320) is transmitted to the memory device. In a first example, the signaling from the host device may instruct the memory device to store target capacitance or related configuration information for one or more capacitive elements 315 in one or more mode registers of the memory device device. In some cases, the mode register may include additional memory dedicated to storing the state of one or more capacitive elements 315 , such as the state of switching element 325 associated with one or more capacitive elements 315 . For example, the mode register may store information (eg, one or more logical values) indicating the number of switching elements 325 to be closed or activated. Additionally or alternatively, the mode register may store one or more logical values as a dot map, where each bit of the dot map may correspond to a switching element 325 of the capacitive element 315 . Thus, each bit of the bitmap may indicate whether the corresponding switching element 325 is to be activated (closed) or deactivated (opened) (eg, by indicating a logic 0 or a logic 1).

因此,記憶體裝置可將用於一或多個電容性組件315之目標電容或相關組態資訊儲存於模式暫存器中,且可使用所儲存目標電容或相關組態資訊以組態該一或多個電容性組件315 (例如藉由啟動及/或解除啟動切換組件325)且藉此調整與記憶體晶粒相關聯之電容(例如與I/O襯墊305相關聯之電容)。舉例而言,每當記憶體裝置通電時,記憶體裝置(例如記憶體裝置之控制器)就可存取模式暫存器且相應地組態一或多個電容性組件315。Accordingly, the memory device may store target capacitance or related configuration information for one or more capacitive elements 315 in the mode register, and may use the stored target capacitance or related configuration information to configure the one or more capacitive elements 315. One or more capacitive elements 315 (eg, by activating and/or deactivating switching elements 325 ) and thereby adjust the capacitance associated with the memory die (eg, the capacitance associated with I/O pad 305 ). For example, whenever the memory device is powered on, the memory device (eg, the memory device's controller) may access the mode register and configure the one or more capacitive elements 315 accordingly.

在第二實例中,來自主機裝置之傳信可指示或命令用於一或多個電容性組件315之目標電容或組態(例如不向記憶體裝置指定將關聯資訊儲存於一或多個模式暫存器中)。因而,記憶體裝置可根據傳信組態一或多個電容性組件315 (例如藉由對傳信作出回應而直接啟動及/或解除啟動切換組件325)。記憶體裝置可調整電容性組件,而不將與所接收指示相關聯之資訊儲存至一或多個模式暫存器(及稍後自一或多個模式暫存器讀取資訊)。在一些狀況下,記憶體裝置可維持用於一或多個電容性組件315之所指示之目標電容或組態直至自主機裝置接收到指示新目標電容或新組態的新傳信。在一些狀況下,記憶體裝置在斷電時在若尚未接收到新傳信的情況下,可將用於一或多個電容性組件315之目標電容或組態儲存於模式暫存器中。In a second example, signaling from the host device may indicate or command a target capacitance or configuration for one or more capacitive elements 315 (e.g., not specify to a memory device to store associated information in one or more modes in the scratchpad). Thus, the memory device may configure one or more capacitive elements 315 in response to the signaling (eg, by directly activating and/or deactivating the switching element 325 in response to the signaling). The memory device may adjust the capacitive element without storing information associated with the received indication to (and later reading information from) one or more mode registers. In some cases, the memory device may maintain the indicated target capacitance or configuration for one or more capacitive components 315 until a new signaling is received from the host device indicating a new target capacitance or new configuration. In some cases, the memory device may store the target capacitance or configuration for one or more capacitive elements 315 in the mode register when powered down if no new signaling has been received.

用於一或多個電容性組件315之目標電容或組態可基於信號轉換速率、記憶體晶粒電容(例如電容性組件315之寄生電容或除寄生電容之外的其他電容)、信號雜訊(例如反射雜訊)或其類似者中之一或多者,或其任何組合。在一項實例中,用於一或多個電容性組件315之目標電容或組態可支援目標轉換速率。相似地,用於一或多個電容性組件315之目標電容或組態可經組態以降低主機裝置與記憶體裝置之間的信號之雜訊位準(例如自相鄰記憶體裝置反射之雜訊)。用於一或多個電容性組件315之目標電容或組態亦可基於記憶體晶粒之一或多個組件之寄生電容(例如I/O緩衝器310之PMOS電晶體及/或NMOS電晶體之閘極電容)。舉例而言,目標電容或組態可基於記憶體晶粒之寄生電容,使得電容性組件315之電容連同寄生電容可等於目標總電容。目標總電容可基於目標轉換速率或信號雜訊,如上文所描述,且可另外基於記憶體裝置及/或主機裝置模擬結果或量測。The target capacitance or configuration for one or more capacitive elements 315 may be based on signal slew rate, memory die capacitance (eg, parasitic capacitance of capacitive element 315 or other capacitance in addition to parasitic capacitance), signal noise (such as reflection noise) or one or more of the like, or any combination thereof. In one example, a target capacitance or configuration for one or more capacitive components 315 can support a target slew rate. Similarly, the target capacitance or configuration for one or more capacitive elements 315 can be configured to reduce the noise level of the signal between the host device and the memory device (e.g., reflections from adjacent memory devices). noise). The target capacitance or configuration for one or more capacitive components 315 may also be based on the parasitic capacitance of one or more components of the memory die (e.g., PMOS transistors and/or NMOS transistors of I/O buffer 310 the gate capacitance). For example, the target capacitance or configuration can be based on the parasitic capacitance of the memory die such that the capacitance of the capacitive element 315 together with the parasitic capacitance can be equal to the target total capacitance. The target total capacitance may be based on target slew rate or signal noise, as described above, and may additionally be based on memory device and/or host device simulation results or measurements.

用於一或多個電容性組件315之目標記憶體晶粒電容或組態亦可基於記憶體裝置之置放、一或多個關聯(耦接)記憶體裝置之置放或記憶體裝置之一或多個記憶體晶粒之置放。舉例而言,記憶體裝置或一或多個關聯記憶體晶粒之置放可影響與記憶體裝置相關聯之一或多個寄生電容(例如及關聯雜訊),或可影響一或多個其他傳信參數。因而,用於一或多個電容性組件之目標記憶體晶粒電容或組態可基於藉由記憶體裝置或一或多個關聯記憶體裝置及晶粒之置放所引入的電容性或傳信效應。另外或替代地,目標記憶體晶粒電容或組態可基於主機裝置與記憶體裝置之間的信號路由及通信結構。在一些狀況下,記憶體裝置之每一記憶體晶粒可具有用於關聯電容性組件315之不同目標電容或不同組態(例如基於置放及/或路由)。與主機裝置耦接之每一記憶體裝置亦可具有用於關聯電容性組件315之不同目標電容或不同組態。The target memory die capacitance or configuration for one or more capacitive elements 315 may also be based on the placement of the memory device, the placement of one or more associated (coupled) memory devices, or the placement of the memory device. Placement of one or more memory dies. For example, placement of a memory device or one or more associated memory dies may affect one or more parasitic capacitances (eg, and associated noise) associated with the memory device, or may affect one or more Other signaling parameters. Thus, a target memory die capacitance or configuration for one or more capacitive components may be based on the capacitive or conductive capacitance introduced by the placement of the memory device or one or more associated memory devices and die. letter effect. Additionally or alternatively, the target memory die capacitance or configuration may be based on signal routing and communication structures between the host device and the memory device. In some cases, each memory die of a memory device may have a different target capacitance or a different configuration (eg, based on placement and/or routing) for the associated capacitive component 315 . Each memory device coupled with the host device may also have a different target capacitance or a different configuration for the associated capacitive component 315 .

舉例而言,每一記憶體裝置可基於記憶體裝置之位置或置放及/或基於信號路由(例如相對於主機裝置或終端阻抗,諸如依據記憶體裝置與主機裝置之間的信號路徑長度(例如匯流排長度)或終端阻抗)而具有用於電容性組件315之目標電容。在一項實例中,主機裝置可與兩個或多於兩個記憶體裝置耦接,且與相比於第一記憶體裝置更遠離主機裝置的記憶體裝置相比,更接近主機裝置之第一記憶體裝置可具有用於電容性組件315之更高目標電容(例如基於關聯組態) (例如額外2微微法拉(pF))。另外或替代地,將主機與兩個或多於兩個記憶體裝置耦接之匯流排可包括可減弱或消除一些傳輸雜訊之阻抗(例如終端阻抗,諸如終端電阻器(RTT))。因此,與比第一記憶體裝置更接近阻抗的記憶體裝置相比,更遠離阻抗之第一記憶體裝置可具有用於電容性組件315之更高目標電容(例如基於關聯組態)。For example, each memory device may be based on the location or placement of the memory device and/or on signal routing (e.g., relative to the host device or termination impedance, such as in terms of the signal path length between the memory device and the host device ( such as bus length) or termination impedance) to have a target capacitance for capacitive component 315 . In one example, the host device may be coupled to two or more memory devices, with a second memory device closer to the host device than a memory device further away from the host device than a first memory device. A memory device may have a higher target capacitance (eg, based on the associated configuration) for capacitive component 315 (eg, an additional 2 picofarads (pF)). Additionally or alternatively, the bus that couples the host to two or more memory devices may include impedances (eg, termination impedances such as termination resistors (RTT)) that can attenuate or eliminate some transmission noise. Thus, a first memory device that is further away from impedance may have a higher target capacitance for capacitive component 315 (eg, based on the associated configuration) than a memory device that is closer in impedance than the first memory device.

在一項實例中,記憶體晶粒(例如包括記憶體晶粒之記憶體裝置)可經組態以與主機裝置通信(例如傳輸及接收信號),且當自主機裝置接收信號時可經歷干擾或雜訊。舉例而言,來自主機裝置之信號(例如CA信號)可具有較小上升及/或下降時間(較高轉換速率),此可導致(例如經由信號反射)用於相鄰記憶體裝置之較高雜訊位準。在一些狀況下,一或多個相鄰記憶體晶粒之電容可至少部分地造成信號反射(例如歸因於印刷電路板(PCB)不連續性)。主機裝置可經組態以藉由向記憶體晶粒之電容性組件315指示目標電容或組態(例如藉由啟動及/或解除啟動切換組件325)而減少由記憶體晶粒經歷之雜訊。在一些狀況下,由電容性組件315之目標電容或組態指示之電容可減小自主機裝置至記憶體晶粒之傳信之轉換速率(例如記憶體晶粒處之轉換速率),且減小之轉換速率可減少信號反射及關聯雜訊。In one example, a memory die (e.g., a memory device including a memory die) can be configured to communicate (e.g., transmit and receive signals) with a host device, and can experience disturbances when receiving signals from the host device or noise. For example, a signal from a host device (such as a CA signal) may have smaller rise and/or fall times (higher slew rates), which may result (for example, via signal reflections) at higher Noise level. In some cases, the capacitance of one or more adjacent memory dies may at least partially cause signal reflections (eg, due to printed circuit board (PCB) discontinuities). The host device can be configured to reduce the noise experienced by the memory die by indicating a target capacitance or configuration to the capacitive element 315 of the memory die (e.g., by activating and/or deactivating the switching element 325) . In some cases, the capacitance dictated by the target capacitance or configuration of capacitive component 315 may reduce the slew rate of signaling from the host device to the memory die (e.g., the slew rate at the memory die), and reduce The fast slew rate reduces signal reflections and associated noise.

主機裝置可向記憶體晶粒傳信以指示電容性組件315之目標電容或組態(例如包括是否使用模式暫存器之指示)。記憶體晶粒可自主機裝置接收傳信且可基於所指示之目標電容或組態來組態電容性組件315。舉例而言,與記憶體晶粒相關聯之控制器可根據所指示之目標電容或組態來啟動或解除啟動一或多個切換組件325。切換組件325可將一或多個關聯電容器320與記憶體晶粒之I/O襯墊305耦接或解耦,且因此可變更電容性組件315及I/O襯墊305之電容。I/O襯墊305之經調整電容可調整(例如減低)與在記憶體晶粒處所接收之信號相關聯的轉換速率且可減少由經反射信號產生之雜訊,此可增加記憶體裝置準確度。The host device may signal the memory die to indicate a target capacitance or configuration of capacitive element 315 (eg, including an indication of whether to use a mode register). The memory die can receive signaling from the host device and can configure the capacitive component 315 based on the indicated target capacitance or configuration. For example, a controller associated with a memory die may activate or deactivate one or more switching elements 325 according to an indicated target capacitance or configuration. The switching element 325 can couple or decouple one or more associated capacitors 320 from the I/O pad 305 of the memory die, and thus can change the capacitance of the capacitive element 315 and the I/O pad 305 . The adjusted capacitance of the I/O pad 305 can adjust (eg, reduce) the slew rate associated with the signal received at the memory die and can reduce noise generated by the reflected signal, which can increase the accuracy of the memory device. Spend.

4 說明根據如本文中所揭示之實例的用於支援可組態之記憶體晶粒電容之記憶體裝置之匯流排拓樸400的實例。在一些實例中,一或多個記憶體裝置405可使用匯流排拓樸400與主機裝置410 (例如系統單晶片(SoC))耦接。每一記憶體裝置405可包括一記憶體晶粒,該記憶體晶粒可為參考圖2及圖3所描述之記憶體晶粒的實例。在一些狀況下,記憶體裝置405可包括一個記憶體晶粒,且在其他狀況下,記憶體裝置可包括多個記憶體晶粒。記憶體晶粒可包括I/O襯墊,該I/O襯墊可為參考圖3所描述之I/O襯墊的實例。由匯流排拓樸400表示之連接亦可包括一或多個導電路徑(例如跡線、電線、導電線/層等),該一或多個導電路徑可為參考圖1所描述之信號路徑或導電線的實例。匯流排拓樸400中所說明之裝置可經組態以調整或組態記憶體晶粒之電容(例如藉由調整或組態關聯I/O襯墊之電容)。 4 illustrates an example of a bus topology 400 for a memory device supporting configurable memory die capacitance, according to examples as disclosed herein. In some examples, one or more memory devices 405 may be coupled to a host device 410 (eg, a system-on-chip (SoC)) using a bus topology 400 . Each memory device 405 may include a memory die, which may be an example of the memory die described with reference to FIGS. 2 and 3 . In some cases, memory device 405 may include one memory die, and in other cases, memory device may include multiple memory dies. The memory die may include I/O pads, which may be examples of the I/O pads described with reference to FIG. 3 . The connections represented by busbar topology 400 may also include one or more conductive paths (e.g., traces, wires, conductive lines/layers, etc.), which may be signal paths or signal paths as described with reference to FIG. An example of a conductive thread. The devices illustrated in bus topology 400 can be configured to adjust or configure the capacitance of a memory die (eg, by adjusting or configuring the capacitance of an associated I/O pad).

舉例而言,由匯流排拓樸400所說明之每一記憶體裝置可包括一或多個電容性組件,其中電容性組件可為參考圖3所描述之電容性組件315的實例。每一電容性組件可與關聯I/O襯墊可選擇性地耦接(例如經由電容性組件之一或多個切換組件)以便調整或組態I/O襯墊之電容(例如至目標電容)。在一些狀況下,記憶體晶粒或關聯I/O襯墊之目標電容可基於一或多個記憶體裝置405相對於彼此及/或相對於主機裝置410之組態或拓樸(例如可基於匯流排拓樸400之特性)。For example, each memory device illustrated by bus topology 400 may include one or more capacitive elements, where a capacitive element may be an example of capacitive element 315 described with reference to FIG. 3 . Each capacitive element can be selectively coupled with an associated I/O pad (e.g., via one or more switching elements of the capacitive element) in order to adjust or configure the capacitance of the I/O pad (e.g., to a target capacitance ). In some cases, the target capacitance of a memory die or associated I/O pad may be based on the configuration or topology of one or more memory devices 405 relative to each other and/or relative to host device 410 (eg, may be based on characteristics of the bus topology 400).

在一項實例中,多個記憶體裝置405可經由一或多條線415、420及/或425以飛躍式拓樸形式與主機裝置410-a耦接,其中多個記憶體裝置405可經由共同中繼線415-a及各別分支線425與主機裝置410-a耦接,其中每一分支線425將記憶體裝置405與共同中繼線415-a耦接。中繼線415-a (例如中繼PCB跡線)可將主機裝置410-a與記憶體裝置405耦接,且中繼線415-a之長度可取決於主機裝置410-a與記憶體裝置405之間的距離。在一些狀況下,中繼線415-a可為將主機裝置410-a與記憶體裝置405耦接之最長線。跡線420-a、420-b、420-c、420-d及420-e可將用於記憶體裝置405之分支線425彼此耦接,且在一些狀況下,可表示該等分支線425之間的PCB跡線。與跡線420相關聯之長度可基於記憶體裝置405之封裝大小。分支線425-a、425-b、425-c、425-d及425-e可分別表示自中繼線415-a或各別跡線420至記憶體裝置405-a、405-b、405-c、405-d及405-e之接腳(例如對應於球狀柵格陣列(BGA)之球)的PCB跡線。在一些狀況下,分支線425可短於跡線420或中繼線415-a。In one example, the plurality of memory devices 405 can be coupled to the host device 410-a in a leap topology via one or more lines 415, 420, and/or 425, wherein the plurality of memory devices 405 can be coupled via The common trunk line 415-a and respective branch lines 425 are coupled to the host device 410-a, wherein each branch line 425 couples the memory device 405 to the common trunk line 415-a. A relay line 415-a (such as a relay PCB trace) can couple the host device 410-a with the memory device 405, and the length of the relay line 415-a can depend on the distance between the host device 410-a and the memory device 405. distance. In some cases, trunk line 415 - a may be the longest line coupling host device 410 - a with memory device 405 . Traces 420-a, 420-b, 420-c, 420-d, and 420-e may couple stub lines 425 for memory device 405 to one another and, in some cases, may represent stub lines 425 between PCB traces. The length associated with trace 420 may be based on the package size of memory device 405 . The branch lines 425-a, 425-b, 425-c, 425-d, and 425-e may respectively represent from the trunk line 415-a or the respective traces 420 to the memory devices 405-a, 405-b, 405-c , 405-d and 405-e the PCB traces of the pins (eg, corresponding to balls of a ball grid array (BGA)). In some cases, branch line 425 may be shorter than trace line 420 or trunk line 415-a.

在一些實例中,線415、420及425可表示用於CA匯流排路由之線,且在一些狀況下,多個信號(例如20個信號)可在每一線上被攜載(例如圖4中所說明之每條線可對應於平行線之群組)。線415、420及425可表示主機裝置410-a與記憶體裝置405之間的一至多個連接,其中主機裝置410-a上之一個接腳或襯墊可與記憶體裝置405中之多於一者上之接腳或襯墊耦接。舉例而言,主機裝置410-a上之一個接腳可與每一記憶體裝置405上之接腳耦接。In some examples, lines 415, 420, and 425 may represent lines used for CA bus routing, and in some cases multiple signals (eg, 20 signals) may be carried on each line (eg, in FIG. 4 Each line illustrated may correspond to a group of parallel lines). Lines 415, 420, and 425 may represent one or more connections between host device 410-a and memory device 405, where one pin or pad on host device 410-a may be connected to more than one pin in memory device 405. Pins or pads on one are coupled. For example, a pin on the host device 410 - a can be coupled to a pin on each memory device 405 .

主機裝置410可與多個記憶體裝置405耦接以實現一或多個益處。舉例而言,主機裝置410可與多個記憶體裝置405 (例如四個或五個記憶體裝置405)耦接以便增加例如產出量、頻寬及記憶體密度,作為汽車先進駕駛輔助系統(ADAS)、人工智慧(AI)應用或其他應用之部分。在一些狀況下,自主機裝置410 (例如CA信號)至記憶體裝置405之信號可具有較小的上升及/或下降時間,其可造成較高位準之雜訊自相鄰記憶體裝置405反射。在一些狀況下,可能影響與用於解譯傳信之資料窗相關聯之電壓裕度的在記憶體裝置405處之雜訊位準可降至低於記憶體裝置405之輸入位準且可造成記憶體裝置405處之時序誤差。在一些狀況下,終端阻抗(例如RTT 430)可吸收或減弱反射雜訊,且因而,更遠離RTT 430而定位之記憶體裝置405 (例如記憶體裝置405-a及/或405-b)可經歷來自附近記憶體裝置405之更多反射雜訊。Host device 410 may be coupled with multiple memory devices 405 to achieve one or more benefits. For example, the host device 410 can be coupled with multiple memory devices 405 (e.g., four or five memory devices 405) to increase, for example, throughput, bandwidth, and memory density as an automotive ADAS ( ADAS), artificial intelligence (AI) applications, or other applications. In some cases, signals from host device 410 (e.g., CA signals) to memory device 405 may have small rise and/or fall times, which may cause higher level noise to be reflected from adjacent memory devices 405 . In some cases, the noise level at the memory device 405, which may affect the voltage margin associated with the data window used to interpret the signalling, may drop below the input level of the memory device 405 and may cause Timing error at memory device 405 . In some cases, a termination impedance (eg, RTT 430) can absorb or attenuate reflected noise, and thus, memory devices 405 (eg, memory devices 405-a and/or 405-b) positioned farther from RTT 430 can More reflection noise from nearby memory devices 405 is experienced.

因而,記憶體裝置405或記憶體裝置405之一或多個晶粒可組態有電容性組件,該電容性組件可操作以調整或組態與該電容性組件相關聯之記憶體晶粒之電容(例如記憶體晶粒之I/O襯墊之電容)。電容性組件可藉由調整記憶體裝置405之一或多個記憶體晶粒之電容而減少關聯記憶體裝置405處之雜訊(例如反射雜訊)。舉例而言,主機裝置410可經組態以藉由指示用於記憶體裝置405之電容性組件之目標電容或組態而減少由一或多個記憶體裝置405經歷之雜訊。在一些狀況下,電容性組件之所得電容(亦即,如藉由記憶體裝置405基於指示所調整(調諧、組態)之電容性組件之電容)可減小自主機裝置410至記憶體裝置405之信號之轉換速率(例如記憶體裝置405處之轉換速率),且減小之轉換速率可減少信號反射及關聯雜訊。Thus, memory device 405 or one or more dies of memory device 405 may be configured with a capacitive element operable to adjust or configure the memory die associated with the capacitive element. Capacitance (such as the capacitance of the I/O pad of the memory die). Capacitive components can reduce noise (eg, reflection noise) at the associated memory device 405 by adjusting the capacitance of one or more memory dies of the memory device 405 . For example, host device 410 may be configured to reduce noise experienced by one or more memory devices 405 by indicating a target capacitance or configuration for capacitive components of memory device 405 . In some cases, the resulting capacitance of the capacitive element (i.e., the capacitance of the capacitive element as adjusted (tuned, configured) by the memory device 405 based on the indication) may decrease from the host device 410 to the memory device. The slew rate of the signal at 405, such as the slew rate at memory device 405, and a reduced slew rate can reduce signal reflections and associated noise.

舉例而言,較遠離RTT 430之記憶體裝置(例如記憶體裝置405-a及/或405-b)與較接近RTT 430之記憶體裝置405 (例如記憶體裝置405-c及/或405-d)相比可具有用於電容性組件之較高目標電容(例如基於關聯組態)。另外或替代地,較接近主機裝置410之記憶體裝置(例如記憶體裝置405-a及/或405-b)與較遠離主機裝置410之記憶體裝置405 (例如記憶體裝置405-c及/或405-d)相比可具有用於電容性組件之較高目標電容(例如基於關聯組態)。For example, memory devices farther away from RTT 430 (such as memory devices 405-a and/or 405-b) and memory devices 405 closer to RTT 430 (such as memory devices 405-c and/or 405- d) Can have a higher target capacitance for capacitive components than can be (eg based on associated configuration). Additionally or alternatively, memory devices closer to host device 410 (such as memory devices 405-a and/or 405-b) and memory devices 405 farther away from host device 410 (such as memory devices 405-c and/or or 405-d) may have a higher target capacitance for the capacitive component than (eg, based on the associated configuration).

主機裝置410可向記憶體裝置405傳信以指示電容性組件之目標電容或組態(例如,用於記憶體裝置405儲存於模式暫存器中之組態資訊之指示、包含組態資訊之一或多個命令)。記憶體裝置405可自主機裝置410接收信號且可基於所指示之目標電容或組態來組態電容性組件。舉例而言,與記憶體裝置405相關聯之控制器可根據所指示之目標電容或組態而啟動(閉合)或解除啟動(斷開)電容性組件之一或多個切換組件。在經啟動時,切換組件可將一或多個關聯電容器與記憶體裝置405之記憶體晶粒之I/O襯墊耦接,此可變更I/O襯墊及記憶體晶粒之電容(例如記憶體晶粒輸入電容)。I/O襯墊之經調整電容可組態(設定) (例如減低)與在記憶體晶粒處及在記憶體裝置405處所接收之信號相關聯的轉換速率,且可減少由經反射信號產生之雜訊。減少雜訊可例如藉由增加信號準確度及電壓裕度而改良記憶體裝置405處之效能。Host device 410 may signal memory device 405 to indicate a target capacitance or configuration of a capacitive element (e.g., an indication of configuration information, including configuration information, for memory device 405 to store in a mode register). one or more commands). Memory device 405 can receive signals from host device 410 and can configure capacitive components based on the indicated target capacitance or configuration. For example, a controller associated with memory device 405 may activate (close) or deactivate (open) one or more switching components of the capacitive component according to the indicated target capacitance or configuration. When activated, the switching element can couple one or more associated capacitors to the I/O pads of the memory die of the memory device 405, which can change the capacitance of the I/O pads and the memory die ( such as memory die input capacitance). The adjusted capacitance of the I/O pads can configure (set) (e.g., reduce) the slew rate associated with signals received at the memory die and at the memory device 405, and can reduce generation by reflected signals noise. Reducing noise can improve performance at memory device 405, for example, by increasing signal accuracy and voltage margin.

5 說明根據如本文中所揭示之實例的支援可組態之記憶體晶粒電容之記憶體裝置組態500的實例。在一些實例中,記憶體裝置組態500可為或包括記憶體裝置505,該記憶體裝置包括多個記憶體晶粒510,其中記憶體晶粒510可為參考圖2至圖4所描述之記憶體晶粒的實例且記憶體裝置505可為參考圖3及圖4所描述之記憶體裝置的實例。記憶體晶粒510可包括I/O襯墊,該I/O襯墊可為參考圖3及圖4所描述之I/O襯墊的實例。記憶體裝置505可包括一或多個導電路徑515 (例如跡線、電線、導電線/層等),該一或多個導電路徑可為參考圖2及圖3所描述之導電線或導電路徑的實例。記憶體裝置505可操作以調整(調諧、設定、組態)一或多個記憶體晶粒510之電容(例如藉由調整或組態關聯I/O襯墊之電容)。 5 illustrates an example of a memory device configuration 500 supporting configurable memory die capacitance according to examples as disclosed herein. In some examples, the memory device configuration 500 can be or include a memory device 505 that includes a plurality of memory dies 510, where the memory dies 510 can be as described with reference to FIGS. 2-4 An example of a memory die and memory device 505 may be an example of the memory device described with reference to FIGS. 3 and 4 . The memory die 510 may include an I/O pad, which may be an example of the I/O pad described with reference to FIGS. 3 and 4 . Memory device 505 may include one or more conductive paths 515 (e.g., traces, wires, conductive lines/layers, etc.), which may be conductive lines or conductive paths as described with reference to FIGS. 2 and 3 instance of . The memory device 505 is operable to adjust (tune, set, configure) the capacitance of one or more memory die 510 (eg, by adjusting or configuring the capacitance of an associated I/O pad).

舉例而言,記憶體裝置505之記憶體晶粒510可包括一或多個電容性組件,其中電容性組件可為參考圖3及圖4所描述之電容性組件的實例。每一電容性組件可與關聯I/O襯墊可選擇性地耦接(例如經由電容性組件之一或多個切換組件)以便調整或組態I/O襯墊之電容(例如至目標電容)。在一些狀況下,記憶體晶粒510或關聯I/O襯墊之目標電容可基於一或多個記憶體晶粒510相對於彼此及/或相對於記憶體裝置505之組態或拓樸的一或多個特性。另外或替代地,記憶體晶粒510或關聯I/O襯墊之目標電容可基於記憶體裝置505相對於一或多個其他記憶體裝置505及/或主機裝置之組態或拓樸的一或多個特性(例如用以將主機裝置與一或多個記憶體裝置505耦接之匯流排拓樸)。For example, memory die 510 of memory device 505 may include one or more capacitive elements, where the capacitive elements may be examples of the capacitive elements described with reference to FIGS. 3 and 4 . Each capacitive element can be selectively coupled with an associated I/O pad (e.g., via one or more switching elements of the capacitive element) in order to adjust or configure the capacitance of the I/O pad (e.g., to a target capacitance ). In some cases, the target capacitance of memory die 510 or associated I/O pads may be based on the configuration or topology of one or more memory die 510 relative to each other and/or relative to memory device 505 One or more properties. Additionally or alternatively, the target capacitance of the memory die 510 or associated I/O pads may be based on a configuration or topology of the memory device 505 relative to one or more other memory devices 505 and/or the host device. or multiple features (eg, bus topology for coupling the host device to one or more memory devices 505).

在一項實例中,記憶體裝置505可包括可將記憶體裝置505耦接至一或多個其他記憶體裝置505及/或主機裝置(例如經由一或多個跡線或其他互連件,諸如參考圖4之實例所描述)之接腳520 (例如BGA之球、電極、接腳、襯墊等)。接腳520可與記憶體裝置505之一或多個導電路徑515耦接,其中該一或多個導電路徑515可將該接腳與一或多個記憶體晶粒510耦接。舉例而言,導電路徑515可將接腳520耦接至對應於一或多個記憶體晶粒510之一或多個I/O襯墊。另外或替代地,導電路徑515可耦接兩個或多於兩個記憶體晶粒510。舉例而言,導電路徑515可耦接兩個對應記憶體晶粒510之兩個I/O襯墊。In one example, the memory device 505 can include a host device that can couple the memory device 505 to one or more other memory devices 505 and/or a host device (eg, via one or more traces or other interconnects, Pins 520 (eg, BGA balls, electrodes, pins, pads, etc.) such as described with reference to the example of FIG. 4 . The pin 520 can be coupled to one or more conductive paths 515 of the memory device 505 , wherein the one or more conductive paths 515 can couple the pin to one or more memory die 510 . For example, conductive paths 515 may couple pins 520 to one or more I/O pads corresponding to one or more memory dies 510 . Additionally or alternatively, the conductive path 515 may couple two or more than two memory dies 510 . For example, the conductive path 515 can couple two I/O pads of two corresponding memory dies 510 .

在一些狀況下,自主機裝置(例如CA信號)至記憶體裝置505之信號可具有較小上升及/或下降時間(例如較高轉換速率),此可造成較高位準之雜訊自相鄰記憶體裝置505反射。記憶體裝置505處之雜訊位準(其可被稱作或可影響電壓裕度或其他傳信窗)可降至低於用於記憶體裝置505之臨限值位準(例如基於可靠性臨限值)且可造成記憶體裝置505處之時序誤差或其他不利效應。In some cases, the signals from the host device (eg, CA signals) to the memory device 505 may have smaller rise and/or fall times (eg, higher slew rates), which may cause higher levels of noise from adjacent The memory device 505 reflects. Noise levels at the memory device 505 (which may be referred to as or may affect voltage margins or other signaling windows) can be reduced below threshold levels for the memory device 505 (e.g., based on reliability threshold) and may cause timing errors or other adverse effects at the memory device 505.

因而,記憶體裝置505之一或多個晶粒510可組態有電容性組件,該電容性組件可用以調整或組態對應記憶體晶粒510之電容(例如記憶體晶粒510之I/O襯墊之電容)。另外或替代地,一個記憶體晶粒510之電容性組件可用以調整或組態一或多個其他記憶體晶粒510之電容(例如在一或多個其他記憶體晶粒510之間分裂輸入電容、與一或多個其他記憶體晶粒510耦接)。舉例而言,記憶體晶粒510-a之電容性組件可操作以調整或組態記憶體晶粒510-a及510-b或記憶體晶粒510-a、510-b及510-c之電容(例如該電容性組件可與記憶體晶粒510-b及/或510-c之I/O接腳(例如選擇性地)耦接)。一或多個電容性組件可操作以藉由調整記憶體裝置505之一或多個記憶體晶粒510之電容而減少記憶體裝置505處之雜訊(例如反射雜訊)。舉例而言,主機裝置可經組態以藉由指示用於記憶體裝置505之一或多個記憶體晶粒510之電容性組件的目標電容或組態而減少由記憶體裝置505經歷之雜訊。在一些狀況下,與電容性組件相關聯之所得電容(亦即,如藉由記憶體裝置505基於指示所調整(調諧、組態)之電容性組件之電容)可減小自主機裝置至記憶體裝置505之信號之轉換速率(例如記憶體裝置505處之轉換速率),且減小之轉換速率可減少信號反射及關聯雜訊。Thus, one or more dies 510 of the memory device 505 can be configured with capacitive components that can be used to adjust or configure the capacitance of the corresponding memory die 510 (eg, I/O of the memory die 510). O pad capacitance). Additionally or alternatively, the capacitive components of one memory die 510 may be used to adjust or configure the capacitance of one or more other memory dies 510 (e.g., splitting the input between one or more other memory dies 510 capacitor, coupled with one or more other memory die 510). For example, the capacitive components of memory die 510-a are operable to adjust or configure memory dies 510-a and 510-b or memory dies 510-a, 510-b, and 510-c. Capacitor (eg, the capacitive element can be (eg, selectively) coupled to the I/O pins of the memory die 510-b and/or 510-c). The one or more capacitive elements are operable to reduce noise (eg, reflection noise) at the memory device 505 by adjusting the capacitance of one or more memory dies 510 of the memory device 505 . For example, a host device can be configured to reduce the noise experienced by the memory device 505 by indicating a target capacitance or configuration for a capacitive component of one or more memory dies 510 of the memory device 505. News. In some cases, the resulting capacitance associated with the capacitive element (i.e., the capacitance of the capacitive element as adjusted (tuned, configured) by the memory device 505 based on the indication) may decrease from the host device to the memory The slew rate of the signal of the body device 505, such as the slew rate at the memory device 505, and the reduced slew rate can reduce signal reflections and associated noise.

在一些狀況下,主機裝置可向記憶體裝置505傳信以指示一或多個電容性組件之目標電容或組態(例如,用於記憶體裝置505儲存於模式暫存器中之組態資訊之指示、包含組態資訊之一或多個命令)。記憶體裝置505可自主機裝置接收信號且可基於所指示之目標電容或組態來組態一或多個電容性組件。舉例而言,與記憶體裝置505相關聯之控制器可根據所指示之目標電容或組態而啟動(閉合)或解除啟動(斷開)電容性組件之一或多個切換組件。在經啟動時,切換組件可將一或多個關聯電容器與記憶體裝置505之一或多個記憶體晶粒510之一或多個I/O襯墊耦接,此可變更該一或多個I/O襯墊及該一或多個記憶體晶粒510之電容(例如輸入電容)。一或多個I/O襯墊之經調整電容可組態(設定) (例如減低)與在一或多個記憶體晶粒510處及在記憶體裝置505處所接收之信號相關聯的轉換速率,且可減少由經反射信號產生之雜訊。減少雜訊可藉由增加傳信準確度及裕度(例如電壓裕度)而改良裝置效能。In some cases, the host device may signal the memory device 505 to indicate a target capacitance or configuration of one or more capacitive components (e.g., for configuration information stored by the memory device 505 in a mode register). instructions, one or more commands containing configuration information). The memory device 505 can receive a signal from the host device and can configure one or more capacitive components based on the indicated target capacitance or configuration. For example, a controller associated with memory device 505 may activate (close) or deactivate (open) one or more switching components of the capacitive component according to the indicated target capacitance or configuration. When activated, the switching component can couple one or more associated capacitors to one or more I/O pads of one or more memory dies 510 of memory device 505, which can change the one or more I/O pads and the capacitance (eg, input capacitance) of the one or more memory dies 510 . The adjusted capacitance of one or more I/O pads may configure (set) (e.g., reduce) the slew rate associated with signals received at one or more memory die 510 and at memory device 505 , and can reduce the noise generated by the reflected signal. Reducing noise can improve device performance by increasing signaling accuracy and margins, such as voltage margins.

6 繪示根據如本文中所揭示之實例的支援可組態之記憶體晶粒電容之程序流程600的實例。在一些實例中,程序流程600可藉由記憶體裝置605及主機裝置實施,該記憶體裝置及該主機裝置可為參考圖3至圖5所描述之記憶體裝置及主機裝置的實例。記憶體裝置605可包括具有一或多個對應I/O襯墊之一或多個記憶體晶粒,且記憶體裝置605可操作以調整或組態一或多個記憶體晶粒之電容(例如藉由調整或組態關聯I/O襯墊之電容)。舉例而言,主機裝置610可向記憶體裝置605指示組態或調整一或多個記憶體晶粒之電容。 6 illustrates an example of a process flow 600 for supporting configurable memory die capacitance according to examples as disclosed herein. In some examples, program flow 600 may be implemented by memory device 605 and a host device, which may be examples of the memory device and host device described with reference to FIGS. 3-5 . Memory device 605 may include one or more memory dies with one or more corresponding I/O pads, and memory device 605 may be operable to adjust or configure the capacitance of one or more memory dies ( For example by adjusting or configuring the capacitance of the associated I/O pad). For example, the host device 610 may instruct the memory device 605 to configure or adjust the capacitance of one or more memory dies.

在程序流程600之以下描述中,記憶體裝置605與主機裝置610之間的操作可按與所展示次序不同的次序傳輸,或由主機裝置610或記憶體裝置605執行之操作可按不同次序或在不同時間執行。亦可自程序流程600省略特定操作,或可將其他操作添加至程序流程600。儘管主機裝置610及記憶體裝置605被展示為執行程序流程600之操作,但一些操作之一些態樣亦可由另一裝置執行。In the following description of program flow 600, operations between memory device 605 and host device 610 may be transmitted in a different order than shown, or operations performed by host device 610 or memory device 605 may be in a different order or Execute at different times. Certain operations may also be omitted from program flow 600 , or other operations may be added to program flow 600 . Although host device 610 and memory device 605 are shown as performing the operations of program flow 600, some aspects of some operations may also be performed by another device.

在615處,主機裝置610可基於與記憶體裝置605之I/O襯墊相關聯(例如與記憶體裝置605之記憶體晶粒相關聯)之目標電容識別記憶體裝置605之電容性組件之目標組態。在一些狀況下,主機裝置610可基於與記憶體裝置605之一或多個I/O襯墊相關聯(例如與記憶體裝置605之一或多個記憶體晶粒相關聯)之目標電容而識別用於記憶體裝置605之一或多個電容性組件之目標組態。目標電容可基於記憶體裝置605相對於主機裝置610或相對於與耦接主機裝置610及記憶體裝置605之匯流排相關聯之一或多個阻抗的位置。At 615, host device 610 may identify the capacitive components of memory device 605 based on the target capacitance associated with the I/O pads of memory device 605 (e.g., associated with a memory die of memory device 605). target configuration. In some cases, host device 610 may determine based on a target capacitance associated with one or more I/O pads of memory device 605 (e.g., associated with one or more memory dies of memory device 605). A target configuration for one or more capacitive components of memory device 605 is identified. The target capacitance may be based on the location of the memory device 605 relative to the host device 610 or relative to one or more impedances associated with a bus bar coupling the host device 610 and the memory device 605 .

主機裝置亦可基於與第二記憶體裝置之第二I/O襯墊相關聯之第二目標電容而識別該第二記憶體裝置之第二電容性組件之第二目標組態。第二目標電容可不同於目標電容且可基於第二記憶體裝置相對於主機裝置610或相對於與耦接主機裝置610及第二記憶體裝置之匯流排(例如耦接主機裝置610、記憶體裝置605及第二記憶體裝置之匯流排)相關聯之一或多個阻抗的位置。The host device can also identify a second target configuration of a second capacitive component of the second memory device based on a second target capacitance associated with a second I/O pad of the second memory device. The second target capacitance may be different from the target capacitance and may be based on the second memory device relative to the host device 610 or relative to the bus bar coupling the host device 610 and the second memory device (e.g., coupling the host device 610, memory The location of one or more impedances associated with device 605 and the bus bar of the second memory device).

在620處,主機裝置610可基於識別目標組態而將組態資訊傳輸至記憶體裝置605。主機裝置610亦可基於識別第二目標組態而將指示該第二目標組態之第二組態資訊傳輸至第二記憶體裝置。在一些實例中,組態資訊(例如,或第二組態資訊)可包括記憶體裝置605 (例如,或第二記憶體裝置)之電容性組件之目標組態。另外或替代地,組態資訊可包括用於記憶體裝置605 (例如,或第二記憶體裝置)之電容性組件之目標電容。在一些狀況下,組態資訊可包括用於記憶體裝置605儲存於模式暫存器中之組態資訊之指示或包括組態資訊之一或多個命令。At 620, host device 610 may transmit configuration information to memory device 605 based on identifying the target configuration. The host device 610 may also transmit second configuration information indicating the second target configuration to the second memory device based on identifying the second target configuration. In some examples, the configuration information (eg, or second configuration information) may include a target configuration of a capacitive element of memory device 605 (eg, or second memory device). Additionally or alternatively, the configuration information may include a target capacitance for a capacitive component of memory device 605 (eg, or a second memory device). In some cases, the configuration information may include an indication of the configuration information stored in the mode register by the memory device 605 or one or more commands including the configuration information.

在625處,記憶體裝置605可基於組態資訊組態記憶體裝置605之I/O襯墊之電容。舉例而言,如參看圖3至圖5所描述,記憶體裝置605可包括具有可調整電容之一或多個電容性組件,其中該一或多個電容性組件可與記憶體裝置605之一或多個I/O襯墊耦接。在一些狀況下,記憶體裝置605可藉由組態電容性組件(例如根據目標組態或目標電容)而組態I/O襯墊之電容。舉例而言,與記憶體裝置605相關聯之控制器可根據組態資訊而啟動(閉合)或解除啟動(斷開)電容性組件之一或多個切換組件。在一些實例中,記憶體裝置605可將所接收之組態資訊儲存至記憶體裝置605之一或多個模式暫存器且可基於將組態資訊儲存至一或多個模式暫存器而組態電容性組件。At 625, the memory device 605 can configure the capacitance of the I/O pads of the memory device 605 based on the configuration information. For example, as described with reference to FIGS. or multiple I/O pads. In some cases, the memory device 605 can configure the capacitance of the I/O pads by configuring the capacitive elements (eg, according to a target configuration or target capacitance). For example, a controller associated with the memory device 605 can activate (close) or deactivate (open) the capacitive component or one or more switching components based on the configuration information. In some examples, memory device 605 may store the received configuration information to one or more mode registers of memory device 605 and may be based on storing the configuration information to one or more mode registers Configure capacitive components.

在一些狀況下,記憶體裝置605可基於與記憶體裝置605之一或多個I/O襯墊相關聯之目標電容而識別記憶體裝置605之一或多個電容性組件之目標組態。因而,記憶體裝置可基於經識別組態來組態記憶體裝置605之I/O襯墊之電容。In some cases, memory device 605 may identify a target configuration for one or more capacitive components of memory device 605 based on a target capacitance associated with one or more I/O pads of memory device 605 . Thus, the memory device can configure the capacitance of the I/O pads of the memory device 605 based on the identified configuration.

在630處,在一些狀況下,記憶體裝置605可將已組態I/O襯墊之電容之指示傳輸至主機裝置610。At 630 , under some conditions, memory device 605 may transmit an indication of the capacitance of the configured I/O pads to host device 610 .

在635處,主機裝置610可經由I/O襯墊將傳信傳輸至記憶體裝置605 (例如在傳輸組態資訊之後及在記憶體裝置605已組態I/O襯墊之電容之後)。在一些狀況下,傳信之轉換速率(例如記憶體裝置605處之傳信之轉換速率)可基於組態資訊(例如基於記憶體裝置605之一或多個電容性組件之組態)。舉例而言,如藉由記憶體裝置605基於指示所調整(調諧、組態)之電容性組件之電容可調整(例如減小)自主機裝置610至記憶體裝置605之信號之轉換速率。At 635, host device 610 may transmit signaling to memory device 605 via the I/O pads (eg, after transmitting the configuration information and after memory device 605 has configured the capacitance of the I/O pads). In some cases, the signaled slew rate (eg, the signaled slew rate at memory device 605 ) may be based on configuration information (eg, based on the configuration of one or more capacitive components of memory device 605 ). For example, the slew rate of signals from host device 610 to memory device 605 may be adjusted (eg, reduced) based on the capacitance of a capacitive element adjusted (tuned, configured), as indicated by memory device 605 .

在一些實例中,可藉由一或多個電容性組件之組態而降低轉換速率,且較低轉換速率可降低記憶體裝置605處之反射雜訊。記憶體裝置605處之雜訊減少可藉由增加傳信準確度且藉此減低延時且改良可靠性從而改良裝置效能。In some examples, the slew rate can be reduced by the configuration of one or more capacitive elements, and the lower slew rate can reduce reflection noise at the memory device 605 . Noise reduction at the memory device 605 can improve device performance by increasing signaling accuracy and thereby reducing latency and improving reliability.

7 展示根據如本文中所揭示之實例的支援可組態之記憶體晶粒電容之記憶體裝置705的方塊圖700。記憶體裝置705可為如參考圖3至圖6所描述之記憶體裝置之態樣的實例。記憶體裝置705可包括組態資訊接收組件710、電容組態組件715及信號接收組件720。此等模組中之每一者可直接地或間接地(例如,經由一或多個匯流排)彼此通信。 7 shows a block diagram 700 of a memory device 705 supporting configurable memory die capacitance according to examples as disclosed herein. Memory device 705 may be an example of aspects of a memory device as described with reference to FIGS. 3-6 . The memory device 705 may include a configuration information receiving component 710 , a capacitor configuration component 715 and a signal receiving component 720 . Each of these modules can communicate with each other directly or indirectly (eg, via one or more bus bars).

組態資訊接收組件710可在記憶體裝置處接收與記憶體裝置之I/O襯墊之目標電容相關聯之組態資訊。在一些狀況下,組態資訊指示電容性組件之組態。The configuration information receiving component 710 can receive, at the memory device, configuration information associated with a target capacitance of an I/O pad of the memory device. In some cases, the configuration information indicates the configuration of the capacitive component.

電容組態組件715可基於組態資訊在記憶體裝置處組態I/O襯墊之電容。在一些實例中,組態I/O襯墊之電容包括組態電容性組件。在一些實例中,電容組態組件715可將組態資訊儲存至一或多個模式暫存器。在一些實例中,電容組態組件715可基於將組態資訊儲存至一或多個模式暫存器而組態電容性組件。在一些實例中,電容組態組件715可在組態I/O襯墊之電容之後將已組態I/O襯墊之電容之指示傳輸至主機裝置。在一些狀況下,記憶體裝置包括具有可調整電容且與I/O襯墊耦接之電容性組件。The capacitance configuration component 715 can configure the capacitance of the I/O pads at the memory device based on the configuration information. In some examples, configuring the capacitance of the I/O pad includes configuring a capacitive element. In some examples, the capacitive configuration component 715 can store the configuration information in one or more mode registers. In some examples, capacitive configuration component 715 may configure capacitive components based on storing configuration information to one or more mode registers. In some examples, capacitance configuration component 715 can transmit an indication of the configured capacitance of the I/O pad to the host device after configuring the capacitance of the I/O pad. In some cases, memory devices include capacitive elements having adjustable capacitance and coupled to I/O pads.

信號接收組件720可在組態I/O襯墊之電容之後經由I/O襯墊自主機裝置接收傳信。The signal receiving component 720 can receive signaling from the host device via the I/O pad after configuring the capacitance of the I/O pad.

8 展示根據如本文中所揭示之實例的支援可組態之記憶體晶粒電容之主機裝置805的方塊圖800。主機裝置805可為如參考圖3至圖6所描述之主機裝置之態樣的實例。主機裝置805可包括電容性組態組件810、組態資訊傳輸組件815及信號傳輸組件820。此等模組中之每一者可直接地或間接地(例如,經由一或多個匯流排)彼此通信。 8 shows a block diagram 800 of a host device 805 supporting configurable memory die capacitance according to examples as disclosed herein. Host device 805 may be an example of aspects of a host device as described with reference to FIGS. 3-6 . The host device 805 can include a capacitive configuration component 810 , a configuration information transmission component 815 and a signal transmission component 820 . Each of these modules can communicate with each other directly or indirectly (eg, via one or more bus bars).

電容性組態組件810可基於與記憶體裝置之I/O襯墊相關聯之目標電容而識別該記憶體裝置之電容性組件之目標組態。在一些實例中,電容性組態組件810可基於與第二記憶體裝置之第二I/O襯墊相關聯之第二目標電容而識別第二記憶體裝置之第二電容性組件之第二目標組態,其中該第二目標電容可能不同於目標電容。Capacitive configuration component 810 can identify a target configuration for a capacitive component of a memory device based on a target capacitance associated with an I/O pad of the memory device. In some examples, capacitive configuration element 810 may identify a second capacitive element of the second memory device based on a second target capacitance associated with a second I/O pad of the second memory device. A target configuration, where the second target capacitance may be different from the target capacitance.

組態資訊傳輸組件815可基於識別目標組態而將指示目標組態之組態資訊傳輸至記憶體裝置。在一些實例中,組態資訊傳輸組件815可基於識別第二目標組態而將指示第二目標組態之第二組態資訊傳輸至第二記憶體裝置。The configuration information transfer component 815 can transfer configuration information indicative of the target configuration to the memory device based on identifying the target configuration. In some examples, the configuration information transmitting component 815 can transmit the second configuration information indicative of the second target configuration to the second memory device based on identifying the second target configuration.

信號傳輸組件820可在傳輸組態資訊之後經由I/O襯墊將傳信傳輸至記憶體裝置。在一些狀況下,傳信之轉換速率係基於組態資訊。The signal transmission component 820 can transmit the signal to the memory device through the I/O pad after transmitting the configuration information. In some cases, the signaled slew rate is based on configuration information.

9 展示根據本發明之態樣的說明支援可組態之記憶體晶粒電容之一或多個方法900的流程圖。方法900之操作可藉由如本文所描述之記憶體裝置或其組件來實施。舉例而言,方法900之操作可藉由如參看圖7所描述之記憶體裝置來執行。在一些實例中,記憶體裝置可執行指令集以控制記憶體裝置之功能元件來執行所描述功能。另外或替代地,記憶體裝置可使用特殊用途硬體來執行所描述功能之態樣。 9 shows a flowchart illustrating one or more methods 900 of supporting configurable memory die capacitances in accordance with aspects of the present invention. The operations of method 900 may be implemented by a memory device or components thereof as described herein. For example, the operations of method 900 may be performed by a memory device as described with reference to FIG. 7 . In some examples, a memory device can execute a set of instructions to control functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may employ special purpose hardware to perform aspects of the described functions.

在905處,記憶體裝置可在記憶體裝置處接收與記憶體裝置之I/O襯墊之目標電容相關聯之組態資訊。905之操作可根據本文所描述之方法來執行。在一些實例中,905之操作之態樣可藉由如參看圖7所描述之組態資訊接收組件來執行。At 905, the memory device can receive at the memory device configuration information associated with a target capacitance of an I/O pad of the memory device. The operation of 905 may be performed according to the methods described herein. In some examples, aspects of the operation of 905 may be performed by a configuration information receiving component as described with reference to FIG. 7 .

在910處,記憶體裝置可基於組態資訊在記憶體裝置處組態I/O襯墊之電容。910之操作可根據本文所描述之方法來執行。在一些實例中,910之操作之態樣可藉由如參看圖7所描述之電容組態組件來執行。At 910, the memory device can configure the capacitance of the I/O pad at the memory device based on the configuration information. The operation of 910 may be performed according to methods described herein. In some examples, aspects of the operation of 910 may be performed by capacitively configured components as described with reference to FIG. 7 .

在915處,記憶體裝置可在組態I/O襯墊之電容之後經由I/O襯墊自主機裝置接收傳信。915之操作可根據本文所描述之方法來執行。在一些實例中,915之操作之態樣可藉由如參看圖7所描述之信號接收組件來執行。At 915, the memory device may receive signaling from the host device via the I/O pad after configuring the capacitance of the I/O pad. The operation of 915 may be performed according to methods described herein. In some examples, aspects of the operation of 915 may be performed by signal receiving components as described with reference to FIG. 7 .

在一些實例中,如本文所描述之設備可執行一或多個方法,諸如方法900。該設備可包括用於在記憶體裝置處接收與記憶體裝置之I/O襯墊之目標電容相關聯之組態資訊、基於該組態資訊在記憶體裝置處組態I/O襯墊之電容且在組態I/O襯墊之電容之後經由I/O襯墊自主機裝置接收傳信的特徵、構件或指令(例如儲存可由處理器執行之指令之非暫時性電腦可讀媒體)。在方法900及本文中所描述之設備之一些實例中,記憶體裝置可包括具有可調整電容且與I/O襯墊耦接的電容性組件,組態I/O襯墊之電容可包括組態該電容性組件,且組態資訊可指示該電容性組件之組態。In some examples, an apparatus as described herein may perform one or more methods, such as method 900 . The apparatus may include means for receiving, at the memory device, configuration information associated with a target capacitance of an I/O pad of the memory device, configuring the I/O pad at the memory device based on the configuration information Capacitance and receive a signaled feature, component or instruction (eg, a non-transitory computer-readable medium storing instructions executable by a processor) from a host device via the I/O pad after configuring the capacitance of the I/O pad. In some examples of method 900 and apparatus described herein, a memory device may include a capacitive element having an adjustable capacitance coupled to an I/O pad, and configuring the capacitance of the I/O pad may include setting The capacitive device can be configured, and the configuration information can indicate the configuration of the capacitive device.

方法900及本文中所描述之設備之一些實例可進一步包括用於將組態資訊儲存至一或多個模式暫存器且基於將組態資訊儲存至一或多個模式暫存器而組態電容性組件的操作、特徵、構件或指令。方法900及本文中所描述之設備之一些實例可進一步包括用於在組態I/O襯墊之電容之後將可已組態I/O襯墊之電容之指示傳輸至主機裝置的操作、特徵、構件或指令。Method 900 and some examples of the apparatus described herein may further include storing configuration information to one or more mode registers and configuring based on storing configuration information to one or more mode registers An operation, feature, component or instruction of a capacitive component. Some examples of the method 900 and apparatus described herein may further include operations for transmitting an indication of the configurable capacitance of the I/O pad to the host device after the configuration of the capacitance of the I/O pad, features , component or directive.

10 展示根據本發明之態樣的說明支援可組態之記憶體晶粒電容之一或多個方法1000的流程圖。方法1000之操作可藉由如本文所描述之記憶體裝置或其組件來實施。舉例而言,方法1000之操作可藉由如參看圖7所描述之記憶體裝置來執行。在一些實例中,記憶體裝置可執行指令集以控制記憶體裝置之功能元件來執行所描述功能。另外或替代地,記憶體裝置可使用特殊用途硬體來執行所描述功能之態樣。 FIG. 10 shows a flowchart illustrating one or more methods 1000 of supporting configurable memory die capacitance in accordance with aspects of the present invention. The operations of method 1000 may be implemented by a memory device or components thereof as described herein. For example, the operations of method 1000 may be performed by a memory device as described with reference to FIG. 7 . In some examples, a memory device can execute a set of instructions to control functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may employ special purpose hardware to perform aspects of the described functions.

在1005處,記憶體裝置可在記憶體裝置處接收與記憶體裝置之I/O襯墊之目標電容相關聯之組態資訊。1005之操作可根據本文所描述之方法來執行。在一些實例中,1005之操作之態樣可藉由如參看圖7所描述之組態資訊接收組件來執行。At 1005, the memory device can receive, at the memory device, configuration information associated with a target capacitance of an I/O pad of the memory device. The operation of 1005 may be performed according to the methods described herein. In some examples, aspects of the operation of 1005 may be performed by a configuration information receiving component as described with reference to FIG. 7 .

在1010處,記憶體裝置可基於組態資訊在記憶體裝置處組態I/O襯墊之電容。1010之操作可根據本文所描述之方法來執行。在一些實例中,1010之操作之態樣可藉由如參看圖7所描述之電容組態組件來執行。At 1010, the memory device may configure the capacitance of the I/O pad at the memory device based on the configuration information. The operations of 1010 may be performed according to methods described herein. In some examples, aspects of the operation of 1010 may be performed by capacitively configured components as described with reference to FIG. 7 .

在1015處,記憶體裝置可將組態資訊儲存至一或多個模式暫存器。1015之操作可根據本文所描述之方法來執行。在一些實例中,1015之操作之態樣可藉由如參看圖7所描述之電容組態組件來執行。At 1015, the memory device may store configuration information to one or more mode registers. The operation of 1015 may be performed according to the methods described herein. In some examples, aspects of the operation of 1015 may be performed by capacitively configured components as described with reference to FIG. 7 .

在1020處,記憶體裝置可基於將組態資訊儲存至一或多個模式暫存器而組態電容性組件。1020之操作可根據本文所描述之方法來執行。在一些實例中,1020之操作之態樣可藉由如參看圖7所描述之電容組態組件來執行。At 1020, the memory device can configure the capacitive device based on storing configuration information to one or more mode registers. The operation of 1020 may be performed according to the methods described herein. In some examples, aspects of the operation of 1020 may be performed by capacitively configured components as described with reference to FIG. 7 .

在1025處,記憶體裝置可在組態I/O襯墊之電容之後經由I/O襯墊自主機裝置接收傳信。1025之操作可根據本文所描述之方法來執行。在一些實例中,1025之操作之態樣可藉由如參看圖7所描述之信號接收組件來執行。At 1025, the memory device may receive signaling from the host device via the I/O pad after configuring the capacitance of the I/O pad. The operation of 1025 may be performed according to the methods described herein. In some examples, aspects of the operation of 1025 may be performed by a signal receiving component as described with reference to FIG. 7 .

11 展示根據本發明之態樣的說明支援可組態之記憶體晶粒電容之一或多個方法1100的流程圖。方法1100之操作可藉由如本文所描述之主機裝置或其組件來實施。舉例而言,方法1100之操作可藉由如參看圖8所描述之主機裝置來執行。在一些實例中,主機裝置可執行指令集以控制主機裝置之功能元件來執行所描述功能。另外或替代地,主機裝置可使用特殊用途硬體來執行所描述功能之態樣。 11 shows a flowchart illustrating one or more methods 1100 of supporting configurable memory die capacitance in accordance with aspects of the present invention. The operations of method 1100 may be implemented by a host device or components thereof as described herein. For example, the operations of method 1100 may be performed by a host device as described with reference to FIG. 8 . In some examples, a host device can execute a set of instructions to control functional elements of the host device to perform the described functions. Additionally or alternatively, the host device may use special purpose hardware to perform aspects of the described functions.

在1105處,主機裝置可基於與記憶體裝置之I/O襯墊相關聯之目標電容而識別記憶體裝置之電容性組件之目標組態。1105之操作可根據本文所描述之方法來執行。在一些實例中,1105之操作之態樣可藉由如參看圖8所描述之電容性組件組態來執行。At 1105, the host device can identify a target configuration of capacitive components of the memory device based on the target capacitance associated with the I/O pads of the memory device. The operation of 1105 may be performed according to the methods described herein. In some examples, the aspect of operation of 1105 may be performed by a capacitive component configuration as described with reference to FIG. 8 .

在1110處,主機裝置可基於識別目標組態而將指示該目標組態之組態資訊傳輸至記憶體裝置。1110之操作可根據本文所描述之方法來執行。在一些實例中,1110之操作之態樣可藉由如參看圖8所描述之組態資訊傳輸組件來執行。At 1110, the host device may transmit configuration information indicative of the target configuration to the memory device based on identifying the target configuration. The operations of 1110 may be performed according to methods described herein. In some examples, aspects of the operation of 1110 may be performed by configuring information transfer components as described with reference to FIG. 8 .

在1115處,主機裝置可在傳輸組態資訊之後經由I/O襯墊將傳信傳輸至記憶體裝置。1115之操作可根據本文所描述之方法來執行。在一些實例中,1115之操作之態樣可藉由如參考圖8所描述之信號傳輸組件來執行。At 1115, the host device may transmit signaling to the memory device via the I/O pad after transmitting the configuration information. The operation of 1115 may be performed according to methods described herein. In some examples, aspects of the operation of 1115 may be performed by signaling components as described with reference to FIG. 8 .

在一些實例中,如本文所描述之設備可執行一或多個方法,諸如方法1100。該設備可包括用於基於與記憶體裝置之I/O襯墊相關聯之目標電容識別記憶體裝置之電容性組件之目標組態、基於識別目標組態而將指示該目標組態之組態資訊傳輸至記憶體裝置且在傳輸組態資訊之後經由I/O襯墊將傳信傳輸至記憶體裝置的特徵、構件或指令(例如儲存可由處理器執行之指令的非暫時性電腦可讀媒體)。在本文中所描述之方法1100及設備之一些實例中,傳信之轉換速率可基於組態資訊。In some examples, an apparatus as described herein may perform one or more methods, such as method 1100 . The apparatus may include for identifying a target configuration of a capacitive component of a memory device based on a target capacitance associated with an I/O pad of the memory device, a configuration that will indicate the target configuration based on identifying the target configuration A feature, component, or instruction (such as a non-transitory computer-readable medium that stores instructions executable by a processor) that transmits information to a memory device and, after transmitting configuration information, signals to the memory device via an I/O pad ). In some examples of the method 1100 and apparatus described herein, the signaled slew rate can be based on configuration information.

應注意,本文所描述之方法係可能的實施,且操作及步驟可經重新配置或以其他方式修改,且其他實施係可能的。另外,可組合來自該等方法中之兩者或多於兩者的部分。It should be noted that the methods described herein are possible implementations, and that operations and steps may be reconfigured or otherwise modified, and that other implementations are possible. Additionally, portions from two or more of these methods may be combined.

描述一種設備。該設備可包括一記憶體晶粒,該記憶體晶粒包括:一I/O襯墊;包括於該記憶體晶粒中之一輸入緩衝器,該輸入緩衝器與該I/O襯墊耦接;及具有一可調整電容且包括於該記憶體晶粒中之一電容性組件,該電容性組件與該I/O襯墊耦接。Describe a device. The device may include a memory die including: an I/O pad; an input buffer included in the memory die, the input buffer coupled to the I/O pad and having an adjustable capacitance and including a capacitive element in the memory die, the capacitive element is coupled with the I/O pad.

在一些實例中,該電容性組件包括一電容器及可操作以將該電容器與該I/O襯墊選擇性地耦接之一切換組件。在一些實例中,該電容性組件包括一電容器集合及一切換組件集合,該集合之每一各別切換組件可操作以將該集合之一各別電容器與該I/O襯墊選擇性地耦接。該設備之一些實例可包括:一模式暫存器,其可操作以儲存一或多個邏輯值;及一控制器,其可操作以致使該設備基於該一或多個邏輯值組態該電容性組件,以可具有由該電容性組件支援的一電容集合中之一者。In some examples, the capacitive component includes a capacitor and a switching component operable to selectively couple the capacitor with the I/O pad. In some examples, the capacitive element includes a set of capacitors and a set of switching elements, each respective switching element of the set operable to selectively couple a respective capacitor of the set to the I/O pad catch. Some examples of the apparatus may include: a mode register operable to store one or more logical values; and a controller operable to cause the apparatus to configure the capacitor based on the one or more logical values A capacitive element may have one of a set of capacitances supported by the capacitive element.

在一些實例中,該電容性組件包括一切換組件集合,且該一或多個邏輯值指示用於使該控制器閉合的該切換組件集合之一數量。在一些實例中,該電容性組件包括一切換組件集合;且該一或多個邏輯值包括一點陣圖,該點陣圖之每一位元指示該控制器是可開啟抑或閉合該切換組件集合中之一各別切換組件。In some examples, the capacitive component includes a set of switching components, and the one or more logical values indicate a quantity of the set of switching components for closing the controller. In some examples, the capacitive element includes a set of switching elements; and the one or more logical values include a bitmap, each bit of the bitmap indicates whether the controller can turn on or turn off the set of switching elements One of them switches components individually.

該設備之一些實例可包括一控制器,該控制器與該電容性組件耦接且可操作以基於組態該電容性組件之該可調整電容而組態經由該I/O襯墊所接收的一信號之一轉換速率。Some examples of the apparatus may include a controller coupled to the capacitive component and operable to configure the data received via the I/O pad based on configuring the adjustable capacitance of the capacitive component. One slew rate of one signal.

該設備之一些實例可包括一第二記憶體晶粒,該第二記憶體包括一第二I/O襯墊及一第二電容性組件,該第二電容性組件具有一第二可調整電容且與該第二I/O襯墊耦接。Some examples of the device may include a second memory die including a second I/O pad and a second capacitive element having a second adjustable capacitance And coupled with the second I/O pad.

描述一種系統。該系統可包括一記憶體裝置及與該記憶體裝置耦接之一主機裝置。該記憶體裝置可包括一記憶體晶粒,該記憶體晶粒包括一I/O襯墊及具有一可調整電容且與該I/O襯墊耦接之一電容性組件。該主機裝置可操作以將組態資訊提供至該記憶體裝置,且該記憶體裝置可操作以基於該組態資訊組態該電容性組件之該可調整電容。Describe a system. The system may include a memory device and a host device coupled to the memory device. The memory device may include a memory die including an I/O pad and a capacitive element having an adjustable capacitance coupled to the I/O pad. The host device is operable to provide configuration information to the memory device, and the memory device is operable to configure the adjustable capacitance of the capacitive element based on the configuration information.

在一些實例中,該記憶體裝置之該電容性組件包括一或多個電容器及一或多個切換組件,其中該一或多個切換組件中之每一者可操作以將該一或多個電容器之一各別電容器與該I/O襯墊選擇性地耦接。在一些實例中,該主機裝置可操作以基於向該記憶體裝置發佈指示該組態資訊之一命令來提供該組態資訊。在一些實例中,自該主機裝置傳輸至該記憶體裝置之一信號之一轉換速率係基於該電容性組件之該可調整電容。In some examples, the capacitive element of the memory device includes one or more capacitors and one or more switching elements, wherein each of the one or more switching elements is operable to switch the one or more A respective one of the capacitors is selectively coupled to the I/O pad. In some examples, the host device is operable to provide the configuration information based on issuing a command to the memory device indicating the configuration information. In some examples, a slew rate of a signal transmitted from the host device to the memory device is based on the adjustable capacitance of the capacitive element.

該記憶體裝置之一些實例可包括一模式暫存器,其中該記憶體裝置可操作以基於儲存於該模式暫存器中之一或多個邏輯值來組態該電容性組件之該可調整電容。在一些實例中,該主機裝置可操作以基於將該一或多個邏輯值之一指示傳輸至該記憶體裝置而提供該組態資訊,且該記憶體裝置可操作以基於該指示將該一或多個邏輯值儲存於該模式暫存器中。Some examples of the memory device may include a mode register, wherein the memory device is operable to configure the adjustable of the capacitive element based on one or more logic values stored in the mode register capacitance. In some examples, the host device is operable to provide the configuration information based on transmitting an indication of the one or more logical values to the memory device, and the memory device is operable to transmit an indication of the one or more logical values to the memory device based on the indication. or multiple logical values are stored in the mode register.

該記憶體裝置之一些實例可包括與該I/O襯墊耦接之一輸入緩衝器。該記憶體裝置之一些實例可包括一或多個額外記憶體晶粒,其各自包括一各別I/O襯墊。在一些實例中,該記憶體裝置可操作以將該電容性組件與該一或多個額外記憶體晶粒中之至少一者之該各別I/O襯墊耦接。該系統之一些實例可包括一或多個額外記憶體裝置,其各自包括一各別記憶體晶粒,該各別記憶體晶粒包括一各別I/O襯墊及一各別電容性組件。在一些實例中,該各別電容性組件可具有一各別可調整電容且可與該各別I/O襯墊耦接。在一些實例中,該主機裝置之單一I/O襯墊與包括該記憶體裝置之該I/O襯墊及該一或多個額外記憶體裝置中之每一者之該各別I/O襯墊的複數個I/O襯墊耦接。Some examples of the memory device may include an input buffer coupled to the I/O pad. Some examples of the memory device may include one or more additional memory die, each including a respective I/O pad. In some examples, the memory device is operable to couple the capacitive element to the respective I/O pad of at least one of the one or more additional memory dies. Some examples of the system may include one or more additional memory devices each including a respective memory die including a respective I/O pad and a respective capacitive element . In some examples, the respective capacitive element can have a respective adjustable capacitance and can be coupled with the respective I/O pad. In some examples, the single I/O pad of the host device and the separate I/O pads of each of the one or more additional memory devices comprising the I/O pad of the memory device A plurality of I/O pads of the pad are coupled.

在該系統之一些實例中,該記憶體裝置之該電容性組件可經組態為具有一第一電容,且包括於該一或多個額外記憶體裝置之一第二記憶體裝置中之一第二電容性組件可經組態為具有一第二電容。在一些實例中,該記憶體裝置可比該第二記憶體裝置更接近該主機裝置且該第一電容可大於該第二電容。在該系統之一些實例中,該系統可進一步包括用於與該主機裝置、該記憶體裝置及該第二記憶體裝置耦接之一匯流排之一終端阻抗,其中該記憶體裝置可比該第二記憶體裝置更遠離該終端阻抗,且其中該第一電容可大於該第二電容。In some examples of the system, the capacitive component of the memory device can be configured to have a first capacitance and be included in one of the second memory devices of the one or more additional memory devices The second capacitive component can be configured to have a second capacitance. In some examples, the memory device may be closer to the host device than the second memory device and the first capacitance may be greater than the second capacitance. In some examples of the system, the system can further include a terminating impedance for a bus coupled with the host device, the memory device, and the second memory device, wherein the memory device can be compared to the second memory device The second memory device is further away from the terminal impedance, and wherein the first capacitance can be larger than the second capacitance.

可使用多種不同技術及技藝中之任一者來表示本文中所描述之資訊及信號。舉例而言,可由電壓、電流、電磁波、磁場或磁粒子、光場或光粒子或其任何組合表示遍及以上描述可能參考的資料、指令、命令、資訊、信號、位元、符號及碼片。一些圖式可將信號說明為單一信號;然而,一般熟習此項技術者應理解,該信號可表示信號之匯流排,其中該匯流排可具有多種位元寬度。The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some of the figures may illustrate the signal as a single signal; however, one of ordinary skill in the art will understand that the signal may represent a bus of signals, where the bus may be of various bit widths.

術語「電子通信」、「導電接觸」、「連接」及「耦接」可指支援在組件之間信號流動的組件之間的關係。若在組件之間存在可在任何時間支援組件之間信號流動的任何導電路徑,則組件被認為彼此電子通信(或彼此導電接觸或彼此連接或彼此耦接)。在任何給定時間,彼此電子通信(或彼此導電接觸或彼此連接或彼此耦接)的組件之間的導電路徑基於包括所連接組件之裝置之操作而可為開路或閉路。所連接組件之間的導電路徑可為組件之間的直接導電路徑,或所連接組件之間的導電路徑可為可包括中間組件,諸如開關、電晶體或其他組件的間接導電路徑。在一些狀況下,可例如使用諸如開關或電晶體之一或多個中間組件將所連接組件之間的信號流動中斷一段時間。The terms "electronically communicate," "conductive contact," "connect" and "couple" may refer to a relationship between components that enables the flow of signals between components. Components are considered to be in electronic communication with each other (or to be in conductive contact or connected to or coupled to each other) if there is any conductive path between the components that can at any time support the flow of signals between the components. At any given time, a conductive path between components that are in electronic communication with each other (or are in conductive contact with each other or connected or coupled to each other) can be an open circuit or a closed circuit based on the operation of the device that includes the connected components. The conductive path between connected components may be a direct conductive path between components, or the conductive path between connected components may be an indirect conductive path that may include intermediate components, such as switches, transistors, or other components. In some cases, signal flow between connected components may be interrupted for a period of time, eg, using one or more intermediate components such as switches or transistors.

術語「耦接」係指自其中信號目前不能夠經由導電路徑在組件之間被傳達的組件之間的開路關係至其中信號能夠經由導電路徑在組件之間被傳達的組件之間的閉路關係之移動條件。當諸如控制器之組件將其他組件耦接在一起時,該組件起始一改變,該改變會允許信號經由先前並不准許信號流動的導電路徑而在該等其他組件之間流動。The term "coupled" refers to the transition from an open circuit relationship between components in which signals are not currently capable of being communicated between components via conductive paths to a closed circuit relationship between components in which signals can be communicated between components via conductive paths. Move condition. When a component such as a controller couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that previously did not permit signal flow.

術語「隔離」係指組件之間的關係,其中信號目前不能夠在該等組件之間流動。若在組件之間存在斷路,則該等組件彼此隔離。舉例而言,由定位於組件之間的開關分離的兩個組件在開關斷開時彼此隔離。當控制器隔離兩個組件時,控制器影響一改變,該改變會防止信號使用先前准許信號流動的導電路徑在組件之間流動。The term "isolation" refers to a relationship between components in which signals are not currently able to flow between those components. If there is an open circuit between components, the components are isolated from each other. For example, two components separated by a switch positioned between the components are isolated from each other when the switch is open. When the controller isolates two components, the controller effects a change that prevents signals from flowing between the components using conductive paths that previously permitted signal flow.

本文所使用之術語「層」係指幾何結構之一層或薄片。每一層可具有三個維度(例如高度、寬度及深度)且可覆蓋表面之至少一部分。舉例而言,層可為三維結構,其中兩個維度大於第三維度,例如薄膜。層可包括不同元件、組件及/或材料。在一些狀況下,一個層可由兩個或多於兩個子層構成。在一些隨附圖中,出於說明之目的描繪三維層之兩個維度。As used herein, the term "layer" refers to a layer or sheet of a geometric structure. Each layer can have three dimensions (eg, height, width, and depth) and can cover at least a portion of the surface. For example, a layer can be a three-dimensional structure, where two dimensions are greater than the third, such as a film. Layers may comprise different elements, components and/or materials. In some cases, a layer may consist of two or more sub-layers. In some of the accompanying figures, two dimensions of a three-dimensional layer are depicted for purposes of illustration.

如本文所使用,術語「電極」可指電導體,且在一些狀況下可用作至記憶體胞元或記憶體陣列之其他組件的電接點。電極可包括在記憶體陣列之元件或組件之間提供導電路徑的跡線、電線、導電線、導電層,或其類似者。As used herein, the term "electrode" may refer to an electrical conductor, and in some cases may serve as an electrical contact to a memory cell or other component of a memory array. The electrodes may include traces, wires, conductive lines, conductive layers, or the like that provide conductive paths between elements or components of the memory array.

可在諸如矽、鍺、矽-鍺合金、砷化鎵、氮化鎵等之半導體基板上形成本文所論述的包括記憶體陣列之裝置。在一些狀況下,基板為半導體晶圓。在其他狀況下,基板可為絕緣層上矽(SOI)基板,諸如玻璃上矽(SOG)或藍寶石上矽(SOP),或另一基板上之半導體材料的磊晶層。可經由使用包括但不限於磷、硼或砷之各種化學物質摻雜而控制基板或基板之子區的導電性。可藉由離子植入或藉由任何其他摻雜方式在基板之初始形成或生長期間執行摻雜。Devices including memory arrays discussed herein can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled through doping with various chemistries including but not limited to phosphorous, boron or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other means of doping.

本文中所論述之切換組件或電晶體可表示場效電晶體(FET)且包含包括源極、汲極及閘極之三個端子裝置。該等端子可經由導電材料(例如金屬)連接至其他電子元件。源極及汲極可為導電的,且可包含大程度摻雜(例如,變質)之半導體區。源極與汲極可由輕微摻雜之半導體區或通道分離。若通道為n型(亦即,大多數載波為信號),則FET可被稱為n型FET。若通道為p型(亦即,大多數載波為電洞),則FET可被稱為p型FET。通道可由絕緣閘氧化物覆蓋。可藉由將電壓施加至閘極來控制通道導電性。舉例而言,將正電壓或負電壓分別施加至n型FET或p型FET可導致通道變得導電。當將大於或等於電晶體之臨限電壓的電壓施加至電晶體閘極時,電晶體可「接通」或「啟動」。當將小於電晶體之臨限電壓的電壓施加至電晶體閘極時,電晶體可「斷開」或「解除啟動」。A switching element or transistor as discussed herein may represent a field effect transistor (FET) and includes a three terminal device including a source, a drain and a gate. The terminals can be connected to other electronic components via conductive materials such as metals. The source and drain can be conductive and can include heavily doped (eg, altered) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (ie, most of the carrier is a signal), the FET may be referred to as an n-type FET. If the channel is p-type (ie, most of the carrier is a hole), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. A transistor can be "turned on" or "activated" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the gate of the transistor. A transistor can be "turned off" or "deactivated" when a voltage less than the threshold voltage of the transistor is applied to the gate of the transistor.

本文中結合附圖闡述之描述描述實例組態,且並不表示可實施或在申請專利範圍之範疇內的所有實例。本文中所使用之術語「例示性」意謂「充當實例、例子或說明」,且並不意謂「較佳」或「優於其他實例」。詳細描述包括特定細節以提供對所描述技藝之理解。然而,可在無此等特定細節的情況下實踐此等技藝。在一些情況下,以方塊圖形式展示熟知之結構及裝置以便避免混淆所描述實例之概念。The description set forth herein in conjunction with the drawings describes example configurations and does not represent all examples that may be implemented or that are within the scope of the claimed claims. As used herein, the term "exemplary" means "serving as an example, instance, or illustration," and does not mean "preferred" or "over other examples." The detailed description includes specific details to provide an understanding of the described technology. However, such techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

在附圖中,類似組件或特徵可具有相同參考標記。此外,可藉由在參考標記之後加上破折號及在類似組件之間進行區分之第二標記來區分同一類型之各種組件。若在說明書中僅使用第一參考標記,則描述適用於具有相同第一參考標記而與第二參考標記無關的類似組件中之任一者。In the drawings, similar components or features may have the same reference label. Further, various components of the same type can be distinguished by following the reference label by a dash and a second label that distinguishes among similar components. If only a first reference label is used in the specification, the description applies to any of similar components having the same first reference label independently of the second reference label.

結合本文中本發明所描述的各種說明性區塊及模組可使用通用處理器、DSP、ASIC、FPGA或其他可程式化邏輯裝置、離散閘或電晶體邏輯、離散硬體組件或其經設計以執行本文所描述之功能的任何組合來實施或執行。通用處理器可為微處理器,但在替代例中,處理器可為任何處理器、控制器、微控制器或狀態機。處理器亦可實施為計算裝置之組合(例如,DSP與微處理器之組合、多個微處理器、結合DSP核心之一或多個微處理器,或任何其他此組態)。The various illustrative blocks and modules described in connection with the invention herein may use a general purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or designed Implemented or performed in any combination that performs the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (eg, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

本文中所描述之功能可以硬體、由處理器執行之軟體、韌體或其任何組合實施。若以由處理器執行之軟體實施,則可將功能作為一或多個指令或程式碼儲存於電腦可讀媒體上或經由電腦可讀媒體傳輸。其它實例及實施在本發明及隨附申請專利範圍之範疇內。舉例而言,歸因於軟體之性質,所描述之功能可使用由處理器、硬體、韌體、硬連線或此等中之任一者的組合執行之軟體來實施。實施功能之特徵亦可實體地位於各種位置處,包括經分配以使得功能之部分在不同實體位置處實施。又,如本文中所使用(包括在申請專利範圍中),「或」在用於項目清單(例如,以諸如「中之至少一者」或「中之一或多者」之片語作為開頭之項目清單)中時指示包括性清單,使得(例如)A、B或C中之至少一者之清單意謂A或B或C或AB或AC或BC或ABC(亦即,A及B及C)。此外,如本文中所使用,片語「基於」不應被認作對封閉條件集合之參考。舉例而言,在不脫離本發明之範疇的情況下,被描述為「基於條件A」之例示性步驟可基於條件A及條件B兩者。換言之,如本文中所使用,應以與片語「至少部分地基於」相同之方式來解釋片語「基於」。The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, functions described can be implemented using software executed by a processor, hardware, firmware, hardwiring or combinations of any of these. Features implementing functions may also be physically located at various locations, including being distributed such that portions of functions are performed at different physical locations. Also, as used herein (including in claims), "or" is used in lists of items (for example, beginning with phrases such as "at least one of" or "one or more of" list of items) indicates an inclusive list such that, for example, a list of at least one of A, B or C means A or B or C or AB or AC or BC or ABC (that is, A and B and C). Furthermore, as used herein, the phrase "based on" should not be taken as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the invention. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

電腦可讀媒體包括電腦儲存媒體及通信媒體兩者,通信媒體包括促進電腦程式自一處傳送至另一處之任何媒體。非暫時性儲存媒體可為可由通用或專用電腦存取之任何可用媒體。作為實例而非限制,非暫時性電腦可讀媒體可包含RAM、ROM、電可抹除可程式化唯讀記憶體(EEPROM)、緊密光碟(CD) ROM或其他光碟儲存器、磁碟儲存器或其他磁性儲存裝置,或可用以攜載或儲存呈指令或資料結構形式之所要程式碼構件且可由一般用途或特殊用途電腦或者一般用途或特殊用途處理器存取之任何其他非暫時性媒體。又,任何連接被適當地稱為電腦可讀媒體。舉例而言,若使用同軸纜線、光纖纜線、雙絞線、數位用戶線(DSL)或諸如紅外、無線電及微波之無線技術自網站、伺服器或其他遠端源傳輸軟體,則同軸纜線、光纖纜線、雙絞線、數位用戶線(DSL)或諸如紅外、無線電及微波之無線技術包括於媒體之定義中。如本文所使用,磁碟及光碟包括CD、雷射光碟、光學光碟、數位多功能光碟(digital versatile disc,DVD)、軟性磁碟及Blu-ray光碟,其中磁碟通常以磁性方式再現資料,而光碟藉由雷射以光學方式再現資料。以上各者之組合亦包括於電腦可讀媒體之範疇內。Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a general purpose or special purpose computer. By way of example and not limitation, non-transitory computer readable media may include RAM, ROM, Electrically Erasable Programmable Read Only Memory (EEPROM), Compact Disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage device, or any other non-transitory medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer or general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable Wire, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. Disk and disc, as used herein, includes CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, Optical discs reproduce data optically by means of lasers. Combinations of the above are also included within the scope of computer-readable media.

本文中之描述經提供以使熟習此項技術者能夠進行或使用本發明。對本發明之各種修改對於熟習此項技術者而言將為顯而易見的,且可在不脫離本發明之範疇的情況下將本文中定義之一般原理應用於其他變化。因此,本發明並不限於本文中所描述之實例及設計,而是應符合與本文中所揭示之原理及新穎特徵相一致的最廣範疇。The description herein is provided to enable any person skilled in the art to make or use the invention. Various modifications to this invention will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other changes without departing from the scope of the invention. Thus, the invention is not to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

100:系統 105:外部記憶體控制器 110:記憶體裝置 115:通道 120:處理器 125:基本輸入/輸出系統(BIOS)組件 130:周邊組件 135:輸入/輸出(I/O)控制器 140:匯流排 145:輸入裝置/輸入 150:輸出裝置/輸出 155:裝置記憶體控制器 160-a:記憶體晶粒 160-b:記憶體晶粒 160-N :記憶體晶粒 165-a:本端記憶體控制器 165-b:本端記憶體控制器 165-N :本端記憶體控制器 170-a:記憶體陣列 170-b:記憶體陣列 170-N :記憶體陣列 186:命令/位址(CA)通道 188:時脈信號(CK)通道 190:資料(DQ)通道 192:其他通道 200:記憶體晶粒 205:記憶體胞元 210:字線 215:數位線 220:列解碼器 225:行解碼器 230:電容器 235:切換組件 240:電壓源 245:感測組件 250:參考信號 255:輸入/輸出 260:本端記憶體控制器 300:電路 305:輸入/輸出(I/O)襯墊 310:輸入緩衝器 315:電容性組件 320-a:電容器 320-b:電容器 320-c:電容器 325-a:切換組件 325-b:切換組件 325-c:切換組件 330:導電路徑 400:匯流排拓樸 405-a:記憶體裝置 405-b:記憶體裝置 405-c:記憶體裝置 405-d:記憶體裝置 405-e:記憶體裝置 410-a:主機裝置 415-a:共同中繼線 420-a:跡線 420-b:跡線 420-c:跡線 420-d:跡線 420-e:跡線 425-a:分支線 425-b:分支線 425-c:分支線 425-d:分支線 425-e:分支線 430:終端電阻器(RTT) 500:記憶體裝置組態 505:記憶體裝置 510-a:記憶體晶粒 510-b:記憶體晶粒 510-c:記憶體晶粒 515:導電路徑 520:接腳 600:程序流程 605:記憶體裝置 610:主機裝置 615:操作 620:操作 625:操作 630:操作 635:操作 700:方塊圖 705:記憶體裝置 710:組態資訊接收組件 715:電容組態組件 720:信號接收組件 800:方塊圖 805:主機裝置 810:電容性組態組件 815:組態資訊傳輸組件 820:信號傳輸組件 900:方法 905:操作 910:操作 915:操作 1000:方法 1005:操作 1010:操作 1015:操作 1020:操作 1025:操作 1100:方法 1105:操作 1110:操作 1115:操作 DL_1:數位線 DL_2:數位線 DL_3:數位線 DL_N:數位線 Vpl:胞元板參考電壓 WL_1:字線 WL_2:字線 WL_M:字線100: System 105: External Memory Controller 110: Memory Device 115: Channel 120: Processor 125: Basic Input/Output System (BIOS) Components 130: Peripheral Components 135: Input/Output (I/O) Controller 140 : bus bar 145: input device/input 150: output device/output 155: device memory controller 160-a: memory die 160-b: memory die 160- N : memory die 165-a: Local memory controller 165-b: local memory controller 165- N : local memory controller 170-a: memory array 170-b: memory array 170- N : memory array 186: command /Address (CA) channel 188: clock signal (CK) channel 190: data (DQ) channel 192: other channels 200: memory grain 205: memory cell 210: word line 215: digital line 220: row Decoder 225: row decoder 230: capacitor 235: switching component 240: voltage source 245: sensing component 250: reference signal 255: input/output 260: local memory controller 300: circuit 305: input/output (I /0) pad 310: input buffer 315: capacitive component 320-a: capacitor 320-b: capacitor 320-c: capacitor 325-a: switching component 325-b: switching component 325-c: switching component 330: Conductive path 400: busbar topology 405-a: memory device 405-b: memory device 405-c: memory device 405-d: memory device 405-e: memory device 410-a: host device 415 -a: common trunk 420-a:trace 420-b:trace 420-c:trace 420-d:trace 420-e:trace 425-a:branch line 425-b:branch line 425-c : branch line 425-d: branch line 425-e: branch line 430: terminal resistor (RTT) 500: memory device configuration 505: memory device 510-a: memory crystal grain 510-b: memory crystal grain Grain 510-c: memory die 515: conductive path 520: pin 600: program flow 605: memory device 610: host device 615: operation 620: operation 625: operation 630: operation 635: operation 700: block diagram 705 : memory device 710: configuration information receiving component 715: capacitor configuration component 720: signal receiving component 800: block diagram 805: host device 810: capacitive configuration component 815: configuration information transmission component 820: signal transmission component 900 :method 905:op 910:op 915:op 1000:method 1005:op 1010:op 1015:op 1020:op 1025:op 1100:method 1105:op 1110:op 1115:op DL _1: Digit line DL_2: Digit line DL_3: Digit line DL_N: Digit line Vpl: Cell plate reference voltage WL_1: Word line WL_2: Word line WL_M: Word line

圖1說明根據如本文中所揭示之實例的支援可組態之記憶體晶粒電容之系統的實例。1 illustrates an example of a system supporting configurable memory die capacitance according to examples as disclosed herein.

圖2說明根據如本文中所揭示之實例的支援可組態之記憶體晶粒電容之記憶體晶粒的實例。2 illustrates an example of a memory die supporting configurable memory die capacitance according to examples as disclosed herein.

圖3說明根據如本文中所揭示之實例的支援可組態之記憶體晶粒電容之電路的實例。3 illustrates an example of a circuit supporting configurable memory die capacitance according to examples as disclosed herein.

圖4說明根據如本文中所揭示之實例的支援可組態之記憶體晶粒電容之匯流排拓樸的實例。4 illustrates an example of a bus topology to support configurable memory die capacitance according to examples as disclosed herein.

圖5說明根據如本文中所揭示之實例的支援可組態之記憶體晶粒電容之記憶體裝置組態的實例。5 illustrates an example of a memory device configuration supporting configurable memory die capacitance according to examples as disclosed herein.

圖6說明根據如本文中所揭示之實例的支援可組態之記憶體晶粒電容之程序流程的實例。6 illustrates an example of a program flow to support configurable memory die capacitance according to examples as disclosed herein.

圖7展示根據本發明之態樣的支援可組態之記憶體晶粒電容之記憶體裝置的方塊圖。7 shows a block diagram of a memory device supporting configurable memory die capacitance according to aspects of the present invention.

圖8展示根據本發明之態樣的支援可組態之記憶體晶粒電容之主機裝置的方塊圖。8 shows a block diagram of a host device supporting configurable memory die capacitors according to aspects of the invention.

圖9至圖11展示說明根據如本文中所揭示之實例的支援可組態之記憶體晶粒電容之一或多個方法的流程圖。9-11 show flowcharts illustrating one or more methods of supporting configurable memory die capacitance according to examples as disclosed herein.

300:電路300: circuit

305:輸入/輸出(I/O)襯墊305: Input/Output (I/O) Pad

310:輸入緩衝器310: input buffer

315:電容性組件315: capacitive components

320-a:電容器320-a: Capacitor

320-b:電容器320-b: Capacitor

320-c:電容器320-c: Capacitor

325-a:切換組件325-a: Toggle component

325-b:切換組件325-b: Toggle components

325-c:切換組件325-c: Toggle Components

330:導電路徑330: Conductive path

Claims (29)

一種記憶體設備,其包含:一記憶體晶粒,該記憶體晶粒包含:一輸入/輸出(I/O)襯墊;包括於該記憶體晶粒中之一輸入緩衝器,該輸入緩衝器與該I/O襯墊耦接;及具有一可調整電容且包括於該記憶體晶粒中之一電容性組件,該電容性組件與該I/O襯墊耦接。 A memory device comprising: a memory die including: an input/output (I/O) pad; an input buffer included in the memory die, the input buffer a device coupled with the I/O pad; and a capacitive element having an adjustable capacitance and included in the memory die, the capacitive element coupled with the I/O pad. 如請求項1之記憶體設備,其中該電容性組件包含一電容器及可操作以將該電容器與該I/O襯墊選擇性地耦接之一切換組件。 The memory device of claim 1, wherein the capacitive element comprises a capacitor and a switching element operable to selectively couple the capacitor to the I/O pad. 如請求項1之記憶體設備,其中該電容性組件包含複數個電容器及複數個切換組件,該複數個切換組件中之每一各別切換組件可操作以將該複數個電容器中之一各別電容器與該I/O襯墊選擇性地耦接。 The memory device as claimed in claim 1, wherein the capacitive element includes a plurality of capacitors and a plurality of switching elements, each individual switching element in the plurality of switching elements is operable to individually separate one of the plurality of capacitors A capacitor is selectively coupled to the I/O pad. 如請求項1之記憶體設備,其進一步包含:一模式暫存器,其可操作以儲存一或多個邏輯值;及一控制器,其可操作以致使該設備至少部分地基於該一或多個邏輯值組態該電容性組件,以具有由該電容性組件支援的複數個電容中之一者。 The memory device of claim 1, further comprising: a mode register operable to store one or more logic values; and a controller operable to cause the device to be based at least in part on the one or more logical values Logical values configure the capacitive element to have one of a plurality of capacitances supported by the capacitive element. 如請求項4之記憶體設備,其中: 該電容性組件包含複數個切換組件;且該一或多個邏輯值指示用於使該控制器閉合的該複數個切換組件之一數量。 Such as the memory device of claim 4, wherein: The capacitive element includes a plurality of switching elements; and the one or more logical values indicate a quantity of one of the plurality of switching elements for closing the controller. 如請求項4之記憶體設備,其中:該電容性組件包含複數個切換組件;且該一或多個邏輯值包含一點陣圖,該點陣圖之每一位元指示該控制器是開啟抑或閉合該複數個切換組件中之一各別切換組件。 The memory device as claimed in claim 4, wherein: the capacitive element includes a plurality of switching elements; and the one or more logic values include a bitmap, and each bit of the bitmap indicates whether the controller is turned on or One of the plurality of switching components is closed respectively. 如請求項1之記憶體設備,其進一步包含:一控制器,其與該電容性組件耦接且可操作以至少部分地基於組態該電容性組件之該可調整電容而組態經由該I/O襯墊所接收的一信號之一轉換速率。 The memory device of claim 1, further comprising: a controller coupled to the capacitive element and operable to configure the adjustable capacitance via the I based at least in part on configuring the adjustable capacitance of the capacitive element The slew rate of a signal received by the /O pad. 如請求項1之記憶體設備,其進一步包含:一第二記憶體晶粒,其包含一第二I/O襯墊及一第二電容性組件,該第二電容性組件具有一第二可調整電容且與該第二I/O襯墊耦接。 The memory device of claim 1, further comprising: a second memory die comprising a second I/O pad and a second capacitive element, the second capacitive element has a second The capacitance is adjusted and coupled with the second I/O pad. 一種記憶體系統,其包含:一記憶體裝置,該記憶體裝置包含:一記憶體晶粒,其包含一輸入/輸出(I/O)襯墊;及一電容性組件,其具有一可調整電容且與該I/O襯墊耦接;以及一主機裝置,其與該記憶體裝置耦接,其中: 該主機裝置可操作以將組態資訊提供至該記憶體裝置;且該記憶體裝置可操作以至少部分地基於該組態資訊組態該電容性組件之該可調整電容。 A memory system comprising: a memory device comprising: a memory die comprising an input/output (I/O) pad; and a capacitive element having an adjustable capacitor and coupled with the I/O pad; and a host device coupled with the memory device, wherein: The host device is operable to provide configuration information to the memory device; and the memory device is operable to configure the adjustable capacitance of the capacitive element based at least in part on the configuration information. 如請求項9之記憶體系統,其中該記憶體裝置之該電容性組件包含一或多個電容器及一或多個切換組件,該一或多個切換組件中之每一者可操作以將該一或多個電容器之一各別電容器與該I/O襯墊選擇性地耦接。 As the memory system of claim 9, wherein the capacitive element of the memory device includes one or more capacitors and one or more switching elements, each of the one or more switching elements is operable to the A respective one of the one or more capacitors is selectively coupled to the I/O pad. 如請求項9之記憶體系統,其中該主機裝置可操作以至少部分地基於向該記憶體裝置發佈指示該組態資訊之一命令來提供該組態資訊。 The memory system of claim 9, wherein the host device is operable to provide the configuration information based at least in part on issuing a command to the memory device indicating the configuration information. 如請求項9之記憶體系統,其中該記憶體裝置進一步包含一模式暫存器,且其中該記憶體裝置可操作以至少部分地基於儲存於該模式暫存器中之一或多個邏輯值來組態該電容性組件之該可調整電容。 The memory system of claim 9, wherein the memory device further comprises a mode register, and wherein the memory device is operable based at least in part on one or more logical values stored in the mode register to configure the adjustable capacitance of the capacitive component. 如請求項12之記憶體系統,其中:該主機裝置可操作以至少部分地基於將該一或多個邏輯值之一指示傳輸至該記憶體裝置而提供該組態資訊;且該記憶體裝置可操作以至少部分地基於該指示將該一或多個邏輯值儲存於該模式暫存器中。 The memory system of claim 12, wherein: the host device is operable to provide the configuration information based at least in part on transmitting an indication of the one or more logical values to the memory device; and the memory device is operable to store the one or more logical values in the mode register based at least in part on the indication. 如請求項9之記憶體系統,其中該記憶體裝置進一步包含與該I/O襯墊耦接之一輸入緩衝器。 The memory system according to claim 9, wherein the memory device further comprises an input buffer coupled to the I/O pad. 如請求項9之記憶體系統,其中該記憶體裝置進一步包含一或多個額外記憶體晶粒,該一或多個額外記憶體晶粒各自包含一各別I/O襯墊。 The memory system of claim 9, wherein the memory device further comprises one or more additional memory dies, and each of the one or more additional memory dies comprises a respective I/O pad. 如請求項15之記憶體系統,其中該記憶體裝置可操作以將該電容性組件與該一或多個額外記憶體晶粒中之至少一者之該各別I/O襯墊耦接。 The memory system of claim 15, wherein the memory device is operable to couple the capacitive element to the respective I/O pad of at least one of the one or more additional memory dies. 如請求項9之記憶體系統,其進一步包含:一或多個額外記憶體裝置,其各自包含一各別記憶體晶粒,該各別記憶體晶粒包含一各別I/O襯墊及一各別電容性組件,該各別電容性組件具有一各別可調整電容且與該各別I/O襯墊耦接。 As the memory system of claim 9, it further comprises: one or more additional memory devices, each of which includes a respective memory die, the respective memory die includes a respective I/O pad and A respective capacitive element having a respective adjustable capacitance coupled to the respective I/O pad. 如請求項17之記憶體系統,其中:該記憶體裝置之該電容性組件經組態為具有一第一電容;且該一或多個額外記憶體裝置之一第二記憶體裝置中所包括的一第二電容性組件經組態為具有一第二電容。 The memory system of claim 17, wherein: the capacitive component of the memory device is configured to have a first capacitance; and one of the one or more additional memory devices includes a second memory device A second capacitive component of is configured to have a second capacitance. 如請求項18之記憶體系統,其中:該記憶體裝置比該第二記憶體裝置更接近該主機裝置;且該第一電容大於該第二電容。 The memory system of claim 18, wherein: the memory device is closer to the host device than the second memory device; and the first capacitance is greater than the second capacitance. 如請求項18之記憶體系統,其進一步包含:用於與該主機裝置、該記憶體裝置及該第二記憶體裝置耦接的一匯 流排之一終端阻抗,其中該記憶體裝置比該第二記憶體裝置更遠離該終端阻抗,且其中該第一電容大於該第二電容。 The memory system of claim 18, further comprising: a pool for coupling with the host device, the memory device, and the second memory device A terminal impedance of the current bank, wherein the memory device is farther from the terminal impedance than the second memory device, and wherein the first capacitance is greater than the second capacitance. 如請求項17之記憶體系統,其中該主機裝置之一單一I/O襯墊與包括該記憶體裝置之該I/O襯墊及該一或多個額外記憶體裝置中之每一者之該各別I/O襯墊的複數個I/O襯墊耦接。 The memory system of claim 17, wherein a single I/O pad of the host device is connected to each of the I/O pad including the memory device and the one or more additional memory devices A plurality of I/O pads of the respective I/O pads are coupled. 如請求項9之記憶體系統,其中自該主機裝置傳輸至該記憶體裝置之一信號之一轉換速率係至少部分基於該電容性組件之該可調整電容。 The memory system of claim 9, wherein a slew rate of a signal transmitted from the host device to the memory device is based at least in part on the adjustable capacitance of the capacitive element. 一種用於記憶體操作之方法,其包含:在一記憶體裝置處接收與該記憶體裝置之一輸入/輸出(I/O)襯墊之一目標電容相關聯的組態資訊;在該記憶體裝置處至少部分地基於該組態資訊組態該I/O襯墊之一電容;及在組態該I/O襯墊之該電容之後經由該I/O襯墊自一主機裝置接收傳信。 A method for memory operations, comprising: receiving, at a memory device, configuration information associated with a target capacitance of an input/output (I/O) pad of the memory device; configuring a capacitance of the I/O pad based at least in part on the configuration information at the host device; and receiving a signal from a host device via the I/O pad after configuring the capacitance of the I/O pad letter. 如請求項23之方法,其中:該記憶體裝置包含具有一可調整電容且與該I/O襯墊耦接之一電容性組件;組態該I/O襯墊之該電容包含組態該電容性組件;且該組態資訊指示該電容性組件之一組態。 The method of claim 23, wherein: the memory device includes a capacitive element having an adjustable capacitance coupled to the I/O pad; configuring the capacitance of the I/O pad includes configuring the a capacitive component; and the configuration information indicates a configuration of the capacitive component. 如請求項24之方法,其進一步包含:將該組態資訊儲存至一或多個模式暫存器;及至少部分地基於將該組態資訊儲存至該一或多個模式暫存器來組態該電容性組件。 The method of claim 24, further comprising: storing the configuration information to one or more mode registers; and configuring at least in part based on storing the configuration information to the one or more mode registers state the capacitive component. 如請求項23之方法,其進一步包含:在組態該I/O襯墊之該電容之後將已組態該I/O襯墊之該電容之一指示傳輸至該主機裝置。 The method of claim 23, further comprising: transmitting an indication that the capacitance of the I/O pad has been configured to the host device after configuring the capacitance of the I/O pad. 一種用於記憶體操作之方法,其包含:至少部分地基於與一記憶體裝置之一輸入/輸出(I/O)襯墊相關聯之一目標電容而識別該記憶體裝置之一電容性組件之一目標組態;至少部分地基於識別該目標組態而將指示該目標組態之組態資訊傳輸至該記憶體裝置;及在傳輸該組態資訊之後經由該I/O襯墊將傳信傳輸至該記憶體裝置。 A method for memory operations comprising: identifying a capacitive component of a memory device based at least in part on a target capacitance associated with an input/output (I/O) pad of the memory device a target configuration; based at least in part on identifying the target configuration, transmitting configuration information indicative of the target configuration to the memory device; and transmitting the transmitted configuration information via the I/O pad after transmitting the configuration information The message is transferred to the memory device. 如請求項27之方法,其進一步包含:至少部分地基於與一第二記憶體裝置之一第二輸入/輸出(I/O)襯墊相關聯之一第二目標電容而識別該第二記憶體裝置之一第二電容性組件之一第二目標組態,其中該第二目標電容不同於該目標電容;及至少部分地基於識別該第二目標組態而將指示該第二目標組態之第二組態資訊傳輸至該第二記憶體裝置。 The method of claim 27, further comprising: identifying a second memory device based at least in part on a second target capacitance associated with a second input/output (I/O) pad of the second memory device A second target configuration of a second capacitive component of the bulk device, wherein the second target capacitance is different from the target capacitance; and based at least in part on identifying the second target configuration will indicate the second target configuration The second configuration information is transmitted to the second memory device. 如請求項27之方法,其中該傳信之一轉換速率係至少部分基於該組態資訊。 The method of claim 27, wherein the signaling of a slew rate is based at least in part on the configuration information.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6812869B1 (en) * 2003-02-13 2004-11-02 Lattice Semiconductor Corporation Noise reduction techniques for programmable input/output circuits
US20080169851A1 (en) * 2007-01-17 2008-07-17 Nanya Technology Corporation Delay locked loop
US8502342B1 (en) * 2004-10-26 2013-08-06 Marvell Israel (M.I.S.L.) Ltd. Circuits, systems, and methods for reducing effects of cross talk in I/O lines and wire bonds
CN104299640A (en) * 2014-09-29 2015-01-21 灿芯半导体(上海)有限公司 Slew rate adaptive adjustment output circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6812869B1 (en) * 2003-02-13 2004-11-02 Lattice Semiconductor Corporation Noise reduction techniques for programmable input/output circuits
US8502342B1 (en) * 2004-10-26 2013-08-06 Marvell Israel (M.I.S.L.) Ltd. Circuits, systems, and methods for reducing effects of cross talk in I/O lines and wire bonds
US20080169851A1 (en) * 2007-01-17 2008-07-17 Nanya Technology Corporation Delay locked loop
CN104299640A (en) * 2014-09-29 2015-01-21 灿芯半导体(上海)有限公司 Slew rate adaptive adjustment output circuit

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