TWI780118B - Technique to tune sidewall passivation deposition conformality for high aspect ratio cylinder etch - Google Patents

Abstract

Methods, apparatus and systems for forming a recessed feature in dielectric material on a semiconductor substrate are provided. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective film on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective film may be deposited under different conditions (e.g., pressure, duration of reactant delivery, duration of plasma exposure, RF power, and/or RF duty cycle, etc.) in different deposition operations. Such conditions may affect the degree of conformality at which the protective film forms. In various embodiments, one or more protective films may be sub-conformal. In these or other embodiments, one or more other protective films may be conformal.

Description

Conformal Tuning Techniques for Sidewall Protect Deposition for High Aspect Ratio Cylindrical Etch

The present invention relates to a conformal tuning technique for sidewall protection layer deposition for high aspect ratio cylindrical etch.

One process commonly used during semiconductor device fabrication is to form etched cylinders in a dielectric material. Exemplary contexts in which such processes may be performed include, but are not limited to, memory applications such as DRAM and 3D NAND structures. As the semiconductor industry advances and device sizes become smaller, it becomes more difficult to etch such cylinders in a uniform manner, especially for high aspect ratio cylinders that are narrow in width and/or deep in depth.

Certain embodiments herein relate to methods and apparatus for forming etched features in dielectric materials on semiconductor substrates. The disclosed embodiments may use certain techniques to deposit a protective film on the sidewalls of etched features, thereby allowing etching to occur at high aspect ratios. In various embodiments, the deposition process can be adjusted such that depositions performed earlier and depositions performed later occur under different deposition conditions. In this way, the protective film deposited on the sidewalls of a partially etched feature can be tailored as needed to further etch the feature. In one example, the conformality of the protective film can be adjusted so that the deposited protective film has different degrees of conformality at different iterations. The difference in conformality allows the protective film to be deposited only in the most favorable areas, such as where the bow is (or is about to be) formed.

In an aspect of the disclosed embodiments, there is provided a method of forming etched features in a substrate comprising a dielectric material, the method comprising: (a) generating a first plasma comprising an etch reactant, causing exposing the substrate to the first plasma, and partially etching the feature in the substrate; (b) after (a), depositing a protective film on the sidewalls of the feature, wherein the protective film is deposited by plasma assisted atomic layer a deposition reaction comprising: (i) exposing the substrate to a first deposition reactant and allowing the first deposition reactant to adsorb to the sidewall of the feature; (ii) after (i), exposing the substrate to a second plasma , the second plasma includes a second deposition reactant, wherein the step of exposing the substrate to the second plasma drives a surface reaction between the first deposition reactant and the second deposition reactant, thereby forming a protective film at the feature and (c) repeating (a)-(b) until the feature is etched to a final depth in which the protective film deposited in (b) substantially prevents the feature from forming during (a) and wherein the feature has an aspect ratio of about 5 or greater at its final depth.

In another aspect of the disclosed embodiments, an apparatus for forming etched features in a substrate comprising a dielectric material is provided, the apparatus comprising: one or more reaction chambers, wherein at least one reaction chamber is designed or configured to perform etching, and at least one reaction chamber is designed or configured to perform deposition, each reaction chamber includes: an inlet for introducing a plurality of process gases into the reaction chamber; an outlet for removing material, and a plasma source; and a controller having instructions for: (a) generating a first plasma including etch reactants, exposing the substrate to the first plasma, and, in part, etching a feature in a substrate, wherein (a) is performed in a reaction chamber designed or configured to perform the etching; (b) after (a), depositing a protective film on the sidewalls of the feature, wherein the deposition of the protective film A plasma-assisted atomic layer deposition reaction comprising: (i) exposing the substrate to a first deposition reactant, and allowing the first deposition reactant to adsorb to the sidewall of the feature; (ii) after (i), exposing the substrate to a second plasma, the second plasma comprising a second deposition reactant, wherein exposing the substrate to the second plasma drives a surface reaction between the first deposition reactant and the second deposition reactant, Thereby forming a protective film on the sidewalls of the feature, wherein (b) is performed in a reaction chamber designed or configured to perform the deposition; and (c) repeating (a)-(b) until the feature is etched to A final depth, wherein the protective film deposited in (b) substantially prevents lateral etching of the feature during (a), and wherein the feature has an aspect ratio of about 5 or greater at its final depth.

In yet another aspect of the disclosed embodiments, there is provided a method of forming etched features in a substrate comprising a dielectric material, the method comprising: (a) generating a first plasma comprising an etch reactant, exposing the substrate to the first plasma, and partially etching the feature in the substrate; (b) after (a), depositing a protective film on the sidewalls of the feature; and (c) repeating (a)-(b ) until the feature is etched to a final depth, wherein the feature has an aspect ratio of about 5 or greater at its final depth, and wherein the protective film deposited in the first iteration of (b) is less than ( The protective film deposited in the second iteration of b) was more conformal.

In certain embodiments, the first iteration of (b) is performed prior to the second iteration of (b). In other embodiments, the first iteration of (b) is performed after the second iteration of (b). The protective film deposited in the first iteration of (b) may be conformal and the protective film deposited in the second iteration of (b) may be sub-conformal . In some of these cases, the protective film deposited in the second iteration of (b) may not extend to the bottom of the partially etched feature.

In various embodiments, the protective film deposited in the first iteration of (b) may be deposited under different conditions than the protective film deposited in the second iteration of (b). In one example, the protective film deposited in the first iteration of (b) can be deposited at a higher pressure than the protective film deposited in the second iteration of (b). In these or other examples, the protective film deposited in the first iteration of (b) may proceed at a lower reactant transport rate than the protective film deposited in the second iteration of (b) deposition. In these or other examples, the protective film deposited in the first iteration of (b) can have a shorter duration of reactant delivery than the protective film deposited in the second iteration of (b) to deposit. In these or other examples, the protective film deposited in the first iteration of (b) can be exposed to the plasma for a shorter duration than the protective film deposited in the second iteration of (b) to deposit. In these or other examples, the protective film deposited in the first iteration of (b) can be deposited at a higher RF power than the protective film deposited in the second iteration of (b). In these or other examples, the protective film deposited in the first iteration of (b) can be deposited at a higher RF duty cycle than the protective film deposited in the second iteration of (b) . In various embodiments, the protective film deposited in the first iteration of (b) can be deposited using the first set of deposition conditions, and the protective film deposited in the second iteration of (b) can be deposited using the first set of deposition conditions. The deposition is performed under two sets of deposition conditions, the first set and the second set of deposition conditions may differ in at least two parameters selected from the group consisting of pressure, reactant delivery flow rate, reactant delivery duration, The group consisting of plasma exposure duration, RF power, and RF duty cycle. In some such embodiments, the first set of deposition conditions may have a lower reactant delivery flow rate and (i) a shorter duration of reactant delivery, and/or (ii) a shorter duration of plasma exposure any of the times.

In some implementations, at least one iteration of (a) may result in an arc formed within the feature, and one subsequent iteration of (b) may result in the formation of a protective film at least as deep as the arc , but not as deep as the characteristic part. Protective films can be deposited by several different techniques. In one example, the protective film can be deposited by thermal ALD or plasma assisted ALD. In another example, the protective film can be deposited by molecular layer deposition. In another example, the protective film can be deposited by a self-assembled monolayer reaction. In another example, the protective film can be deposited by thermal chemical vapor deposition or plasma enhanced chemical vapor deposition.

In yet another aspect of the disclosed embodiments, an apparatus for forming etched features in a substrate comprising a dielectric material is provided, the apparatus comprising: one or more reaction chambers, wherein at least one reaction chamber Designed or configured to perform etching, wherein at least one reaction chamber is designed or configured to perform deposition, each reaction chamber comprising: an inlet for introducing process gas into the reaction chamber, and an inlet for removing process gas from the reaction chamber In addition to an outlet for material, and a controller having instructions for: (a) generating a first plasma comprising etch reactants, exposing the substrate to the first plasma, and partially etching features in In a substrate, where (a) is performed in a reaction chamber designed or configured to perform etching; after (a), depositing a protective film on the sidewalls of features, where (b) is performed in a chamber designed or configured to perform deposition and (c) repeating (a)-(b) until the feature is etched to a final depth, wherein the feature has an aspect ratio of about 5 or greater at its final depth, and wherein The protective film deposited in the first iteration of (b) was more conformal than the protective film deposited in the second iteration of (b).

In some embodiments, the reaction chamber designed or configured to perform etching may be the same as the reaction chamber designed or configured to perform deposition such that both (a) and (b) occur in the same reaction chamber middle. In certain other embodiments, the reaction chamber may be designed or configured to perform etching differently than the reaction chamber designed or configured to perform deposition, and the controller may further include a plurality of instructions for use in the design or configuration to perform etching The substrate is transferred between a reaction chamber and a reaction chamber designed or configured to perform deposition.

These and other features are described below with reference to the related drawings.

In this application, the terms "semiconductor wafer", "wafer", "substrate", "wafer substrate" and "partially fabricated integrated circuit" are used interchangeably. Those skilled in the art will understand that the term "partially fabricated integrated circuit" may refer to a silicon wafer during any of the numerous stages of integrated circuit fabrication. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, 300 mm, or 450 mm. The following detailed description assumes that the invention is implemented on a wafer. However, the present invention is not limited thereto. Workpieces can be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that may benefit from the present invention include various items such as printed circuit boards, magnetic recording media, magnetic recording sensors, mirrors, optical components, micromechanical devices, and the like.

In the following description, various specific details are set forth in order to provide a thorough understanding of the described embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described using specific embodiments, it should be understood that no limitation of the disclosed embodiments is intended. I. Techniques for Etching High Aspect Ratio Features in Dielectric Materials

The fabrication of certain semiconductor devices involves etching features into a dielectric material or dielectric materials. The dielectric material can be a single layer of material or a stack of multiple materials. In some cases, the stack includes alternating layers of dielectric material (eg, silicon nitride and silicon oxide). An example of an etched feature is a cylinder, which can have a high aspect ratio. As the aspect ratios of such features continue to increase, it becomes increasingly difficult to etch the features into the dielectric material. One problem that arises during etching of high aspect ratio features is a non-uniform etch profile. In other words, the features are not etched in a vertically downward direction. Instead, the sidewalls of the features are generally curved such that the middle of the etched feature is wider (ie, more etched) than the top and/or bottom of the feature. This overetching near the middle of the feature can cause the structural and/or electrical integrity of the remaining material to be adversely affected. The outwardly curved feature portion may occupy a relatively small portion or a relatively large portion of the total feature depth. The portion of the feature that bows outward is the portion of the feature that has the largest critical dimension (CD). A critical dimension corresponds to the diameter of a feature at a particular location. It is generally desirable that the maximum CD of a feature be approximately equal to the CD elsewhere in the feature, such as near the bottom of the feature.

Without being bound by any theory or mechanism of action, it is generally believed that overetching at the middle of a cylinder or other feature occurs at least in part because the sidewalls of the cylinder are not adequately protected against etching. Conventional etch chemistries use fluorocarbon etchants to form cylinders in dielectric materials. Fluorocarbon etchants are excited by plasma exposure, thus forming various fluorocarbon fragments including, for example, CF, _CF2 , and _CF3 . The reactive fluorocarbon fragments etch with the assistance of ions to remove the dielectric material at the bottom of the feature (eg, cylinder). Other fluorocarbon fragments are deposited on the sidewalls of the etched cylinder, thereby forming a protective polymer sidewall coating. This protective sidewall coating promotes preferential etching at the bottom of the feature (relative to the sidewall of the feature). Without this sidewall protection, the features start to take on a non-uniform profile, with wider etch/barrel widths where the sidewall protection is insufficient.

Sidewall protection is particularly difficult to achieve in high aspect ratio features. One reason for this difficulty is the inability of current fluorocarbon-based processes to form protective polymer sidewall coatings in the cylinder where lateral overetching occurs. FIG. 1 shows a diagram of a cylinder 102 etched into a dielectric material 103 covered by a patterned mask layer 106 . Although sometimes referred to as a cylinder in the following discussion, this concept applies to other feature shapes, such as rectangles and other polygons. A protective polymeric sidewall coating 104 is concentrated near the upper portion of the barrel 102 . The _{CxFy chemistry} provides both the etch reactant (or reactants) to etch the cylinder vertically and the reactant (or reactants) to form the protective polymer sidewall coating 104 ). Since the protective polymeric sidewall coating 104 does not extend deep enough into the cylinder (i.e., is not sufficiently deposited on the sidewall), the middle portion of the cylinder 102 becomes longer than the cylinder. The top and bottom of the bar 102 are wider. The wider middle portion of the cylinder 102 is referred to as the arc 105 . The arcuate portion can be expressed numerically as a comparison between the critical dimension of the feature in the arcuate region (a relatively wide area) and the critical dimension below the arcuate region (eg, the bottom region of the feature). The arc can be expressed numerically as a distance (e.g., CD at the widest point of the feature minus CD at the narrowest point below the arc of the feature), or as a ratio/percentage (the CD of the feature Divide the critical dimension at the widest point by the critical dimension at the narrowest point below the arc of the feature). This arc 105 and associated non-uniform etch profile is undesirable. Since high ion energies are typically used in such etching processes, arcs are often created when etching cylinders with high aspect ratios. In some applications, even aspect ratios as low as about 5 may still result in cambers. Accordingly, conventional fluorocarbon etch chemistries are generally limited to forming relatively low aspect ratio cylinders in dielectric materials. Certain current applications require cylinder aspect ratios that are higher than those achievable with conventional etch chemistries. II. Background and Applications

In various embodiments herein, features are etched into a substrate (typically a semiconductor wafer) with a dielectric material on the surface. The dielectric material can be a stack of plural materials. The etch process is generally a plasma-based etch process. The bulk feature formation process can be performed in multiple stages: one stage involves etching the dielectric material, and another stage involves forming protective sidewall coatings without substantially etching the dielectric material. The protective sidewall coatings passivate the sidewalls and protect the features from over-etching (ie, the sidewall coatings prevent lateral etching of the features). These two stages can be repeated until the feature is etched to its final depth. By cycling through these two stages, the diameter of the feature can be controlled throughout the depth of the feature, thereby forming features with a more uniform diameter/better profile.

A feature is a depression in the surface of the substrate. Features may have many different shapes including, but not limited to, cylinders, rectangles, squares, other polygonal depressions, grooves, and the like.

Aspect ratio is the ratio of the depth of a feature to the critical dimension of the feature (usually width/diameter). For example, a cylinder with a depth of 2 µm and a width of 50 nm has an aspect ratio of 40:1, often written more briefly as 40. Since a feature may have a non-uniform critical dimension throughout its depth, the aspect ratio may vary with measurement location. For example, sometimes an etched cylinder may have a wider middle portion than the upper and bottom portions. As mentioned above, this wider middle portion may be referred to as an arcuate portion. Aspect ratios based on critical dimensions at the upper part of the barrel (i.e., neck) may be higher than measurements based on critical dimensions at the wider middle/arc of the barrel aspect ratio. Unless otherwise indicated, aspect ratios used herein are based on critical dimensions measured near the opening of the feature.

Features formed by the disclosed methods can be high aspect ratio features. In certain applications, the high aspect ratio features are those having at least about 5, at least about 10, at least about 20, at least about 30, at least about 40, at least about 50, at least about 60, at least about 80, or at least about 100 The characteristic part of the aspect ratio. Features formed by the disclosed methods can have a critical dimension of about 200 nm or less, such as about 100 nm or less, about 50 nm or less, or about 20 nm or less.

In various cases, the material etched to form the features may be a dielectric material. Exemplary materials include, but are not limited to, silicon oxide, silicon nitride, silicon carbide, oxynitride, oxycarbide, carbo-nitride, doped Heterogeneous forms (eg, doped with boron, phosphorus, etc.), stacks of any combination of these materials. Certain exemplary materials include stoichiometric and non-stoichiometric formulations of SiO ₂ , SiN, SiON, SiOC, SiCN, and the like. In various cases, the material or materials being etched may also contain other elements, such as hydrogen. In some embodiments, the nitride and/or oxide material that is etched has a composition that includes hydrogen. It should be understood that silicon oxide materials, silicon nitride materials, etc., as used herein include both stoichiometric and non-stoichiometric forms of such materials, and that such materials may have other elements, as described above.

One application of the disclosed method is in the context of forming DRAM devices. In this case, the features may primarily be etched in silicon oxide. The substrate may also include, for example, one, two, or more layers of silicon nitride. In one example, the substrate includes a silicon oxide layer sandwiched between two silicon nitride layers, the thickness of the silicon oxide layer is between about 800-1200 nm, and the thickness of the one or more silicon nitride layers is The thickness is between about 300-400 nm. The etched feature may be a cylinder having a depth of between about 1-3 µm, such as between about 1.5-2 µm. The cylinder may have a width of between about 20-50 nm, such as between about 25-30 nm. After etching of the cylinder, capacitor memory cells may be formed therein.

Another application of the disclosed method is in the context of forming vertical NAND (VNAND, also known as 3D NAND) devices. In this case, the material that is etched to form the features therein may have a repeating layered structure. For example, the material may comprise a plurality of alternating layers of oxide (eg, SiO ₂ ) and nitride (eg, SiN), or a plurality of alternating layers of oxide (eg, SiO ₂ ) and polysilicon. A plurality of alternating layers forms a plurality of pairs of materials. In certain cases, the number of pairs can be at least about 20, at least about 30, at least about 40, at least about 60, or at least about 70. The thickness of the oxide layer may be between about 20-50 nm, such as between about 30-40 nm. The thickness of the nitride or polysilicon layer may be between about 20-50 nm, such as between about 30-40 nm. The depth of the features etched into the alternating layers may be between about 2-6 μm, such as between about 3-5 μm. The width of the features may be between about 50-150 nm, such as between about 50-100 nm. III. Etching/deposition process

FIG. 2 shows a flowchart of a method 200 for forming etched features on a semiconductor substrate. The operations shown in FIG. 2 are described with reference to FIGS. 3A-3D , which show a partially fabricated semiconductor substrate as features are etched. A particular embodiment of the method 200 of FIG. 2 is described below with reference to FIGS. 3E-3I. In operation 201 , a feature 302 is etched to a first depth in a substrate having a material 303 and a patterned mask layer 306 . Material 303 can be a single material or a stack of multiple materials. Material 303 typically includes one or more layers of dielectric material. The first depth is only a fraction of the final desired depth of the feature. The chemistry used to etch the features may be a fluorocarbon based chemistry (C _x F _y ). Other etch chemistries may be used. This etch operation 201 may result in the formation of a first sidewall cladding layer 304 . As described with reference to FIG. 1 , the first sidewall coating 304 may be a polymer sidewall coating. The first sidewall cladding 304 extends toward the first depth, but in many cases the first sidewall cladding 304 does not actually reach the bottom of the feature 302 . In particular, in many cases, the first sidewall cladding 304 does not reach the region where the arc is formed in the feature.

The first sidewall coating 304 is formed indirectly from the _CxFy etch chemistry when certain fluorocarbon species/debris deposits on the sidewalls of the feature ₍ i.e., certain fluorocarbon species are the first sidewall coating layer 304 precursor). One reason why the first sidewall cladding 304 does not reach the bottom of the feature 302 may be related to the viscosity of the precursor before the cladding is formed. In particular, it is generally believed that the viscosity coefficients of these first sidewall cladding precursors are too high for certain etchants, causing substantially most of the precursor molecules to adhere to the feature very quickly after entering the feature. side wall. Consequently, a small number of sidewall cladding precursor molecules can penetrate deep into the feature resulting in favorable sidewall protection. Thus, the first sidewall cladding 304 can only provide partial protection to the sidewalls of the feature 302 against overetching. In some implementations, the etch conditions provide little, if any, sidewall protection.

Next, in operation 203, the etching process is stopped. After the etch is stopped, a second sidewall cladding 310 is deposited in operation 205 . In some cases, the second sidewall cladding 310 may actually be the first sidewall cladding. The second sidewall coating 310 is often referred to as a protective film or protective layer. This deposition can be performed via various reaction mechanisms including, but not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD) (either of which can be plasma assisted or thermally driven), molecular layer deposition (MLD) method, and self-assembled monolayer (SAM) method. Molecular layer deposition is further discussed in US Patent No. 9,384,998, and self-assembled monolayer deposition is further discussed in US Patent Application Serial No. 15/225,489, each of which is incorporated herein by reference.

ALD and other adsorption-based methods are particularly suitable for forming films with a desired degree of conformality to cover or partially cover the surface of a feature sidewall. For example, certain adsorption-based deposition methods facilitate the formation of highly conformal films that transport reactants deep into features through the adsorption-driven nature of such methods. In conformal films, the thickness of the deposited film is relatively uniform at all areas of the feature. In contrast, for subconformal film deposition, the deposited film is relatively thick near the top of the feature and relatively thin (or completely thin) near the bottom of the feature. No). For ultra-conformal film deposition, the deposited film is relatively thin near the top of the feature and relatively thick near the bottom of the feature. Each of these types of deposition may facilitate one or more of the deposition processes described herein. Conformal, sub-conformal, and super-conformal protective films can be combined as desired for a particular application. In some cases, non-adsorption-based deposition techniques (eg, CVD) may also be used to form conformal, sub-conformal, and/or ultra-conformal protective films.

As used herein, conformality can be calculated according to Equation 1. Equation 1:

As used herein, a conformal or highly conformal film is a film having a conformality of between about 1.0-1.5. A sub-conformal film is a film having a conformality of at least about 1.5. In some cases, a sub-conformal film can have a conformality of at least about 2.5. A superconformal film is a film having a conformality of about 1.0 or less. These conformal systems are calculated according to Equation 1 above.

In some embodiments, the deposition of second sidewall cladding layer 310 (during one or more iterations of deposition operations 205 and/or 215) uses reactants with relatively low viscosities (e.g., silicon-containing reactants and/or boron-containing reactants). In transporting reactants, the coefficient of viscosity may be low regardless of what species are present on the sidewall (eg, the coefficient of viscosity may be low relative to the native sidewall and/or any species present on the sidewall). Furthermore, the relevant viscosity is that of the species actually contacting the sidewall; such species may not be reactants entering the chamber. In one embodiment, the second sidewall cladding layer 310 is deposited by ALD, and the deposition in operation 205 and/or operation 215 includes: (a) flowing a low viscosity reactant into the reaction chamber, and allowing the reactants to adsorb onto the substrate surface, thereby forming the adsorbed precursor layer 312; (b) optionally purging the reaction chamber (e.g., by purging, evacuating the reaction chamber with a purge gas; , or both); (c) exposing the substrate to a plasma generated by oxygen- and/or nitrogen-containing reactants (usually also provided together with hydrogen) to drive surface reactions to form a second sidewall coating 310 (The second sidewall coating 310 is generally an etch-resistant film); (d) optionally blowing the reaction chamber; and (e) repeating (a)-(d) to form an additional layer of the second sidewall coating 310 Floor. The adsorbed precursor layer 312 is shown in FIG. 3B, and the second sidewall coating 310 is shown in FIG. 3C. Precursor adsorption (FIG. 3B) and film formation (FIG. 3C) can be cycled several times to form a film with a desired thickness.

In another embodiment, the second sidewall cladding layer 310 is deposited by CVD, which may include flowing a low-viscosity reactant into the reaction chamber, optionally accompanied by co-reactants (e.g., oxygen-containing reactions). and/or nitrogen-containing reactants, optionally together with hydrogen), while simultaneously exposing the substrate to the plasma. The plasma drives a gas phase reaction that results in the deposition of the second sidewall cladding layer 310 . In this example, the method is represented by FIGS. 3A , 3C, and 3D (the adsorbed precursor layer 312 is not formed, so FIG. 3B is omitted).

The viscosity coefficient is a term used to describe the ratio of the number of adsorbed species (eg, atoms or molecules) adsorbed/adhered to a surface compared to the total number of species hitting the surface during the same period of time. The symbol Sc is sometimes used to indicate the coefficient of viscosity. The value of Sc is between 0 (indicating that no species adheres) and 1 (indicating that all impacting species adhere). Various factors affect the viscosity coefficient, including the type of impacting species, surface temperature, surface coverage, structural details of the surface, and the kinetic energy of the impacting species. Some species are inherently more "sticky" than others, making it more likely that each time the species hits the surface, it will stick to the surface. These viscous species have larger viscosity coefficients (all other factors being equal) and are more likely to adsorb near the entrances of depressed features than less viscous species with lower viscosity coefficients. Fluorocarbon species such as those used in conventional etch processes (and which may form first sidewall cladding 304 ) have relatively high viscosity coefficients and thus concentrate near the top of feature 302 , where Where it hits the side wall for the first time. In contrast, species with lower viscosity coefficients, even if they impinge on surfaces near the upper portion of the sidewall, are less likely to adsorb during each impact and thus have a higher probability of reaching deeper into the feature 302 .

In some embodiments, the silicon-containing reactant and the boron-containing reactant are used to form the second sidewall cladding layer 310 and have a lower viscosity than the fluorocarbon species forming the first sidewall cladding layer 304 . Thus, these reactants are suitable for forming a protective coating that reaches the bottom of etched features. In addition, certain adsorption-based ALD methods are particularly well-suited for forming a second sidewall coating that reaches the bottom of an etched feature because the reactants can be transported until they cover substantially the entire sidewall of the feature. The reactants do not accumulate near the upper top of the feature because typically only a monolayer of reactants adsorbs to the surface during each cycle.

Returning to FIG. 2 , the method continues at operation 207 where the deposition process is stopped. The method then repeats the following operations: partially etching features into the substrate (operation 211, similar to operation 201); stopping etching (operation 213, similar to operation 203); depositing a protective coating over the partially etched features on the sidewall (operation 215, similar to operation 205); and stop deposition (operation 217, similar to operation 207).

The process conditions used for each operation may be the same or different during the different iterations. For example, the etching conditions of the first etching operation may be different from the etching conditions of the second etching operation. Similarly, the deposition conditions of the first deposition operation may be different from the deposition conditions of the second deposition operation. As features are etched deeper, changing conditions may result in changing feature shapes. For example, as a feature is etched deeper, the relative position of the arcuate regions within the feature changes. When additional etch and/or deposition iterations are performed, the process conditions for each iteration can be tailored/optimized for the current feature shape by varying the etch and/or deposition conditions. This allows protection of the arcuate region at any depth of the feature (thereby minimizing the extent of arcuate formation during etching). In one example, further explained using FIGS. 3E-3I , the deposition conditions are different between at least two iterations of the plurality of deposition operations. In a specific example, the pressure, reactant flow rate, reactant supply time, RF time, RF power, and/or RF duty cycle may be different between two deposition operations, e.g., such that in each operation The degree of conformality of the deposited protective films varies. By tailoring the conformality of each deposition, each protective film can be deposited where it is most useful (for example, where arcs may be formed).

Returning to FIG. 2 , in operation 219 , it is determined whether the feature is fully etched. If the feature has not been etched completely, the method repeats from operation 211 with additional etching and deposition of a protective coating. Etching operation 211 may alter second sidewall cladding 310 to form a film that is even more etch resistant than the films deposited in operations 205 and 215 . In one example, a deposition operation 205 forms a layer of boronitride (e.g., by alternating cycles of _BCl3 and _N2 + _H2 and exposure to plasma), and an etch operation 211 reacts the boronitride film to form boron oxide (for example, using chemicals with a combination of fluorocarbons (or fluorocarbons) and oxygen). Once the features are etched completely, the method is complete.

In various embodiments, the etch operation 201 and the protective sidewall coating deposition operation 205 are repeated several times in a cycle. For example, each of these operations may occur at least two times (as shown in FIG. 2 ), such as at least about 3 times, or at least about 5 times. In some cases, the number of cycles is between about 2-10, such as between about 2-5 (each cycle includes etching operation 201 and protective sidewall coating deposition operation 205, wherein etching operation 211 and deposition Operation 215 counts as the second loop). Each time an etching operation occurs, the etching depth increases. The distance to etch can be the same between cycles, or it can be different. In some embodiments, the distance etched in each cycle decreases as additional etching is performed (i.e., etching operations performed later may etch a smaller amount than etching operations performed earlier) . The thickness of the second sidewall cladding 310 deposited in each deposition operation 205 may be the same between cycles, or the thickness of such cladding may vary. An example thickness of the second sidewall cladding layer 310 may range between about 1-10 nm, such as between about 3-5 nm, during each cycle. Similarly, the conformality of the second sidewall cladding 310 may be the same from cycle to cycle, or may vary from cycle to cycle, as illustrated in Figures 3E-3I. Furthermore, the type of coating formed may be the same between cycles, or it may change.

Etching operation 201 and deposition operation 205 may occur in the same reaction chamber or in different reaction chambers. In one example, etch operation 201 occurs in a first reaction chamber and deposition operation 205 occurs in a second reaction chamber, wherein the first and second reaction chambers together form a multi-chamber process tool, such as a cluster formula tool. Loadlocks and other suitable vacuum seals may be provided for transferring substrates between associated chambers in some cases. Substrates can be transferred by robotic arms or other mechanical structures. The reaction chamber used for etching (and deposition, in some cases) can be a Flex™ reaction chamber, eg, the 2300® Flex ^™ product series available from Lam Research Corporation of Fremont, CA. The reaction chamber used for deposition can be a chamber from the Vector ^® product line or the Altus ^® product line, both commercially available from Lam Research Corporation. In certain embodiments, it may be advantageous to use a bonded reactor for both etching and deposition because the need to transfer the substrate is avoided. In other embodiments, where it is desired to specifically optimize the reactor for each operation, it may be advantageous to use different reactors for etching and deposition. Related reaction chambers are discussed further below.

As noted above, the deposition operation helps to optimize the etch operation by forming a protective layer at the relevant sidewall locations that minimizes or prevents lateral etching of features during the etch operation. This facilitates the formation of etched features with very vertical sidewalls, with little or no curvature. In certain implementations, the etched final feature having an aspect ratio of at least about 80 has an arc of less than about 60% (by (widest CD - narrowest CD below) / below The narrowest critical dimension * 100 to be measured). For example, a feature with the widest CD 50 nm and the narrowest CD 40 nm (where the 40 nm CD is below the 50 nm CD in the feature) has a 25% arc (100*(50 nm - 40 nm nm)/40 nm = 25%). In another implementation, the etched final features having an aspect ratio of at least about 40 have a curvature of less than about 20%.

In certain implementations, deposition conditions may be adjusted for a particular deposition operation. For example, conditions may be adjusted such that a first set of deposition conditions used in a first deposition operation differs from a second set of deposition conditions used in a second deposition operation. Differences in deposition conditions may result in differences in film thickness, conformality, density, composition, etc. 3E-3I illustrate a partially etched substrate at various points during the process, in one embodiment, where the conformality of the protective film is adjusted for different deposition operations. Adjustment of conformality allows the protective film to be formed at feature depths where the protective film is most useful (eg, where arcs are likely to form).

FIG. 3E shows a partially etched substrate including a patterned mask layer 306 on material 303 . As noted above, material 303 may be a single material or a stack of multiple materials, and may include one or more dielectric materials. Features 302 are formed in the substrate. In FIGS. 3E-3I , any protective film layers formed during the etching operation (eg, first sidewall cladding 304 in FIGS. 3A-3D ) are omitted from the drawings. Such film layers may or may not be formed during etching operations. The asterisks (*) in FIGS. 3E-3I emphasize areas of the sidewalls where arcs may form if no protective film is deposited on the sidewalls. In some embodiments, even though a protective film is provided, an arc may indeed form in this region (although this arc is smaller than it would be without the protective film). After partially etching feature 302, as shown in FIG. 3E, a first protective film 320a is deposited on the sidewall of feature 203, as shown in FIG. 3F. In this example, the first protective film 320a is highly conformal and deposited along substantially the entire length of the sidewalls. The first protective film 320a may or may not be formed on the bottom surface of the feature, depending on the deposition conditions used and the shape of the feature.

Next, the features are etched to a greater depth, as shown in Figure 3G. During this etching operation, the first protection film 320a may be partially, substantially, or completely etched away. Apparently, the first protective film 320a is provided deep enough to reach the area marked with an asterisk (*), if the first protective film 320a does not cover this area, an arc may be formed there. After etching, a second protective film 320b is deposited, as shown in FIG. 3H. In this example, second protective film 320b is subconformal, meaning that it is deposited to a greater thickness on the sidewalls near the opening of feature 302 and to a lower thickness on the sidewall near the bottom of feature 302 (or no thickness). The second protective film 320b is deposited deep enough to cover the area marked with an asterisk (*), if the second protective film 320b does not cover this area, an arc may be formed there. After forming the second protective film 320b, the feature 302 is further etched, as shown in FIG. 3I.

FIG. 3J illustrates partially etched feature 302 formed in substrate 330 . In this example, the arc has been etched into the feature during a previous etch operation. The arc is next to the asterisk. The protective film 320c is deposited in a sub-conformal manner. Protective film 320c is deposited beyond the depth of the arc, but not all the way down to the bottom of the feature. In this way, the protective film 320c is aligned where it is most useful. During subsequent etching operations, the protection film 320c will prevent or minimize the degree of lateral etching of the arc-shaped region. During subsequent etching operations, the protective film 320c acts as a sacrificial material to ensure that the sidewalls of the feature are not over-etched in this area. The sub-conformal nature of the protective film 320c also ensures that the bottom of the feature is open (which allows relatively harsher/faster etch conditions to be used in subsequent etch operations), which reduces process time and increases throughput.

In various embodiments, the advantage of the protective film is greatest when the critical dimension reduction (due to the deposition of the protective film) is greater at the arcuate region compared to the critical dimension reduction immediately adjacent the bottom of the feature. In other words, the protective film may be most useful when it is deposited in an aligned manner in the area where the arc may be formed or is being formed (as opposed to deposited below the area where the arc may be formed). Because the arc is a measure of the difference between the largest critical dimension of the feature (for example, at the arc) and the narrowest area below the arc, when the cover protects the arc it does not protect (or does not Overprotection) is most advantageous on the sidewalls below the curved area. When the protective film is deposited in the area below where the arc may form (the lower sidewall), the protective film may protect the lower sidewall too much, resulting in an undesirably small critical dimension immediately adjacent the bottom of the feature, and limiting subsequent etching process.

Another advantage of tailoring the conformality of the protective film for different deposition operations is that it allows the etch process to be optimized to open/etch the bottom of the feature in a more aggressive manner (e.g. because of the The bottom sidewall of the feature may not be covered by the protective film in the region under which the feature is or may be formed). A further advantage associated with adjusting the conformality of the deposited protective film in different deposition operations is that the shape of the bottom of the feature can be improved. In each case, when the conformality of the resist was adjusted/changed for different resist depositions, the feature bottoms were squarer (less rounded) than when the resist was always deposited in a highly conformal manner. ).

Relatedly, the disclosed embodiments result in the formation of highly desirable (eg, highly vertical) feature profiles with small slopes. Typically, where the resists are both highly conformal, the resulting features have slopes because the bottoms of the features are overprotected and not etched away enough due to the highly conformal resists. In contrast, when the protective film is deposited in an aligned manner in the area where the arc is or may form, this overprotection of the area below the arc is avoided and a more vertical profile results. Another advantage associated with the disclosed embodiments is that the growth rate of the arcs can be minimized. Because the protective film is formed in an aligned manner in and immediately below the area where the arc is or may form, the arc area is subject to a greater degree of stress than the area below the arc. Protect. Because the arc can be measured by the difference between the largest CD at the arc and the narrowest CD below the arc, alignment at the arc compared to the area below the arc The protection slows down the growth of the arc in the feature.

Another advantage associated with the disclosed embodiments is that the risk of capping/blocking features is reduced. The relatively high reactant flow rates and long reactant supply times associated with more conformal protective film deposition are associated with an increased risk of clogging one or more features during deposition. The risk of such clogging is minimized by using lower reactant flow rates and/or shorter reactant supply times (alone or in combination with other process condition changes) in at least some protective layer depositions. In addition, the use of sub-conformal resists in at least some resist deposition operations reduces the risk of etch stalls or slowdowns. In some cases, a protective film deposited in a highly conformal manner on the sidewalls and bottom of the feature may prevent further etching of the feature. This result is undesirable. This risk is reduced by depositing the protective layer in a sub-conformal manner during at least some of the deposition operations.

A further advantage of the disclosed embodiments is that the sub-conformal protective film can enable different mixtures of species to be formed at different depths of the features. Diffusion of neutral species into recessed features depends on the reactivity and composition of the surface in the feature. By providing a sub-conformal protective film, sidewall reactivity and composition may be different at different feature depths (eg, selectively providing the protective film toward the upper sidewall of a feature as compared to the bottom sidewall of the feature). This may result in different mixtures of neutral species as a function of depth in the feature, which may be advantageous in certain embodiments. The disclosed embodiments have been shown to produce high quality results even over a wide range of process temperatures.

In order to align the deposition of the protective film in the desired area, the deposition conditions for a particular deposition operation can be tailored depending on the then feature shape/depth. For example, referring to FIGS. 3E-3I , the first protective film 320a is deposited in a highly conformal manner such that it covers substantially the entire depth of the partially etched feature 302 . This deposition is tailored to be highly conformal to ensure that the first protective film 320a covers the sidewalls at the areas indicated by asterisks (*), where arcs may form. In contrast, the second protective film 320b is deposited in a sub-conformal manner so that it reaches a depth that is (a) at least as deep as the region indicated by the asterisk (*), wherein the arcuate portion May form in the area marked by an asterisk (*), and (b) is not deep enough to reach the bottom of the feature. In many cases, the sub-conformal protective film 320b can be deposited to a depth that does not substantially exceed the depth at which the arc would have formed if no protective layer had been provided. In some cases, this may mean that the sub-conformal protective film reaches no more than about 2 times (and in some cases, no more than about 1.5 times) the depth at which the arc may form. In these or other cases, this may mean that the second protective film reaches a depth of no more than about 1 μm, or no more than about 0.5 μm, below the depth at which the arc may be formed. In these or other cases, the sub-conformal protective film can reach a depth that is a distance of at least about 0.5 μm, such as at least about 1 μm, from the bottom of the feature. The desired depth of a particular protective film depends on the geometry of the feature and the conditions used for etching at a particular time.

Although the examples shown in FIGS. 3E-3I involve depositing a more conformal protective film before depositing a less conformal protective film, embodiments are not so limited. In certain other embodiments, an earlier deposited protective film may be less conformal than a later deposited protective film. In one implementation, the protective film becomes less conformal as the features are etched further into the substrate. In a different implementation, the protective film becomes more conformal as the features are etched further into the substrate. In another implementation, the first protective film is deposited in a highly conformal manner, the second protective film is deposited in a subconformal manner, and the third protective film is deposited in a highly conformal manner, wherein The first, second and third protective films are deposited in this order. In general, each protective film deposition can be tailored according to the needs.

Various process conditions can be varied individually or together to tailor the conformality (and/or other film properties) of the deposited protective film layer. Exemplary process conditions that can be changed between different protective film depositions include pressure, reactant flow rate, reactant contact time, RF time, RF power, and/or RF duty cycle. For the case of depositing a protective film in a plasma-based process, RF time refers to the duration during which RF energy is supplied to generate/sustain a plasma. RF power refers to the amount of RF power used to drive the plasma. RF duty cycle refers to the fraction of time that RF power is actively applied. RF power can be provided continuously or in pulses.

It is generally believed that higher reaction chamber pressures generally result in more conformal membranes. Similarly, it is generally believed that higher reactant flow rates and longer reactant contact times result in more conformal films. These factors may affect how deep reactants can penetrate into partially etched features, thereby controlling how deep the protective film is formed. It is also generally believed that longer RF times and/or higher RF powers and/or higher RF duty cycles result in more conformal films, eg, due to more complete conversion of reactants. For conformal adjustments, each of these variables may be effective, within certain limits.

For cyclic deposition processes, the relative process variables described herein relate to the process variables used during a single deposition cycle. For example, when the protective layer is formed by plasma-assisted atomic layer deposition, the RF exposure time and reactant delivery time each correspond to the duration of such operations during a single plasma-assisted ALD cycle (rather than across all cumulative duration of the ALD cycle).

In one example, the first set of deposition conditions is used in the first deposition operation to deposit the first protective film, and the second set of deposition conditions is used in the second deposition operation to deposit the second protective film. At least one deposition parameter in the set of deposition conditions is different, and the deposition parameter is selected from the group consisting of reaction chamber pressure, reactant flow rate, reactant supply time, RF time and RF power. The second protective film can be deposited at a lower pressure than the first protective film. Compared with the first protective film, the second protective film can be deposited at a lower reactant flow rate. The second protective film can be deposited with a shorter reactant supply time than the first protective film. The second protective film can be deposited with a shorter RF time than the first protective film. The second protective film can be deposited at lower RF power than the first protective film. Compared with the first protective film, the second protective film can be deposited at a lower duty cycle. In a specific example, the first protective film is formed by continuous plasma, and the second protective film is formed by pulsed plasma. The second protective film may be deposited after the first protective film. In other examples, the second protective film may be deposited before the first protective film. Of course, the methods herein can use any number of different sets of deposition conditions to deposit any number of protective films. IV. Materials and Parameters for Process Operation A. Substrate

The methods disclosed herein are particularly useful for etching semiconductor substrates having dielectric materials thereon. Exemplary dielectric materials include silicon oxides, silicon nitrides, silicon carbides, oxynitrides, oxycarbides, carbonitrides, doped versions of these materials (eg, doped with boron, phosphorus, etc.), and A stack formed of any combination of these materials. Certain exemplary materials include stoichiometric and non-stoichiometric formulations of SiO ₂ , SiN, SiON, SiOC, SiCN, and the like. As noted above, the etched dielectric material may comprise more than one type/layer of material. In special cases, the dielectric material can be provided in multiple alternating layers of SiN and SiO ₂ or in multiple alternating layers of polysilicon and SiO ₂ . Further details are provided above. The substrate may have a blanket mask layer that defines where the features will be etched. In some cases, the mask layer is Si, which may be between about 500-1500 nm thick. B. Etching process

In various embodiments, the etching process is a reactive ion etching process that involves flowing a chemical etchant into a reaction chamber (typically through a showerhead), generating a plasma from the etchant (for example), and exposing the substrate to to plasma. The plasma dissociates etchant compounds into neutral and ionic species (eg, charged or neutral materials such as CF, CF ₂ and CF ₃ ). In many cases, the plasma is a capacitively coupled plasma, but other types of plasmas may be suitably used. Ions in the plasma are directed towards the wafer and cause the dielectric material to be etched away upon impact.

Exemplary equipment that can be used to perform the etch process includes the 2300® FLEX ^™ product line of reactive ion etch reactors available from Lam Research Corporation of Fremont, CA. Etch reactors of this type are further described in the following US Patents: US Patent No. 8,552,334 and US Patent No. 6,841,943, each of which is incorporated herein by reference.

Various reagent options may be used to etch features into the dielectric material. In some cases, the etch chemistry includes one or more fluorocarbons. In these or other cases, the etch chemistry may include other etchants, such as _NF3 . One or more co-reactants may also be provided. In some cases, oxygen (O ₂ ) is provided as a co-reactant. Oxygen may assist in the modest formation of a protective polymeric sidewall coating (eg, first sidewall coating 304 of FIGS. 3A-3D ).

In some implementations, the etch chemistry includes a combination of fluorocarbons and oxygen. For example, in one example, the etch chemistry includes C ₄ F ₆ , C ₄ F ₈ , N ₂ , CO, CF ₄ , and O ₂ . Other known etch chemistries and non-conventional chemistries can also be used. The flow rate of the fluorocarbon flow may be between about 0-500 seem, such as between about 10-200 seem. When _C4F6 and _C4F8 are _used , the flow rate of _C4F6 can range between about _10-200 seem, and the flow rate of _C4F8 can range between about _10-200 seem _. The flow rate of oxygen may range between about 0-500 seem, such as between about 10-200 seem. The flow rate of nitrogen may range between about 0-500 seem, such as between about 10-200 seem. The flow rate of tetrafluoromethane may range between about 0-500 seem, such as between about 10-200 seem. The carbon monoxide flow rate may range between about 0-500 sccm, such as between about 10-200 sccm. In a reactor volume of about 50 liters, these flow rates are adequate.

In some embodiments, the substrate temperature is between about 30-200 ºC during etching. In some embodiments, the pressure is between about 5-80 mTorr during etching. The ion energy can be quite high, for example between about 1-10 kV. Ion energy is determined by the applied RF power. In each case, dual frequency RF power was used to generate the plasma. Thus, RF power may include a first frequency portion (eg, about 2 MHz) and a second frequency portion (eg, about 60 MHz). Different powers may be provided at each frequency portion. For example, the first frequency portion (eg, about 2 MHz) may be provided at a power of between about 3-24 kW (eg, about 10 kW), and at a power of, for example, between about 0.5-10 kW (eg, about 10 kW) A second frequency portion (eg, about 60 MHz) is provided at a lower power of about 2 kW). In some embodiments, three different frequencies of RF power are used to generate the plasma. For example, a combination of 2 MHz, 27 MHz, and 60 MHz can be used. The power levels for the third frequency portion (eg, about 27 MHz) may be similar to those provided above for the second frequency portion. These power levels assume RF power is delivered to a single 300 mm wafer. For additional substrates and/or substrates of other sizes, the power level can be scaled linearly with the substrate area (thereby maintaining a uniform power density delivered to the substrate). In some embodiments, the RF power applied during etching can be adjusted between a higher power and a lower power at a repetition rate between about 100 - 40,000 Hz.

Each cycle of the etch process etches the dielectric material to some extent. The distance etched during each cycle may be between about 10-500 nm, such as between about 50-200 nm. The total etch depth will depend on the particular application. For some cases (eg, DRAM), the total etch depth can be between about 1.5-2 µm. For other cases (eg, 3D NAND), the total etch depth may be at least about 3 µm, such as at least about 4 µm. In these or other cases, the total etch depth can be about 5 μm or less.

As explained in the discussion of FIGS. 3A-3D , the etch process may result in a first sidewall cladding (eg, first sidewall cladding 304 , which may be a polymer). However, the depth of this sidewall cladding may be limited to an area near the upper portion of the feature and may not extend all the way down into the feature where sidewall protection is also required. Thus, as described herein, a single deposition operation is performed to form a sidewall cladding that covers substantially the entire depth of the etched feature.

In some processes, the operation of depositing a protective sidewall coating (e.g., the second sidewall cladding layer 310 in FIGS. 3C and 3D ) results in the deposition of a first type of film, and the etching operation alters this first type of film. to form the second type of film. Films of the second type may be more etch resistant than films of the first type. For example, a deposition operation may involve the formation of a boron nitride (BN) film, which is then processed into a boron oxide (BO) film during an etch operation. The inclusion of oxygen in the etch chemistry may at least partially drive this change. Oxide boron films are particularly resistant to etching, providing very good protection against overetching of the sidewalls. C. Deposition process

A deposition process is first performed to deposit a protective layer on the sidewalls within the etched features. The deposition process for a particular deposition operation may be tuned based, for example, on the shape of the feature at the time of deposition of the associated protective layer. Because the feature shape changes as the etch of the feature is more complete, the deposition conditions can be changed to conform to the changing feature shape. Furthermore, certain properties of the protective film can be changed for different deposition operations. In one example, the conformality of the protective layer may vary throughout the process of fully etching a feature (eg, an earlier deposited protective layer is formed to a different conformality than a later deposited protective layer). In another example, the thickness, density, and/or composition of the protective layer can be varied throughout the process of fully etching the feature (e.g., an earlier deposited protective layer has a different thickness, density, and/or density than a later deposited protective layer). or composition).

In some cases it may be advantageous for the protective layer to extend deep into the feature. Even in high aspect ratio features, this protective layer should extend deep into the feature. Formation of protective layers deep within high aspect ratio features can be achieved with reactants having relatively low viscosity coefficients. In addition, reaction mechanisms that rely on adsorption-based deposition (e.g., ALD reactions, MLD reactions, and SAM reactions) can promote the formation of protective layers deep within etched features, especially at relatively high pressures, high reactant flow rates, Long reactant supply time, long RF time, high RF power and high RF duty cycle. In these and other cases, it may be advantageous to deposit the protective film in a subconformal manner, meaning that it is deposited relatively thick near the top of the sidewall and relatively thin (or completely absent) near the bottom of the sidewall. ). In some cases, highly conformal or subconformal protective layer deposition may be combined in a single embodiment, eg, as described in relation to Figures 3E-3I.

After the features are partially etched, deposition of the protective layer begins. As described in the discussion of FIG. 2, the deposition operation can be cycled with the etch operation to form additional sidewall protection when the feature is etched deeper into the dielectric material. In some cases, deposition of the protective layer begins when or after the feature is etched to at least 1/3 of its final depth. In certain embodiments, the deposition of the protective layer begins once the features reach an aspect ratio of at least about 2, at least about 5, at least about 10, at least about 15, at least about 20, or at least about 30. In these or other cases, deposition may begin before the features reach an aspect ratio of about 4, about 10, about 15, about 20, about 30, about 40, or about 50. In certain embodiments, deposition begins after the features are at least about 1 µm deep, or at least about 1.5 µm deep (eg, in 3D NAND embodiments with final feature depths of 3-4 µm). In other embodiments, deposition begins after the features are at least about 600 nm deep, or at least about 800 nm deep (eg, in DRAM embodiments where the final feature depth is 1.5-2 μm deep). The best time to start the deposition of the protective layer is immediately before the sidewalls would otherwise be over-etched to form the bow. The exact timing of this event depends on the shape of the feature being etched, the material being etched, the chemicals used to etch and deposit the protective layer, and the process conditions used to etch and deposit the associated materials.

The protective layer formed during the deposition process can have various compositions. As noted, the protective layer may or may not penetrate deep into the etched feature, and is generally relatively resistant to the etch chemistry used to etch the feature. In some cases, the protective layer (or one of the plurality of protective layers) is a ceramic material or an organic polymer. Organic, non-polymeric films can also be used. Exemplary inorganic materials may include, but are not limited to, boron-containing materials such as stoichiometric and non-stoichiometric formulations of boron oxides (B _x O _y ) and boron nitrides (B _x N _y ). Other examples include formulations of ideal stoichiometry and non-ideal stoichiometry of silicon-containing materials such as silicon oxide ( _{Six O y )} , silicon nitride ( _{Six N y )} , silicon carbide ( _Six C _y ), silicon oxynitride ( _{Six O y N y ) ,} silicon oxycarbide ( _Six O _y C _z ), silicon oxysulfide ( _{Six O y S z} ). Other examples include stoichiometric and non-stoichiometric formulations of metal-containing materials, such as metal oxides, metal nitrides, metal carbides, and combinations thereof. Other examples include carbon polymer films.

In some cases, exemplary organic materials can include polyolefins, such as polyfluoroolefins. A specific example is polytetrafluoroethylene. The precursor fragment used to form certain polyfluoroolefins is CF ₂ (which in some cases can be derived from hexafluoropropylene oxide (HFPO)), which has a very low viscosity and thus facilitates access to the etched The depth of the characteristic department. Other examples may include stoichiometric and non-stoichiometric formulations of borocarbides or silicon carbides. In further embodiments, the protective layer formed during the deposition process may be a metal oxide, metal nitride, or metal carbide.

In some embodiments, the protective layer formed during the deposition process is an organic polymer. In some cases, the organic polymer is polyamide or polyester. In a specific instance, the polyamide protective layer is formed from a combination of amide chloride and diamine. In certain other cases, the polyamide protective layer can be formed from a combination of anhydrides and diamines. In certain other embodiments, the polyester protective layer may be formed from a combination of amide chloride and diol. In some embodiments, the polyester protective layer may be formed from a combination of anhydrides and diols. In some implementations, the protective layer can be a metal-containing polymer formed from a combination of an organometallic precursor and a diamine. In certain other implementations, the protective layer can be a metal-containing polymer formed from a combination of an organometallic precursor and a diol. Exemplary anhydrides include, but are not limited to, maleic anhydride. Exemplary metal organic precursors include, but are not limited to, trimethylaluminum. In some specific examples, the protective layer is a polyamide layer formed of a combination of malonyl dichloride and ethylenediamine. In various embodiments, such reactants may be used in MLD processes to form protective layers.

In cases where the protective layer comprises boron, boron-containing reactants may be used. Exemplary boron-containing reactants include, but are not limited to, triisopropyl borate ([(CH ₃ ) ₂ CHO] ₃ B), trimethylboron-d9 (B(CD ₃ ) ₃ ), triphenylborane ( (C ₆ H ₅ ) ₃ B), and para(pentafluorophenyl)borane ((C ₆ F ₅ ) ₃ B). Examples of other boron-containing reactants include boron trichloride (BCl ₃ ), borane (BH ₃ ), diborane (B ₂ H ₆ ), boron trifluoride (BF ₃ ), and trimethyl borate (B (OCH ₃ ) ₃ ). In a specific example, the boron-containing reactant is selected from the group consisting of B ₂ H ₆ , BCl ₃ , BF ₃ , and combinations thereof. Cyclic ALD or ALD-like deposition reactions can deposit boron-containing protective layers. Alternatively, a non-cyclic process (eg, bulk CVD deposition) can deposit the boron-containing protective layer.

Where the protective layer comprises silicon, a silicon-containing reactant may be used. Silicon-containing reactants can be, for example, silanes, halosilanes, or aminosilanes. Silanes contain hydrogen and/or carbon groups, but no halogens. Examples of silanes are silane (SiH ₄ ), disilane (Si ₂ H ₆ ), and organosilanes such as methylsilane, ethylsilane, isopropylsilane, tert-butylsilane, dimethylsilane, diethylsilane Silane, di-tert-butylsilane, allylsilane, secondary butylsilane, tert-hexylsilane, isoamylsilane, tert-butyldisilane, di-tert-butyldisilane, etc. Halosilanes contain at least one halogen group, which may or may not contain hydrogen and/or carbon groups. Examples of halosilanes are iodosilanes, bromosilanes, chlorosilanes, and fluorosilanes. While halosilanes, especially fluorosilanes, may form reactive halide species capable of etching silicon materials, in certain embodiments described herein, silicon-containing reactants are not present when the plasma is ignited. Specific chlorosilanes are tetrachlorosilane (SiCl ₄ ), trichlorosilane (HSiCl ₃ ), dichlorosilane (H ₂ SiCl ₂ ), monochlorosilane (ClSiH ₃ ), chloroallylsilane, chloromethylsilane, Dichloromethylsilane, chlorodimethylsilane, chloroethylsilane, tert-butylchlorosilane, di-tert-butylchlorosilane, chloroisopropylsilane, chlorodibutylsilane, tert-butyldimethylsilane Silane, tert-hexyldimethylchlorosilane, etc. A particular bromosilane is SiBr ₄ . Aminosilanes contain at least one nitrogen atom bonded to a silicon atom, but may also contain hydrogen, oxygen, halogens, and carbon. Examples of aminosilanes are mono-, di-, tri-, and tetraaminosilanes (H ₃ Si(NH ₂ ) ₄ , H ₂ Si(NH ₂ ) ₂ , HSi(NH ₂ ) ₃ and Si(NH ₂ ) ₄ ), and substituted one, two, three, and tetraaminosilanes, such as tert-butylaminosilane, methylaminosilane, tert-butylsilylamine, bis(tert-butylamino)silane (SiH ₂ (NHC(CH ₃ ) ₃ ) ₂ , BTBAS), tert-butyl silylcarbamate, SiH(CH ₃ )-(N(CH ₃ ) ₂ ) ₂ , SiHCl-(N( CH ₃ ) ₂ ) ₂ , (Si(CH ₃ ) ₂ NH) ₃ , etc. A further example of an aminosilane is trisilylamine (N(SiH ₃ ) ₃ ). In a specific example, the silicon-containing reactant is selected from the group consisting of SiCl ₄ , SiH ₄ , SiF ₄ , SiBr ₄ , and combinations thereof. Cyclic ALD or ALD-like deposition reactions can deposit silicon-containing protective layers. Alternatively, a non-cyclic process (eg, bulk CVD deposition) can deposit the silicon-containing protective layer. In some embodiments, a silicon-containing precursor is reacted with an oxidizing agent (eg, nitrous oxide and/or molecular oxygen) to produce a silicon oxide protective coating.

In cases where the protective film contains nitrogen (eg, silicon nitride, silicon oxynitride, or boronitride), nitrogen-containing reactants may be used. Nitrogen-containing reactants containing at least one nitrogen, such as nitrogen, ammonia, hydrazine, amines (for example, amines with carbon), such as methylamine, dimethylamine, ethylamine, isopropylamine Amine, tert-butylamine, di-tert-butylamine, cyclopropylamine, secondary butylamine, cyclobutylamine, isopentylamine, 2-methylbutan-2-amine, trimethylamine, di Isopropylamine, diethylisopropylamine, di-t-butylhydrazine, and aromatic-containing amines (such as aniline, pyridine, and benzylamine). Amines can be primary, secondary, tertiary, or quaternary (eg, tetraalkylammonium compounds). Nitrogen-containing reactants may contain heteroatoms other than nitrogen, for example, hydroxylamine, tert-butoxycarbonylamine, and N-tert-butylhydroxylamine-based nitrogen-containing reactants. Another example is carbon monoxide.

In cases where the protective film contains oxygen (eg, silicon oxide, boron oxide, or metal oxide), an oxygen-containing reactant may be used. Examples of oxygenated reactants include, but are not limited to, oxygen, ozone, nitrous oxide, nitrogen monoxide, nitrogen dioxide, carbon monoxide, carbon dioxide, sulfur oxides, sulfur dioxide, oxygenated hydrocarbons (C _x H _y O _z ) , water, and mixtures thereof. The disclosed precursors are not intended to be limiting.

When the protective coating comprises an organic polymer, a low viscosity precursor is used. Examples of such precursors include precursors that produce _CF2 fragments.

Other reactants known to those of ordinary skill in the art may also be used. For example, where the protective film includes a metal (eg, metal oxide, metal nitride, metal carbide, etc.), a metal-containing reactant may be used. Exemplary metals include, but are not limited to, tungsten, titanium, tantalum, ruthenium, aluminum, iron, and hafnium.

Exemplary aluminum-containing reactants include, but are not limited to, aluminum para(2,2,6,6-tetramethyl-3,5-heptanedionate), triisobutylaluminum, trimethylaluminum, and (Dimethylamide)aluminum(III), etc.

Exemplary tungsten-containing reactants include, but are not limited to, bis(butylcyclopentadienyl)tungsten(IV) diiodide, bis(tert-butylimino)bis(tert-butylamino)tungsten, bis(tert-butylamino)tungsten, (tert-butylimino)bis(dimethylamino)tungsten(VI), bis(cyclopentadienyl)tungsten(IV) dichloride, bis(cyclopentadienyl)tungsten(IV) dihydrogenate ), bis(isopropylcyclopentadienyl) tungsten(IV) dihydrogenate, cyclopentadienyl tungsten tricarbonyl(II), tetracarbonyl(1,5-cyclooctadienyl)tungsten(0) , Tungsten (IV) tricarbonyltriamine, tungsten hexacarbonyl, tungsten hexafluoride, etc.

Exemplary titanium-containing reactants include, but are not limited to, bis(tert-butylcyclopentadienyl)titanium(IV) dichloride, tetrakis(diethylamido)titanium(IV), tetrakis(dimethyl Amido)titanium(IV), tetrakis(ethylmethylamido)titanium(IV), diisopropoxybis(2,2,6,6-tetramethyl-3,5-heptanedionate ) titanium(IV), titanium(IV) isopropoxide, titanium tetrachloride, etc.

Exemplary tantalum-containing reactants include, but are not limited to, tantalum(V)(dimethylamido)tantalum(V), tantalum(V)ethoxide, cerium(diethylamido)(tert-butylamido) Tantalum (V), ginseng (ethylmethylamido) (tert-butylimide) tantalum (V), etc.

Exemplary ruthenium-containing reactants include, but are not limited to, bis(cyclopentadienyl)ruthenium(II), bis(ethylcyclopentadienyl)ruthenium(II), bis(pentamethylcyclopentadienyl) ) ruthenium(II), triruthenium dodecacarbonyl, etc.

Exemplary iron-containing reactants include, but are not limited to, [1,1'-bis(diphenylphosphino)ferrocene]molybdenum(0)tetracarbonyl, bis(pentamethylcyclopentadienyl)iron ( II), 1,1'-diethylferrocene, iron pentacarbonyl (0), reference (2,2,6,6-tetramethyl-3,5-heptanedionate) iron (III), Wait.

Exemplary hafnium-containing reactants include, but are not limited to, bis(tert-butylcyclopentadienyl)dimethylhafnium(IV), bis(methyl-η5-cyclopentadienyl)dimethylhafnium, bis (Methyl-η5-cyclopentadienyl)methoxymethyl hafnium, bis(trimethylsilyl)amido hafnium(IV) chloride, dimethyl bis(cyclopentadienyl) hafnium( IV), hafnium(IV) tert-butoxide, hafnium isopropoxide isopropanol, tetrakis(diethylamido)hafnium(IV), tetrakis(dimethylamido)hafnium(IV), tetrakis(ethylamido)hafnium(IV), methylamido) hafnium(IV), etc.

Similarly, where the protective film comprises carbon, carbon-containing reactants may be used.

A few specific examples of reactant combinations are provided below, but these examples are not intended to be limiting. In one example, a boron-containing precursor film is formed by adsorbing a boron-containing reactant (such as B ₂ H ₆ , BCl ₃ or BF ₃ ) onto the substrate surface. The precursor film is converted into a protective film by exposure to an oxidizing or nitridating plasma such as a plasma generated from _O2 , _N2 , _NH3 , _N2O , _H2 , and combinations thereof.

In a specific example, _BCl3 is adsorbed to form a boron-containing precursor layer, and a plasma is generated from the combination of _N2 and _H2 , which drives the formation of the boron nitride protective film. The reaction can occur via a cyclic process such as ALD. In a similar example, the reaction can occur via a continuous process, such as CVD, where _BCl3 , _N2 , and _H2 are all supplied simultaneously when the substrate is exposed to the plasma. After the boronitride film is formed, the substrate may be further etched. _The etch chemistry may include oxygen (along with other etch chemistries, eg, fluorocarbons such as _C4F6 and/or _C4F8 ), which may react with the _boronitride film to form boron oxide. Boron oxides are particularly resistant to fluorocarbon-based etch chemistries, providing very good protection against overetching of sidewalls.

In another example, silicon-containing species (eg, SiCl ₄ , SiH ₄ , SiF ₄ , SiBr ₄ , etc.) are adsorbed on the substrate surface to form a silicon-containing precursor film. Silicon-containing precursor films can be converted to silicon oxides or silicon nitrides by exposure to plasmas generated by _O2 , _N2 , _NH3 , _N2O , _H2 , and combinations thereof. If the dielectric material to be etched comprises silicon oxide, it is preferred to form a protective layer such as silicon nitride (and vice versa).

As noted above, the precursor (or precursors) used to form one or more protective layers may have a relatively low viscosity, allowing the precursors to penetrate deep into etched features to form highly Conformal protective film. In some cases, during formation of at least one of the protective layers, the viscosity coefficient of the precursor (under relevant deposition conditions) may be about 0.05 or less, eg, about 0.001 or less. In cases where it is desired to form a sub-conformal protective film, a higher viscosity precursor (or precursors) may be used.

The reaction mechanism can be cyclic (eg, ALD) or continuous (eg, CVD). Any method that results in the formation of a protective sidewall film at desired sidewall locations may be used. As mentioned, ALD, MLD and SAM reactions may be particularly suitable for this purpose due to their tunable conformal and self-limiting properties. Plasma-assisted atomic layer deposition may be particularly suitable for adjustable conformality. However, other types of reactions can be used as long as a film can be formed at the desired location to protect the sidewalls in etched features (especially where arcs are formed, or possibly arcs if no protective layer is provided). area). The basic operations for ALD and CVD reactions are described above with respect to operation 205 of FIG. 2 . Briefly, a plasma-assisted ALD reaction involves cyclically performing the following operations: (a) delivery of a first reactant to form an adsorbed precursor layer, (b) optional purge operation to remove delivery of the first reactant, (c) delivery of the second reactant, often in the form of a plasma, (d) optional purge to remove excess reactant, and (e) repeating (a) - ( d) until the film reaches the desired thickness. Because the reactants are provided at different times and the reactions are surface reactions, the membrane is adsorption limited. This results in the formation of a very conformal film that can cover the entire surface of the recessed feature. In contrast, plasma assisted CVD reactions involve the continuous delivery of reactants to the substrate while exposing the substrate to the plasma. The CVD reaction is a gas phase reaction that deposits the reaction product on the substrate surface. As noted above, MLD and SAM reactions are further described in certain patents or patent applications, which are hereby incorporated by reference. Briefly, the MLD reaction uses an ALD cycle involving two half-reactions to deposit thin films of organic polymers. The SAM reaction uses a single precursor with a head group and a tail group to deposit adsorption-limited thin films of organic materials.

In certain embodiments, the following reaction conditions may be used, wherein the deposition reaction for forming at least one protective film occurs by an ALD method. The substrate temperature may be maintained between about 0-500°C, such as between about 20-200°C. Pressure can be maintained as low as about 100 or 200 mTorr and as high as about 1, 2, or 3 Torr. Ion energies can be relatively low, eg, below about 1 kV. The RF frequency used to generate the plasma may be about 60 MHz, although other frequencies may also be used. RF power can be several hundred watts, such as about 500 W or less, about 400 W or less, or about 300 W or less (assuming power is delivered to a single 300 mm wafer, power is based on additional or different sized substrates substrate area scales linearly). The adsorbed reactants may be delivered at a flow rate between about 50-1000 seem for a duration between about 0.5-20 seconds during each ALD cycle. The first purge may have a duration between about 0-60 seconds. The substrate may be exposed to the plasma for a duration between about 0.5-120 seconds at a flow rate of the reactants (excluding any inert gas provided with the reactants) between about 50-1000 sccm. During plasma exposure, the flow rate of hydrogen may be between about 0-1000 sccm. The RF post purge may have a duration between about 0-60 seconds.

In certain embodiments, the following reaction conditions may be used, wherein the deposition reaction for forming at least one protective film occurs by a CVD method. The substrate temperature may be maintained between about 0-500°C, such as between about 20-200°C. The pressure can be maintained between about 100-3000 mT. The RF frequency used to generate the plasma can be 2-60 MHz. The RF power used to generate the plasma may be between about 50-2000 W, such as between about 100-800 W (assuming a single 300 mm substrate). The duration of reactant delivery and plasma exposure can be between about 1-180 seconds. Flow rates depend on the specific reactants. In one example, _BCl3 , _N2 , and _H2 are provided, wherein _BCl3 is provided at a flow rate between about 50-1000 sccm, _N2 is provided at a flow rate between about 50-1000 sccm, and _H2 is provided at a flow rate between about 50-1000 sccm. ALD and CVD reaction conditions are provided as a guide and are not intended to be limiting. v. equipment

The methods described herein can be performed by any suitable device or combination of devices. Suitable equipment includes hardware for performing process operations, and a system controller having instructions for controlling process operations in accordance with the present invention. For example, in some embodiments, hardware may include one or more processing stations included in a processing tool. One processing station may be an etching station, while the other processing station may be a deposition station. In another embodiment, etching and deposition occur in a single station/chamber.

4A-4C illustrate an embodiment of an adjustable-gap capacitively coupled confinement RF plasma reactor 400 that may be used to perform the etching operations described herein. As shown, the vacuum chamber 402 includes a chamber cover 404 surrounding an interior space containing a lower electrode 406 . In the upper part of the chamber 402, the upper electrode 408 is separated from the lower electrode 406 in the vertical direction. The planar surfaces of the upper and lower electrodes 408, 406 are substantially parallel and orthogonal to the vertical direction between the electrodes. Preferably, the upper and lower electrodes 408, 406 are circular and coaxial with respect to a vertical axis. The lower surface of the upper electrode 408 is facing the upper surface of the lower electrode 406 . The spaced and facing electrode surfaces define an adjustable gap 410 therebetween. During operation, RF power is supplied to the bottom electrode 406 by an RF power supplier (matcher) 420 . RF power is supplied to the lower electrode 406 via RF supply conduit 422 , RF strap 424 and RF power member 426 . A ground shield 436 may surround the RF power member 426 to provide a more uniform RF field to the bottom electrode 406 . A wafer is inserted through the wafer port 482 and supported in the gap 410 above the bottom electrode 406 for processing, process gases are supplied to the gap 410 and excited into a plasma state by RF power, as described in commonly owned U.S. Patent No. 7,732,728 No., the entire contents of which are incorporated herein by reference. The upper electrode 408 can be powered or grounded.

In the embodiment shown in FIGS. 4A-4C , the lower electrode 406 is supported on a lower electrode support plate 416 . An insulating ring 414 interposed between the lower electrode 406 and the lower electrode support plate 416 isolates the lower electrode 406 from the support plate 416 .

RF bias housing 430 supports lower electrode 406 on RF bias housing bowl 432 . The bowl 432 is connected to a conduit support plate 438 through an opening in the chamber wall 418 by an arm 434 of the RF bias housing 430 . In a preferred embodiment, the RF bias housing bowl 432 and the RF bias housing arm 434 are integrally formed as one piece, however, the arm 434 and bowl 432 could also be two parts that are bolted or joined together. independent components.

RF bias housing arm 434 includes one or more hollow passages for routing RF power and utilities (e.g., gas coolant, liquid coolant, RF energy, cables for lift pin control, power monitoring, and actuation signals) The space on the back side of the lower electrode 406 is conveyed from outside the vacuum chamber 402 to inside the vacuum chamber 402 . The RF supply conduit 422 is insulated from the RF bias housing arm 434 which provides a return path for the RF power to the RF power supply 420 . Facility conduit 440 provides access to facility components. Further details of the facility components are described in US Patent Nos. 5,948,704 and 7,732,728 and will not be shown here for brevity of illustration. Gap 410 is preferably surrounded by a confinement ring assembly or retainer (not shown), details of which can be found in commonly owned US Patent No. 7,740,736, which is incorporated herein by reference. The interior of the vacuum chamber 402 is maintained at a low pressure by being connected to a vacuum pump through a vacuum inlet 480 .

Conduit support plate 438 is attached to actuation mechanism 442 . Details of the actuation mechanism are described in commonly-owned US Patent No. 7,732,728, which is incorporated herein above. An actuation mechanism 442 such as a servo mechanical motor, stepper motor or the like is attached to a vertical linear bearing 444 such as by a helical gear 446 such as a ball screw and a motor for turning the ball screw. During the operation of adjusting the size of gap 410 , actuation mechanism 442 moves along vertical linear bearing 444 . Figure 4A illustrates the configuration when the actuator mechanism 442 is in a high position on the linear bearing 444, which results in a small gap 410a. FIG. 4B illustrates the configuration when the actuator mechanism 442 is in an intermediate position on the linear bearing 444 . As shown, the lower electrode 406, RF bias housing 430, conduit support plate 438, and RF power supply 420 are all moved lower relative to the chamber housing 404 and upper electrode 408, resulting in a moderately sized gap 410b.

Figure 4C illustrates the large gap 410c when the actuator mechanism 442 is in the low position on the linear bearing. Preferably, the upper and lower electrodes 408, 406 remain coaxial during gap adjustment, and the opposing surfaces of the upper and lower electrodes remain parallel across the gap.

For example, in order to maintain uniform etching across large diameter substrates (such as 300 mm wafers or flat panel displays), this embodiment allows the gap 410 between the lower and upper electrodes 406, 408 in the CCP chamber 402 to be processed in a multi-step process recipe. (BARC, HARC, and STRIP, etc.) period can be adjusted. Specifically, this chamber is about a mechanical arrangement that allows the linear movement required to provide an adjustable gap between the lower and upper electrodes 406,408.

4A illustrates a laterally deflected bellow 450 that is sealed proximally to catheter support plate 438 and distally to stepped flange 428 of chamber wall 418 . The inner diameter of the stepped flange defines an opening 412 in the chamber wall 418 through which the RF bias housing arm 434 passes. The distal end of bellows 450 is clamped by clamping ring 452 .

The laterally deflected bellows 450 provide a vacuum seal while allowing vertical movement of the RF bias housing 430 , conduit support plate 438 and actuation mechanism 442 . The RF bias housing 430, conduit support plate 438, and actuation mechanism 442 can be considered a cantilever assembly. Preferably, the RF power supply 420 moves with the boom assembly and is attachable to the conduit support plate 438 . Figure 4B shows the bellows 450 in a neutral position when the boom assembly is tethered in the neutral position. Figure 4C shows the bellows 450 deflecting laterally when the boom assembly is in the low position.

Labyrinth packing 448 provides a particle barrier between bellows 450 and the interior of plasma processing chamber enclosure 404 . The fixed shield 456 is non-removably attached to the inner inner wall of the chamber housing 404 at the chamber wall 418 so as to provide a labyrinth 460 (slit) in which the movable shield 458 is perpendicular ground movement to accommodate the vertical movement of the cantilever assembly. In all vertical positions of the lower electrode 406, the outer portion of the movable shield 458 remains in the slot.

In the illustrated embodiment, the labyrinth packing 448 includes a fixed shield 456 attached to the inner surface of the chamber wall 418 at the periphery of the opening 412 in the chamber wall 418, defining the labyrinth. groove 460 . A movable shield plate 458 is attached and extends radially from the RF bias housing arm 434 , where the arm 434 passes through the opening 412 in the chamber wall plate 418 . The movable shield plate 458 extends into the labyrinth channel 460 while being spaced from the fixed shield 456 by a first gap and from the interior surface of the chamber wall 418 by a second gap, thereby allowing the cantilever assembly to move vertically . The labyrinth seal 448 blocks the migration of particles exfoliated from the bellows 450 into the vacuum chamber interior 405 and prevents free radicals from the process gas plasma from migrating to the bellows 450 where they may form deposits that subsequently exfoliate.

Figure 4A shows the movable shield plate 458 is in a higher position in the labyrinth channel 460 on the RF bias housing arm 434 when the cantilever assembly is in the high position (small gap 410a). Figure 4C shows the movable shield plate 458 is in a lower position in the labyrinth channel 460 on the RF bias housing arm 434 when the cantilever assembly is in the lower position (large gap 410c). Figure 4B shows the movable shield 458 in a neutral or neutral position within the labyrinth 460 when the boom assembly is in the neutral position (medium gap 410b). While the labyrinth packing 448 is shown as being symmetrical with respect to the RF bias housing arm 434 , in other embodiments the labyrinth packing 448 may be asymmetrical with respect to the RF biasing arm 434 .

Figure 5 provides a simplified block diagram depicting the various reactor components used to practice the deposition methods described herein. As shown, the reactor 500 includes a process chamber 524 that surrounds the other components of the reactor and is used to contain the plasma generated by a capacitive discharge system that includes a heater connected to ground. Block 520 incorporates the showerhead 514 in operation. High frequency (HF) radio frequency (RF) generator 504 and low frequency (LF) RF generator 502 may be connected to matching network 506 and showerhead 514 . The power and frequency supplied by the matching network 506 may be sufficient to generate a plasma from the process gases supplied to the process chamber 524 . For example, matching network 506 may provide 50 W to 500 W of HFRF power. In some examples, the matching network 506 can provide 100 W to 5000 W of HFRF power and 100 W to 5000 W of LFRF power total energy. In a typical process, the HFRF component can typically be between 5 MHz and 60 MHz, eg 13.56 MHz. In operation with LF components, the LF components may be from about 100 kHz to 2 MHz, eg 430 kHz.

Within the reactor, a wafer pedestal 518 may support a substrate 516 . Wafer base 518 may include chucks, forks, or lift pins (not shown) to hold and transport substrates during and between deposition and/or plasma processing reactions. The chuck can be an electrostatic chuck, a mechanical chuck, or various other types of chucks that are available for industrial use and/or for research.

Various process gases may be introduced through inlet 512 . A plurality of source gas lines 510 are connected to manifold 508 . The gases may or may not be premixed. Appropriate valve adjustment and mass flow control mechanisms can be used to ensure that the correct process gases are delivered during the deposition and plasma treatment stages of the process. Where the chemical precursor is delivered in liquid form, a liquid flow control mechanism may be used. Such liquids can then be vaporized before reaching the deposition chamber and mixed with process gases during delivery in a manifold heated above the vaporization point of the chemical precursors supplied in liquid form.

Process gases may exit chamber 524 through outlet 522 . A vacuum pump 540 (e.g., a one- or two-stage mechanical dry pump and/or a turbomolecular pump) can be used to pump process gases out of the process chamber 524 and use a closed-loop controlled flow restriction device (e.g., a throttle or pendulum valve) to An appropriate low pressure within the process chamber 524 is maintained.

As noted above, the deposition techniques discussed herein can be implemented on multi-station or single-station tools. In a particular implementation, a 300 mm Lam Vector ^™ tool with a 4-station deposition architecture, or a 200 mm Sequel ^™ tool with a 6-station deposition architecture may be used. In some implementations, tools for processing 450 mm wafers may be used. In various implementations, the wafer can be indexed after each deposition and/or post-deposition plasma treatment, or after the etch operation if the etch chamber or station is also part of the same tool, or after the indexing Wafers can be previously deposited and processed at a single station.

In some embodiments, an apparatus may be provided for implementing the techniques described herein. Suitable equipment may include hardware for performing various process operations, as well as a system controller 530 having instructions for controlling the process operations in accordance with disclosed embodiments. System controller 530 typically includes one or more memory devices and one or more processors that communicate with and execute instructions from various process control devices (e.g., valves, RF generators, wafer handling systems, etc.) to causing the device to implement techniques in accordance with the disclosed embodiments. A machine-readable medium containing instructions for controlling process operations in accordance with the present disclosure may be coupled to system controller 530 . System controller 530 can be in communication with various hardware devices (eg, mass flow controllers, valves, RF generators, vacuum pumps, etc.) to assist in the control of various process parameters associated with the deposition operations described herein.

In some embodiments, system controller 530 may control all activities of reactor 500 . The system controller 530 can execute system control software, which is stored in the mass storage device, loaded into the memory device, and executed on the processor. The system control software may include instructions to control the timing of gas flow, wafer movement, RF generator activation, etc., as well as mixing of gases, chamber and/or station pressure, chamber and/or station temperature, Wafer temperature, target power level, RF power level, substrate mount, chuck and/or holder position, and other parameters for a particular process being performed by reactor apparatus 500 . System control software may be configured in any suitable manner. For example, various process tool component subroutines or control objects can be written to control the operation of the process tool components needed to perform the various process tool processes. System control software can be coded in any suitable computer readable programming language.

System controller 530 may generally include one or more memory devices, and one or more processors for executing instructions such that a device will implement techniques in accordance with this disclosure. A machine-readable medium containing instructions to control process operations according to disclosed embodiments may be coupled to system controller 530 .

One or more processing stations may be included in a multi-station processing tool. 6 shows a schematic diagram of an embodiment of a multi-station processing tool 600 having an inbound load lock chamber 602 and an outbound load lock chamber 604, either or both of which may contain Remote plasma source. Robot arm 606 at atmospheric pressure is used to move wafers from cassettes (loaded through cassette 608 ) into inbound load lock chamber 602 via atmospheric port 610 . The wafer is placed on the pedestal 612 in the inbound load lock chamber 602 by the robotic arm 606, the atmospheric port 610 is closed, and the load lock chamber is evacuated. Where the inbound load lock chamber 602 includes a remote plasma source, the wafers may be exposed to remote plasma processing in the load lock chamber before being introduced into the process chamber 614 . In addition, the wafer may also be heated in the inbound load lock chamber 602, for example, to remove moisture and sorbed gases. Next, the chamber transfer port 616 to the process chamber 614 is opened and another robotic arm (not shown) places the wafer in the reactor and on the base of the first station (shown in the reactor) for processing . While the illustrated embodiment includes a load lock chamber, it should be understood that in some embodiments wafers may enter directly into a processing station.

In the embodiment shown in FIG. 6 , the process chamber 614 is depicted as including four processing stations, numbered 1-4. Each station has a heated base (shown at 618 of station 1), and a gas line inlet. It should be appreciated that in some embodiments, each processing station may have different or multiple purposes. For example, each of processing stations 1-4 may be a chamber for performing one or more of ALD, CVD, CFD, or etching (any of which may be plasma assisted). In one embodiment, at least one of the processing stations is a deposition station with a reaction chamber as shown in Figure 5, and at least one of the other processing stations is a deposition station with a reaction chamber as shown in Figures 4A-4C The etching station. Although the depicted process chamber 614 includes four stations, it should be understood that a process chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, a process chamber may have five or more stations, while in other embodiments, a process chamber may have three or fewer stations.

FIG. 6 also depicts an embodiment of a wafer handling system 609 for transferring wafers within a process chamber 614 . In some embodiments, the wafer handling system 609 may transfer wafers between various processing stations and/or between a processing station and a load lock. It should be appreciated that any suitable wafer handling system may be employed. Non-limiting examples include wafer carousels and wafer handling robots. FIG. 6 also depicts an embodiment of a system controller 650 for controlling process conditions and hardware status of the processing tool 600 . System controller 650 may include one or more memory devices 656 , one or more mass storage devices 654 , and one or more processors 652 . The processor 652 may include a CPU or computer, analog and/or digital input/output connectors, a stepper motor controller board, and the like.

In some implementations, the system controller is part of the system, which may be part of the above examples. Such systems may include semiconductor processing equipment including a processing tool or tools, a chamber or chambers, a platform or platforms for processing, and/or specific processing components (wafer base, gas flow system, etc.). These systems can be integrated with electronics used to control the operation of semiconductor wafers or substrates before, during, and after their processing. Electronic components may be referred to as "controllers," which control various components or subsections of a system or systems. Depending on the type of system and/or process requirements, the controller can be programmed to control any of the processes disclosed herein, including delivery of process gases, temperature settings (e.g., heating and/or cooling), pressure settings, vacuum settings, Power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid transfer settings, positioning and operation settings, wafer transfers into and out of tools connected to or interfaced with specific systems and Other transfer means and/or load lock chambers.

In a broad sense, a controller can be defined as a variety of integrated circuits, logic, memory, and / or electronic components of software. An integrated circuit may include a chip in the form of firmware storing program instructions, a digital signal processor (DSP), a chip defined as an application-specific integrated circuit (ASIC), and/or one or more microprocessors, or executing program Instructions (eg, software) of the microcontroller. Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operating parameters for performing specific processes on or to the semiconductor wafer or to the system. In some embodiments, the operating parameters may be part of a recipe defined by a process engineer for one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and One or more process operations are completed during the manufacture of the die and/or the die.

In some implementations, the controller can be part of or coupled to a computer that is integrated with the system, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the "cloud," or all or part of the factory's mainframe computer system that enables remote control of wafer processing. The computer enables remote control of the system to monitor the current process of the manufacturing operation, check the history of past manufacturing operations, check the trend or performance evaluation of multiple manufacturing operations, change the parameters of the current process, set the current process Subsequent process operations, or start a new process. In some examples, a remote computer (eg, a server) can provide the recipe to the system via a network, which can include a local area network or the Internet. The remote computer may include a user interface that enables the input or programming of parameters and/or settings that are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data specifying parameters for each of the process operations to be performed during one or more operations. It should be appreciated that the parameters may be specific to the type of process to be performed, and the type of tool with which the controller interfaces or controls. Thus, as noted above, the controller may be decentralized, eg, by including one or more independent controllers networked together and working toward a common goal, such as the process and control described herein. An example of a distributed controller for such purposes would be one or more integrated circuits in a chamber that are connected to one or more integrated circuits located remotely (e.g., at platform level or as a remote computer part of) one or more integrated circuits in communication to control the processing in the chamber.

Without limitation, exemplary systems may include plasma etch chambers or modules, deposition chambers or modules, spin cleaning chambers or modules, metal plating chambers or modules, cleaning chambers or modules, ramp Edge etching chamber or module, physical vapor deposition (PVD) chamber or module, chemical vapor deposition (CVD) chamber or module, atomic layer deposition (ALD) chamber or module, molecular layer deposition ( MLD) chamber or module, self-assembled monolayer (SAM) chamber or module, atomic layer etching (ALE) chamber or module, ion implantation chamber or module, orbital chamber or module, and Any other semiconductor processing system relating to or used in the processing and/or manufacturing of semiconductor wafers.

As noted above, depending on the process operations to be performed by the tool, the controller may communicate with one or more of the following: other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, Proximity to tools, tools located throughout the fab, host computer, another controller, or material transfer tools used to move wafer containers into and out of tool locations and/or load ports in a semiconductor fabrication facility.

In some embodiments, the controller has instructions to carry out the operations shown and described with respect to FIG. 2 . For example, the controller may have instructions to cyclically: (a) perform an etch operation to partially etch features on the substrate, and (b) deposit a protective sidewall coating in the etched features without substantially etch the substrate. Instructions are available for carrying out these processes using the disclosed reaction conditions. In some cases, the instructions for depositing the first protective film are different than the instructions for depositing the second protective film. Instructions may vary in reaction chamber pressure, reactant delivery rate, reactant supply time, RF time, RF power, RF duty cycle, and the like. Differences in the instructions for depositing the first protective layer and the second protective layer may result in the first and second protective layers being formed to have different properties, such as conformality, thickness, density, and/or composition. In some implementations, the instructions may also relate to transferring the substrate between the etch and deposition chambers.

Returning to the embodiment of FIG. 6 , in some embodiments, the system controller 650 controls all activities of the processing tool 600 . System controller 650 executes system control software 658 that is stored in mass storage device 654 , loaded into memory device 656 , and executed on processor 652 . Alternatively, the control logic may be hard-coded into the system controller 650 . For these purposes, application specific integrated circuits, programmable logic devices (eg, field programmable gate arrays, or FPGAs), and the like may be used. In the following discussion, wherever "software" or "coding" is used, functionally comparable hard-coded logic may be used as appropriate. System control software 658 may include instructions to control timing, mixing of gases, chamber and/or station pressure, chamber and/or station temperature, wafer temperature, target power level, RF power level, RF exposure time, substrate mount, chuck and/or holder positions, and other parameters of the particular process being performed by processing tool 600 . System control software 658 may be configured in any suitable manner. For example, various process tool component subroutines or control objects can be written to control the operation of the process tool components needed to perform the various process tool processes. System control software 658 can be encoded in any suitable computer readable programming language.

In some embodiments, the system control software 658 may include input/output control (IOC) sequence commands to control the various parameters described above. For example, each stage of the CFD process may include one or more instructions executed by the system controller 650 . Instructions for setting process conditions of the ALD process stage may be included in the corresponding ALD recipe stage. In some embodiments, the ALD recipe stages may be sequenced such that all instructions for an ALD process stage are executed concurrently with that process stage.

In some embodiments, other computer software and/or programs stored on mass storage device 654 and/or memory device 656 associated with system controller 650 may be employed. Examples of programs or program segments used for this purpose include substrate positioning programs, process gas control programs, pressure control programs, heater control programs, and plasma control programs.

The substrate positioning program may include code for process tool components used to load substrates onto pedestal 618 and to control the spacing between substrates and other parts of process tool 600 .

A process gas control program may include code to control gas composition and flow rates, and optionally, code to flow gases into one or more process stations to stabilize process station pressures prior to deposition. In some embodiments, the controller includes instructions for depositing a nanolaminate protective layer on the core layer and instructions for depositing a conformal layer on the protective layer.

The pressure control program may include code to control the pressure within the processing station by adjusting, for example, a throttle valve in the exhaust system of the processing station, the flow of gas into the processing station, and the like. In some embodiments, the controller includes instructions for depositing a nanolaminate protective layer on the core layer and instructions for depositing a conformal layer on the protective layer.

The heater control program may include code to control the electrical current to the heating unit used to heat the substrate. Alternatively, the heater control program can control the delivery of a heat transfer gas (eg, helium) to the substrate. In some implementations, the controller includes instructions to deposit the nanolaminate protective layer at a first temperature, and instructions to deposit a conformal layer on the protective layer at a second temperature, wherein the second temperature is higher than at the first temperature.

According to embodiments herein, a plasma control program may include code to set RF power levels and exposure times in one or more processing stations. In some embodiments, the controller includes instructions to deposit the nanostack protective layer at a first RF power level and RF duration, and to deposit Instructions for conformal layer over protective layer. The second RF power level and/or the second RF duration may be higher/longer than the first RF power level/duration.

In some embodiments, there may be a user interface associated with the system controller 650 . User interfaces may include display screens, graphical software displays of equipment and/or process conditions, and user input devices such as pointing devices, keyboards, touch screens, microphones, and the like.

In some embodiments, the parameters adjusted by the system controller 650 may be related to process conditions. Non-limiting examples include process gas composition and flow rate, temperature, pressure, plasma conditions (eg, RF bias power level and exposure time), and the like. These parameters may be provided to the user in the form of a recipe, which may be entered using the user interface.

Through analog and/or digital input connections of the system controller 650, signals for monitoring the process can be provided from various process tool sensors. Signals used to control the process can be output on analog and digital output connections of the processing tool 600 . Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (eg, manometers), thermocouples, and the like. Appropriately programmed feedback and control algorithms can be used with data from these sensors to maintain process conditions.

The system controller 650 may provide program instructions for implementing the deposition process described above. Program instructions can control various process parameters, such as DC power level, RF bias power level, pressure, temperature, and so on. According to various embodiments described herein, instructions may control parameters to operate in situ deposition of film stacks.

Typically, the system controller will include one or more memory devices, and one or more processors for executing instructions such that the apparatus will implement methods according to the disclosed embodiments. A machine-readable, non-transitory medium may be coupled to the system controller, the machine-readable, non-transitory medium containing instructions for controlling process operations according to disclosed embodiments.

The various hardware and method embodiments described above may be used in conjunction with lithographic patterning tools or processes, for example, in the fabrication or production of semiconductor devices, displays, LEDs, photovoltaic panels, and the like. Typically, but not necessarily, such tools/processes will be used or performed together in a common manufacturing facility.

FIG. 7 depicts a semiconductor processing cluster architecture with various modules interfaced with a vacuum transfer module 738 (VTM). The configuration of transfer modules that "transfer" substrates among multiple storage devices and process modules may be referred to as a "cluster tool architecture" system. A plenum 730 (also known as a load lock or transfer module) is shown in a VTM 738 with four process modules 720a-720d that can be individually optimized to perform various manufacturing processes. For example, process modules 720a-720d may be implemented to perform substrate etching, deposition, ion implantation, substrate cleaning, sputtering, and/or other semiconductor processing, as well as laser metrology and other defect detection and defect identification methods. One or more of the process modules (any of 720a-720d) may be implemented as disclosed herein, i.e., for etching recessed features into the substrate, depositing a protective film over the recessed features sidewalls, and other suitable functions according to the disclosed embodiments. The plenum 730 and process modules 720a-720d may be referred to as "stations." Each station has a face 736 that interfaces the station with a VTM 738 . In this section, sensors 1-18 are used to detect the passage of a substrate 726 as it moves between individual stations.

Robotic arm 722 transfers substrates between stations. In one implementation, the robotic arm may have one arm, and in another implementation, the robotic arm may have two arms, where each arm has an end effector 724 for picking up substrates for transfer. In the atmospheric transfer module (ATM) 740, the front robot arm 732 can be used to transfer the substrate from the cassette in the load port module (LPM) 742 or the front opening wafer transfer box (Front Opening Unified Pod, FOUP) 734 to Gas chamber 730 . Module center 728 inside process modules 720a-720d may be a location for placing substrates. Aligners 744 in ATM 740 may be used to align substrates.

In an exemplary process method, the substrate is placed in one of the FOUPs 734 in the LPM 742 . The front end robot 732 transfers the substrate from the FOUP 734 to the aligner 744, which allows the substrate 726 to be properly centered before being etched, or deposited thereon, or otherwise processed. After being aligned, the front end robot 732 moves the substrate into the plenum 730 . Because the plenum module has the ability to match the environment between the ATM and the VTM, the substrate can move between the two pressure environments without damage. The robot arm 722 moves the substrate from the plenum 730 via the VTM 738 into one of the process modules 720a-720d, such as the process module 720a. To achieve this substrate movement, the robotic arm 722 uses end effectors 724 on each of its arms. In process module 720a, the substrate is etched as described herein to form partially etched features. Robotic arm 722 then moves the substrate out of process module 720a, into VTM 738, and then into a different process module 720b. In process module 720b, a protective film is deposited on the sidewalls of the partially etched features. Robotic arm 722 then moves the substrate out of process module 720b, into VTM 738, and into process module 720a, where the partially etched features are further etched. Etch/deposition can be repeated until the feature is fully etched.

It should be noted that the computer controlling the movement of the substrates may be inside the cluster, or may be located outside the cluster in the manufacturing site, or in a remote location connected to the cluster via a network.

Photolithographic patterning of films typically involves some or all of the following operations, each provided in several possible tools: (1) on a workpiece (e.g., a substrate having a silicon nitride film formed thereon) Coating of photoresist using spin-coating or spraying tools; (2) curing of photoresist using a hot plate or oven or other suitable curing tool; (3) tooling (e.g., wafer stepper) exposing the photoresist to visible or UV light or x-ray light; (4) developing the photoresist so that it can be selectively removed and thus patterned using a tool such as a wet clean station or a spray developer ; (5) transfer the photoresist pattern to the underlying film or workpiece using dry or plasma assisted etching tools; and (6) remove the photoresist using tools such as RF or microwave plasma photoresist strippers. In some embodiments, an ashable hard mask layer, such as an amorphous carbon layer, and another suitable hard mask, such as an anti-reflective layer, may be deposited prior to coating the photoresist. Experimental and Simulation Results

8A-8C depict conformal (FIG. 8A), super-conformal (FIG. 8B) and sub-conformal (FIG. 8C) deposition regimes in high aspect ratio cylinders. Each figure shows the protective film formed on the sidewall of the feature, in this example, the feature is formed in alternating layers of oxide and polysilicon, and has a layer of silicon nitride (SiN) and an ashable hard Mask (AHM) on top. 8D-8F present graphs depicting the thickness of the protective film at different feature depths, where the deposition is conformal (FIG. 8D, corresponding to the example of FIG. 8A), super-conformal (FIG. 8E, corresponding to the example of FIG. 8A ). embodiment of FIG. 8B ), or subconformal (FIG. 8F , corresponding to the embodiment of FIG. 8C ). Figures 8A-8F are not about experimental or simulation results, but generally depict different deposition states. The conformal state is sometimes referred to as "highly conformal," meaning that the film thickness is relatively uniform throughout the feature. For ultra-conformal films, the deposition of the film is relatively thick near the bottom sidewall of the feature and relatively thin near the top sidewall of the feature. In contrast, for a sub-conformal film, the deposition of the film is relatively thick near the top sidewall of the feature and relatively thin (or absent at all) near the bottom sidewall of the feature.

Certain embodiments herein may use a combination of conformal, ultra-conformal, and/or sub-conformal deposition on the protective layer. In one example, at least one protective film is highly conformal and at least one other protective film is less conformal. In another example, at least one protective film is subconformal and at least one other protective film is even more subconformal (e.g., extending less deeply into the feature, such as the instant feature depth percentage).

FIG. 9A depicts simulation results showing the average critical dimension of etched features versus etch depth according to a subconformal deposition state. The upper line shows the average CD of the features after the etch process, before depositing a protective film on the feature sidewalls. The lower line shows the average critical dimension of the features after depositing the protective film on the feature sidewalls. Clearly, the protective film is deposited thicker near the top of the feature (where the CD is greatest before deposition) and thinner near the bottom of the feature. The thickness of the protective film corresponds to the difference between the average CD before deposition of the protective film and the average CD after deposition. For example, in the region under the mask layer, near the top of the stack (at the arcuate region about 200 nm deep), the protective film is about 5 nm thick. Deeper into the features (eg, at an etch depth of about 600 nm), the protective film is thinner, with an average thickness of about 3.5 nm. Near the bottom of the features (eg, at an etch depth of about 1200 nm), the protective film is substantially thinner, with an average thickness of only about 0.7 nm. These results suggest that sub-conformal films may form at the relevant feature geometries described herein. Furthermore, these results suggest that the sub-conformal film may be specifically aligned to be deposited relatively thickly at (or over) the arcuate region and relatively thin (or not at all) below the arcuate region. After several iterations of etching and deposition, the result is that the etched features have relatively straight/vertical profiles. In contrast, where the protective film is always deposited conformally, the resulting features typically have a sloped profile (features are thicker near the top and narrower near the bottom).

In cases where the protective film is conformally formed, a sloped profile may result because the protective film is formed to an equal thickness over all areas of the feature sidewalls. Figure 9B shows simulation results showing the thickness of the protective film as a function of etch depth for protective layers deposited according to the conformal state. As noted above, for the two deposited films shown in Figure 9B, the thickness is fairly constant throughout the entire feature. When this is the case, the arcuate area is protected to about the same degree as the area below the arcuate portion. However, during subsequent etch operations, process conditions are most severe at the arcuate region (eg, due to feature geometry and directionality of the etch process), and features are etched the most in this region. As a result, through several iterations of etch/deposition, the arcuate area still increases (compared to the area under the arcuate portion). Although the arc will not grow as fast as without the protective film, it will still increase (compared to the area under the arc), the area under the arc is also properly protected but the surface For less severe etch conditions. Using a subconformal pellicle allows the pellicle to be aligned where it is most useful (for example, in arcuate regions where etch conditions are most severe). In fact, the protection film acts as a sacrificial material that can be completely or partially etched away during each etching operation.

It should be appreciated that the configurations and/or methods described herein are exemplary in nature and that these particular embodiments or examples should not be considered limiting, as many variations are possible. A particular procedure or method described herein may represent one or more of any number of process strategies. As such, performance of the various acts described may be performed in the sequence described, in other sequences, in parallel, or in some cases omitted. Likewise, the order of the above-described processing may be changed.

The subject matter of the present disclosure includes all novel and nonobvious combinations and subcombinations of various processes, systems, and arrangements, and other features, functions, acts, and/or properties disclosed herein, and any and all equivalents thereof .

102‧‧‧cylindrical object 103‧‧‧dielectric material 104‧‧‧polymer sidewall coating 105‧‧‧curved portion 106‧‧‧patterned mask layer 200‧‧‧method 201‧‧‧operation 203‧‧‧operation 205‧‧‧operation 207‧‧‧operation 211‧‧‧operation 213‧‧‧operation 215‧‧‧operation 217‧‧‧operation 219‧‧‧operation 302‧‧‧feature part 303‧‧‧ Material 304‧‧‧first sidewall coating 306‧‧‧patterned mask layer 310‧‧‧second sidewall coating 312‧‧‧precursor layer 320a‧‧‧first protection film 320b‧‧‧first protection Membrane 320c‧‧‧protective film 330‧‧‧substrate 400‧‧‧RF plasma reactor 402‧‧‧chamber 404‧‧‧chamber cover 405‧‧‧vacuum chamber interior 406‧‧‧lower electrode 408‧ ‧‧Upper electrode 410‧‧‧Gap 410a‧‧‧Gap 410b‧‧‧Gap 410c‧‧‧Gap 412‧‧‧Opening 414‧‧‧Insulating ring 416‧‧‧Support plate 418‧‧‧Chamber wall plate 420 ‧‧‧RF Power Supply 422‧‧‧RF Supply Conduit 424‧‧‧RF Band 426‧‧‧RF Power Member 428‧‧‧Stepped Flange 430‧‧‧RF Bias Housing 432‧‧‧RF Bias Housing Bowl 434‧‧‧RF Biasing Housing Arm 436‧‧‧Ground Shield 438‧‧‧Conduit Support Plate 440‧‧‧Facility Conduit 442‧‧‧Actuation Mechanism 444‧‧‧Linear Bearing 446‧‧‧Helical Gear 448‧‧‧Labyrinth packing 450‧‧‧Bellows 452‧‧‧Clamping ring 456‧‧‧Fixed shielding 458‧‧‧Movable shielding plate 460‧‧‧A labyrinth groove 480‧‧‧Vacuum inlet 482‧ ‧‧Wafer Port 500‧‧‧Reactor 502‧‧‧Low Frequency RF Generator 504‧‧‧High Frequency RF Generator 506‧‧‧Matching Network 508‧‧‧Manifold 510‧‧‧Source Gas Pipeline 512‧ ‧‧Inlet 514‧‧‧Shower Head 516‧‧‧Substrate 518‧‧‧Wafer Base 520‧‧‧Heater Block 522‧‧‧Outlet 524‧‧‧Process Chamber 530‧‧‧System Controller 540‧ ‧‧Vacuum pump 600‧‧‧Multi-station processing tool 602‧‧‧Inbound load lock chamber 604‧‧‧Outbound load lock chamber 606‧‧‧Robot arm 608‧‧‧Wafer cassette 609‧‧‧Wafer handling System 610‧‧‧atmospheric port 612‧‧‧base 614‧‧‧process chamber 616‧‧‧chamber transfer port 618‧‧‧base 650‧‧‧system controller 652‧‧‧processor 654‧‧‧big Capacity storage device 656‧‧‧memory device 658‧‧‧system control software 720a‧‧‧process module 720b‧‧‧process module 720c‧‧‧process module 720d‧‧‧process module 722‧‧‧machinery Arm 724‧‧‧end effector 726‧‧‧base plate 728‧ ‧‧Module Center 730‧‧‧Air Chamber 732‧‧‧Front Robotic Arm 734‧‧‧Front Opening Wafer Transfer Box 736‧‧‧Face 738‧‧‧Vacuum Transfer Module 740‧‧‧Atmospheric Transfer Module 742 ‧‧‧Loading Port Module 744‧‧‧Aligner

Figure 1 shows an etched cylinder with an undesired arc caused by overetching of the sidewall.

2 shows a flowchart of a method for forming etched features on a semiconductor substrate, according to various disclosed embodiments.

3A-3D depict etched cylinders in a semiconductor substrate covered by periodic etching and protective sidewall coatings, according to various embodiments.

3E-3I show etched cylinders in a semiconductor substrate covered by periodic etching and protective sidewall coatings on different Deposition Repeated processes are deposited with varying degrees of conformality.

FIG. 3J illustrates an etched cylinder in a semiconductor substrate, wherein the cylinder includes arcuate regions and forms a sub-conformal protective film on sidewalls of features.

4A-4C illustrate a reaction chamber that may be used to perform the etching processes described herein, according to certain embodiments.

Figure 5 depicts a reaction chamber that may be used to perform the deposition processes described herein, according to certain embodiments.

Figure 6 shows a multi-station apparatus that may be used to perform a deposition process, according to certain implementations.

Figure 7 shows a cluster tool that may be used to perform both deposition and etch, according to certain embodiments.

8A-8C depict partially etched features covered with a protective sidewall film that is conformal (FIG. 8A), ultra-conformal (FIG. 8B), or sub-conformal (FIG. 8C). ).

8D-8F are graphs showing the deposited thickness of the protective sidewall film, which is conformal (FIG. 8D), super-conformal, as a function of etch depth, on each side of a partially etched feature. (Fig. 8E), or subconformal (Fig. 8F).

Figure 9A shows simulation results plotting average CD versus etch depth before and after depositing a sub-conformal protective film.

Figure 9B presents simulation results showing the thickness of the conformal protection film versus etch depth.

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Claims (18)

A method of forming etched features in a substrate comprising a dielectric material, the method comprising: (a) generating a first plasma comprising an etch reactant, exposing the substrate to the first plasma , and partially etching the feature in the substrate; (b) after (a), depositing a protective film on the plurality of sidewalls of the feature by atomic layer deposition (ALD); and (c) repeating ( a)-(b) until the feature is etched to a final depth, wherein the feature has an aspect ratio at its final depth of about 5 or greater, and wherein the process is repeated with a second in (b) Compared with the protective film deposited by ALD in (b), the protective film deposited by ALD in the first iteration of (b) was deposited under different conditions and had a different degree of conformality. The method of forming an etched feature in a substrate as claimed in claim 1, wherein the first iterative process of (b) is performed before the second iterative process of (b). The method of forming etched features in a substrate as claimed in claim 1, wherein the protective film deposited in the first iteration of (b) is conformal, and in (b) ) The protective film deposited in the second iteration of the process is sub-conformal. A method of forming etched features in a substrate as claimed in claim 3, wherein the protective film deposited in the second iteration of (b) does not extend to the partially etched features bottom. The method of forming an etched feature in a substrate as claimed in claim 1, wherein compared to the protective film deposited in the second repeated process of (b), the first of (b) The protective film deposited in repeated processes is deposited at a higher pressure. The method of forming an etched feature in a substrate as claimed in claim 1, wherein compared to the protective film deposited in the second repeated process of (b), the first of (b) The protective films deposited in repeated processes were deposited with lower reactant transport rates. The method of forming an etched feature in a substrate as claimed in claim 1, wherein compared to the protective film deposited in the second repeated process of (b), the first of (b) The protective films deposited in repeated processes were deposited with shorter reactant delivery durations. The method of forming an etched feature in a substrate as claimed in claim 1, wherein compared to the protective film deposited in the second repeated process of (b), the first of (b) The protective films deposited in repeated processes were deposited with shorter plasma exposure durations. The method of forming an etched feature in a substrate as claimed in claim 1, wherein compared to the protective film deposited in the second repeated process of (b), the first of (b) The protective films deposited in repeated processes were deposited with higher RF power. The method of forming an etched feature in a substrate as claimed in claim 1, wherein compared to the protective film deposited in the second repeated process of (b), the first of (b) The protective films deposited in repeated processes were deposited with higher RF duty cycles. The method of forming an etched feature in a substrate according to claim 1, wherein the protective film deposited in the first repeated process of (b) is deposited using a first set of deposition conditions wherein the protective film deposited in the second iteration of (b) is deposited using a second set of deposition conditions, wherein the first set of deposition conditions and the second set of deposition conditions are related to at least two parameters Alternatively, the at least two parameters are selected from the group consisting of pressure, reactant delivery flow rate, reactant delivery duration, plasma exposure duration, RF power, and RF duty cycle. The method of forming etched features in a substrate as claimed in claim 11, wherein the first set of deposition conditions has a lower reactant delivery rate and at least one of the following: (i) shorter reaction duration of material delivery, and (ii) shorter duration of plasma exposure. A method of forming etched features in a substrate as claimed in claim 1, wherein at least one repeated process of (a) results in the formation of an arc within the feature, and wherein one of (b) is subsequently repeated. This results in the protective film being formed at least as deep as the arc, but not as deep as the feature. A method of forming etched features in a substrate according to any one of claims 1-13, wherein the protective film is deposited by a thermal atomic layer deposition reaction or a plasma-assisted atomic layer deposition reaction . An apparatus for forming etched features in a substrate comprising a dielectric material, the apparatus comprising: one or more reaction chambers, at least one of which is designed or configured to perform etching, and at least one of which Reaction chambers are designed or configured to perform deposition, each reaction chamber comprising: an inlet for introducing a plurality of process gases into the reaction chamber, an outlet for removing material from the reaction chamber, and a Controller with plural instructions for: (a) generating a first plasma comprising an etch reactant, exposing the substrate to the first plasma, and partially etching the feature in the substrate, wherein (a) is designed or configured to perform The etching is performed in the reaction chamber; (b) after (a), depositing a protective film by atomic layer deposition (ALD) on the plurality of sidewalls of the feature, wherein (b) is designed or configured to performing in the reaction chamber in which the deposition is performed; and (c) repeating (a)-(b) until the feature is etched to a final depth, wherein the feature has a depth of about 5 or more at its final depth width ratio, and wherein compared with the protective film deposited by ALD in the second iteration of (b), the protective film deposited by ALD in the first iteration of (b) is Deposited under different conditions and with varying degrees of conformality. An apparatus for forming etched features in a substrate as claimed in claim 15, wherein the reaction chamber designed or configured to perform etching is the same as the reaction chamber designed or configured to perform deposition, so that Both (a) and (b) take place in the same reaction chamber. An apparatus for forming etched features in a substrate as claimed in claim 15, wherein the reaction chamber designed or configured to perform etching is different from the reaction chamber designed or configured to perform deposition, and wherein The controller further includes instructions for transferring the substrate between the reaction chamber designed or configured to perform etching and the reaction chamber designed or configured to perform deposition. A method of forming etched features in a substrate comprising a dielectric material, the method comprising: (a) generating a first plasma comprising an etch reactant, exposing the substrate to the first plasma , and partially etching the feature in the substrate; (b) after (a), deposit a protective film on the plurality of sidewalls of the feature by molecular layer deposition (MLD); and (c) repeat (a)-(b) until the feature is etched to a final depth, wherein the feature has an aspect ratio of about 5 or greater at its final depth, and wherein compared to the protective film deposited by MLD in a second iteration of (b), The protective films deposited by MLD in the first iteration of (b) were deposited under different conditions and had different degrees of conformality.

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