TWI779607B - Method of forming semiconductor structure - Google Patents

Abstract

A method of forming semiconductor structure includes forming a patterned hard mask layer on a semiconductor material layer, removing a portion of the semiconductor material layer by an etching process to form semiconductor pillars and trenches. A residue is formed during the etching process. The method further includes removing the residue. Removing the residue includes using a first gas cleaning process to remove at least a portion of the residue, and after the first gas cleaning process, using a second gas cleaning process to remove a left part of the residue. A condition of the first gas cleaning process is different from that of the second gas cleaning process.

Description

Methods of Forming Semiconductor Structures

The present disclosure relates to methods of forming semiconductor structures, and more particularly, methods of forming semiconductor structures having larger aspect ratios.

In the process of forming the semiconductor structure, by-products or residual etchant generated during the process can be removed by a wet cleaning process to clean the semiconductor structure after etching. During cleaning and drying of semiconductor structures, liquids, such as cleaning solutions, deionized water, or volatile solutions, enter the pitches of the semiconductor structures for cleaning.

As technology advances, dynamic random access memory (DRAM) becomes more highly integrated. The goal of technology development is achieved by shrinking the semiconductor structure in the DRAM to form a more slender semiconductor structure (ie, a structure with a larger aspect ratio) and pitch. During the post-etch cleaning process, the influence of the liquid on the semiconductor structure becomes more and more obvious, for example, the semiconductor structure cannot withstand the force generated by the liquid and thus deforms and/or collapses.

Therefore, how to complete post-etch cleaning without affecting the semiconductor structure has become an important issue.

According to some embodiments of the present disclosure, a method of forming a semiconductor structure includes forming a patterned hard mask on a semiconductor material layer, removing a portion of the semiconductor material layer by an etching process and the patterned hard mask to form a plurality of semiconductor Columns and several grooves. Residues are generated in the trenches during the etching process. The method further includes removing the residue. Removing the residue includes using a first vapor-phase cleaning process to remove at least a portion of the residue, and after using the first vapor-phase cleaning process, using a second vapor-phase cleaning process to remove a remaining portion of the residue. Conditions of the first vapor cleaning process are different from conditions of the second vapor cleaning process.

In some embodiments, the first gas composition of the first gas-phase cleaning process includes an oxygen-containing gas.

In some embodiments, the second gas composition of the second gas-phase cleaning process includes a hydrogen-containing gas and a carrier gas.

In some embodiments, the operating temperature of the first vapor cleaning process is a first temperature, and the operating temperature of the second vapor cleaning process is a second temperature, wherein the second temperature is higher than the first temperature.

The method of forming a semiconductor structure provided by the present disclosure uses a multi-step vapor phase cleaning process to remove residues on the semiconductor structure as a post-etch cleaning operation. Through the choice of gas composition and the arrangement of process conditions, the impact on the semiconductor structure is minimized during the post-etch cleaning operation.

100: Semiconductor Structures

110: semiconductor material layer

120: Hard mask material layer

130: Patterned mask

132: Parallel structure

134: Groove

200: Patterned Hard Mask

202: Parallel structure

204: Groove

400: Etching process

410: Patterned semiconductor materials

412: Semiconductor pillar

414: Groove

416: Semiconductor substrate

420: Residue

420A: remainder

430: The first gas phase cleaning process

440: oxide

450: The second gas phase cleaning process

600: Isolation area

A-A: Sectional line

D: Direction

W1, W2: width

H1, H2: Height

X, Y, Z: axes

θ: angle

The following embodiments are read together with the accompanying drawings to clearly understand the viewpoints of the present disclosure. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily expanded or reduced for clarity of discussion.

FIG. 1A illustrates a top view of one of the process stages of forming a semiconductor structure according to some embodiments of the present disclosure.

FIG. 1B illustrates a cross-sectional view of the semiconductor structure of FIG. 1A along section line A-A, according to some embodiments of the present disclosure.

FIG. 2A illustrates a top view of one of the process stages of forming a semiconductor structure according to some embodiments of the present disclosure.

FIG. 2B illustrates a cross-sectional view of the semiconductor structure of FIG. 2A along section line A-A, according to some embodiments of the present disclosure.

FIG. 3A illustrates a top view of one of the process stages of forming a semiconductor structure according to some embodiments of the present disclosure.

Figure 3B illustrates a cross-sectional view of the semiconductor structure of Figure 3A along section line A-A, according to some embodiments of the present disclosure.

FIG. 4A illustrates a top view of one of the process stages of forming a semiconductor structure according to some embodiments of the present disclosure.

4B shows a cross-sectional view of the semiconductor structure of FIG. 4A along line A-A during one of the etch-related process stages, according to some embodiments of the present disclosure.

FIG. 4C illustrates the semiconductor junction of FIG. 4A according to some embodiments of the present disclosure. The structure is a cross-sectional view along the section line A-A at the stage of the first gas-phase cleaning process.

FIG. 4D shows a cross-sectional view of the semiconductor structure of FIG. 4A along section line A-A at a stage of a second vapor-phase cleaning process, according to some embodiments of the present disclosure.

FIG. 5A illustrates a top view of one of the process stages of forming a semiconductor structure according to some embodiments of the present disclosure.

FIG. 5B illustrates a cross-sectional view of the semiconductor structure of FIG. 5A along section line A-A, according to some embodiments of the present disclosure.

FIG. 6A illustrates a top view of one of the process stages of forming a semiconductor structure according to some embodiments of the present disclosure.

FIG. 6B illustrates a cross-sectional view of the semiconductor structure of FIG. 6A along section line A-A, according to some embodiments of the present disclosure.

When an element is referred to as being "on", it can generally mean that the element is directly on other elements, or there may be other elements present in between. Conversely, when an element is said to be "directly on" another element, it cannot have other elements in between. As used herein, the word "and/or" includes any combination of one or more of the associated listed items.

In the present disclosure, terms such as first, second and third are used to describe various elements, components, regions, layers and/or blocks to be understood. But these elements, components, regions, layers and/or blocks should not be limited by these terms. These terms are limited to identifying a single element, component, region, layer and/or block. Therefore, a first element, component, region, layer and/or block hereinafter may also be referred to as a second element, component, region Domains, layers and/or blocks without departing from the intent of this disclosure.

As used in this disclosure, "about" generally means within about 20 percent, preferably within about 10 percent, and more preferably about 5 percent, of the error or range of the value of the index within. If there is no explicit statement in the text, the values mentioned are regarded as approximate values, that is, the error or range indicated by "approximately".

After the etching process, the semiconductor structure may be cleaned using a liquid (such as a cleaning solution, deionized water, or a volatile solvent) as a cleaning medium to remove residues, such as by-products of the etching process or residual etchant. During the cleaning process, although the surface tension of the liquid exerts a force on the semiconductor structure, the semiconductor structure may be strong enough to withstand this force and remain unaffected. However, when the semiconductor structure gradually becomes slender and has a larger aspect ratio, the semiconductor structure may not be able to withstand the above-mentioned force, resulting in deformation and/or collapse of the semiconductor structure under the uneven external force. The following various examples describe a method of using a gas instead of a liquid as a post-etch cleaning medium to form a semiconductor structure.

FIGS. 1A-6B illustrate top views of formed semiconductor structures 100 (eg, memory device structures, including DRAM device structures) according to some embodiments of the present disclosure (FIGS. 1A, 2A, 3A, 4A, 5A, and 6A) and cross-sectional views (1B, 2B, 3B, 4B, 4C, 4D, 5B, and 6B) .

It should be noted that when Figures 1A to 6B are shown or described as a series of operations or events, the description order of these operations or events should not restricted. For example, some operations or events may be undertaken in a different order than in the present disclosure, some operations or events may occur concurrently, some operations or events may not be required, and/or some operations or events may be repeated. Moreover, the actual process may require additional steps before, during, or after forming the semiconductor structure 100 to completely form the semiconductor structure 100 . Therefore, this disclosure may briefly illustrate some of these additional operational steps. Furthermore, unless otherwise stated, the same explanations discussed in Figures 1A to 6B can be directly applied to the other figures.

Please refer to FIG. 1A and FIG. 1B. FIG. 1A shows a top view of one of the process stages of forming a semiconductor structure 100 according to some embodiments of the present disclosure, and FIG. 1B shows forming a semiconductor structure 100 according to some embodiments of the present disclosure. A cross-sectional view of structure 100 at one of its fabrication stages.

The semiconductor structure 100 may include a semiconductor material layer 110 ( FIG. 1B ), a hard mask material layer 120 on the semiconductor material layer 110 , and a patterned mask 130 on the hard mask material layer 120 .

The semiconductor material layer 110 is a semiconductor material, which may include silicon, such as crystalline silicon, polycrystalline silicon, or amorphous silicon. The semiconductor material layer 110 may include an elemental semiconductor such as germanium (Ge). The semiconductor material layer 110 may include alloy semiconductors, such as silicon germanium (SiGe), silicon carbide (SiPC), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), arsenide Gallium indium gallium (GaInAs), gallium indium phosphide (GaInP), gallium indium phosphide (GaInAsP), or other suitable materials. The semiconductor material layer 110 may include compound semiconductors such as silicon carbide (SiC), silicon phosphide (SiP), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), zinc oxide (ZnO), zinc selenide (ZnSe), zinc sulfide (ZnS), zinc telluride (ZnTe), cadmium selenide (CdSe), cadmium sulfide (CdS), Cadmium telluride (CdTe), or other suitable materials.

In addition, the semiconductor material layer 110 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (germanium-on-insulator) substrate. , GeOI) substrate. The semiconductor-on-insulator substrate can be fabricated by separation by implantation of oxygen technology, wafer bonding technology, other suitable technologies, or a combination of the above.

The hard mask material layer 120 may be composed of at least one of carbon, silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, aluminum oxide, silicon oxynitride, and other suitable materials. The hard mask material layer 120 can be a single layer or a multi-layer structure. For example, the hard mask material layer 120 can be a single-layer oxide, such as silicon dioxide or aluminum oxide. Alternatively, in some embodiments, the hard mask material layer 120 may be a double-layer structure including silicon oxide and silicon nitride.

The formation method of the hard mask material layer 120 may include physical vapor deposition (physical vapor deposition, PVD), chemical vapor deposition (chemical vapor deposition, CVD), atomic layer deposition (atomic layer deposition, ALD), thermal nitrogen of silicon Nitriding, plasma anodic nitridation, spin coating, or other suitable methods. CVD may include plasma enhanced chemical vapor deposition (plasma enhanced CVD, PECVD) or low pressure chemical vapor deposition (low pressure CVD, LPCVD).

The patterned mask 130 includes a plurality of parallel structures 132 and grooves 134 , wherein the grooves 134 separate each parallel structure 132 such that adjacent parallel structures 132 are arranged at equal distances along the X-axis and the Y-axis. In the top view shown in FIG. 1A , hard mask material layer 120 can be seen through trenches 134 .

The parallel structure 132 has a minor axis and a major axis. In some embodiments, the long axis of the parallel structure 132 extends along a direction D, wherein the direction D forms an angle θ with the X axis. Also, each parallel structure has substantially the same minor and major axis lengths.

The material of parallel structures 132 may be selected from a material that is etch-selective to hard mask material layer 120 to facilitate selective removal of a portion of parallel structures 132 by one or more processes, and/or by one or more other processes. A portion of the hard mask material layer 120 is selectively removed. In some embodiments, the parallel structure 132 includes a nitrogen-containing dielectric material, such as silicon nitride. In some embodiments, parallel structures 132 include a photoresist material.

Please refer to FIG. 2A and FIG. 2B. FIG. 2A shows a top view of one of the process stages of forming semiconductor structure 100 according to some embodiments of the present disclosure, and FIG. FIG. 1 is a cross-sectional view of the semiconductor structure 100 along the section line A-A.

Next, a portion of the hard mask material layer 120 is selectively removed by an etching process to form a patterned hard mask 200 on the semiconductor material layer 110 . In detail, the etchant removes the hard mask material layer 120 exposed in the trench 134 through the patterned mask 130 to form the hard mask material layer 120 into a patterned hard mask 200 . In some embodiments, the etch process selectively shifts The hard mask material layer 120 is removed without removing the semiconductor material layer 110 .

The pattern of the patterned hard mask 200 may correspond to the pattern of the patterned mask 130 . For example, the patterned hard mask 200 may include a plurality of parallel structures 202 and trenches 204, wherein the parallel structures 202 have a topography similar to the parallel structures 132, and the trenches 204 have a topography similar to the trench 134. , the foregoing feature descriptions for the parallel structures 132 and the trenches 134 are generally applicable to the parallel structures 202 and the trenches 204 , so details are not described again.

Please refer to FIG. 3A and FIG. 3B. FIG. 3A shows a top view of one of the process stages of forming semiconductor structure 100 according to some embodiments of the present disclosure, and FIG. FIG. 1 is a cross-sectional view of the semiconductor structure 100 along the section line A-A.

Next, the patterning mask 130 is removed. Since the material of the patterned mask 130 has an etch selectivity to the material of the patterned hard mask 200, and the material of the patterned mask 130 also has an etch selectivity to the material of the semiconductor material layer 110, only the patterned mask 130 remove. Thereby, a patterned hard mask 200 is formed on the semiconductor material layer 110 , and the patterned hard mask 200 serves as an etching mask for the semiconductor material layer 110 in a subsequent etching process.

Please refer to FIG. 4A and FIG. 4B. FIG. 4A shows a top view of one of the process stages of forming semiconductor structure 100 according to some embodiments of the present disclosure, and FIG. FIG. 1 is a cross-sectional view of the semiconductor structure 100 along the line A-A at one of the etching-related process stages.

Next, by etching process 400 and patterning hard mask 200 A portion of the semiconductor material layer 110 is removed to form a patterned semiconductor material 410 . In the embodiment shown in FIG. 4B , the patterned semiconductor material 410 includes a plurality of semiconductor pillars 412 , a plurality of trenches 414 , and a semiconductor substrate 416 . The semiconductor pillars 412 protrude upward (eg, parallel to the Z-axis) from the semiconductor substrate 416 , and the trenches 414 separate adjacent semiconductor pillars 412 .

The semiconductor column 412 in FIG. 4B has a width W1 and a height H1, and the width W1 and the height H1 are determined according to product design or process conditions. In some embodiments, the aspect ratio of the height of semiconductor pillar 412 (eg, height H1 of FIG. 4B ) to the width of semiconductor pillar 412 (eg, width W1 of FIG. 4B times sin θ ) is at least greater than about 12. In some embodiments, height H1 is about 120 nm to about 240 nm.

The etching process 400 for removing the semiconductor material layer 110 may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. For example, the dry etching process may use oxygen-containing gases, fluorine-containing gases (eg, CF ₄ , SF ₆ , CH ₂ F ₂ , CHF ₃ , and/or C ₂ F ₆ ), chlorine-containing gases (eg, Cl ₂ , CHCl ₃ , CCl ₄ , and/or BCl ₃ ), bromine-containing gas (eg, HBr), iodine-containing gas, other suitable gases and/or plasmas, or combinations thereof. In another example, the wet etching process may use diluted hydrofluoric acid (DHF), potassium hydroxide (KOH) solution, ammonia, hydrofluoric acid (HF), nitric acid (HNO ₃ ) and/or Acetic acid (CH ₃ COOH) solution, other suitable wet etchant, or a combination of the above. In some embodiments, etching process 400 uses a reactive ion etching process.

In some embodiments, during etching process 400, A residue 420 is formed within the trenches 204/414. In detail, the residue 420 adheres to the sidewalls of the semiconductor pillars 412 , the sidewalls of the parallel structures 202 of the patterned hard mask 200 , or the top surface of the semiconductor substrate 416 , as shown in FIG. 4B .

The residue 420 may be a by-product formed after the etchant in the etching process 400 reacts with the material of the semiconductor material layer 110 and/or the material of the patterned hard mask 200 . In some embodiments, the residue 420 comprises components from the etchant used in the etching process 400, such as carbon or other suitable materials. Therefore, the etching process 400 may be followed by a cleaning process to remove the residue 420 in the semiconductor structure 100, as illustrated in FIGS. 4C and 4D below.

Please refer to FIG. 4C , which shows a cross-sectional view of the semiconductor structure 100 in FIG. 4A along the section line AA at the stage of the first vapor-phase cleaning process 430 according to some embodiments of the present disclosure. First, at least a portion of the residue 420 is removed using a first vapor phase cleaning process 430 . The gas composition of the first gas-phase cleaning process 430 includes an oxygen-containing gas. In an embodiment including an oxygen-containing gas, the gas composition of the first gas-phase cleaning process 430 further includes a fluorine-containing gas, which includes at least one of CF ₄ , SF ₆ , NF ₃ , or CHF ₃ , and the oxygen-containing gas The composition is higher than that of fluorine-containing gases. In some embodiments, the composition ratio of oxygen-containing gas to fluorine-containing gas is about 10 to 1. In some embodiments, the gas composition of the first gas-phase cleaning process 430 includes oxygen and a fluorine-containing gas, wherein the oxygen is more than the fluorine-containing gas. In some embodiments, the first vapor phase cleaning process 430 is a selective isotropic etch.

The operating temperature of the first vapor cleaning process 430 may be about 10° C. and about 120°C, such as 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110 or 120°C. If the operating temperature of the first gas-phase cleaning process 430 is higher than the above-mentioned upper limit, the etching selectivity of the gas composition to the residue 420 to the material of the semiconductor pillar 412 may be reduced, resulting in unexpected loss of the semiconductor structure 100 (eg, , resulting in the excessive formation of oxide 440 hereinafter). If the operating temperature of the first vapor-phase cleaning process 430 is lower than the above-mentioned lower limit, there is no substantial benefit to the process. In some embodiments, the operating temperature of the first vapor-phase cleaning process 430 is between about 10°C and about 30°C. In some embodiments, the operating temperature of the first vapor-phase cleaning process 430 is between about 60°C and about 80°C.

The first vapor phase cleaning process 430 can be combined with plasma. By adjusting the operating parameters of the plasma, the plasma interacts with the gas used in the process to generate a gas composition in a radical state. Next, the plasma is separated from the gas composition in the free radical state. In some embodiments, a charged grating (not shown) may be used to block the movement of charged ions from the plasma and allow uncharged particles (eg, gas constituents in a free radical state) to pass through the charged grating. For example, a charged grating can prevent the passage of charged ions (eg, positively or negatively charged ions) by repelling or attracting the charged ions. Any device that can separate the gas composition of the plasmonic and radical states is applicable to the present disclosure. The gas composition in a free radical state can then diffuse into trenches 204 and 414 and can react with residue 420 .

The first vapor phase cleaning process 430 may remove at least a portion of the residue 420 of FIG. 4B. When the first vapor cleaning process 430 fails to completely remove the residue 420, there are still residues after the first vapor cleaning process 430 The remaining portion 420A of object 420 remains in trench 414. A portion (eg, the first portion) of the semiconductor pillar 412 is covered by the remaining portion 420A of the residue 420 and another portion (eg, the second portion) is not covered by the remaining portion 420A of the residue 420 .

In some embodiments, the semiconductor pillar 412 (ie, the second portion) that is not covered by the remaining portion 420A of the residue 420 and exposed in the trench 414 is removed during the etching process 400, the first vapor-phase cleaning process 430, or other During the process, the exposed material may come into contact with moisture or other gases in the process environment, and an oxidation reaction occurs to form oxide 440, as shown in FIG. 4C. For example, the oxide 440 may be a native oxide formed on the exposed semiconductor pillar 412 (ie, on the second portion). Alternatively, the oxide 440 may be the oxide 440 formed by the reaction of at least part of the gas composition (eg, oxygen-containing gas) of the first gas-phase cleaning process 430 with the material of the exposed semiconductor pillar 412 . Therefore, after the first vapor-phase cleaning process 430 , the semiconductor pillar 412 (ie, the second portion) not covered by the remaining portion 420A of the residue 420 may have the oxide 440 .

In some embodiments, the semiconductor pillar 412 (ie, the first portion) covered by the remaining portion 420A of the residue 420 is not conducive to the formation of the oxide 440 because it is not easily exposed to moisture or other gases. In this case, the location of the oxide 440 does not overlap with the location of the remaining portion 420A of the residue 420 .

In other embodiments, although the semiconductor pillar 412 is covered by the remaining portion 420A of the residue 420 (ie, the first portion), the moisture Or other gases may be diffused, or the structure of the remaining portion 420A of the residue 420 cannot block the passage of water vapor or other gases, so that the oxide 440 may still be formed at the position covered by the residue 420 (ie, the first portion). In this case, besides being formed on the exposed semiconductor pillar 412 (ie, the second portion), the oxide 440 may also be formed between the remaining portion 420A of the residue 420 and the semiconductor pillar 412 (ie, the first portion).

Please refer to FIG. 4D in succession. FIG. 4D shows a cross-sectional view of the semiconductor structure 100 in FIG. 4A along the line A-A at the stage of the second vapor-phase cleaning process 450 according to some embodiments of the present disclosure. After using the first vapor cleaning process 430, a second vapor cleaning process 450 may be further used to remove the remaining portion 420A of the residue 420, wherein the conditions of the first vapor cleaning process 430 are different from those of the second vapor cleaning process. 450 condition.

Regarding the gas composition, the gas composition of the second gas phase cleaning process 450 includes a hydrogen-containing gas and a carrier gas. In some embodiments, the gas composition of the second gas phase cleaning process 450 may include hydrogen and a carrier gas. Furthermore, the composition ratio of hydrogen is about 4% to about 50%, such as 5, 10, 15, 20, 25, 30, 35, 40, 45, or 50%. In some embodiments, the composition ratio of hydrogen is about 4%. The selected carrier gas has low reactivity to the material of the semiconductor structure 100 , such as nitrogen, inert gases (helium, neon, argon, krypton, xenon), other suitable low-reactivity gases, or combinations thereof. In some embodiments, the gas composition of the second gas-phase cleaning process 450 can use conventional reducing gases such as hydrogen-nitrogen mixed gas (forming gas). In some embodiments, the second vapor phase cleaning process 450 is a selective isotropic etch.

Regarding the operating temperature, the operating temperature of the second vapor cleaning process 450 is higher than the operating temperature of the first vapor cleaning process 430 . The operating temperature of the second vapor cleaning process 450 may be in the range of about 200°C and 300°C, such as 200, 210, 220, 230, 240, 250, 260, 270, 280, 290, or 300°C. If the operating temperature of the second vapor cleaning process 450 is lower than the above lower limit, the gas composition of the second vapor cleaning process 450 cannot remove the remaining portion 420A of the residue 420 within the expected time. If the operating temperature of the second vapor-phase cleaning process 450 is higher than the above-mentioned upper limit, there is no substantial benefit to the process. In some embodiments, the operating temperature of the second vapor-phase cleaning process 450 is between about 270°C and about 290°C. Regarding the operating time, the operating time of the second vapor cleaning process 450 is less than that of the first vapor cleaning process 430 .

The second vapor-phase cleaning process 450 can be combined with plasma. By adjusting the operating parameters of the plasma, the plasma interacts with the gas used in the etching process to produce a gas composition in a radical state. The manner in which the second vapor-phase cleaning process 450 can be used in combination with plasma is similar to the manner in which the first vapor-phase cleaning process 430 can be used in combination with plasma, so it will not be described in detail here.

In addition to removing the remaining portion 420A of the residue 420 to clean the semiconductor structure 100, the second vapor-phase cleaning process 450 can also remove the oxide 440 (FIG. 4C). Removing the oxide 440 refers to reducing the oxide 440 in the second vapor phase cleaning process 450 . Specifically, the oxide 440 formed by the material of the semiconductor pillar 412 exposed in the first gas-phase cleaning process 430 and the moisture (or other gas) in the process environment can be combined with at least the second gas-phase cleaning process 450 Partial gas composition (for example, containing Hydrogen gas) reacts to reduce the oxide 440 and form the material of the semiconductor pillar 412 . The wear to the semiconductor pillar 412 of the semiconductor structure 100 is thereby minimized.

After sequentially performing the first vapor cleaning process 430 and the second vapor cleaning process 450 , the semiconductor pillar 412 in FIG. 4D has a width W2 and a height H2 . In some embodiments, width W2 is substantially the same as width W1. In some embodiments, height H2 is substantially the same as height H1. Therefore, the foregoing description of the aspect ratio of the semiconductor pillar 412 is applicable here, and will not be described in detail here.

Please refer to FIG. 5A and FIG. 5B. FIG. 5A shows a top view of one of the process stages of forming semiconductor structure 100 according to some embodiments of the present disclosure, and FIG. FIG. 1 is a cross-sectional view of the semiconductor structure 100 along the section line A-A. Next, the patterned hard mask 200 is removed. Since the material of the patterned hard mask 200 has etch selectivity to the material of the patterned semiconductor material 410, only the patterned hard mask 200 is removed.

Please refer to FIG. 6A and FIG. 6B. FIG. 6A shows a top view of one of the process stages of forming semiconductor structure 100 according to some embodiments of the present disclosure, and FIG. FIG. 1 is a cross-sectional view of the semiconductor structure 100 along the section line A-A.

Next, an isolation region 600 is formed between adjacent semiconductor pillars 412 , thereby separating the semiconductor pillars 412 . The formation of the isolation region 600 may include a deposition process, an annealing process, a chemical mechanical planarization (CMP) process, etch back (etching back) process, other suitable processes, or a combination of the above. For example, a flowable dielectric material is deposited on patterned semiconductor material 410 and fills trenches 414 (FIG. 4D). Subsequently, an annealing process converts the fluid dielectric material into a solid dielectric material. Next, one or more CMP processes and/or etch-back processes are performed to remove excess dielectric material. The dielectric material of the isolation region 600 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The isolation region 600 may be a single-layer or multi-layer structure. For example, the isolation region 600 may include silicon oxide and silicon nitride.

The combination of the isolation region 600, the semiconductor pillar 412 and the semiconductor substrate 416 can be used as a substrate for a subsequent process (not shown). For example, the semiconductor pillar 412 in FIG. 6A and FIG. 6B can be used as an active area in subsequent DRAM manufacturing processes.

In summary, the present disclosure provides a method of forming a semiconductor structure, in which a vapor phase cleaning process is used to remove residues on the semiconductor structure as a post-etch clean. For a semiconductor structure with a large aspect ratio, the impact on the semiconductor structure is minimized during the process of removing residues through the selection of gas composition, operation sequence, and arrangement of process conditions.

The features of several embodiments of the present disclosure are briefly described above, so that those skilled in the art can understand the present disclosure more easily. Those skilled in the art should understand that this specification can be easily used as a basis for other structural or process changes or designs to achieve the same purpose and/or obtain the same advantages as the embodiments of the present disclosure. any Those with ordinary knowledge in the technical field can also understand that the structures equivalent to the above do not deviate from the spirit and protection scope of the disclosure, and can be changed, substituted and modified without departing from the spirit and scope of the disclosure. .

100: Semiconductor Structures

200: Patterned Hard Mask

202: Parallel structure

204: Groove

410: Patterned semiconductor materials

412: Semiconductor pillar

414: Groove

416: Semiconductor substrate

450: The second vapor phase cleaning process

W2: width

H2: height

X, Y, Z: axes

Claims (10)

A method of forming a semiconductor structure, comprising: forming a patterned hard mask on a semiconductor material layer; removing a portion of the semiconductor material layer by an etching process and the patterned hard mask to form a plurality of semiconductor pillars and a plurality of trenches, wherein a residue is generated in the trenches during the etching process; and removing the residue comprises: using a first vapor-phase cleaning process to remove at least a portion of the residue, wherein after using the first vapor-phase cleaning process, the semiconductor pillars include an oxide; and after using the first vapor-phase cleaning process, using a second vapor-phase cleaning process to remove a remainder of the residue part, wherein the conditions of the first gas-phase cleaning process are different from the conditions of the second gas-phase cleaning process, and the oxide is reduced in the second gas-phase cleaning process. The method of forming a semiconductor structure as claimed in claim 1, wherein a first gas composition of the first gas-phase cleaning process includes an oxygen-containing gas. The method of forming a semiconductor structure as claimed in claim 2, wherein the first gas composition includes a fluorine-containing gas, wherein the fluorine-containing gas includes at least one of CF ₄ , SF ₆ , NF ₃ , or CHF ₃ . The method for forming a semiconductor structure as claimed in claim 3, Wherein the composition ratio of the oxygen-containing gas to the fluorine-containing gas is about 10:1. The method of forming a semiconductor structure as claimed in claim 1, wherein a second gas composition of the second gas-phase cleaning process includes a hydrogen-containing gas and a carrier gas. The method of forming a semiconductor structure as claimed in claim 1, wherein after using the first vapor-phase cleaning process, the semiconductor pillars comprise: a first portion, wherein the remaining portion of the residue covers the first portion; and A second portion, uncovered by the remainder of the residue and exposed within the trenches to form the oxide. The method for forming a semiconductor structure as claimed in claim 1, wherein the operating temperature of the first gas-phase cleaning process is a first temperature, and the operating temperature of the second gas-phase cleaning process is a second temperature, wherein the second The temperature is higher than the first temperature. The method of forming a semiconductor structure as claimed in claim 7, wherein the first temperature is in the range of about 10°C and about 120°C. The method for forming a semiconductor structure as claimed in claim 1, wherein the operating time of the first gas-phase cleaning process is a first time, and the second The operating time of the two gas-phase cleaning processes is a second time, wherein the second time is shorter than the first time. The method for forming a semiconductor structure as claimed in claim 1, wherein the first vapor-phase cleaning process or the second vapor-phase cleaning process is isotropic etching.

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