TWI778692B - Semiconductor devices and method of forming the same - Google Patents

Abstract

A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed over the gate stack. A portion of the first contact structure is disposed within the gate capping structure and is separated from the gate stack by a portion of the conductive gate cap.

Description

Semiconductor device and method of forming the same

This application relates to a semiconductor device.

As semiconductor technology advances, higher storage capacities, faster processing systems, higher performance, and lower costs have been increasingly required. To meet these demands, the semiconductor industry continues to scale down semiconductor devices such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs and fin field effect transistors (finFETs). )))size of. Such scaling down has increased the complexity of the semiconductor manufacturing process.

In some embodiments, a semiconductor device includes: a substrate; a fin structure disposed on the substrate; a source/drain (S/D) region disposed on the fin structure; and a gate structure, and the The S/D regions are adjacently disposed on the fin structure. The gate structure includes a gate stack disposed on the fin structure and a gate disposed on the gate Gate cap structure on stack. The gate cap structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed on the gate stack. A portion of the first contact structure is disposed within the gate cap structure and is separated from the gate stack by a portion of the conductive gate cap.

In some embodiments, a semiconductor device includes: a substrate; a fin structure disposed on the substrate; a first source/drain (S/D) region and a second source/drain region disposed on the substrate on the fin structure; a first S/D contact structure and a second S/D contact structure, respectively disposed on the first S/D region and the second S/D region; and a first gate structure and a first gate structure A two-gate structure is disposed on the fin structure. Each of the first gate structure and the second gate structure includes a gate stack and a gate cap structure including a conductive gate cap and an insulating gate cap. The semiconductor device further includes a fused via-contact structure disposed on the first S/D contact structure and on the gate stack of the first gate structure. A portion of the fused via-contact structure is disposed within the gate cap structure of the first gate structure.

In some embodiments, a method includes: forming a fin structure on a substrate; forming source/drain (S/D) regions on the fin structure; forming a polysilicon structure on the fin structure; utilizing a gate stack replacing the polysilicon structure; forming a conductive gate cap on the gate stack; forming an insulating gate cap on the gate stack; forming a contact structure on the S/D region; and forming the contact Structural shape forming a via hole, wherein the forming the via hole includes forming a doped region surrounding the via hole.

100: FET/NFET/PFET

104: Substrate

106: Fin Structure

110A, 110B, 110C: S/D area

112A, 112B, 112C: gate structure

114: Gate spacer/spacer

116: Shallow Trench Isolation (STI) Area

117A, 117B, 152: Etch Stop Layer (ESL)

118A, 118B, 118C: Interlayer Dielectric (ILD) Layers

120:S/D contact structure

122: silicide layer

124: Adhesive layer

126: Contact plug

128: Diffusion barrier layer

130: Through hole

130b: Bottom surface

130s, 131s: Sidewalls

131: Doping region

132: Gate stack

134: Gate top cover structure

136: Interface oxide (IO) layer

138: High-k (HK) gate dielectric

140:WFM layer

142: Oxygen barrier layer

144: gate metal filling layer

146: Conductive gate top cover

148: Insulated gate top cover

150: Growth Promotion Layer (GPL)

154: Gate Contact Structure

156, 162: padding

158, 164: Contact plug

160: Fusion via-contact structure

200, 2800: method

205, 210, 215, 220, 225, 230, 235, 240, 2805~2830, 2835, 2840: Operation

312: Polysilicon Structure

566: Gate top cover opening

650, 850, 1524, 1624, 1724, 1824: metal nitride layer

768, 1582: curtain layer

850s: Surface

1280: Contact opening

1328: Dielectric Nitride Layer

1826, 1926, 2230, 2388: metal layer

2184: Through hole opening

2386: Adhesive layer

2590: Patterned Overlay

2592: Opening

2694, 3094: Contact opening

3200: ALE Control System

3270: Training Module

3272: Communication Module

3274: Memory

3276: Analysis Module

3278: Processor

A-A: Line

D1, D2: distance

T1, T2, T3, T4, T5, T6, T7, T8, T9: Thickness

X, Y, Z: axis

Various aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings.

FIG. 1A shows an isometric view of a semiconductor device in accordance with some embodiments.

1B-1E illustrate cross-sectional views of a semiconductor device having a multi-layer gate cap structure in accordance with some embodiments.

2 is a flowchart of a method for fabricating a semiconductor device having a multi-layer gate cap structure in accordance with some embodiments.

3-27 illustrate cross-sectional views of a semiconductor device at various stages of a fabrication process for a semiconductor device having a multi-layer gate cap structure in accordance with some embodiments.

28 is a flowchart of a method for fabricating a semiconductor device having a multilayer gate cap structure in accordance with some embodiments.

29-31 illustrate cross-sectional views of a semiconductor device at various stages of a fabrication process for a semiconductor device having a multi-layer gate cap structure, according to some embodiments.

32 shows a block diagram of a control system of an atomic layer etch (ALE) system in accordance with some embodiments.

Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings, the same reference numbers generally indicate the same, functionally similar and/or structurally similar elements pieces. The discussion of elements with the same annotation applies to each other unless otherwise mentioned.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the process for forming a first feature over a second feature in the following description may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include the first feature Embodiments in which additional features may be formed with the second feature such that the first feature may not be in direct contact with the second feature. As used herein, forming a first feature on a second feature means that the first feature is formed in direct contact with the second feature. Additionally, the present disclosure may reuse reference numbers and/or letters in various instances. Such repetition is not in itself indicative of a relationship between the embodiments and/or configurations discussed herein.

Also, for ease of description, for example, "beneath", "below", "lower", "above" may be used herein. )", "upper" and other spatially relative terms are used to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It should be noted that references in the specification to "one embodiment," "embodiment," "an example embodiment," "exemplary," etc. indicate that Embodiments may include particular features, structures, or characteristics, but each embodiment does not necessarily include particular features, structures, or characteristics. Furthermore, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure or characteristic is described in connection with one embodiment, whether explicitly stated or not, it would be within the knowledge of those skilled in the art to achieve such feature, structure or characteristic in connection with other embodiments.

It is to be understood that a phrase or phrase herein is used for the purpose of description and not of limitation so that the phrase or phrase of the specification will be interpreted by one skilled in the relevant art in light of the teachings herein.

In some embodiments, the terms "about" and "substantially" may indicate a value of a given amount that is within 5% of the value (eg, ±1% of the value, ±2%, ±3%, ±4%, ±5%). These values are examples only and are not intended to be limiting. The terms "about" and "substantially" can refer to a percentage of a value as interpreted by one skilled in the relevant art in light of the teachings herein.

The fin structures disclosed herein may be patterned by any suitable method. For example, the fin structure may be patterned using one or more photolithography processes, including a dual patterning process or a multi-patterning process. A double-patterning process or a multi-patterning process can combine photolithography with a self-aligned process, such that a pitch will be formed with, for example, smaller pitches than would otherwise be obtainable using a single direct photolithography process picture of. For example, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the fin structures can then be patterned using the remaining spacers.

The present disclosure provides exemplary semiconductor devices (eg, finFETs, gate-all-around (GAA) FETs, and/or MOSFETs) having gate capping structures in the gate structures. In addition, the present disclosure provides exemplary methods of forming such semiconductor devices having reduced contact resistance between gate structures and gate contact structures via a gate A pole cap structure is formed. The gate cap structure improves the conductive interface between the gate structure and the gate contact structure while protecting the integrity of the gate structure during fabrication of the semiconductor device.

In some embodiments, each of the gate structures may include a gate stack with a high dielectric constant (high-k) gate dielectric layer, a work function metal (WFM) ) layer, an oxygen barrier layer and a gate metal filling layer; and a gate top cap structure, which is arranged on the gate stack. In some embodiments, the gate cap structure may include a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The conductive gate cap improves the conductive interface between the gate stack and the gate contact structure to electrically connect the gate stack without directly forming the gate contact structure on or within the gate stack to the gate contact structure. The gate contact structure is not directly formed on or within the gate stack to prevent the gate stack from being affected by the formation of the gate contact structure. Any of the used processing materials is contaminated. Contamination of the gate stack can lead to degradation of device performance. Thus, by using a conductive gate cap, the gate stack can be electrically connected to the gate contact structure without compromising the integrity of the gate structure.

In some embodiments, the insulating gate cap protects the underlying conductive gate cap and gate stack from structural and/or compositional degradation during subsequent processing of the semiconductor device. In some embodiments, the conductive gate cap may include a growth promotion layer (GPL) disposed on the gate stack and an etch stop layer (ESL) disposed on the GPL. GPL and ESL may contain different conductive materials from each other. In addition to providing a conductive interface between the gate stack and the gate contact structure, GPL also provides a surface that facilitates bottom-up deposition of ESL. Without the GPL, ESL may not be selectively deposited on the gate stack and may be deposited on FET structures that may be in contact with subsequently formed adjacent structures such as source/drain /drain, S/D) contact structure) is electrically short-circuited. The GPL may include materials for which the ESL has higher deposition selectivity than one of the materials for the gate stack (eg, the dielectric material of the high-k gate dielectric layer and the dielectric material of the oxygen barrier layer) or deposition selectivity of many. In other words, ESL can be deposited on GPL at a higher rate than on the gate stack. In addition to providing a conductive interface between the gate stack and the gate contact structure, the ESL also controls the depth profile of the gate contact structure and prevents the gate contact structure from extending into the gate stack.

FIG. 1A shows an isometric view of a FET (field effect transistor) 100 in accordance with some embodiments. According to some embodiments, the FET 100 may have different cross-sectional views, as shown in FIGS. 1B-1E . 1B-1E show the FET 100 along the line A-A Cross-sectional view with additional structures not shown in FIG. 1A for simplicity. Unless otherwise mentioned, the discussion of elements in FIGS. 1A-1E with the same annotation applies to each other. In some embodiments, unless otherwise mentioned, FET 100 may represent n-type FET 100 (NFET 100 ) or p-type FET 100 (PFET 100 ) and the discussion of FET 100 applies to both NFET 100 and PFET 100 .

1A, FET 100 may include: an array of gate structures 112A-112C disposed on fin structure 106; and S/D regions 110A-110C (S/D region 110C can be seen in FIG. 1A; 110A-110B 1B-1E), disposed on the portion of the fin structure 106 that is not covered by the gate structures 112A-112C. FET 100 may further include gate spacers 114, shallow trench isolation (STI) regions 116, etch stop layers (ESL) 117A-117B (ESL 117A is not shown in FIGS. 1B-1B for simplicity ; ESL 117B is not shown in FIG. 1A for simplicity, shown in FIG. 1B ) and interlayer dielectric (ILD) layers 118A-118C (ILD layers 118B-118C are not shown in FIG. 1A for simplicity ; shown in Figure 1B to Figure 1E). ILD layer 118A may be disposed on ESL 117A. In some embodiments, gate spacers 114, STI regions 116, ESLs 117A-117B, and ILD layers 118A-118C may include insulating materials such as silicon oxide, silicon nitride (SiN), silicon nitride carbon (SiCN) , silicon oxynitride (SiOCN) and silicon germanium oxide. In some embodiments, gate spacers 114 may have a thickness of about 2 nanometers to about 9 nanometers to sufficiently electrically isolate gate structures 112A-112C from adjacent structures.

FET 100 may be formed on substrate 104 . There may be formed on the substrate 104 other FETs and/or structures (eg, isolation structures) on the . The substrate 104 may be a semiconductor material such as silicon, germanium (Ge), silicon germanium (SiGe), silicon-on-insulator (SOI) structures, and combinations thereof. Additionally, the substrate 104 may be doped with p-type dopants (eg, boron, indium, aluminum, or gallium) or n-type dopants (eg, phosphorus or arsenic). In some embodiments, the fin structure 106 may comprise a material similar to the substrate 104 and extend along the X-axis.

1B, the FET 100 may include: S/D regions 110A to 110B; an S/D contact structure 120 disposed on the S/D regions 110A to 110B; a diffusion barrier layer 128; On structure 120; gate structures 112A to 112C, disposed on fin structure 106; and gate contact structure 154, disposed on gate structures 112A and 112C. Unless otherwise mentioned, the discussion of gate structures 112A-112C applies to each other. In some embodiments, gate structure 112B may be a dummy gate structure and may not be electrically connected to other elements of FET 100 .

For NFET 100, each of S/D regions 110A-110B may include: an epitaxially grown semiconductor material, such as Si; and an n-type dopant, such as phosphorus and other suitable n-type dopants. For PFET 100, each of S/D regions 110A-110B may include: epitaxially grown semiconductor materials, such as Si and SiGe; and p-type dopants, such as boron and other suitable p-type dopants. In some embodiments, each of the S/D contact structures 120 may include: (i) a silicide layer 122 disposed within each of the S/D regions 110A-110B; (ii) an adhesion layer 124 , disposed on the silicide layer 122 ; and (iii) contact plugs 126 , disposed on the adhesive layer 124 .

In some embodiments, for the NFET 100, the silicide layer 122 may include a material having a valence band-edge energy closer to the conduction band-edge energy than the S/D regions 110A-110B ) of the work function value of the metal or metal silicide. For example, the metal or metal silicide may have a work function value of less than 4.5 electron volts (eg, about 3.5 electron volts to about 4.4 electron volts), which may be higher than that of the silicon-based S/D regions 110A-110B The valence band energy of the material (eg, 5.2 electron volts for silicon) is close to the conduction band energy (eg, 4.1 electron volts for silicon). In some embodiments, for the NFET 100, the metal silicide of the silicide layer 122 may include titanium silicide (Ti _x Si _y ), tantalum silicide (T _x Si _y ), molybdenum silicide (Mo _x Si _y ), zirconium silicide ( Zr _x Si _y ), hafnium silicide (Hf _x Si _y ), scandium silicide (Sc _x Si _y ), yttrium silicide (Y _x Si _y ), silicide (Tb _x Si _y ), silicide (Lu _x Si _y ) , erbium silicide (Er _x Si _y ), ytterbium silicide (Yb _x Si _y ), europium silicide ( _{Eux Si y ), thorium silicide (Th x Si y )} , other suitable metal silicide materials, or combinations thereof.

In some embodiments, for PFET 100, silicide layer 122 may comprise a metal or metal silicide having a work function value closer to the valence band edge energy than the conduction band edge energy of the material of S/D regions 110A-110B. For example, the metal or metal silicide may have a work function value greater than 4.5 electron volts (eg, about 4.5 electron volts to about 5.5 electron volts), which may be higher than that of the silicon-based S/D regions 110A-110B The conduction band energy of the material (eg, 4.1 electron volts for silicon) is close to the valence band energy (eg, 5.2 electron volts for silicon). In some embodiments, for PFET 100, the metal silicide of silicide layer 122 may include nickel silicide (Ni _x Si _y ), cobalt silicide (C _x Si _y ), manganese silicide (Mn _x Si _y ), tungsten silicide ( W _x Si _y ), iron silicide (F _x Si _y ), rhodium silicide (Rh _x Si _y ), palladium silicide (Pd _x Si _y ), ruthenium silicide (Ru _x Si _y ), platinum silicide (Pt _x Si _y ) , iridium silicide (Ir _x Si _y ), osmium silicide (Os _x Si _y ), other suitable metal silicide materials, or combinations thereof.

The adhesion layer 124 may facilitate the formation of the contact plugs 126 without voids, and may include metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), and other suitable metal nitride materials. In some embodiments, each of the adhesion layers 124 may include a single layer of metal nitride or may include a stack of metal layers and metal nitride layers. A metal layer can be disposed on the silicide layer 122 and a metal nitride layer can be disposed on the metal layer. In some embodiments, the metal layer may comprise Ti, Ta, or other suitable metal and may comprise the same metal as the metal nitride layer.

The contact plug 126 may comprise a conductive material having a low resistivity (eg, about 50 microohm-cm, about 40 microohm-cm, about 30 microohm-cm, about 20 microohm-cm, or about 10 microohm-cm) Materials such as cobalt (Co), tungsten (W), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), with Other suitable conductive materials of low resistivity, and combinations thereof. The diffusion barrier layer 128 may prevent oxidation of the contact plug 126 by preventing oxygen atoms from diffusing from the ILD layer 118B to the contact plug 126 . In some embodiments, the diffusion barrier layer 128 may include a dielectric nitride, such as silicon nitride _{( SixNy} ), silicon oxynitride (SiON), silicon nitride carbon (SiCN), and other suitable dielectric nitrogens chemical material.

S/D contact structures 120 may be electrically connected to overlying interconnect structures (not shown), power sources (not shown), and/or other elements of FET 100 via vias 130 . The vias 130 may be disposed on the S/D contact structure 120 and may include conductive materials such as Ru, Co, Ni, Al, Mo, W, Ir, Os, Cu, and Pt. In some embodiments, the conductive material of the via 130 is formed by a bottom-up method as detailed below, and thus, the via 130 is formed without an adhesive layer along the sidewalls of the via 130 (also known as a "pad" or "bond layer"). In some embodiments, the via 130 may be formed using a precursor gas of tungsten hexafluoride (WF ₆ ), and thus, the via 130 may include tungsten with fluorine atomic impurities. The concentration of the fluorine atomic impurity in each through hole 130 may be in a range of about 1 atomic percent to about 10 atomic percent of the total atomic concentration in each through hole 130 . In some embodiments, the bottom surface 130b of the via hole 130 may have a curved profile to increase the contact area between the via hole 130 and the contact plug 126 and thus reduce the contact between the via hole 130 and the contact plug 126 resistance. In some embodiments, the vias 130 may have a diameter (or width) in the range of about 10 nanometers to about 20 nanometers along the X-axis, to allow the An optimal contact area is provided between the /D contact structure 120 and the overlying interconnect structure (not shown).

In some embodiments, the vias 130 may be surrounded by the doped regions 131 of the ILD layer 118C. The doped region 131 may contain a dopant with atoms having an atomic radius larger than that of Si atoms in the ILD layer 118C. For example, the ILD layer 118C may include SiO ₂ and the doped regions 131 of the ILD layer 118C may include dopant Ge atoms or other suitable dopant atoms having an atomic radius larger than that of Si atoms. During fabrication of vias 130, dopant atoms are introduced into ILD layer 118C to close any gaps at the interface between vias 130 and ILD layer 118C, as described in detail below. In some embodiments, each of the doped regions 131 may have a dopant concentration ranging from about 1 atomic percent to about 10 atomic percent of the total atomic concentration in the ILD layer 118C for adequate sealing Any gaps at the interface between vias 130 and ILD layer 118C. In some embodiments, the doped regions 131 may extend from the sidewalls 130s of the vias 130 by a distance D1 in the range of about 1 nm to about 60 nm. In other words, the sidewalls 131s of the doped regions 131 are spaced apart from the sidewalls 130s of the through holes 130 by the distance D1. Due to the migration of dopant atoms from the doped region 131, the region of the ILD layer 118C adjacent to the doped region 131 may be undoped or may have less than about 1 atomic percent of the total atomic concentration in the ILD layer 118C dopant concentration.

1B , each of the gate structures 112A-112C may include: a gate stack 132 disposed on the fin structure 106 ; and a gate cap structure 134 disposed on the gate stack 132 . The gate stack 132 may include: (i) an interfacial oxide (IO) layer 136 disposed on the fin structure 106; (ii) a high-k (HK) gate dielectric layer 138 disposed on the On IO layer 136; (iii) WFM layer 140, disposed on HK gate dielectric layer 138; (iv) oxygen barrier layer 142, disposed on WFM layer 140; and (v) gate metal fill layer 144, disposed on the oxygen barrier layer 142 .

In some embodiments, the IO layer 136 may include SiO ₂ , silicon germanium oxide (SiGeO _x ), germanium oxide (GeO _x ), or other suitable oxide materials. In some embodiments, the HK gate dielectric layer 138 may include: (i) a high-k dielectric material such as hafnium oxide (HfO ₂ ), titanium oxide (TiO ₂ ), hafnium zirconium oxide (HfZrO), tantalum oxide ( Ta ₂ O ₃ ), hafnium silicate (HfSiO ₄ ), zirconium oxide (ZrO ₂ ), and zirconium silicate (ZrSiO ₂ ); and (ii) high-k dielectric materials with lithium (Li), beryllium (Be), Magnesium (Mg), Calcium (Ca), Strontium (Sr), Scandium (Sc), Yttrium (Y), Zirconium (Zr), Aluminum (Al), Lanthanum (La), Cerium (Ce), Sodium (Pr), Neodymium (Nd), Samarium (Sm), Europium (Eu), Glybium (Gd), Xtterbium (Tb), Dysprosium (Dy), Y (Ho), Erbium (Er), Ytterbium (Tm), Ytterbium (Yb), (Lu) oxides; (iii) combinations thereof; or (iv) other suitable high-k dielectric materials. As used herein, the term "high-k" refers to a high dielectric constant. In the field of semiconductor device structures and fabrication processes, high-k refers to a dielectric constant greater than that of _SiO2 (eg, greater than 3.9).

For NFET 100, WFM layer 140 may comprise titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al doped Ti, Al doped TiN, Al-doped Ta, Al-doped TaN, other suitable Al-based conductive materials, or combinations thereof. For PFET 100, WFM layer 140 may include a Ti-based or Ta-based nitride or alloy that is substantially free of Al (eg, without Al), such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium gold (Ti-Au) alloy, titanium copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum gold (Ta-Au) alloy, tantalum copper (Ta-Cu) alloy, others Suitable substantially Al-free conductive materials, or combinations thereof.

Oxygen barrier layer 142 may prevent oxidation of WFM layer 140 during processing of overlying layers (eg, gate metal fill layer 144 and/or gate capping structure 134 ), and may include Si, Ge, Ti, Al, Hf, Ta, Ni, Co, silicon oxide (SiO _x ), germanium oxide (GeO _x ), titanium oxide (TiO _x ), aluminum oxide (AlO _x ), hafnium oxide (HfO _x ), tantalum oxide (TaO _x ), nickel oxide (NiO _x ), cobalt oxide (CoO _x ), indium oxide (InO _x ), zinc oxide (ZnO _x ), zirconium oxide (ZrO _x ), magnesium oxide (MgO _x ), or capable of blocking oxygen atoms from diffusing to the WFM layer 140 of other suitable materials. Since the oxidized WFM layer 140 can shift the work function value of the gate stack 132, the WFM layer 140 is prevented from being oxidized, and thus, the threshold voltage of the FET 100 is increased. In some embodiments, the oxygen barrier layer 142 may include a thickness ranging from about 1 nanometer to about 2 nanometers. Below a thickness of 1 nm, the oxygen barrier layer 142 may be insufficient to prevent oxidation of the WFM layer 140 . On the other hand, if the thickness is greater than 2 nm, the volume area of the gate metal filling layer 144 decreases, and thus increases the gate resistance of the gate structures 112A to 112C.

In some embodiments, when the oxygen barrier layer 142 includes a dielectric material and/or an oxide material (eg, _SiOx , _GeOx , _HfOx , _TiOx , _AlOx , _TaOx , _NiOx , _CoOx , _InOx , _ZnOx , _ZrOx , and _MgOx ), or other suitable dielectric materials and/or oxides, the oxygen barrier layer 142 extends over the top surface of the WFM layer 140 and/or the top surface of the gate metal fill layer 144 , as shown in Figure 1B. On the other hand, when the oxygen barrier layer 142 includes metal materials (eg, Ti, Al, Ta, Ni, and Co), or other suitable metal materials, the top surfaces of the oxygen barrier layer 142 and the WFM layer 140 and/or the gate metal The top surfaces of fill layer 144 are substantially coplanar, as shown in FIG. 1C . The planarity of the top surface of the oxygen barrier layer 142 relative to the top surface of the WFM layer 140 and/or the top surface of the gate metal fill layer 144 depends on the relative etch rate, WFM of the material of the oxygen barrier layer 142 during fabrication of the gate stack 132 The relative etch rate of the material of layer 140 and the relative etch rate of the material of gate metal fill layer 144 will be described in detail below.

In some embodiments, the gate metal fill layer 144 may comprise a suitable conductive Electrical materials (such as tungsten (W), titanium (Ti), silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), aluminum (Al), iridium (Ir), Nickel (Ni)), other suitable conductive materials, or combinations thereof. In some embodiments, gate metal fill layer 144 may include a substantially fluorine-free metal layer (eg, fluorine-free W), which may include ions, atoms, and/or The amount of fluorine contaminant in molecular form less than about 5 atomic percent.

In some embodiments, the gate cap structure 134 may include a conductive gate cap 146 disposed on the gate stack 132 and an insulating gate cap 148 disposed on the conductive gate cap 146 . The insulating gate cap 148 protects the underlying conductive gate cap 146 and gate stack 132 from structural and/or compositional degradation during subsequent processing of the semiconductor device. In some embodiments, insulating gate cap 148 may comprise a nitride material, such as silicon nitride, and may have a thickness T1 in the range of about 2 nanometers to about 10 nanometers to adequately protect the underlying Conductive gate cap 146 and gate stack 132 .

The conductive gate cap 146 provides a conductive interface between the gate stack 132 and the gate contact structure 154 to connect the gate without directly forming the gate contact structure 154 on or within the gate stack 132 The pole stack 132 is electrically connected to the gate contact structure 154 . The gate contact structure 154 is not formed directly on or within the gate stack 132 to prevent contamination of the gate stack 132 with any of the processing materials used to form the gate contact structure 154, as will be done below elaborate. Contamination of the gate stack 132 can lead to degradation of device performance. Therefore, by using the conductive gate cap 146, the gate structures 112A-112C can be protected without damaging the gate structures 112A-112C. The gate stack 132 is electrically connected to the gate contact structure 154 under the condition of integrity.

In some embodiments, when the oxygen barrier layer 142 includes a dielectric material and/or oxide, the conductive gate cap 146 may include a growth promoting layer (GPL) 150 disposed on the gate stack 132 and disposed on the GPL 150 an etch stop layer (ESL) 152 on top, as shown in FIG. 1B . The GPL 150 and the ESL 152 may contain different conductive materials from each other. In some embodiments, GPL 150 may include nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), other suitable nitride materials, and its combinations. In some embodiments, ESL 152 may include metallic materials such as W, Ru, Ir, Mo, other suitable metallic materials, and combinations thereof. In some embodiments, the ESL 152 may be formed using a precursor gas of tungsten pentachloride (WCl ₅ ) or tungsten hexachloride (WCl ₆ ), and thus, the ESL 152 may include tungsten with an impurity of chlorine atoms. The concentration of chlorine atomic impurities may range from about 1 atomic percent to about 10 atomic percent of the total atomic concentration in each ESL 152 .

Since the dielectric material and/or oxide material may inhibit bottom-up deposition of metal materials of the ESL 152, when the oxygen barrier layer 142 includes a dielectric material and/or oxide, the GPL 150 may provide a favorable bottom-up ESL 152 is deposited on the surface as shown in Figure IB. In some embodiments, when the oxygen barrier layer 142 includes a metal material, the ESL 152 can be deposited on the gate stack 132 using a bottom-up deposition process without the GPL 150, as shown in FIG. 1C, and ESL 152 may be used as conductive gate cap 146 . The bottom-up deposition process selectively deposits ESL 152 directly or indirectly on gate stack 132 and prevents ESL 152 from being deposited on FET structures such as spacers 114 and ILD layer 118A, which may be related to subsequent Forming Adjacent structures (eg, S/D contact structures 120 ) are electrically shorted.

In addition to providing a conductive interface between gate stack 132 and gate contact structure 154 , ESL 152 can also control the depth profile of gate contact structure 154 and prevent gate contact structure 154 from extending into gate stack 132 . In some embodiments, ESL 152 may have a thickness T5 in a range from about 2 nm to about 15 nm, and gate contact structure 154 may extend into ESL 152 from about 1 nm to about 10 nm A distance D2 in the range of meters is used to adequately control the depth profile of the gate contact structure 154 . To prevent gate contact structure 154 from extending into GPL 150 (FIG. IB) or into gate stack 132 (FIG. 1C), ESL 152 is formed to have a thickness T5 greater than D2.

GPL 150 may include materials, such as nitride materials, for which ESL 152 is more selective for deposition than for dielectric and/or oxide materials for HK gate dielectric layer 138 and oxygen barrier layer 142 . As used herein, the term "deposition selectivity" refers to the ratio of deposition rates on two different materials or surfaces under the same deposition conditions. In some embodiments, GPL 150 may have a non-uniform thickness across the top surface of gate stack 132 . The first portion of GPL 150 on HK gate dielectric layer 138 may have thickness T2, the second portion of GPL 150 on oxygen barrier layer 142 may have thickness T3, thickness T3 may be greater than thickness T2, and the second portion of GPL 150 on oxygen barrier layer 142 may have thickness T3 The gate metal fill layer 144 and the third portion on the WFM layer 140 may have a thickness T4, which may be greater than the thickness T2 to the thickness T3. To sufficiently facilitate bottom-up deposition of ESL 152, thicknesses T2-T4 may range from about 1 nm to about 5 nm.

The gate contact structure 154 may include a pad 156 and a contact plug 158 disposed on the pad 156 . In some embodiments, liner 156 may include a nitride material (eg, TiN), and contact plug 158 may include a conductive material similar to via 130 . In some embodiments, the liner 156 may include a bilayer of Ti and TiN and the contact plug 158 may include W. In some embodiments, the pad 156 may include TaN and the contact plug 158 may include Ru.

In some embodiments, instead of vias 130 over S/D regions 110B and gate contact structures 154 over gate structures 112C, fused via-contacts are provided over S/D regions 110B and gate structures 112C Structure 160, as shown in Figure ID. When the FET 100 is formed in the logic device region and/or the static random access memory (SRAM) device region of an integrated circuit (not shown), the fused via-contact structure 160 will S/D The region 110B and the gate structure 112C are electrically connected to each other and to the overlying interconnect structure (not shown). The fused via-contact structure 160 may include a pad 162 and a contact plug 164 disposed on the pad 162 . In some embodiments, liner 162 and contact plug 164 may comprise similar materials to liner 156 and contact plug 158, respectively.

In some embodiments, referring to FIG. 1E , gate contact structure 154 , gate cap structure 134 , and fused via-contact structure 160 may have cross-sectional views different from the cross-sectional views shown in FIGS. 1B-1D . In some embodiments, instead of the substantially coplanar top surface of GPL 150 shown in Figures IB and ID, GPL 150 may have a non-coplanar top surface with raised edges, as shown in Figure IE. In some embodiments, a portion of the fused via-contact structure 160 may be disposed on the gate structure 112B, such as shown in Figure 1E.

FIG. 2 is a flowchart of an exemplary method 200 for fabricating the FET 100 having the cross-sectional view shown in FIG. 1B in accordance with some embodiments. For illustrative purposes, the operations shown in FIG. 2 will be explained with reference to an exemplary fabrication process for fabricating FET 100 as shown in FIGS. 3-27 . 3-27 are cross-sectional views of FET 100 along line A-A shown in FIG. 1A at various stages of fabrication, in accordance with some embodiments. Depending on the application, the operations may or may not be performed in a different order. It should be noted that method 200 may not result in a complete FET 100 . Accordingly, it should be understood that additional processes may be provided before, during, and after method 200, and that some other processes may only be briefly described herein. Elements in FIGS. 3-27 have the same annotations as those in FIGS. 1A-1E as described above.

In operation 205, polysilicon structures and S/D regions are formed on the fin structures on the substrate. For example, as shown in FIG. 3 , a polysilicon structure 312 and S/D regions 110A- 110B are formed on the fin structure 106 , which is formed on the substrate 104 . During subsequent processing, the polysilicon structure 312 may be replaced in a gate replacement process to form the gate structures 112A-112C. After forming S/D regions 110A-110C, ESL 117A (shown in FIG. 1A ; not shown in FIGS. 3-27 for simplicity) and ILD layer 118A may be formed to form the structure shown in FIG. 3 .

Referring to FIG. 2, in operation 210, the polysilicon structure is replaced with a gate stack. For example, as described with reference to FIGS. 4-5 , the polysilicon structure 312 is replaced with the gate stack 132 . The formation of gate stack 132 may include the following sequential operations: (i) utilizing the layers of gate stack 132 - IO layer 136, HK gate dielectric layer 138, WFM layer 140, oxygen barrier layer 142, and gate metal fill layer 144—replacement polysilicon structure 312, as shown in FIG. 4; and (ii) etching the layers of gate stack 132 to form gate cap opening 566, as in shown in Figure 5.

Referring to FIG. 2, in operation 215, a GPL of a gate cap structure is formed on the gate stack. For example, as described with reference to FIGS. 6-9 , GPL 150 is formed on gate stack 132 . Formation of GPL 150 may include the following sequential operations: (i) forming metal nitride layer 650 on the structure shown in FIG. 5 , as shown in FIG. 6 ; (ii) having gate cap opening 566 on metal nitride layer 650 A mask layer 768 (eg, a photoresist layer or an anti-reflection coating) is formed on the portion of the compound layer 850, the top surface of the metal nitride layer 850 is substantially coplanar with the top surface of the gate spacer 114 and the top surface of the mask layer 768, as shown in FIG. 8; (iv) from FIG. 8 and (v) selectively etching the sidewall portion of the metal nitride layer 850 extending over the surface 850s of the structure shown in FIG. 8 to form the GPL 150, as shown in FIG. 9 .

The formation of metal nitride layer 650 may include the following sequential operations: (i) depositing a metal layer (not shown) on the structure shown in FIG. 5 using a directional deposition process, such as a physical vapor deposition (PVD) process and other suitable directional deposition processes. shown); and (ii) performing a nitridation process on the deposited metal layer using ammonia (NH ₃ ) or nitrogen. The metal nitride layer 650 is formed along the sidewall of the gate cap opening 566 to a thickness T6, and is formed on the gate metal filling layer 144 to a thickness T7, which is greater than the thickness T6. Portions of metal nitride layer 650 along the sidewalls of gate cap opening 566 are formed thinner than portions on gate metal fill layer 144 to facilitate selective removal of the portions along the sidewalls.

Selectively etching the sidewall portions of the metal nitride layer 850 may include etching using an atomic layer etch (ALE) process using _WC15 gas, _O2 gas, and argon or other suitable gases. In some embodiments, each cycle of the ALE process may include sequential cycles of: (i) a first etch gas (eg, _WCl5 ) flow; (ii) a first cleaning process with argon; (iii) a first Two etch gas (eg, O ₂ ) gas flows; and (iv) a second purge process with argon. In some embodiments, an ALE process for etching sidewall portions may include the following sequential operations: (i) predicting an etch recipe using the training module 3270 of the ALE control system 3200 shown in FIG. 32; (ii) based on The predicted etching recipe, using the communication module 3272 of the ALE control system 3200 to adjust the process parameters of the etching equipment (not shown); (iii) using the etching equipment to etch the sidewall portion based on the adjusted process parameters; (iv) Use a measurement system (not shown) to measure the thickness of the remaining sidewall portion; (v) send the measurement data to the memory 3274 of the ALE control system 3200; (vi) use the analysis module 3276 of the ALE control system 3200 to Analyze the measurement data to determine whether the thickness of the remaining sidewall portion is equal to about zero nanometers; and (vii) if the thickness is equal to about zero nanometers, use the processor 3278 and/or the communication module 3272 of the ALE control system 3200 to end The etching process in the etching apparatus, or operations (i) through (vi), are repeated until the thickness is equal to about zero nanometers and the GPL 150 is formed, as shown in FIG. 9 . In some embodiments, the training module 3270, the communication module 3272, the memory 3274, the analysis module 3276, and the processor 3278 are wired or wirelessly connected to each other. In some embodiments, the adjustment of process parameters of the etching apparatus may include adjustment of etching duration, etching gas flow, and/or etching temperature.

Using the ALE control system 3200 to predict the etch recipe may include executing a computational program to: (i) analyze etch process data collected from previous etch processes performed on other structures using the etch equipment; and (ii) based on the analysis data to predict etch process characteristics (eg, etch rate, etch duration) that are used to take advantage of different etch process parameters (eg, ampoule life, temperature and humidity in the etch chamber, light absorption or reflection in the etch chamber) , the pressure in the etching chamber, the carrier gas conditions, the length of the etching gas supply pipe, etc.) to etch the sidewall portion. The computer program may include one or more mathematical operations, pattern recognition programs, big data mining programs, or machine learning programs (eg, neural network road algorithms) to analyze etch process data (eg, ampoule lifetime, etch chamber lifetime, effective etch density, Effective etching area size, etching gas parameters, etc.) and predict etching process characteristics. Similarly, analysis of measurement data using ALE control system 3200 may include executing computational routines. In some embodiments, the portion of metal nitride layer 850 on gate stack 132 may be etched during the ALE process and may be thinned to thickness T4, as shown in FIG. 9 .

Referring to FIG. 2, in operation 220, an ESL of the gate cap structure is formed on the GPL. For example, as shown in FIG. 10 , ESL 152 is formed on GPL 150 . In some embodiments, the formation of ESL 152 can include utilizing a WCl precursor using a temperature in a range from about 300°C to about ₅₅₀ °C and a pressure in a range from about 15 torr to about 40 torr A gas-based bottom-up deposition process deposits about 3 nm to about 5 nm of a fluorine-free W layer on GPL 150 . Other thickness, temperature and pressure ranges are within the scope of this disclosure. The use of fluorine-free W for the ESL 152 prevents the degradation of the underlying gate stack 132 caused by fluorine contamination.

Referring to FIG. 2, in operation 225, an insulating gate cap of a gate cap structure is formed on the ESL. For example, as shown in FIG. 11 , an insulating gate cap 148 is formed on the ESL 152 . The formation of insulating gate cap 148 may include the following sequential operations: (i) depositing an insulating nitride layer (not shown) on the structure shown in FIG. 10; and (ii) chemical mechanical polishing of the insulating nitride layer polish, CMP) process to form the structure shown in FIG. 11 . After the insulating gate cap 148 is formed, the ILD layer 118B may be formed on the structure shown in FIG. 11 .

Referring to FIG. 2, in operation 230, an S/D contact structure is formed on the S/D region. For example, as described with reference to FIGS. 12 to 20 , the S/D contact structure 120 is formed on the S/D regions 110A to 110B. The formation of S/D contact structure 120 may include the following sequential operations: (i) forming contact openings 1280 on S/D regions 110A-110B by ILD layers 118A-118B, as shown in FIG. 12; (ii) in FIG. A dielectric nitride layer 1328 is deposited on the structure shown in 12, as shown in FIG. 13; (iii) from the top surface of the ILD layer 118B and the top surface of the S/D regions 110A-110B to the portion of the dielectric nitride layer 1328 Etching is selectively performed to form diffusion barrier layer 128, as shown in FIG. 14; (iv) silicide layer 122 is formed in S/D regions 110A to 110B, as shown in FIG. 14; (v) in FIG. A metal layer (not shown) is deposited on the structure shown in 14; (vi) a nitridation process is performed on the deposited metal layer using ammonia ( _NH3 ) or nitrogen gas to form a metal nitride layer 1524, as shown in FIG. 15; ( vii) forming a mask layer 1582 (eg, a photoresist layer or an anti-reflection coating) on the portion of the metal nitride layer 1524 within the contact opening 1280, with the top surface of the mask layer 1582 and the top surface of the ILD layer 118B substantially coplanar, as shown in FIG. 15; (viii) etching portions of metal nitride layer 1524 from the top surface of ILD layer 118B to form metal nitride layer 1624, as shown in FIG. 16; (ix) ) remove mask layer 1582, as shown in FIG. 16; (ix) selectively etch sidewall portions of metal nitride layer 1624 using an ALE process similar to the ALE process described in operation 215 to form metal nitride layer 1724, as shown in FIG. 17; (x) performing a cleaning process (eg, a fluorine-based dry etch process) on the structure shown in FIG. 17 to remove native oxide from the top surface of metal nitride layer 1724; ( xi) depositing a metal nitride layer 1824 on the cleaned structure shown in FIG. 17, as shown in FIG. 18; (xii) depositing a metal layer 1826 on the metal nitride layer 1824, as shown in FIG. 18; (xiii) ) depositing a metal layer 1926 on the structure shown in FIG. 18 to form the structure shown in FIG. 19; and (xiv) performing a CMP process on the structure shown in FIG. 19 to form the adhesion layer 124 and the contact plug 126, as shown in FIG. 20 shown. Adhesion layer 124 is formed with dual metal nitride layers 1724 and 1824 to form a base portion having thickness T8 on silicide layer 122, the base portion being thicker than the sidewall portion having thickness T9, as shown in FIG. 20 .

In some embodiments, the metal nitride layer 1824 may be deposited to have a thickness of about 1 nanometer to about 2 nanometers using an ALD process conducted at a temperature of about 400°C to about 450°C. Other thicknesses and temperature ranges are within the scope of this disclosure. In some embodiments, metal nitride layer 1824 may include a metal similar to or different from that included in metal nitride layer 1724 . In some embodiments, metal layer 1826 may include a metal similar to or different from that included in metal layer 1926 . in forming After the S/D contact structure 120, an ESL 117B may be formed on the structure shown in FIG. 20 and an ILD layer 118C may be formed on the ESL 117B.

Referring to FIG. 2, in operation 235, vias are formed on the S/D contact structure. For example, as described with reference to FIGS. 21 to 25 , vias 130 are formed on the S/D contact structure 120 . The formation of vias 130 may include the following sequential operations: (i) forming via openings 2184 on contact plugs 126 using an isotropic etching process, as shown in FIG. 21 ; (ii) depositing metal within via openings 2184 layer 2230, as shown in FIG. 22; (iii) depositing an adhesive layer 2386 substantially conformally on the structure shown in FIG. 22, as shown in FIG. 23; (iv) depositing a metal layer 2388 on the adhesive layer 2386, As shown in FIG. 23; (v) performing a CMP process on the structure shown in FIG. 23 to form the vias 130, as shown in FIG. 24; (vi) forming a patterned mask layer 2590 on the structure shown in FIG. 24 (eg, a photoresist layer), as shown in FIG. 25; (vii) doped regions 131 are formed by implanting dopants through openings 2592 in patterned mask layer 2590, as shown in FIG. 25 and (vii) removing the patterned mask layer 2590.

In some embodiments, bottom _- up deposition with WF and H precursor gases at temperatures between about ₂₅₀ °C to about 300°C and pressures between about 2 Torr and about 10 Torr may be used process to deposit the metal layer 2230. Other thickness, temperature and pressure ranges are within the scope of this disclosure. The subbing layer 2386 can be deposited using _WF and H precursor gases at a temperature in a range of about ₂₅₀ ° C. to about 300° C. and a pressure in a range of about 2 Torr to about 10 Torr to facilitate having Deposition of metal layer 2388 having a thickness in the range of about 3 nanometers to about 5 nanometers. Other thickness, temperature and pressure ranges are within the scope of this disclosure.

Referring to FIG. 2, in operation 240, a gate contact structure is formed on the gate structure. For example, as described with reference to FIGS. 26-27 , gate contact structures 154 are formed on gate structures 112A-112B. Formation of gate contact structure 154 may include the following sequential operations: (i) forming contact openings 2694 extending into ESL 152, as shown in FIG. 26; (ii) depositing material for liner 156 on the structure shown in FIG. 26 (iii) depositing contact plug 158 material on the liner 156 deposition material; and (iv) performing a CMP process on the liner 156 deposition material and the contact plug 158 deposition material to form the liner 156 and contact Plug 158 , as shown in FIG. 27 .

28 is a flowchart of an exemplary method 2800 for fabricating the FET 100 having the cross-sectional view shown in FIG. ID, according to some embodiments. For illustrative purposes, the operations shown in FIG. 28 will be explained with reference to an exemplary fabrication process for fabricating FET 100 as shown in FIGS. 3-25 and 29-31 . 3-25 and 29-31 are cross-sectional views of FET 100 along line A-A shown in FIG. 1A at various stages of fabrication, according to some embodiments. Depending on the application, the operations may or may not be performed in a different order. It should be noted that method 2800 may not result in a complete FET 100 . Accordingly, it should be understood that additional processes may be provided before, during, and after method 2800, and that some other processes may only be briefly described herein. Elements in FIGS. 3-25 and 29-31 have the same annotations as those in FIGS. 1A-1E as described above.

Referring to FIG. 28 , operations 2805 to 2830 are similar to operations 205 to 230 shown in FIG. 2 . After operation 2830, a structure similar to that shown in FIG. 20 is formed.

28, in operation 2835, the first in the S/D contact structure Vias are formed on the S/D contact structure. For example, as shown in FIG. 29, a via 130 having a surrounding doped region 131 is formed on the S/D contact structure 120 formed on the S/D region 110A. Vias 130 and doped regions 131 may be formed in operations similar to operation 235 .

Referring to FIG. 28, in operation 2840, a gate contact structure is formed on a first gate structure of the gate structures and a second S/D contact structure and a second one of the gate structures are formed on the S/D contact structure A fused via-contact structure is formed on the gate structure. For example, as described with reference to FIGS. 30-31 , the gate contact structure 154 and the fused via-contact structure 160 are formed simultaneously. Formation of gate contact structure 154 and fused via-contact structure 160 may include the following sequential operations: (i) forming contact openings 2694 and 3094, as shown in FIG. 30; (ii) depositing a liner on the structure shown in FIG. 30 material for pads 156 and 162; (iii) material for depositing contact plugs 158 and 164 on the deposition material for pads 156 and 162; and (iv) deposition material for pads 156 and 162 and contact plugs 158 and 164 A CMP process is performed to form pads 156 and 162 and contact plugs 158 and 164 as shown in FIG. 31 .

The present disclosure provides exemplary semiconductor devices (eg, finFETs, gate-all-around (GAA) FETs, and/or MOSFETs) having gate cap structures (in gate structures). In addition, the present disclosure provides exemplary methods of forming such semiconductor devices having reduced contact resistance between gate structures and gate contact structures via a gate A pole cap structure is formed. The gate cap structure provides a conductive interface between the gate structure and the gate contact structure while protecting the integrity of the gate structure during fabrication of the semiconductor device.

In some embodiments, each of the gate structures can include a gate stack having a high-k gate dielectric layer, a work function metal (WFM) layer, an oxygen barrier layer, and a gate metal fill Floor. In some embodiments, the gate cap structure may include a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The conductive gate cap provides a conductive interface between the gate stack and the gate contact structure to electrically connect the gate stack to the gate stack without directly forming the gate contact structure on or within the gate stack gate contact structure. The gate contact structure is not formed directly on or within the gate stack to prevent contamination of the gate stack with any of the processing materials used in forming the gate contact structure. Contamination of the gate stack can lead to degradation of device performance. Thus, by using a conductive gate cap, the gate stack can be electrically connected to the gate contact structure without compromising the integrity of the gate structure.

In some embodiments, the insulating gate cap protects the underlying conductive gate cap and gate stack from structural and/or compositional degradation during subsequent processing of the semiconductor device. In some embodiments, the conductive gate cap may include a growth promotion layer (GPL) disposed on the gate stack and an etch stop layer (ESL) disposed on the GPL. GPL and ESL may contain different conductive materials from each other. In addition to providing a conductive interface between the gate stack and the gate contact structure, GPL also provides a surface that facilitates bottom-up deposition of ESL. Without GPL, ESL may not be selectively deposited on the gate stack and may be deposited on FET structures that may be /D) Contact structure) electrical short circuit. The GPL may contain the following materials: ESL's sinking of said materials The active selectivity is higher than the deposition selectivity to one or more of the materials of the gate stack (eg, the dielectric material of the high-k gate dielectric layer and the dielectric material of the oxygen barrier layer). In other words, ESL can be deposited on GPL at a higher rate than on the gate stack. In addition to providing a conductive interface between the gate stack and the gate contact structure, the ESL also controls the depth profile of the gate contact structure and prevents the gate contact structure from extending into the gate stack.

In some embodiments, a semiconductor device includes: a substrate; a fin structure disposed on the substrate; a source/drain (S/D) region disposed on the fin structure; and a gate structure, and the The S/D regions are adjacently disposed on the fin structure. The gate structure includes a gate stack disposed on the fin structure and a gate cap structure disposed on the gate stack. The gate cap structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed on the gate stack. A portion of the first contact structure is disposed within the gate cap structure and is separated from the gate stack by a portion of the conductive gate cap.

In some embodiments, a semiconductor device includes: a substrate; a fin structure disposed on the substrate; a first source/drain (S/D) region and a second source/drain region disposed on the substrate on the fin structure; a first S/D contact structure and a second S/D contact structure, respectively disposed on the first S/D region and the second S/D region; and a first gate structure and a first gate structure A two-gate structure is disposed on the fin structure. Each of the first gate structure and the second gate structure includes a gate stack and a gate cap structure including a conductive gate cap and an insulating gate cap. the half The conductor arrangement further includes a fused via-contact structure disposed over the first S/D contact structure and over the gate stack of the first gate structure. A portion of the fused via-contact structure is disposed within the gate cap structure of the first gate structure.

In some embodiments, a method includes: forming a fin structure on a substrate; forming source/drain (S/D) regions on the fin structure; forming a polysilicon structure on the fin structure; utilizing a gate stack replacing the polysilicon structure; forming a conductive gate cap on the gate stack; forming an insulating gate cap on the gate stack; forming a contact structure on the S/D region; and forming the contact A via is formed on the structure, wherein the forming the via includes forming a doped region surrounding the via.

The foregoing disclosure outlines features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the embodiments described herein Same advantages. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and change.

100: FET/NFET/PFET

104: Substrate

106: Fin Structure

110A, 110B: S/D area

112A, 112B, 112C: gate structure

114: Gate spacer/spacer

117B, 152: Etch Stop Layer (ESL)

118B, 118C: Interlayer dielectric (ILD) layers

120:S/D contact structure

122: silicide layer

124: Adhesive layer

126: Contact plug

128: Diffusion barrier layer

130: Through hole

130b: Bottom surface

130s, 131s: Sidewalls

131: Doping region

132: Gate stack

134: Gate top cover structure

136: Interface oxide (IO) layer

138: High-k (HK) gate dielectric

140:WFM layer

142: Oxygen barrier layer

144: gate metal filling layer

146: Conductive gate top cover

148: Insulated gate top cover

150: Growth Promotion Layer (GPL)

154: Gate Contact Structure

156: Padding

158: Contact Plug

D1, D2: distance

T1, T2, T3, T4, T5: Thickness

X, Y, Z: axis

Claims (8)

A semiconductor device, comprising: a substrate; a fin structure disposed on the substrate; a source/drain (S/D) region disposed on the fin structure; a gate structure and the source/drain A region is disposed adjacently on the fin structure, wherein the gate structure includes a gate stack disposed on the fin structure and a gate cap structure disposed on the gate stack, and wherein the gate The pole top cover structure includes a conductive gate top cover disposed on the gate stack and an insulating gate top cover disposed on the conductive gate top cover, and the conductive gate top cover includes a conductive gate top cover disposed on the gate electrode a growth promotion layer (GPL) on the stack and an etch stop layer (ESL) disposed on the growth promotion layer; and a first contact structure disposed over the gate stack, wherein the first contact structure has A portion is disposed within the gate cap structure and is separated from the gate stack by a portion of the conductive gate cap. The semiconductor device of claim 1, wherein the portion of the first contact structure is disposed within the etch stop layer. The semiconductor device of claim 1, wherein the portion of the first contact structure is separated from the gate stack by a portion of the growth promoting layer or the etch stop layer. A semiconductor device, comprising: a substrate; a fin structure arranged on the substrate; a first source/drain (S/D) region and a second source/drain region arranged on the fin structure; a first source/drain contact structure and a second source/drain contact structure, respectively disposed on the first source/drain region and the second source/drain region; the first gate structure and the second gate structure, set On the fin structure, wherein each of the first gate structure and the second gate structure includes a gate stack and a gate cap structure, the gate cap structure includes a conductive gate cap and an insulating gate cap, and the conductive gate cap includes a growth promotion layer (GPL) disposed on the gate stack and an etch stop layer (ESL) disposed on the growth promotion layer; and a fusion pass a hole-contact structure disposed on the first source/drain contact structure and on the gate stack of the first gate structure, wherein a portion of the fused via-contact structure is disposed on the first gate structure inside the gate cap structure of the first gate structure. The semiconductor device of claim 4, further comprising: an interlayer dielectric (ILD) layer disposed on the first source/drain contact structure and the second source/drain contact structure; doping a region located in the interlayer dielectric layer; and a via hole disposed on the second source/drain contact structure and surrounded by the doped region. The semiconductor device according to claim 4, further comprising: A gate contact structure over the gate stack of a second gate structure, wherein a portion of the gate contact structure is disposed within the gate cap structure of the second gate structure. A method for forming a semiconductor device, comprising: forming a fin structure on a substrate; forming a source/drain (S/D) region on the fin structure; forming a polysilicon structure on the fin structure; the polysilicon structure; forming a conductive gate cap on the gate stack, wherein forming the conductive gate cap comprises: forming a growth promotion layer (GPL) on the gate stack; and on the growing forming an etch stop layer (ESL) on a facilitation layer; forming an insulating gate cap on the gate stack; forming a contact structure on the source/drain regions; and forming a via on the contact structure, wherein The forming the through hole includes forming a doped region surrounding the through hole. The method of claim 7, wherein the forming the conductive gate cap comprises: depositing a metal nitride layer on the gate stack; etching sidewall portions of the metal nitride layer to form the and depositing a metal layer on the metal nitride layer to form the etch stop layer.

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