TWI777598B - Software/firmware protection system - Google Patents

Abstract

The program protection system provided by the present invention is based on a self-defined instruction set architecture, records the generated hardware description file into a logic device, and generates a assembler based on the instruction set architecture at the same time, After the program group is translated into machine code by the set of compilers, it is executed by the logic device, and the instruction set structure is not disclosed, so that even if the machine code of the program is hacked, hacking It is also impossible to reverse the function of analyzing the machine code, so as to ensure the security of the program.

Description

program protection system

The present invention relates to the security protection of computer equipment, in particular to a program protection system.

In the prior art, for the protection means of programs such as software (software) and firmware (firmware), the packing technology is generally used to achieve the purpose of protection, so as to prevent external reverse analysis. The program still needs to be restored in the memory when it is executed before it can be executed. It is difficult to avoid the external use of dynamic reverse assembly to obtain the function corresponding to the machine code in the memory, which makes the protection effect of the packing technology difficult to play. .

In order to prevent the machine code of the program from being deciphered by reverse assembly, in the Chinese Patent Publication No. 112394943A, it is disclosed that the virtual machine technology is used to define the mapping relationship between the virtual machine instructions and the machine instructions, so that the instruction set The instruction function disclosed by the architecture is different from the instruction function executed by the virtual machine, thereby ensuring the security of the program running in the virtual machine.

Through virtual machine technology, it is possible to avoid decomposing and deciphering machine code based on instruction set architecture. However, since the operation of virtual machine requires certain basic resource support, it is difficult to be widely used, especially for the lack of basic resources. For embedded systems, the technology that can protect programs through virtual machines is difficult to apply.

Therefore, the main purpose of the present invention is to provide a program protection system, which makes the machine code after the program is assembled and translated does not correspond to the disclosed instruction set structure, so that the machine code of the program obtained from the outside cannot be obtained locally. Decompiled by the public instruction set architecture to ensure the safety of the program.

The reason is that, in order to achieve the above-mentioned purpose, the program protection system provided by the present invention is based on a self-defined instruction set architecture (Instruction Set Architecture, ISA), and records the generated hardware description file into a logical device , at the same time, a assembler is generated based on the instruction set architecture, and after the assembler interprets the program assembly into machine code, it is executed by the logic device, and the instruction set architecture is not disclosed, Therefore, even if the machine code of the program is hacked, the hacker cannot reverse the function of analyzing the machine code, thereby ensuring the security of the program.

Wherein, the logic device may be a Field Programmable Gate Array (FPGA).

Since the logic resources of logic devices such as field programmable logic gate arrays are limited, in order to effectively utilize the resources, another technical feature of the present invention is to use the hardware description file generated based on the instruction set architecture. Both the assembler and the assembler are limited to the instructions required by the program, and do not include functional blocks that are not used by the program, so as to ensure the efficient use of the resources of the logic device.

Hereby, a preferred embodiment of the present invention is used to illustrate the technical features of this case, wherein, the technical content known to the common knowledge in the technical field of the present invention will not be described in this embodiment, and this implementation The experimental examples exemplified are also only used to illustrate the specific examples that the present invention can be implemented, and should not be used to limit the scope of protection of the present invention.

The program protection system provided in this embodiment includes an unpublished instruction set architecture (Instruction Set Architecture, ISA) description text file. After reading and analyzing the description text file, it is stored on a system platform. A data structure table of the instruction set architecture is established, a hardware description file is generated according to the data structure table, and the hardware description file is recorded into a logic device.

Using the data structure table as an input, the data structure table is embedded in a preset assembler program template to generate a set of interpreters accordingly.

The program planned to be executed on the system platform can be translated into machine code through the assembler group, and downloaded into the memory of the logic device as an instruction source for the logic device to perform logic operations.

Therefore, even if the machine code recorded in the memory of the logic device is hacked, the function blocks corresponding to the machine code cannot be reversely analyzed through the public instruction set architecture, so as to ensure the security of the program. And prevent the program from being tampered with.

On the basis of the above-mentioned embodiment, a specific experimental example is further described.

First of all, the description text file of the instruction set architecture, which is the basis of the present invention, in this experimental example, part of the content is illustrated in the following table 1, including the instruction name (memo), the operation code (OP-code) and the instruction type.

Table I

After the description text file is read and analyzed, the data structure table established on the system platform is shown in Table 2, but what should be pointed out is that what is shown in Table 2 only corresponds to the part exemplified in Table 1 , not all of the instruction set architectures.

Table II command name OP-code Instruction type LD 0x00 5 ST 0x01 5 LDB 0x02 5 STB 0x03 5 LDR 0x04 6 … … …

Next, convert the data structure table shown in Table 2 into a hardware description file, and the conversion can be performed by using a hardware description language such as verilog to generate the hardware description file shown in Table 3 below.

Table 3

The completed hardware description file as shown in Table 3 is compiled and programmed into a logic device such as a Field Programmable Gate Array (FPGA), so that the logic device can be configured as a custom logic process device.

Further, this experimental example uses the data structure table shown in Table 2 as input, and embeds it into the default assembler program template, so as to create the assembler code that conforms to the instruction set architecture, and then generates it through compiling. The executable file of the assembler, whereby the program to be run by the custom logical processor can be used as the input of the assembler to be assembled into machine code, as shown in Table 4 below. Take the assembly language program as an example, the machine code assembled by the assembly compiler is shown in Table 5.

Table 4

Table 5

The assembled machine code can be downloaded into the memory of the customized logical processor for execution.

In this experimental example, the machine code illustrated in Table 5 can only run normally on the system platform of the custom logic processor, so even if it is stolen, it cannot be executed by a platform other than the custom logic processor. At the same time, it is impossible to parse the functions, functions and other information corresponding to the machine codes through the public instruction set architecture, so as to ensure the security of the program.

Furthermore, as far as the logic devices such as the field programmable logic gate array used in the above-mentioned experimental example are concerned, their own resources are far less than those of general-purpose logic processors. Therefore, in order to effectively utilize the limited resources , for example, the set of instructions required by the program shown in Table 4 can be limited, and only the corresponding set of instructions in the instruction set architecture can be established as the data structure table of the instruction set architecture, so that the established The data structure table is only a subset of the instruction set architecture, removing redundant function blocks that are not required by the program, thereby ensuring the effective use of limited data, so that the remaining resources can be reserved for other functions. The invention may be particularly suitable for application in resource-limited embedded systems.

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Claims (5)

A program protection system, comprising: a description text file of an undisclosed and self-defined instruction set architecture; creating a data structure table with the description text file of the instruction set architecture, and the process of constructing the data structure table does not include Not jumping or changing the execution order of the description file; generating a hardware description file according to the data structure table, and recording the hardware description file into a logic device; generating a set of translators according to the data structure table; A program is translated into machine code by the compiler and loaded into the memory of the logic device. The program protection system of claim 1, wherein the logic device is a field programmable logic gate array. The program protection system of claim 1 or 2, wherein the instruction set of the data structure table is a subset of the instruction set architecture. The program protection system as claimed in claim 3, wherein the data structure table is created with the instruction required by the program as the optional object, and the instruction set architecture is created by the instruction set corresponding to the optional object. The program protection system of claim 1, wherein the program is firmware.