TWI776580B - Adders, arithmetic circuits, chips and computing devices - Google Patents

Abstract

The present disclosure relates to adders, arithmetic circuits, chips, and computing devices. An adder is disclosed for calculating the sum of two numbers of inputs, the adder has two inputs representing the two numbers respectively, each input is divided into a plurality of sub-parts corresponding to each other, and the plurality of sub-parts are from low-order to high-order In order to represent the partial bits of the input, the adder includes: a plurality of first-stage addition modules, each of which is used to sum corresponding subsections of the two inputs; a plurality of intermediate registers, each of which is coupled to the corresponding first-stage an addition module for storing the sum of the corresponding subsections of the two inputs; one or more carry registers, each coupled to the corresponding first-level addition module, for storing the carry of the corresponding subsections of the two inputs; and a second stage addition module coupled to the plurality of intermediate registers and one or more carry registers for summing the sum from each intermediate register with the carry from the corresponding preceding carry register.

Description

Adders, arithmetic circuits, chips and computing devices

The present disclosure generally relates to digital circuits. Specifically, it relates to an adder, an arithmetic circuit including the adder, and a chip and a computing device.

Adders, which are used to perform addition operations, are an important part of many arithmetic circuits. In the related art, if the operation speed of the adder needs to be improved, a high-speed device is usually used to realize the adder.

According to one aspect of the present disclosure, there is provided an adder for calculating the sum of two numbers of an input, the adder having two inputs respectively representing the two numbers, wherein each input is corresponding to each other Divided into a plurality of sub-parts, the plurality of sub-parts represent partial bits of the input sequentially from low bits to high bits, and the adder includes: a plurality of first-stage addition modules, each first-stage addition module is used to The corresponding subsections of the two inputs are summed; a plurality of intermediate registers, each of which is coupled to a corresponding first-stage addition module, is used to store the sum of the corresponding subsections of the two inputs; one or a plurality of carry registers, each carry register coupled to a corresponding first stage addition module for storing carry bits of corresponding sub-portions of the two inputs; and a second stage addition module coupled to the plurality of intermediate A register and the one or more carry registers for summing the sum from each intermediate register with the carry from the corresponding preceding carry register.

According to another aspect of the present disclosure, there is provided an adder for calculating the sum of a number of an input and a predetermined constant, the adder having an input representing the number, the input divided into a plurality of sub-numbers part, the plurality of sub-parts sequentially represent partial bits of the input from low bits to high bits, and the adder includes: one or more first-stage addition modules, each first-stage addition module is used for adding the input to the input. The corresponding subsections of the input are summed with the corresponding bits of the constant; a plurality of intermediate registers, each of which is coupled to the corresponding first-level addition module, is used to store the corresponding subsections of the input and the constants. a sum of corresponding bits; one or more carry registers, each of which is coupled to a corresponding first-stage addition module, for storing the carry of the corresponding subsection of the input and the corresponding bit of the constant; and A second-level addition module, coupled to the plurality of intermediate registers and the one or more carry registers, for summing the sum from each intermediate register with the carry from the corresponding preceding carry register.

According to another aspect of the present disclosure, there is provided an arithmetic circuit comprising an adder as described above; and a pre-combination logic module coupled to an input of the adder and a pre-combination logic module coupled to an output of the adder at least one of the post-combination logic modules.

According to another aspect of the present disclosure, there is provided a wafer including the arithmetic circuit as described above.

According to yet another aspect of the present disclosure, there is provided a computing device comprising a wafer as described above.

Other features of the present disclosure and advantages thereof will become more apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings.

Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application or uses in any way. That is, the structures and methods herein are shown by way of example to illustrate various embodiments of the structures and methods in the present disclosure. Those skilled in the art will appreciate, however, that they are merely illustrative, and not exhaustive, of the ways in which the disclosure may be practiced. Furthermore, the drawings are not necessarily to scale and some features may be exaggerated to show details of particular components.

Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the authorized description.

In all examples shown and discussed herein, any specific value should be construed as illustrative only and not as limiting. Accordingly, other examples of exemplary embodiments may have different values.

In the related art, if the operation speed of the adder needs to be improved, a high-speed device is usually used to realize the adder. However, high-speed devices have larger areas and higher power consumption, which lead to corresponding increases in the area and power consumption of the adder and the operation circuit including the adder, which significantly increases the manufacturing cost and power consumption of the chip. Therefore, it is desired to increase the operation speed of the adder with lower manufacturing cost and power consumption, and thus an improved adder is required.

FIG. 1 shows a schematic diagram of an adder 100 in accordance with one or more exemplary embodiments of the present disclosure. The adder 100 is used to calculate the sum of the two numbers input.

As shown in FIG. 1 , the adder 100 has two inputs 111 , 112 and two outputs 161 , 162 . Wherein, the two inputs 111 and 112 respectively represent the two input numbers, and the outputs 161 and 162 respectively represent the sum and the carry of the summation result of the two numbers.

Those skilled in the art should understand that the configuration of the input and output of the adder 100 is not limited to the embodiment shown in FIG. 1 . The configuration of the input and output of the adder 100 can be appropriately adjusted according to the function of the adder and the needs of the operation circuit, and the configuration of each module of the adder 100 can be adjusted accordingly. For example, in some embodiments, the adder may also have only one output, ie, only the sum of the summation results, without the carry.

As shown in FIG. 1 , each input 111 , 112 is divided into N sub-parts corresponding to each other, and the N sub-parts sequentially represent the partial bits of the input from low-order to high-order. For example, input 111 is divided into subsections 111-1, 111-2, …, 111-N from low to high, and input 112 is divided into subsections 112-1, 112-2, …, 112- from low to high N.

Specifically, the first subsections 111-1 and 112-1 represent the least significant one or more bits of the inputs 111 and 112, respectively, and the bits represented by 111-1 and 112-1 are the same. Correspondingly, the second subsections 111-2 and 112-2 respectively represent one or more bits of the inputs 111 and 112 higher than 111-1 and 112-1, and the bits represented by 111-2 and 112-2 are the same . And so on, the Nth subsections 111-N and 112-N represent the highest one or more bits of the inputs 111 and 112, respectively, and the bits represented by 111-N and 112-N are the same.

where N should be an integer greater than or equal to 2. That is, each input 111, 112 has at least two subsections.

In some embodiments, as shown in Figure 1, the output 161 representing the sum of the inputs 111 and 112 is divided into two subsections 161-1, 161-2. Among them, 161-1 corresponds to the first subsections 111-1 and 112-1 of the inputs 111 and 112, representing the lowest one or more bits of the output 161; 161-2 corresponds to the other subsections of the inputs 111 and 112 , representing the other one or more bits of output 161.

It should be understood by those skilled in the art that the input and output are divided into multiple sub-sections herein only for the convenience of describing different coupling relationships of the sub-sections, and does not mean or imply that the sub-sections must be physically separated or partitioned. In particular, those skilled in the art will understand that dividing the input and output into multiple sub-sections with different coupling relationships does not require introducing additional components or incurring additional costs into the digital circuit.

As shown in FIG. 1 , the adder 100 includes a first-stage addition module group 120 , an intermediate register group 130 , a carry register group 140 and a second-stage addition module 150 .

The first-stage addition module group 120 is coupled to the inputs 111, 112, and includes a plurality of first-stage addition modules 120-1, 120-2, . . . , 120-N. Each of the first stage addition modules 120-1, 120-2, . . . , 120-N is used to sum corresponding sub-portions of the two inputs 111, 112.

For example, the first first stage summing module 120-1 is coupled to the first subsections 111-1 and 112-1 of the two inputs 111, 112 for summing 111-1 and 112-1.

The number of the first-stage addition modules is equal to the number of input subsections, and the configuration of each first-stage addition module can be determined according to the number of bits of the input corresponding subsections.

The outputs of the first-stage addition module group 120 are coupled to the intermediate register group 130 and the carry register group 140, and output the sum and carry of the summation result to the intermediate register group 130 and the carry register group 140, respectively.

The intermediate register group 130 includes a plurality of intermediate registers 130-1, 130-2, . . . , 130-N. Each intermediate register 130-1, 130-2, ..., 130-N is coupled to a corresponding first stage addition module 120-1, 120-2, ..., 120-N for storing the two inputs 111, 112 The sum of the results of the sum of the corresponding subsections of .

For example, the first intermediate register 130-1 is coupled to the first first stage addition module 120-1 for storing the sum of the summation results of 111-1 and 112-1. That is, the first intermediate register 130-1 corresponds to the first subsections 111-1 and 112-1 of the two inputs 111, 112, and is used to store the two inputs 111, 112 by 111-1 and 112-1 The sum of the summation results of the least significant one or more digits represented.

The number of intermediate registers is equal to the number of input subsections, and the configuration of each intermediate register can be determined according to the number of bits of the input corresponding subsection.

The carry register group 140 includes a plurality of carry registers 140-1, 140-2, . . . , 140-N. Each carry register 140-1, 140-2, ..., 140-N is coupled to a corresponding first stage addition module 120-1, 120-2, ..., 120-N for storing the two inputs 111, 112 The carry of the sum of the corresponding subparts of .

For example, the first carry register 140-1 is coupled to the first first stage addition module 120-1 for storing the carry of the summation results of 111-1 and 112-1. That is, the first carry register 140-1 is used to store the carry of the summation result of the least significant one or more bits of the two inputs 111, 112 represented by 111-1 and 112-1.

The number of carry registers can be determined based on the number of subsections of the input. In the embodiment shown in Figure 1, the number of carry registers is equal to the number of input subsections. In other embodiments, the number of carry registers may be one less than the number of subsections of the input. That is, the Nth carry register 140-N may not exist in the carry register group 140, and the summation result of the highest one or more bits of the two inputs 111 and 112 represented by 111-N and 112-N may not be stored. carry.

The number of carry registers can be determined as needed. In embodiments where the adder 100 needs to output a carry of the summed result of the two inputs 111, 112 (ie, the adder 100 includes an output 162), the number of carry registers may be determined to be equal to the number of subsections of the inputs. In embodiments where the adder 100 does not need to output a carry of the summed result of the two inputs 111, 112 (ie, the adder 100 does not include an output 162), the number of carry registers may be determined to be greater than the number of subsections of the inputs 1 less, thereby reducing the additional cost of the adder 100. For example, in an embodiment where the two inputs 111, 112 each have two subsections, the adder 100 may include only one carry register.

The carry register is only used to store the carry bit, so each carry register can be implemented by a 1-bit register.

The outputs of the intermediate register group 130 and the carry register group 140 are coupled to the second-stage addition module 150, and the result of summing the corresponding sub-parts of the two inputs 111 and 112 respectively (including the sum and carry) is output to the second stage. Stage addition module 150 .

The second stage addition module 150 is used to sum the sum from each intermediate register and the carry from the corresponding previous carry register to obtain the sum of the two inputs 111, 112.

Specifically, the second-stage addition module 150 may sum the least significant one or more bits represented by 111-1 and 112-1 of the two inputs 111, 112 output from the first intermediate register 130-1 The summed output of the results is the corresponding least significant one or more bits of the sum of the summed results of the two inputs 111, 112 (ie, subsection 161-1 of output 161).

Further, the second-stage addition module 150 may obtain a summation result of one or more bits represented by 111-2 and 112-2 of the two inputs 111, 112 output from the second intermediate register 130-2 The sum is summed with the carry of the summation result of the least significant one or more bits represented by 111-1 and 112-1 of the two inputs 111, 112 output from the first carry register 140-1, and then the The sum output of the summation result is the corresponding one or more bits of the sum of the two inputs 111 , 112 , and the carry of the summation result is used for further operations in the second-stage addition module 150 .

And so on, the second-stage addition module 150 may sum the most significant one or more bits represented by 111-N and 112-N of the two inputs 111, 112 output from the Nth intermediate register 130-N The sum of the result and the sum of one or more bits represented by 111-N-1 and 112-N-1 of the two inputs 111, 112 output from the N-1th carry register 140-N-1 The carry of the result is summed, and then the sum of the summation result is output as the corresponding highest one or more digits of the sum of the two inputs 111 and 112 .

Further, the second-stage addition module 150 may combine the carry of the above summation result with the most significant bit represented by 111-N and 112-N of the two inputs 111, 112 output from the Nth carry register 140-N or the carry of the multi-bit summation result is summed, and then the summation result is output as the carry of the summation result of the two inputs 111 and 112 , that is, the output 162 .

Those skilled in the art should understand that the processing performed by the second-stage addition module 150 is not limited to the processing described above. The configuration of the second-stage adding module 150 may be determined according to the function of the adder 100 . For example, in embodiments that do not need to output a carry of the summed result of the two inputs 111 , 112 (ie, the adder does not include an output 162 ), the second stage addition module 150 may not perform the computation and output the two inputs 111 , 112 The processing of the carry of the summation result.

The output of the second stage addition module 150 is coupled to outputs 161 and 162, which represent the sum and carry of the summation results of the two inputs 111, 112, respectively.

In some embodiments, the output 161 may be divided into two subsections: the first subsection 161-1, representing the sum of the summed results of the two inputs 111, 112, corresponds to 111-1 and 112-1 and the second subsection 161-2, representing the other one or more bits of the sum of the summation results of the two inputs 111, 112.

As shown in FIG. 1 , in some embodiments, the second stage addition module 150 may directly couple the output of the first intermediate register 130 - 1 to the first subsection 161 - 1 of the output 161 .

Those skilled in the art should understand that the registers mentioned herein may be edge-triggered registers (eg, D-type flip-flops) or level-triggered registers (eg, latches).

The calculation speed of the adder 100 mainly depends on the calculation speed of the first-stage addition module group 120 and the second-stage addition module 150 , while the calculation speed of the first-stage addition module group 120 and the second-stage addition module 150 is related to the two inputs 111 . , The number of subparts of 112 is related to the number of bits. Therefore, the number and the number of bits of the subsections of the two inputs 111, 112 can be appropriately determined, thereby increasing the calculation speed of the adder 100.

The overall calculation delay of the first-stage addition module group 120 is determined by the calculation delay of the first-stage addition module with the longest calculation delay among the plurality of first-stage addition modules 120-1, 120-2, . . . , 120-N. Each of the first-level addition modules 120-1, 120-2, ..., 120-N is used to sum the corresponding sub-parts of the two inputs 111 and 112. The calculation delay of the first-level addition module is longer.

Therefore, the overall computation delay of the first-stage addition block group 120 depends on the largest number of bits among the number of bits of the multiple subsections of the inputs 111 , 112 . The larger the maximum number of bits is, the longer the overall calculation delay of the first-stage addition module group 120 is.

The second stage addition module 150 is used to sum the sums from the plurality of intermediate registers and the carry from the corresponding previous carry register. Wherein, the output of the first intermediate register 130-1 represents the corresponding lowest one or more bits of the sum of the summation result. Therefore, the second stage addition module 150 may not perform additional processing on the output of the first intermediate register 130-1. In particular, in some embodiments, the second-stage addition module 150 may also perform certain processing on the output of the first intermediate register 130-1 as required, but the processing time will be much less than the second-stage addition Module 150 requires the summation process as described above for the outputs of the other intermediate registers and the carry register. That is, the calculation delay of the second-stage addition module 150 is determined by the calculation delay of the summation processing as described above.

Therefore, the calculation delay of the second stage addition module 150 may depend on the number of subsections other than the first subsection 111-1, 112-1 among the subsections of the input 111, 112 and the sum of their bits and. The greater the number of the other subsections, or the greater the sum of the number of bits, the longer the calculation delay of the second-stage addition module 150 is. In other words, the smaller the number of subsections of the input 111 and 112, or the larger the number of bits of the first subsections 111-1 and 112-1, the shorter the calculation delay of the second-stage addition module 150 is.

Therefore, it is desirable to reduce the maximum number of bits in the number of bits of the subsections of the two inputs 111, 112. At the same time, it is desired to reduce the number of subsections of the inputs 111, 112, and to increase the number of bits of the first subsection.

In some embodiments, the number of bits of the first subsection 111-1, 112-1 of the input 111, 112 is greater than or equal to the number of bits of the other subsections. In other embodiments, the number of bits of the subsections of the inputs 111, 112 are substantially equal. This is beneficial to reduce the calculation delay of the first-stage addition module group 120 and the second-stage addition module 150, thereby increasing the calculation speed of the adder 100, and further reducing the power consumption and computing power ratio of the chip.

In some embodiments, the input 111 , 112 has two subsections, and the first subsection 111 - 1 , 112 - 1 has a number of bits greater than or equal to half the number of bits of the input 111 , 112 . This is beneficial to reduce the extra cost while increasing the calculation speed of the adder 100 .

It should be noted that the expression "substantially equal" herein means that the two are approximately equal, but not necessarily strictly and precisely equal. Those skilled in the art should understand that this is consistent with technical principles and engineering practice. For example, the two may differ by about 5% or 10%. In some contexts, the two may differ by about 15% or 20%.

FIG. 2 shows a schematic diagram of an adder 200 in accordance with one or more exemplary embodiments of the present disclosure. The adder 200 is used to calculate the sum of an inputted number and a predetermined constant.

As shown in FIG. 2 , the adder 200 has one input 210 and two outputs 261 , 262 . The input 210 represents the input number, and the outputs 261 and 262 represent the sum and the carry of the summation result of the number and a predetermined constant, respectively.

Similarly, in some embodiments, the adder 200 may also have only one output 261, that is, only the sum of the summation results, but not the carry.

The configuration of the adder 200 is similar to that of the adder 100, and can be appropriately adjusted according to the predetermined constant.

As shown in FIG. 2 , the input 210 is divided into N sub-parts, and the N sub-parts represent the partial bits of the input sequentially from low-order to high-order. That is, the input 210 is divided into subsections 210-1, 210-2, . . . , 210-N from low to high. where N should be an integer greater than or equal to 2. That is, input 210 has at least two subsections.

In some embodiments, as shown in Figure 2, the output 261 representing the sum of the input 210 and the constant is divided into two subsections 261-1, 261-2. Among them, 261-1 corresponds to the first subsection 210-1 of the input 210, representing the lowest one or more bits of the output 261; 261-2 corresponds to the other subsections 210-2, ..., 210-N of the input 210 Correspondingly, represent the other one or more bits of output 261.

As shown in FIG. 2 , the adder 200 includes a first-stage addition module group 220 , an intermediate register group 230 , a carry register group 240 and a second-stage addition module 250 .

The first-stage addition module group 220 is coupled to the input 210 and includes a plurality of first-stage addition modules 220-1, 220-2, . . . , 220-N. Each of the first stage addition modules 220-1, 220-2, . . . , 220-N is used to sum the corresponding sub-portion of the input 210 with the corresponding bits of the constant.

The configuration of each of the first stage addition modules 220-1, 220-2, . . . , 220-N may be related to the corresponding bit of the constant. In some embodiments, the number and configuration of the first stage addition modules 220-1, 220-2, . . . , 220-N may be determined or adjusted based at least in part on the constant. For example, for any subsection of the input 210, if it is known that the corresponding bits of the predetermined constant are all zero, the subsection and the corresponding bits of the constant may not be summed, so the first-level addition module group 220 can The corresponding first-level addition module is not included. This is beneficial to reduce the manufacturing cost of the adder 200 .

For example, in some embodiments, if the constant is small (ie, the higher bits are all zeros), the first-stage addition module group 220 may include only one first-stage addition module, that is, only the first-stage addition module with the input 210 is included. The first first-stage addition module 220-1 corresponding to the sub-sections 210-1. In particular, when the constant is 1, the adder 200 is a self-adding 1 adder, and may include only one first-stage adding module.

The outputs of the first-stage addition module group 220 are coupled to the intermediate register group 230 and the carry register group 240, and output the summation result (including the sum and carry) to the intermediate register group 230 and the carry register group 240, respectively.

The intermediate register group 230 includes a plurality of intermediate registers 230-1, 230-2, . . . , 230-N. As shown in FIG. 2, each of the intermediate registers 230-1, 230-2, ..., 230-N is coupled to the corresponding first-stage addition module 220-1, 220-2, ..., 220-N for storing The sum of the corresponding subsection of input 210 and the result of summing the corresponding bit of the constant.

The carry register group 240 includes a plurality of carry registers 240-1, 240-2, . . . , 240-N. Each carry register 240-1, 240-2, . . . , 240-N is coupled to a corresponding first-stage addition module 220-1, 220-2, . The carry of the result of the summation with the corresponding bits of this constant.

The configuration of the intermediate register group 230 and the carry register group 240 can be appropriately adjusted according to the configuration of the first-stage addition module group 220 . For example, when the first-stage addition module corresponding to any sub-portion of input 210 is not included in the first-stage addition module group 220 , the corresponding intermediate register in the intermediate register group 230 may be directly coupled to the sub-section of the input 210 part, and the corresponding carry register may not be included in the carry register group 240 .

In the embodiment shown in Figure 2, the number of carry registers is equal to the number of input subsections. In other embodiments, the number of carry registers may be one less than the number of input subsections, ie there is no Nth carry register 240-N.

The outputs of the intermediate register group 230 and the carry register group 240 are coupled to the second-stage addition module 250, and the result (including the sum and carry) of the summation of the respective sub-parts of the input 210 and the corresponding bits of the constant (including the sum and carry) is output to the first stage. Secondary addition module 250 .

The second-stage addition module 250 is used to sum the sum from each intermediate register and the carry from the corresponding previous carry register, that is, the result of summing the respective sub-parts of the input 210 and the corresponding bits of the constant. (including the sum and carry) to get the sum of the input 210 and the constant.

Specifically, the second-stage addition module 250 may output the lowest one or more bits of the input 210 represented by 210-1 output from the first intermediate register 230-1 and the corresponding lowest one or more bits of the constant The sum output is the corresponding least significant one or more bits of the sum of input 210 and the constant (ie, subsection 261-1 of output 261).

Further, the second-stage addition module 250 may add a sum of one or more bits of the input 210 represented by 210-2 output from the second intermediate register 230-2 and the corresponding one or more bits of the constant summing with the carry output from the first carry register 240-1, then outputting the sum of the summation result as the corresponding one or more bits of the sum of the input 210 and the constant, and adding the carry of the summation result For further operations in the second stage addition module 250 .

And so on, the second-stage addition module 250 can output the highest one or more bits of the input 210 represented by 210-N output from the Nth intermediate register 230-N and the corresponding highest one or more bits of the constant sum the sum of the N-1 th carry register 240-N-1, and then output the sum of the summation result as the highest one or more bits corresponding to the sum of the input 210 and the constant .

Further, the second-level addition module 250 may sum the carry of the above summation result and the carry output from the Nth carry register 240-N, and then output the summation result as the summation result of the input 210 and the constant. carry (i.e. output 262).

Those skilled in the art should understand that the processing performed by the second-level addition module 250 is not limited to the above. The configuration of the second-stage adding module 250 may be determined according to the function of the adder. For example, in embodiments where adder 200 does not include output 262, the configuration of second stage adder module 250 and the processing performed by it may be adjusted accordingly.

The output of the second stage addition module 250 is coupled to outputs 261 and 262, which respectively represent the sum and carry of the summation result of the input 210 and the constant.

In some embodiments, output 261 may be divided into two subsections: a first subsection 261-1, representing the least significant bit corresponding to 210-1 of the sum of input 210 and the result of summing the constant, or multiple bits; and a second subsection 261-2 representing the other one or more bits of the sum of the input 210 and the result of summing the constant. As shown in FIG. 2 , in some embodiments, the second stage addition module 250 may directly couple the output of the first intermediate register 230 - 1 to the first subsection 261 - 1 of the output 261 .

The calculation speed of the adder 200 mainly depends on the calculation speed of the first-stage addition module group 220 and the second-stage addition module 250 .

Regarding the second stage addition module 250, similarly, the smaller the number of subsections of the input 210, or the larger the number of bits of the first subsection 210-1, the shorter the computation delay of the second stage addition module 250. Therefore, it is desirable to reduce the number of subsections of the input 210 and increase the number of bits of the first subsection 210-1.

On the other hand, unlike the adder 100, in the adder 200, the configurations of the first-stage adding modules 220-1, 220-2, . . . , 220-N can be related to the constant. As described above, if for a certain sub-portion of the input 210, the corresponding bits of the constant are all zero, the first-stage addition module group 220 may not include the corresponding first-stage addition module. Therefore, the computation delay of the first-stage addition block group 220 is independent of the number of bits of such subsections, but only depends on other subsections of the input 210 (ie, for these subsections, the corresponding bits of the constant are not all zeros) number of digits. In particular, it is desirable to appropriately increase the number of bits of the subsections corresponding to the bits of all zeros of the constant, and it is desirable to decrease the maximum number of bits among the number of bits of the other subsections.

In some embodiments, the number of subsections of input 210 and the number of bits per subsection are determined based at least in part on the constant. For example, if the constant is small (ie, the higher bits of the constant are all zeros, eg, the constant is 1), then the input 210 may have two subsections such that the bits of the constant corresponding to the second subsection are all zeros . For example, if the constant includes a plurality of consecutive bits that are all zeros, a sub-portion of the input 210 may be divided corresponding to at least a portion of the consecutive plurality of bits.

FIG. 3 illustrates a portion of an arithmetic circuit 3000 including an adder 300 according to one or more exemplary embodiments of the present disclosure.

For example only, in FIG. 3, adder 300 is shown as an adder as shown in FIG. 1 for calculating the sum of two numbers input. However, those skilled in the art should understand that the adder 300 can be replaced with an adder for calculating the sum of an input number and a predetermined constant as shown in FIG.

The arithmetic circuit 3000 includes registers 3101 and 3102 of the previous stage, an adder 300 , and a register 3200 of the subsequent stage. In addition, in some embodiments, the operation circuit 3000 may further include a pre-combination logic module 3110 and a post-combination logic module 3120 .

In some embodiments, the previous stage registers 3101 , 3102 may be directly coupled to the adder 300 . In some embodiments, the previous stage registers 3101 , 3102 may be coupled to the adder 300 via a pre-combination logic module 3110 . In some embodiments, the adder 300 may be directly coupled to the subsequent stage register 3200 . In some embodiments, the adder 300 may be coupled to the post-stage register 3200 via the post-combination logic module 3120 .

Those skilled in the art should understand that the number and configuration of the previous-level registers 3101 and 3102 and the subsequent-level registers 3200 are not limited to the embodiment shown in FIG. 3 . For example, in some embodiments, the arithmetic circuit 3000 may include only one previous stage register 3101 , which provides two inputs 311 , 312 to the adder 300 via the pre-combination logic module 3110 .

For example only, FIG. 3 shows an embodiment in which the arithmetic circuit 3000 includes a pre-combination logic module 3110 and a post-combination logic module 3120 . Those skilled in the art should understand that the following description is also applicable to the embodiment in which the operation circuit 3000 does not include the pre-combination logic module 3110 or the post-combination logic module 3120, and only needs to make appropriate adjustments.

The adder 300 is similar in configuration to the adder 100 shown in FIG. 1 .

The adder 300 has two inputs 311, 312 respectively representing the two numbers input, and two outputs 361, 362 representing the sum and carry of the summation result of the two numbers, respectively. Therein, the output 361 has two subsections 361-1, 361-2.

The adder 300 includes: a first-stage addition module group 320 , an intermediate register group 330 including a plurality of intermediate registers 330 - 1 , 330 - 2 , . . . , 330 -N, a carry register group 340 , and a second-stage addition module 350 . Wherein, in some embodiments, the second stage addition module 350 directly couples the output of the first intermediate register 330-1 to the first subsection 361-1 of the output 361.

In the arithmetic circuit 3000, the frequencies of the clocks used for the preceding-stage registers 3101 and 3102, the intermediate register group 330, and the succeeding-stage register 3200 are the same. Therefore, it is expected that the operations of the pre-combination logic module 3110 and the first-stage addition module group 320 can be completed in one clock cycle, and the operations of the second-stage addition module 350 and the post-combination logic module 3120 can be completed in one clock cycle. .

Therefore, it is expected that the calculation delay of the first-stage addition module group 320 is less than the difference between the clock cycle and the calculation delay of the pre-combination logic module 3110, and the calculation delay of the second-stage addition module 350 is smaller than the clock cycle and the post-combination logic module 3120. Calculate the difference in delays.

Regarding the first-stage addition module group 320, as described above, in the adder 300, the larger the maximum number of bits among the sub-sections of the inputs 311 and 312 is, the longer the calculation delay of the first-stage addition module group 320 is. long. Accordingly, the upper limit of the maximum number of bits in the number of sub-sections of the inputs 311 , 312 may be determined at least in part based on the difference between the clock period and the computation delay of the pre-combination logic module 3110 .

In some embodiments, the maximum number of bits of the plurality of subsections of the inputs 311 , 312 of the adder 300 may be determined based at least in part on the difference between the clock period and the computation delay of the pre-combination logic module 3110 . Specifically, the maximum number of bits can be determined so that the calculation delay of the first-stage addition module group 320 is smaller than the difference between the clock cycle and the calculation delay of the pre-combination logic module 3110 . In some embodiments, the maximum number of bits may be determined such that the calculation delay of the first-stage addition module group 320 is substantially equal to the difference between the clock period and the calculation delay of the pre-combination logic module 3110 .

Furthermore, in embodiments in which operational circuit 3000 does not include pre-combination logic module 3110, in some examples, the maximum number of bits of the plurality of subsections of inputs 311, 312 of adder 300 is determined based at least in part on clock cycles digits.

On the other hand, when the adder 300 is the adder shown in FIG. 2 for calculating the sum of an input number and a predetermined constant, the calculation delay of the first-stage adding module group 320 is also related to the constant. As mentioned above, the number of bits of the subsections can be adjusted according to this constant.

Therefore, in some embodiments, the maximum number of bits in the number of bits of the multiple sub-sections of the input of the adder 300 may be determined first according to the difference between the clock period and the calculation delay of the pre-combination logic module 3110, and then according to the constant Adjust the number of bits for multiple subsections. For example, if the constant includes consecutive bits that are all zeros, a subsection of the input may be divided corresponding to the consecutive bits, regardless of whether the number of bits in the subsection is greater than the determined maximum number of bits. In some embodiments, the number of bits of the plurality of sub-portions of the input may be adjusted such that the maximum number of bits in the sub-portion that does not correspond to the all-zero bits of the constant is substantially equal to the determined maximum number of bits.

With regard to the second-stage addition module 350, as described above, in the adder 300, the greater the number of sub-sections input 311 and 312, or the smaller the number of bits of the first sub-section, the smaller the number of bits in the second-stage addition module 350. The longer the calculation delay is. Thus, the lower bound on the number of bits of the first subsection of the inputs 311 , 312 of the adder 300 may be determined at least in part from the difference between the clock period and the computation delay of the post-combination logic module 3120 .

In some embodiments, the number of bits of the first subsection of the inputs 311 , 312 of the adder 300 is determined based at least in part on the difference between the clock period and the computation delay of the post-combination logic module 3120 . Specifically, the number of bits of the first subsection can be determined such that the calculation delay of the second-stage addition module 350 is smaller than the difference between the clock cycle and the calculation delay of the post-combination logic module 3120 . In some embodiments, the number of bits of the first subsection may be determined such that the calculation delay of the second stage addition module 350 is substantially equal to the difference between the clock period and the calculation delay of the post-combination logic module 3120 .

Furthermore, in embodiments where the operational circuit 3000 does not include the post-combination logic module 3120, in some examples, the number of bits of the first subsection of the inputs 311, 312 of the adder 300 is determined based at least in part on the clock cycle.

On the other hand, as mentioned above, in some embodiments, the number of bits of the first subsection of the input 311, 312 is determined to be greater than or equal to the number of bits of the other subsections. In some embodiments, the number of bits of the multiple sub-portions of the inputs 311, 312 are determined to be substantially equal.

In some embodiments, the strategies described above may be combined to determine the number and number of bits of subsections of the inputs 311 , 312 of the adder 300 .

For example, in some embodiments, the inputs 311 , 312 of the adder 300 may be determined first according to the difference between the clock cycle and the calculation delay of the pre-combination logic module 3110 and the difference between the clock cycle and the calculation delay of the post-combination logic module 3120 The number of digits in the first subsection of . For example, the upper limit of the number of bits of the first subsection can be determined according to the difference between the clock period and the calculation delay of the pre-combination logic module 3110, and determined according to the difference between the clock period and the calculation delay of the post-combination logic module 3120 The lower bound on the number of bits in this first subsection.

Then, if the determined number of bits of the first subsection is greater than or equal to half of the number of bits of the inputs 311, 312, the other bits of the inputs 311, 312 can be divided into the second subsection. In this way, the input 311, 312 is divided into two subsections, wherein the number of bits in the first subsection is greater than or equal to the number of bits in the second subsection.

If the determined number of bits of the first subsection is less than half of the bits of the input 311, 312, the other bits of the input 311, 312 can be divided into several subsections, so that the number of these subsections is as small as possible, and each The number of bits of each subsection is less than or equal to the number of bits of the first subsection determined. For example, the number of bits of these subsections may be determined to be substantially equal to the number of bits of the first subsection.

When the adder 300 is the adder 200 shown in FIG. 2 for calculating the sum of an input number and a predetermined constant, the number and the number of bits of the subsections can be further adjusted according to the constant. For example, if the constant includes a plurality of consecutive bits that are all zeros, a subsection of the input may be divided corresponding to the consecutive bits, regardless of whether the number of bits in the subsection is greater than the determined first subsection. digits.

Those skilled in the art should understand that the manner of determining the number and the number of bits of the input subsections of the adder is not limited to the specific embodiments described above. The various strategies described in this paper can be used independently or in combination, taking into account various factors such as function, configuration, area, cost, speed, power consumption, etc. of the adder and arithmetic circuit to determine the number and digits.

Compared with the related art that needs to use high-speed devices, the present disclosure achieves an increase in the operation speed of the adder with lower cost and lower power consumption.

In contrast, FIG. 4 shows a part of an arithmetic circuit 4000 including an adder 4120 according to the related art.

The arithmetic circuit 4000 includes first-level registers 4101 and 4102 , a pre-combination logic module 4110 , an adder 4120 , a second-level register 4200 , a post-combination logic module 4210 , and a third-level register 4300 .

The first-level registers 4101 and 4102 are coupled to the second-level register 4200 via the pre-combination logic module 4110 and the adder 4120 . The second level register 4200 is coupled to the third level register 4300 via the post-combination logic module 4210 .

It can be seen that the first level registers 4101 and 4102, the second level register 4200 and the third level register 4300 in the arithmetic circuit 4000 shown in FIG. 4 correspond to the previous level register 3101 in the arithmetic circuit 3000 shown in FIG. 3 respectively And 3102, the intermediate register group 330, and the next-level register 3200. Correspondingly, the pre-combination logic module 4110 and the post-combination logic module 4210 in the operation circuit 4000 correspond to the pre-combination logic module 3110 and the post-combination logic module 3120 in the operation circuit 3000, respectively.

An important difference between the present disclosure and the related art is that the adder 4120 in the operation circuit 4000 of the related art shown in FIG. The adder 300 in the arithmetic circuit 3000 of the present disclosure is coupled between the previous-stage registers 3101 , 3102 and the latter-stage register 3200 across the intermediate register group 330 .

In the related art shown in FIG. 4 , the adder 4120 can only use the clock cycle between the first-level registers 4101 and 4102 and the second-level register 4200 to perform operations together with the pre-combination logic module 4110 . In the technical solution of the present disclosure shown in FIG. 3 , the adder 300 can use the preceding level registers 3101 , 3102 and the intermediate register group 330 and the intermediate registers together with the pre-combination logic module 3110 and the post-combination logic module 3120 The operation takes two clock cycles between the bank 330 and the next stage register 3200 . In the technical solution of the present disclosure, the configuration of the adder 300 can be appropriately adjusted according to the configuration of the pre-combination logic module 3110 and the post-combination logic module 3120, so that the two clock cycles can be used more fully and flexibly. time to complete the addition operation.

In addition, those skilled in the art should understand that the operations performed by the first-stage addition module group 320 and the second-stage addition module 350 in the adder 300 shown in FIG. 3 are essentially the same as those performed by the adder 4120 shown in FIG. 4 . above are equivalent. In other words, the adder 4120 also has modules or units equivalent to or corresponding to the first-stage addition module group 320 and the second-stage addition module 350 in the adder 300 . Therefore, compared with the related art, the configuration of the first-stage addition module group 320 and the second-stage addition module 350 in the adder 300 does not introduce additional cost.

That is, compared with the related art shown in FIG. 4 , the additional module or unit required to implement the adder 300 in the arithmetic circuit 3000 shown in FIG. 3 is only the carry register group 340 . As described above, each carry register in the carry register group 340 is implemented by a 1-bit register, which has a low manufacturing cost. In other words, compared to the related art shown in FIG. 4 , the additional cost of implementing the adder of the present disclosure is substantially only the manufacturing cost of several 1-bit registers.

Therefore, compared with the related art, the adder proposed by the present disclosure creatively utilizes the clock cycles of adjacent stages to complete some operations, thereby effectively improving the operations of the adder and the operation circuit including the adder at a lower cost. speed.

The adder and the arithmetic circuit according to the present disclosure can be implemented in various appropriate manners, such as software, hardware, and a combination of software and hardware. In one implementation, a wafer may include the arithmetic circuitry described above, and the wafer may also be included in a computing device.

The words "front," "rear," "top," "bottom," "over," "under," etc. in the specification and claims, if present, are used for descriptive purposes and not necessarily to describe an invariant relative position. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are, for example, capable of other orientations than those illustrated or otherwise described herein. Operate up.

As used herein, the word "exemplary" means "serving as an example, instance, or illustration" rather than as a "model" to be exactly reproduced. Any implementation illustratively described herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the present disclosure is not to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or detailed description.

As used herein, the word "substantially" is meant to encompass any minor variation due to design or manufacturing imperfections, tolerances of devices or elements, environmental influences, and/or other factors. The word "substantially" also allows for differences from a perfect or ideal situation due to parasitics, noise, and other practical considerations that may exist in an actual implementation.

Additionally, the preceding description may refer to elements or nodes or features being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element/node/feature is electrically, mechanically, logically or otherwise directly connected (or directly connected) to another element/node/feature. communication). Similarly, unless expressly stated otherwise, "coupled" means that one element/node/feature can be mechanically, electrically, logically or otherwise linked, directly or indirectly, with another element/node/feature to allow interaction, even though the two features may not be directly connected. That is, "coupled" is intended to encompass both direct and indirect connections of elements or other features, including connections utilizing one or more intervening elements.

Also, terms like "first," "second," and the like may also be used herein for reference purposes only, and are thus not intended to be limiting. For example, the terms "first," "second," and other such numerical terms referring to structures or elements do not imply a sequence or order unless the context clearly dictates otherwise.

It should also be understood that the term "comprising/comprising" when used herein indicates the presence of the indicated feature, integer, step, operation, unit and/or component, but does not preclude the presence or addition of one or more other features, Entities, steps, operations, units and/or components and/or combinations thereof.

In this disclosure, the term "providing" is used broadly to encompass all ways of obtaining an object, thus "providing something" includes, but is not limited to, "purchasing," "preparing/manufacturing," "arranging/arranging," "installing/ Assembly", and/or "Order" objects, etc.

Those skilled in the art will appreciate that the boundaries between the operations described above are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed at least partially overlapping in time. Furthermore, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in other various embodiments. However, other modifications, changes and substitutions are equally possible. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

While some specific embodiments of the present disclosure have been described in detail by way of examples, those skilled in the art will appreciate that the above examples are provided for illustration only, and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined arbitrarily without departing from the spirit and scope of the present disclosure. It will also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

100: Adder 111, 112: input 111-1~111-N: Subsections 112-1~112-N: Subsections 120: First-level addition module group 120-1~120-N: first-level addition module 130: Intermediate register bank 130-1~130-N: Intermediate register 140: Carry register group 140-1~140-N: carry register 150: Second-level addition module 161, 162: output 161-1, 161-2: Subsections 200: Adder 210: Enter 210-1~210-N: Subsections 220: First-level addition module group 220-1~220-N: first-level addition module 230: Intermediate register bank 230-1~230-N: Intermediate register 240: carry register group 240-1~240-N: carry register 250: Second-level addition module 261, 262: output 261-1, 261-2: Subsections 300: Adder 311, 312: Input 320: First-level addition module group 330: Intermediate register bank 330-1~330-N: Intermediate register 340: carry register group 350: Second-level addition module 361, 362: output 361-1, 361-2: Subsections 3000: Operational Circuits 3101, 3102: previous level register 3110: Front Combination Logic Module 3120: Post Combination Logic Module 3200: next level register 4000: Operational Circuit 4101, 4102: first level register 4110: Front Combination Logic Module 4120: Adder 4200: second level register 4210: Post Combination Logic Module 4300: The third level register

The drawings, which form a part of the specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

The present disclosure may be more clearly understood from the following detailed description with reference to the drawings, wherein:

FIG. 1 shows a schematic diagram of an adder for calculating the sum of two numbers of an input, according to one or more exemplary embodiments of the present disclosure.

FIG. 2 shows a schematic diagram of an adder for calculating the sum of an input number and a predetermined constant according to one or more exemplary embodiments of the present disclosure.

3 illustrates a portion of an operational circuit including an adder according to one or more exemplary embodiments of the present disclosure.

FIG. 4 shows a part of an operation circuit including an adder according to the related art.

Note that, in the embodiments described below, the same drawing symbols are used in common between different drawings to denote the same parts or parts having the same function, and repeated descriptions thereof are omitted. In some cases, similar numbers and letters are used to denote similar items, so once an item is defined in one figure, it does not require further discussion in subsequent figures.

For ease of understanding, the position, size, range, and the like of each structure shown in the drawings and the like may not indicate the actual position, size, range, or the like. Therefore, the present disclosure is not limited to the positions, dimensions, ranges, and the like disclosed in the drawings and the like.

100: Adder

111, 112: input

111-1~111-N: Subsections

112-1~112-N: Subsections

120: First-level addition module group

120-1~120-N: first-level addition module

130: Intermediate register bank

130-1~130-N: Intermediate register

140: Carry register group

140-1~140-N: carry register

150: Second-level addition module

161, 162: output

161-1, 161-2: Subsections

Claims (16)

An adder for calculating the sum of two numbers of inputs, the adder having two inputs representing the two numbers respectively, wherein each of the two inputs is divided into multiples corresponding to each other sub-parts, the plurality of sub-parts represent partial bits of the input sequentially from low bits to high bits, and the adder includes: a plurality of first-stage addition modules operating in parallel with each other, each first-stage addition module is used for adding The corresponding subsections of the two inputs are summed; a plurality of intermediate registers, each of which is coupled to a corresponding first-stage addition module, is used to store the two output from the corresponding first-stage addition module. The sum of corresponding sub-portions of the inputs; one or more carry registers, each carry register coupled to a corresponding first-stage addition module for storing the two output by the corresponding first-stage addition module a carry bit of the corresponding sub-portion of the input; and a second stage addition module, coupled to the plurality of intermediate registers and the one or more carry registers, for summing the sum from each intermediate register with the sum from the corresponding preamble The carry bits of a carry register are summed; wherein the number of bits in each subsection of each of the two inputs is determined at least in part based on the overall computational delay of the plurality of first stage addition modules. The adder of claim 1, wherein a second-stage addition module directly couples an output of a first intermediate register of the plurality of intermediate registers that corresponds to a first subsection of the two inputs to the output of the adder, wherein the first sub-portion of each of the two inputs represents the least significant one or more bits of the input. The adder of claim 1 or 2, wherein the number of bits of the first subsection of each of the two inputs is greater than or equal to the number of bits of the other subsections of the input. The adder of claim 1 or 2, wherein each of the two inputs has two subsections. An adder for calculating the sum of a number of inputs and a predetermined constant, the adder having an input representing the number, the input being divided into a plurality of subsections, the plurality of subsections from low to high The partial bits of the input are represented in sequence, and the adder includes: one or more first-stage addition modules operating in parallel with each other, each first-stage addition module for comparing a corresponding subsection of the input with the The corresponding bits of the constant are summed; a plurality of intermediate registers, each of which is coupled to a corresponding first-stage addition module, is used to store the corresponding subsection of the input output by the corresponding first-stage addition module and The sum of the corresponding bits of the constant; one or more carry registers, each of which is coupled to a corresponding first-stage addition module for storing the input value output by the corresponding first-stage addition module; a carry of the corresponding subsection and the corresponding bit of the constant; and a second stage addition module, coupled to the plurality of intermediate registers and the one or more carry registers, for adding a sum from each intermediate register summing with the carry from the corresponding previous carry register; wherein the number of bits in each subsection of the input is determined at least in part based on the overall computational delay of the plurality of first stage addition modules. The adder of claim 5, wherein a second stage adder module directly couples an output of a first one of the plurality of intermediate registers corresponding to the first sub-portion of the input to an adder the output of the device, wherein the first subsection represents the least significant one or more bits of the input. The adder of claim 5 or 6, wherein the number of subsections of the input and the number of bits per subsection are determined at least in part from the constant. The adder of claim 5 or 6, wherein the number and configuration of first stage adding modules is determined at least in part from the constant. The adder of claim 8, wherein the constant is one. The adder of claim 5 or 6, wherein the input has two subsections. An arithmetic circuit comprising: the adder of any one of claim 1 to 10; and a pre-combination logic module coupled to an input of the adder and coupled to the adder The output of at least one of the post-combination logic modules. The arithmetic circuit of claim 11, wherein the number of subsections of the input and the number of bits per subsection of the adder depend at least in part on at least one of a pre-combinational logic module and a post-combinational logic module The calculation delay of one and the period of the clock used for the arithmetic circuit are determined. The arithmetic circuit of claim 12, wherein, if the arithmetic circuit includes a pre-combination logic module, the maximum number of bits of the number of bits of the plurality of subsections of the input of the adder is at least partially It is determined according to the difference between the period of the clock used for the operation circuit and the calculation delay of the pre-combination logic module. If the operation circuit does not include the pre-combination logic module, the input value of the adder is The maximum number of bits of the plurality of subsections is determined based at least in part on a period of a clock used for the arithmetic circuit. The arithmetic circuit of claim 12, wherein, If the arithmetic circuit includes a post-combination logic module, the number of bits of the first sub-portion of the input of the adder is combined with the post-combination at least in part according to the period of the clock used for the arithmetic circuit The difference in the computation delays of the logic modules is determined, if the arithmetic circuit does not include a post-combination logic module, the number of bits of the first subsection of the input of the adder is based at least in part on the number of bits used for the operation The cycle of the circuit's clock is determined. A wafer comprising the arithmetic circuit of any one of claims 11 to 14. A computing device comprising the wafer of claim 15.

Images