TWI775631B - Flash memory and erase method thereof - Google Patents

Abstract

A flash memory and an erase method thereof are provided. The flash memory includes at least a memory array and a memory control circuit. The memory control circuit biases plural word lines, a common source line and a global bit line included in the memory array to erase plural memory cells in the flash memory. The method comprises grouping the plural word lines into plural word line groups according to erase depths corresponding to each word line; generating a common source line erase voltage and plural multiple-step word line erase voltages; applying the common source line erase voltage to the common source line; and during a period when the common source line erase voltage is applied, the plural multiple-step word line erase voltages is respectively applied to the plural word line groups, wherein the plural multiple-step word line erase voltages is one-by-one corresponding to the plural word line groups.

Description

Flash memory and its erasing method

The present invention relates to a method for operating a flash memory, and more particularly, to a flash memory and an erasing method thereof.

Recently, the development of flash memory has shifted from a two-dimensional architecture (2D) to a three-dimensional architecture (3D), which has resulted in a larger memory cell size and a cylindrical gate-all-around (GAA) shape. structure. Reliability is significantly improved compared to 2D NAND flash memory. The reliability of 3D NAND flash memory depends on many factors. Most of the factors are related to the variability created by the process of each layer. Indicators such as durability, data retention capabilities, and cross-temperature immunity are affected by these variability. Without a system-level solution, it becomes an intractable reliability challenge.

Erase depth control is important for 3D NAND flash memory structures. Due to the etch capability limitation for vertical channels (VCs), vertical channels have large variation along the word line in the vertical direction relative to the substrate, and also cause variation in erase speed. This will impact the performance of many components, For example retention, read distribution, durability, etc. Therefore, how to improve the erase depth variation through operation compensation will be a topic of 3D NAND flash memory.

FIG. 1A is a schematic diagram of waveforms of word line erase voltages according to the prior art. As shown in FIG. 1A, the conventional erase operation is to apply the same word line erase voltage to all word lines during the period when the common source line (CSL) is applying the common source line erase voltage . In a 3D NAND flash memory, word lines are arranged along the vertical direction. During the erasing operation, the voltage difference between the source and the gate (ie the erasing electric field) is used to perform the erasing operation, so the final erasing depth change will reflect the profile of the vertical channel. Generally speaking, since the vertical channel is formed by etching, its profile becomes narrower toward the bottom.

Therefore, the word line closer to the upper side has a slower erasing speed, so the erasing depth is relatively shallow, whereas the word line closer to the bottom has a faster erasing speed, so the relatively lower erasing depth deep. As a result, as shown in FIG. 1B , a schematic diagram of the distribution of the erase depth to word lines after the erase operation is drawn. As shown in FIG. 1, as the word line goes up, the erase depth becomes shallower. Therefore, from the perspective of FIG. 1B , the conventional erasing operation causes the erasing depth to vary greatly along the arrangement direction (vertical direction) of the word lines, that is, the erasing depths are not uniform. This result will have a large impact on metrics such as data retention and read distribution.

Usually NAND flash memory (3D or 2D) is erased in blocks. Here, the concept of erasing depth is briefly explained by using FIG. 1C and a single level cell (SLC) storing a single cell. As shown in FIG. 1C, when erasing is performed, the memory cells that have been programmed from the "0" state to the "1" state are erased. Taking the erase operation of 3D NAND flash memory as an example, for each word line, the threshold voltage VT distribution of the final erase state "1" is also different. As shown in FIG. 1C , the distribution of the threshold voltage VT after erasing some word lines is relatively negative (as shown by the dotted line), which means that the erasing depth is deeper. As a result, after the erase operation, the threshold voltage VT distribution may be too broad, causing a great impact on metrics such as data retention and read distribution. Therefore, it is required that the distribution of the threshold voltage VT after a certain division can be tighter.

Therefore, how to control the erasing depth to be more even, that is, the distribution of the threshold voltage is relatively tight, is a subject in this field. Therefore, it is necessary to develop a method to improve the problem of uneven distribution of erase depths of each word line.

According to an embodiment, the present invention provides a method for erasing a flash memory, wherein the flash memory at least has a memory array and a memory control circuit, and the memory control circuit controls the memory included in the memory array. A plurality of word lines, common source lines and global bit lines are biased to erase a plurality of memory cells in the flash memory. An erasing method of a flash memory includes: dividing a plurality of word lines into a plurality of groups of word lines according to an erasing depth corresponding to each of the plurality of word lines; generating an erase voltage and a plurality of multi-level word lines a line erase voltage; applying an erase voltage to at least one of the common source line and the global bit line; and applying the erase voltage to the plurality of multi-level word lines Erase voltages are applied to the plurality of groups of word lines, wherein the plurality of multi-level word line erase voltages are in a one-to-one correspondence with the groups of word lines.

According to another embodiment, the present invention also provides a flash memory including a memory array and a memory control circuit. The memory array at least includes a plurality of memory cells, a plurality of word lines, a common source line and a global bit line, and the plurality of word lines, the common source line and the bit line are applied biasing voltages to operate on the plurality of memory cells in the flash memory. A memory control circuit is used to control the memory array. The memory control circuit further performs an erase operation, which includes: dividing the plurality of word lines into a plurality of groups of word lines according to the erase depth corresponding to each of the plurality of word lines; multi-level word line erase voltages; applying an erase voltage to at least one of the common source line and the global bit line; and applying the erase voltages to the plurality of erase voltages The multi-level word line erase voltages are applied to the multi-level word line groups, wherein the multi-level word line erase voltages and the multi-level word line groups are in a one-to-one correspondence.

According to an embodiment, in the above-mentioned method for erasing a flash memory or a flash memory, the deeper the erasing depth of each group of the plurality of word lines, the higher the erasing voltages of the plurality of multi-level word lines. The effect time of the first-level voltage of the corresponding multi-level word line erase voltage is shorter.

According to an embodiment, in the above-mentioned method for erasing a flash memory or a flash memory, the voltage values of the corresponding steps of the erase voltages of each of the plurality of multi-step word lines are the same, but the action time is different. In addition, according to an embodiment, in the above-mentioned method for erasing a flash memory or a flash memory, the voltage values of the corresponding steps of the erase voltages of each of the plurality of multi-step word lines are different, but the effect time is different. different.

According to an embodiment, in the above-mentioned method for erasing a flash memory or a flash memory, the numbers of the word lines in the plurality of groups of word lines may be consecutive. In addition, the multigroup The numbering of word lines within a word line may be discontinuous.

According to an embodiment, in the above-mentioned method for erasing a flash memory or a flash memory, the erase voltages of each of the plurality of multi-level word lines are increased step by step.

According to an embodiment, in the above-mentioned method for erasing a flash memory or a flash memory, the flash memory may be a 3D NAND flash memory or a 2D NAND flash memory.

According to an embodiment, in the above-mentioned method for erasing a flash memory or a flash memory, each of the plurality of memory cells is a single-level cell storing one-bit cells, a double-layer cell storing two-bit cells, A three-level cell that stores three bits, a four-level cell that stores four bits, or a multi-level cell that stores multiple bits.

Based on the above, when erasing is performed, the word line erase voltage applied to each group of word lines is a two-level (or more) level of voltage. The word line grouping is done according to the erase depth (or vertical channel profile, etc.). The erasing depth of each group of word lines can be controlled by adjusting the duration of the first stage of the applied word line erasing voltage (the time during which the first stage transitions to the second stage). In this way, after the erase operation is performed on the flash memory, the overall erase depth can be distributed more uniformly, and the multi-component performance such as retention, read distribution, durability, etc., can be improved.

VERS_CSL: Common source line erase voltage

VERS_WL1~VERS_WL4: Word line erase voltage

WLGP1~WLGP4: word line group

VERS_L:

VERS_H: High level voltage

t: the application period of the common source line erase voltage

t1~t4: the action period of the low level voltage

100: Memory control circuit

110: Memory array

FIG. 1A is a schematic diagram of waveforms of word line erase voltages according to the prior art.

FIG. 1B illustrates the distribution of erase depth to word lines after an erase operation according to the prior art picture.

FIG. 1C is a diagram illustrating the erasing depth.

FIG. 2 is a schematic structural diagram of a word line portion of a 3D NAND flash memory.

FIG. 3A is a schematic diagram of waveforms of word line erase voltages according to an embodiment of the present invention.

3B is a schematic diagram illustrating the distribution of erase depth to word lines after an erase operation according to an embodiment of the present invention.

FIG. 4 is a graph showing the relationship between erasing time and threshold voltage.

FIG. 5 is a schematic diagram illustrating waveforms of word line erase voltages according to a variant of the present invention.

FIG. 6A is a schematic diagram of waveforms of word line erase voltages according to a variant embodiment of the present invention.

FIG. 6B is a schematic diagram illustrating the waveform of the word line erase voltage according to the variant embodiment of the present invention.

FIG. 6C is a schematic diagram of waveforms of word line erase voltages according to a variant embodiment of the present invention.

FIG. 7 is a block diagram illustrating a control circuit of a flash memory according to an embodiment of the present invention.

According to the concept of an embodiment of the present invention, word lines are grouped according to erase depth, and during the application of an erase voltage (using a common source line erase voltage as an example in the following description), in each group of word cells The multi-stage word line erasing voltage is applied on the line, thereby adjusting the erasing depth of each group of word lines, so that the erasing depth of each group of word lines can be distributed more evenly. In other words, the word line erase voltage can be used to control the erase except speed.

Hereinafter, a 3D NAND flash memory will be used as an illustrative example, but the present invention is not limited to this. In addition, the word line erase voltage applied to each group is illustrated as a second order, but the present invention is not limited to this, and the order can be adjusted arbitrarily.

FIG. 2 illustrates a memory architecture as an application example of the embodiment of the present invention, which illustrates a partial structure of a 3D NAND flash memory. The schematic structure of the 3D NAND flash memory shown in FIG. 2 has a plurality of word lines WL0~WL47 (48 are used as an example) in the vertical direction z, and the vertical channel VC is also along the formed along the vertical direction z. Each word line extends in the xy plane. The width of the re-straightening channel VC intersecting with a specific word line can be regarded as the size of the re-straightening channel of the specific word line. The straight channel VC is generally formed by etching, for example, and therefore essentially has a variation in size (width) in the vertical direction z along the arrangement (numbering) of the word lines. In other words, from the word line WL47 (upper side) to the word line WL0 (lower side), the size of the re-straightening channel VC between them will become smaller and smaller, that is, the re-straightening channel VC corresponding to each word line The dimensions are not consistent and there is variation. Therefore, when the 3D NAND flash memory is erased, the erase depth of each word line also varies.

In addition, in the structure shown in FIG. 2 , for example, a certain number of bottom dummy word lines, such as dummy word lines DWLB1 and D WLB0 , may also be formed on the lower side of the word line WL0 . Similarly, for example, a certain number of upper dummy word lines, such as dummy word lines DWLT1, DWLT0, etc., may also be formed on the upper side of the word line WL47. In addition, the 3D NAND flash memory may also include a common source line (CSL), which connects the source lines together. 3D NAND flash memory can also include options Lines SSL0, SSL1, SSL2, etc. In the 3D NAND flash memory, a global source line (GSL) can be formed on the lower side of the word line, and a global bit line (GBL) can be formed on the upper side to connect the bit lines. The structure of the 3D NAND flash memory shown in FIG. 2 is only for understanding the relationship between the word line and the vertical channel VC, and is not intended to limit the implementation object of the present invention. Various 3D NAND flash memory structures can apply the erase method of the present invention.

When the above-mentioned 3D NAND flash memory is erased, a common source line erase voltage (erase bias) VERS_CSL is applied from the common source line. Meanwhile, during the period of applying the common source line erase voltage VERS_CSL, the word line erase voltage VERS_WL is applied to each word line, thereby erasing the memory cells on all the word lines. According to the embodiment of the present invention, in order to solve the problem of uneven erase depth, the word line erase voltages VERS_WL applied to each word line are not identical. In this embodiment, a plurality of word lines are firstly grouped, and the grouping can be performed according to the depth of the erasing depth as a basis. In addition, in order to control the erasing speed, the present embodiment adopts multi-level word line erasing voltages.

According to an embodiment of the present invention, for convenience of description, the word lines in the 3D NAND are divided into four groups, namely WLGP1, WLGP2, WLGP3 and WLGP4, and the number of word lines in each group is equal. However, the present invention is not limited to this, and the plurality of word lines can be further divided into 5 groups or more, and the number of word lines in each group can be different, which can be appropriately adjusted according to the erasing depth.

As shown in FIG. 2 , the present embodiment uses 48 word lines WL0 to WL17 as an illustration example. First, the word lines WL0~WL47 are divided into four groups, the first group of word lines WLGP1 includes word lines WL36~WL47, and the second group of word lines WLGP2 includes word lines Lines WL24 to WL35, the third group of word lines WLGP3 includes word lines WL12 to WL23, and the fourth group of word lines WLGP4 includes word lines WL0 to WL11. Since the grouping method in this example is performed in such a manner that the number of word lines in each group is equal, each of the first to fourth groups of word lines WLGP1 to WLGP4 includes 12 word lines. In addition, in this embodiment, the grouping is performed in a sequential manner, that is, it is divided into four groups in sequence from the lowermost word line WL0 to the uppermost word line WL47.

According to the above description, the lower the word line, the faster the corresponding erasing speed and the deeper the erasing depth; conversely, the higher the upper word line, the slower the corresponding erasing speed and the deeper the erasing depth. also shallower. Therefore, the erasing depth corresponding to the first group of word lines WLGP1 is the shallowest, and the erasing speed is the slowest. The fourth group of word lines WLGP4 corresponds to the deepest erasing depth and the fastest erasing speed. Therefore, in terms of the erasing depth, there is the following relationship: WLGP1<WLGP2<WLGP3<WLGP4 (erasing depth)

Regarding the erasing speed, there is also the following relationship: WLGP1<WLGP2<WLGP3<WLGP4 (erasing speed).

According to the embodiment of the present invention, in order to control the corresponding erasing depth of each group of word lines, the word line erase voltage VERS_WL with the same waveform is no longer applied to each group of word lines, but different waveforms are applied to each group of word lines word line erase voltage VERS_WL. Here, the word line erase voltage VERS_WL adopts a multi-level voltage waveform. The multi-step voltage waveform can be at least two steps, but can be set to more steps according to actual needs. Thereby, the corresponding erasing depths of each group of word lines can be controlled more finely, so that the distribution of the erasing depths is more uniform. Hereinafter, the present embodiment will take the second-order word line erase voltage as an illustrative example.

FIG. 3A is a schematic diagram of waveforms of word line erase voltages according to an embodiment of the present invention. picture. As shown in FIG. 3A , the uppermost waveform is the common source line erase voltage VERS_CSL applied to the common source line CSL, and the lower four waveforms are respectively applied to the first to fourth groups of word lines WLGP1~ The word line erase voltages VERS_WL1~VERS_WL4 of WLGP4. Each word line erase voltage VERS_WL1 ˜VERS_WL4 includes two parts, ie, a low-level voltage VERS_L and a high-level voltage VERS_H. In addition, the word line erase voltage may be, for example, 0˜3V. In an example, if the high-level voltage VERS_H is set to 3V, the low-level voltage VERS_L may be lower than 3V.

As shown in FIG. 3A , in this embodiment, the voltage values of the low level voltages VERS_L of the word line erase voltages VERS_WL1 ˜VERS_WL4 are substantially the same, and the voltage values of the high level voltages VERS_H are substantially the same of. However, the action time of the low-level voltage VERS_L of the word line erase voltages VERS_WL1 ˜VERS_WL4 is different, which are t1 , t2 , t3 and t4 respectively. Taking the word line erase voltage VERS_WL2 as an example, during the application period, the low-level voltage VERS_L is converted to the high-level voltage VERS_H after the time t2 elapses. Similarly, during the application of the word line erasing voltage VERS_WL3, the low-level voltage VERS_L is converted to the high-level voltage VERS_H after t3 is applied; during the application of the word-line erasing voltage VERS_WL4, the low-level voltage is applied The bit voltage VERS_L is converted to the high-level voltage VERS_H after the time t4 has elapsed. In addition, during the application of the word line erasing voltage VERS_WL1, since the corresponding erasing depth is the shallowest and the erasing speed is the slowest, it is not necessary to decelerate the erasing speed of the first group of word lines WLGP1, so the low accuracy The bit voltage VERS_L will continue to be sent for a time t1 (ie, the application time t of the common source line erase voltage VERS_CSL), without transitioning to the high-level voltage VERS_H.

As mentioned above, the fourth group of word lines WLGP4 has the fastest erasing speed, and the first group of word lines WLGP1 has the slowest erasing speed. Therefore, in order to make the erasing speed of the entire word lines WL0-WL47 more evenly distributed, the faster erasing speed needs to be slowed down.

By controlling the waveforms of the word line erasing voltages VERS_WL1~VERS_WL4 above, the erasing speed can be controlled. The fourth group of word lines WLGP4 needs to decelerate most early, and then the third group of word lines WLGP3 and the second group of word lines in sequence. WLGP2 and the first group of word lines WLGP1 have the slowest erasing speed, so there is no need to slow down. In order to control the erasing speed, the low-level voltage VERS_L should be pulled up to the high-level voltage VERS_H as soon as possible for deceleration. Therefore, for the fourth group of word lines WLGP4, the action time t4 of the low-level voltage VERS_L is the shortest, that is, the low-level voltage VERS_L is pulled up to the high-level voltage VERS_H at the earliest among all word line groups WLGP1~WLGP4. . In other words, the action time of the low-level voltage VERS_L in each of the word line groups WLGP1 to WLGP4 satisfies the following relationship.

t4(WLGP4)<t3(WLGP3)<t2(WLGP1)<t1(WLGP1)

In addition, the total active time of the word line erase voltages VERS_WL1 to VERS_WL4 of the word line groups WLGP1 to WLGP4 is the same, that is, the active time t of the common source line erase voltage VERS_CSL is the same. Therefore, the action times of the high-level voltage VERS_H in each word line group WLGP1 to WLGP4 are respectively t-t1, t-t2, t-t3, and t-t4, that is, the following relationship is satisfied.

t-t4(WLGP4)>t-t3(WLGP3)<t-t2(WLGP2)<t-t1=0(WLGP1)

Therefore, as described above, the word line erase voltage is controlled by the above The waveforms of VERS_WL1~VERS_WL4, in other words, control the action time of the low level voltage VERS_L (the time point when the low level turns to the high level) among the erase voltages VERS_WL1~VERS_WL4 of each word line, which can effectively control the erasing depth.

For example, for the fourth group of word lines WLGP4, the erasing depth is the deepest and the erasing speed is the fastest, so by converting the low-level voltage VERS_L of the word-line erasing voltage VERS_WL4 into the high-level voltage VERS_H first, The erasing speed can be slowed down the earliest, that is, the most slow down. For the first group of word lines WLGP1, its erasing depth is the shallowest and the erasing speed is the slowest, so the low-level voltage VERS_L of the word line erasing voltage VERS_WL1 will continue during the application of the word line erasing voltage VERS_WL1 applied without switching to the high-level voltage VERS_H. That is, the application period of the high-level voltage VERS_H of the word line erase voltage VERS_WL1 is 0 (t-t1=0).

3B is a schematic diagram illustrating the distribution of erase depth to word lines after an erase operation according to an embodiment of the present invention. As shown in FIG. 3B , after the word line erase voltages VERS_WL1 ˜VERS_WL4 shown in FIG. 3A are applied to the word line groups WLGP1 , WLGP2 , WLGP3 and WLGP4 , the first to fourth word line groups WLGP1 , WLGP2 , the erasing depths of WLGP3 and WLGP4 become approximately the same (uniform). For example, the fourth group of word lines WLGP4 changes from the conventional erase depth region I-4 to the shallower erase depth region II-4; similarly, the third group of word lines WLGP3 changes from the conventional erase depth region I- 3 becomes the shallower erasing depth region II-3, and the second group of word lines WLGP2 changes from the conventional erasing depth region I-2 to the erasing depth region II-2. In addition, since the first group of word lines WLGP1 does not decelerate the erasing speed, the erasing depth remains unchanged.

As a result, it can be seen that after the word lines are grouped according to the embodiment of the present invention, the The erasing depth is used to adjust the voltage action time of each level of the corresponding word line erasing voltage applied to each group of word lines, so that the distribution of the erasing depths of each group tends to be consistent. That is to say, the corresponding erasing depths of the second to fourth groups of word lines WLGP2 ˜ WLGP4 are adjusted to be consistent with the first group of word lines WLGP1 . In this way, the erasing depths of the first to fourth groups of word lines WLGP1 ˜ WLGP4 are approximately in the same range, so that a relatively uniform erasing depth can be obtained.

In addition, generally speaking, the higher the common source line erasing voltage, the deeper the erasing depth and the faster the erasing speed. In addition, under the same common source line erasing voltage, the longer the erasing time, the deeper the erasing depth, and the faster the erasing speed. As shown in FIG. 4 , the logarithm of the threshold voltage VT_ERS after the erasing operation and the erasing time T_ERS is roughly inversely proportional. Therefore, with each increase or decrease of an order of time, it is possible to know how the threshold voltage VT_ERS changes. In other words, if the threshold voltage after erasing is not to be too negative, the target threshold voltage can be obtained from the above relationship, and then the erasing time can be obtained.

Next, the reference for the word line grouping will be further described. In the above example, the outline of the vertical channel narrows as it goes down. Taking the example of FIG. 2 , the width of the vertical channel VC of the word line WL47 is larger, the width of the vertical channel VC is narrower as it goes down, and the vertical channel VC of the bottom word line WL0 is the narrowest. Therefore, in this case, the distribution of the erase depth also corresponds to the profile of the vertical channel VC. In the above grouping example, all word lines WL0 to WL47 are grouped from top to bottom and in the manner of adjacent word lines.

However, the profile of the etched vertical channel does not necessarily show such a change. For example, a vertical channel could have a wider profile at the top and bottom and a narrower profile in the middle, or any other possible profile. As mentioned above, the outline of the vertical channel is reflected in the erasing depth, so when grouping, the word lines can be grouped according to the outline of the vertical channel (ie, the erasing depth). In other words, word lines with relatively close vertical channel profiles (closer erasing depths) can be grouped into the same group. Likewise, word lines grouped in the same group will apply the same erase voltage waveform. Therefore, in this example, the grouping of word lines does not follow the sequence of word line numbers, but presents a state of dispersion.

Therefore, in addition to grouping all the word lines sequentially and evenly in the above embodiment, the word lines that are grouped into the same group may also be non-adjacent or discontinuous word lines.

FIG. 5 is a schematic diagram illustrating waveforms of word line erase voltages according to a variant of the present invention. In the description of the above embodiment, the waveform of the word line erase voltage is 2 as an illustration example, and this modification is a third-order modification. As shown in FIG. 5 , similarly, during the period t during which the common source line erase voltage VERS_CSL is applied, the third-order word line erase voltage VERS_WLi (corresponding to the i-th group of word lines WLGPi) is applied to each group of word lines, wherein The third-level word line erase voltage VERS_WLi may include a low-level voltage VERS_L, a middle-level voltage VERS_M, and a high-level voltage VERS_H. The application time of the low-level voltage VERS_L is, for example, ti1, the application time of the middle-level voltage VERS_M is, for example, ti2, and the application time of the high-level voltage VERS_H is, for example, t-ti1-ti2. In one embodiment, if the third group of word lines WLGP3 is the group with the slowest erasing speed, only the low-level voltage VERS_L can be applied, t31=t, t32=0, t-t31-t32=0, That is, the mid-level voltage VERS_M and the high-level voltage VERS_H are not applied to the third group of word lines WLGP3.

In this way, by controlling the time point at which the low-level voltage VERS_L transitions to the medium-level voltage VERS_M and the time point at which the medium-level voltage VERS_L transitions into the high-level voltage VERS_H, the corresponding erasing speed for each group of word lines can be determined. More granular control. Therefore, the erasing depth of the entire word line can be more finely controlled to be distributed more evenly, that is, the erasing depth can be compensated more accurately.

To sum up, the deeper the erasing depth of each group of multiple word lines, the longer the action time of the first-level voltage of the corresponding multi-level word line erasing voltages among the multiple multi-level word line erasing voltages. shorter. In other words, as shown in FIG. 3A , the corresponding erasing depth of the fourth group of word lines WLGP4 is the deepest, so the action time t4 of the first-level voltage (the second-level example is the low-level voltage VERS_L) is the shortest.

In addition, the voltage values of the corresponding levels of the multi-level word line erase voltages VERS_WL1 ˜VERS_WL4 are the same or different, but the action time is different. In the above example, the low-level voltages VERS_L and the high-level voltages VERS_H of the second-order word line erase voltages VERS_WL1~VERS_WL4 are the same, but the action times t1~t4 are different. In addition, the low-level voltages VERS_L of the multi-level word line erase voltages VERS_WL1 ˜VERS_WL4 may be set to be different, and the high-level voltages VERS_H may also be set to be different. This allows finer adjustments to be made to the erase depth compensation.

6A to 6C are schematic diagrams illustrating waveforms of word line erase voltages according to variations of the present invention. In the example described above, the time point when the word line erase voltage VERS_WL is applied is when the common source line erase voltage VERS_CSL rises and reaches It is applied only when the voltage value is stable, but the application period of the common source line erase voltage VERS_CSL referred to in the embodiment of the present invention may also include at least the following situations.

As shown in FIG. 6A , the time point when the word line erase voltage VERS_WL is applied may be the time point when the common source line erase voltage VERS_CSL starts to rise. In addition, as shown in FIG. 6B , the time point of applying the word line erase voltage VERS_WL may be between the time point (ts) when the common source line erase voltage VERS_CSL starts to rise from 0 (t=t0) to a stable voltage value applied at any point in time. That is, the time point at which the word line erase voltage VE_WL is applied is between the times t0 to ts shown in FIG. 6A . In addition, as shown in FIG. 6C , the time point at which the word line erase voltage VERS_WL is applied can be set earlier than the time point when the common source line erase voltage VERS_CSL starts to rise.

In addition, in the above embodiment, as shown in FIG. 2 , the common source line erase voltage is applied from the common source line CSL from the bottom side, that is, the erase voltage is applied from one side, but the present invention is not limited to this. . For example, the erase voltage can also be applied from the global bit line GBL. In addition, in addition to the method of applying the erase voltage on one side, the erase voltage can also be applied on both sides (ie, from the side of the common source line CSL and the side of the global bit line GBL). That is, the erase voltage may be applied from at least one of the common source line CSL from the bottom side and the global bit line GBL from the top side. In addition, the waveform of the erase voltage applied from the common source line CSL side and/or the bit line side may be the same.

FIG. 7 is a block diagram illustrating a control circuit of a flash memory according to an embodiment of the present invention. Figure 7 shows a simplified schematic diagram of the actual circuit architecture and functional blocks such as row decoders, column decoders, voltage generation circuits, various buffers, control logic, I/O circuits, etc. Those skilled in the art can rely on the concept of the present invention to It needs to be properly designed.

As shown in FIG. 7 , the flash memory includes at least but not limited to the memory control circuit 100 and the memory array 110 . The memory array 100 at least includes a plurality of memory cells, a plurality of word lines, a common source line, and a bit line, and by applying biasing to operate the plurality of memory cells in the flash memory for reading, programming or erasing. Here, the memory array 100 is not particularly limited. As mentioned above, the memory array 100 can be configured as a 3D or 2D NAND flash memory array.

The memory control circuit 100 is basically used to control all operations of the memory array 110, including reading, programming, and erasing. Here, the erasing operation is particularly described, and the rest of the operations such as reading and programming can be any existing operation methods. As described above, the erase operation performed by the memory control circuit 100 is mainly to compensate for the effect of uneven erase depth. The memory control circuit 100 divides the plurality of word lines into multiple groups of word lines WLGP1 ˜ WLGP4 according to the erasing depths corresponding to each of the plurality of word lines, and four groups are taken as an example herein.

The memory control circuit 100 generates a common source line erase voltage VERS_CSL and a plurality of multi-level word line erase voltages. Here, the four second-level word line erase voltages VERS_WL1 corresponding to the above-mentioned four groups of word lines WLGP1 to WLGP4 are used. ~VERS_WL4 as an example. In addition, as long as the technical effect of the present invention can be achieved, the memory control circuit 100 can generate the common source line erase voltage VERS_CSL and a plurality of multi-level word line erase voltages VERS_WL1 ˜VERS_WL4 in various ways and circuit structures. It is not particularly limited. Next, for the The common source line erase voltage VERS_CSL is applied to the same source line CSL, and during the period of applying the common source line erase voltage VERS_CSL, a plurality of multi-level word line erase voltages VERS_WL1 ˜VERS_WL4 are applied to each Group word lines WLGP1~WLGP4.

Here, for the description of the grouping method of the word lines, the waveform and application time of the multi-level word line erase voltage, etc., reference may be made to the above detailed description.

The above-mentioned embodiment takes 3D NAND flash memory as an illustrative example, but the present invention is not limited to NAND type flash memory, and other types of memory can also be applied. Besides, in addition to 3D NAND flash memory, the erase operation method of the present invention can also be applied to 2D flash memory. That is, if there is a problem of inconsistent erasing depths, the word lines of the 2D flash memory can also be grouped into groups. A description.

In addition, the erasing method of the present invention is not only applicable to memories with 2D or 3D architecture, but can also be applied to memory cells that store 1-bit single-level cells (SLC), and double-layer cells that store 2-bits. A cell, a triple-level cell (TLC) storing 3-bit cells, or a quad-level cell (QLC) storing four-bit cells, or a multi-level cell (MLC) structure.

To sum up, according to the embodiments of the present invention, when erasing is performed, the word line erase voltages applied to each group of word lines are two-level (or more) levels of voltages. In other words, for example, the first-stage word line erase voltage VERS_L is applied to a certain group of word lines, and then the second-stage erase word line voltage VERS_H is applied. Here, the word line erase voltage VERS_L of the first level is lower than the word line erase voltage VERS_H of the second level. this In addition, the total application time of the two-level (or more) word line erase voltages applied to each group of word lines is equal, that is, equal to the time of the common source line erase voltage applied to the common source line. Application time t. Therefore, for each group of word lines, the longer the time for applying the first level VERS_L of the word line erase voltage, the shorter the time for applying the second level word line erase voltage VERS_H. By adjusting the duration of applying the first-level word line erase voltage VERS_L, the erase depth of each group of word lines can be controlled. In this way, after the erase operation is performed on the flash memory, the overall erase depth can be distributed more uniformly, and the multi-component performance such as retention, read distribution, durability, etc., can be improved.

VERS_CSL: Common source line erase voltage

VERS_WL1~VERS_WL4: Word line erase voltage

WLGP1~WLGP4: word line group

VERS_L:

VERS_H: High level voltage

t: the application period of the common source line erase voltage

t1~t4: the action period of the low level voltage

Claims (10)

A method for erasing a flash memory, wherein the flash memory at least includes a memory array and a memory control circuit, and the memory control circuit controls a plurality of word lines included in the memory array, a common memory The source line and the global bit line are biased to erase a plurality of memory cells in the flash memory. The erasing method of the flash memory includes: according to and each of the plurality of words According to the corresponding erasing depth of the word line, the plurality of word lines are divided into multiple groups of word lines; the erasing voltage and a plurality of multi-level word line erasing voltages are generated; the common source line and the global bit element applying the erase voltage to at least one of the lines; and applying the plurality of multi-level word line erase voltages to the plurality of groups of word lines during the application of the erase voltage, wherein the A plurality of multi-level word line erase voltages are in a one-to-one correspondence with the plurality of groups of word lines, wherein a first value of each multi-level word line erase voltage of the plurality of multi-level word line erase voltages Except for the step, the rest are used to erase the speed for deceleration. The method for erasing a flash memory according to claim 1, wherein the deeper the erasing depth of each group of the multi-level word lines, the higher the corresponding erasing voltages of the plurality of multi-level word lines. The action time of the first-level voltage of the multi-level word line erase voltage is shorter. The method for erasing a flash memory according to claim 1, wherein the voltage values of the corresponding steps of the erase voltages of each of the plurality of multi-step word lines are different, but the action times are different. The method for erasing a flash memory according to claim 1, wherein the numbers of word lines in the plurality of groups of word lines are consecutive. The method for erasing a flash memory according to claim 1, wherein the numbers of word lines in the plurality of groups of word lines are discontinuous. A flash memory, comprising: a memory array, at least including a plurality of memory cells, a plurality of word lines, a common source line and a bit line, and by comparing the plurality of word lines, the common source lines and the global bit lines for applying bias voltages to operate the plurality of memory cells in the flash memory; and a memory control circuit for controlling the memory array, wherein the The memory control circuit further performs an erase operation, including: dividing the word lines into multiple groups of word lines according to the erase depth corresponding to each of the plurality of word lines; generating an erase voltage and a plurality of multiple word lines. step word line erase voltage; apply the erase voltage to at least one of the common source line and the global bit line; and during the application of the erase voltage, apply the erase voltage to the plurality of The multi-level word line erase voltages are applied to the plurality of groups of word lines, wherein the plurality of multi-level word line erase voltages are in a one-to-one correspondence with the multi-level word lines, wherein the plurality of multi-level word lines are in a one-to-one correspondence. The erasing voltage of each multi-level word line is used to decelerate the erasing speed except for the first level of the erasing voltage of each multi-level word line. The flash memory of claim 6, wherein the deeper the erasing depth of each group of the multi-level word lines, the corresponding multi-level words in the erasing voltages of the multi-level word lines The action time of the first-order voltage of the element line erase voltage is shorter. The flash memory of claim 6, wherein the voltage values of the corresponding steps of the erase voltages of the multi-step word lines are the same, but the action times are different. The flash memory according to claim 6, wherein the voltage values of the corresponding levels of the erase voltages of the multi-level word lines are different, but the action times are different. The flash memory of claim 6, wherein the numbering of word lines in the plurality of groups of word lines is discontinuous.

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