TWI775390B - Method of improving wafer warpage - Google Patents

Abstract

A method of improving wafer warpage is provided in the present invention, including steps of providing a substrate with multiple metal interconnects formed thereon, using HDP-CVD process to form a dielectric layer on the substrate and the metal interconnects, wherein the surface of dielectric layer is higher than the top surface of metal interconnects, performing a CMP process to planarize the dielectric layer, wherein the surface of planarized dielectric layer is higher than the top surface of metal interconnects, and forming a high stress TEOS layer on the dielectric layer.

Description

Ways to Improve Wafer Warpage

The present invention generally relates to a method of improving wafer warpage, and more particularly, to a method of improving wafer warpage through a highly stressed tetraethyl orthosilicate (TEOS) layer structure.

Three-dimensional chip (3D IC) is a technology that vertically integrates multiple chips or multiple wafers in three-dimensional space, in response to the limitation of semiconductor manufacturing process by the physical limitations of current electronics and materials. Among them, in the Wafer-on-Wafer (Wafer, WoW) technology, electronic components are built on two or more semiconductor wafers, and then the wafers are aligned, bonded, diced, etc. A 3D integrated circuit is formed, during which signal transmission between components is achieved through a vertical connection structure of through silicon via (TSV). The advantages of 3D wafers include: more functions can be integrated into a smaller layout space to extend Moore's Law, making a new generation of devices smaller but more powerful, reducing the cost of circuit design and manufacturing, circuit layers Can be built on different types of processes and wafers to achieve device optimization, require shorter interconnects, and greatly reduce the power consumption required by the chip.

However, stacked wafer technology has very strict requirements on the warpage of the constituent wafers. In general, the layer structure formed on the wafer imposes stress on the wafer, either tensile or compressive, causing the wafer to warp up or down. Wafers with severe warpage will affect the bonding of wafers and their electrical connections after stacking. Therefore, how to improve wafer warpage is an important issue in 3D wafer technology one.

In view of the aforementioned conventional problem of wafer warpage, the present invention hereby proposes a method for improving wafer warpage, which is characterized by additionally forming tetraethoxysilane ( tetraethyl orthosilicate, TEOS) layer to offset the inherent stress of the wafer. At the same time, this method can also avoid the generation of holes between the metal interconnect lines.

An object of the present invention is to provide a method for improving wafer warpage, the steps of which include providing a substrate on which a plurality of metal interconnects are formed, and using a high-density plasma chemical vapor deposition process on the substrate and the substrates. A dielectric layer is formed on the metal interconnects, wherein the surface of the dielectric layer is higher than the top surface of the metal interconnects, a chemical mechanical planarization process is performed to planarize the dielectric layer, and the planarized dielectric The surface of the layer is higher than the top surface of the metal interconnects, and a first high stress tetraethoxysilane layer is formed on the dielectric layer.

These and other objects of the present invention should become more apparent to the reader after reading the following detailed description of the preferred embodiment described in the various figures and drawings.

100: base

102: Metal Interconnects

104: Dielectric layer

106: High stress tetraethoxysilane (TEOS) layer

108: High stress tetraethoxysilane (TEOS) layer

110: Hole

S1~S8: Steps

This specification contains accompanying drawings, which constitute a part of this specification, so as to enable readers to have a further understanding of the embodiments of the present invention. The drawings depict some embodiments of the invention and together with the description herein explain the principles thereof. Among these figures: Figures 1 to 3 are cross-sectional schematic diagrams of a method for improving wafer warpage according to a preferred embodiment of the present invention; Figure 4 is a first high The ratio of the thickness of the stressed TEOS layer to the wafer warpage Figure 5 to Figure 7 are cross-sectional schematic diagrams of a method for improving wafer warpage according to another embodiment of the present invention; Figure 8 is another embodiment of the present invention. A line graph showing the normalized value of the thickness ratio of the second high stress TEOS layer to the wafer warpage; and FIG. 9 is a block flow diagram of a method for improving wafer warpage according to another embodiment of the present invention.

It should be noted that all the illustrations in this specification are of the nature of illustrations. For the sake of clarity and convenience of illustration, the sizes and proportions of the components in the illustrations may be exaggerated or reduced. The same reference characters will be used to designate corresponding or similar element features in modified or different embodiments.

Exemplary embodiments of the present invention will now be described in detail below, which will illustrate the described features with reference to the accompanying drawings to facilitate the reader's understanding and to achieve technical effects. The reader will understand that the description herein is by way of illustration only and is not intended to limit the present case. The various embodiments of the present invention and various features of the embodiments that do not conflict with each other may be combined or rearranged in various ways. Modifications, equivalents or improvements to the present invention will be understood by those skilled in the art without departing from the spirit and scope of the present invention, and are intended to be included within the scope of the present invention.

Readers should be able to easily understand that the meanings of "on", "on" and "above" in this case should be interpreted in a broad sense, so that "on" not only means "directly on" "on" something but also includes the meaning of "on" something with intervening features or layers, and "on" or "over" means not only "on" something "on" or The meaning of "above", but can also include its meaning "on" or "over" something without intervening features or layers (ie, directly on something).

Furthermore, spatially relative terms such as "below", "below", "lower", "above", "upper" and the like may be used herein for descriptive convenience to describe one element or feature with another The relationship of one or more elements or features as illustrated in the accompanying drawings.

A reader can usually understand a term, at least in part, from its usage in the context. For example, the term "one or more" as used herein may be used to describe any feature, structure or characteristic in the singular or may be used to describe a combination of features, structures or characteristics in the plural, depending at least in part on the context. Similarly, terms such as "a," "an," "the," or "said" may likewise be understood to convey singular usages or to convey plural usages, depending at least in part on context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but may allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on context.

As used herein, the term "layer" refers to a portion of a material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure, or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any horizontal faces at the top and bottom surfaces. Layers can extend horizontally, vertically and/or along inclined surfaces. A substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, over it, and/or under it. Layers may include multiple layers. For example, the interconnect layer may include one or more conductor and contact layers (in which contacts, interconnect lines and/or vias are formed) and one or more dielectric layers.

Readers will better understand that when the words "comprising" and/or "comprising" are used in this specification, they clearly identify the existence of the stated features, regions, integers, steps, operations, elements and/or parts, but do not The presence or addition of one or more other features, regions, integers, steps, operations, elements, components and/or combinations thereof is not excluded.

Now, the following embodiments will sequentially illustrate the flow of the method for improving wafer warpage of the present invention according to the cross-sectional structures of FIGS. 1 to 3 . It should be noted that the method for improving wafer warpage of the present invention is preferably implemented in In the inter-metal dielectric layer (IMD) in the semiconductor back-end process (BEOL), especially in the wafers that are to be stacked and bonded subsequently, to ensure good electrical properties after wafer stack bonding Connected invention claims. As for the structures and components generally included in the front-end semiconductor process (FEOL), such as active regions, transistors, etc., since they are not the focus of the present invention and have nothing to do with the features of the present invention, for the sake of simplicity of illustration and description, Fig. These elements will be omitted.

Referring first to FIG. 1, a substrate 100 is provided, such as a substrate formed of semiconductor materials, wherein the semiconductor materials can be selected from the group consisting of silicon, germanium, silicon germanium compound, silicon carbide, and gallium arsenide. The substrate 100 preferably includes an active region, a transistor, an inter-layer dielectric (ILD) and/or an inter-metal dielectric (IMD), a metal interconnect structure, and other structures (not shown). Show). Metal interconnect lines 102 are formed on the substrate 100 , which are spaced apart and have top surfaces of the same height. In the embodiment of the present invention, the metal interconnection line 102 can be a metal interconnection layer in a general back-end process, such as M1, M2, M3 and other metal interconnection layers, and its material can be aluminum-copper alloy, which can be a physical vapor deposition process. (PVD) or various chemical vapor deposition (CVD) processes to form a metal layer and then pattern it through a photolithography process. Vias (not shown) may be electrically interconnected between different metal interconnect layers.

Please refer to Figure 2. After the metal interconnection lines 102 are formed, a dielectric layer 104 is then formed on the substrate 100 and the metal interconnection lines 102 . In the embodiment of the present invention, the dielectric layer 104 can be an intermetal dielectric layer, and the material thereof can be silicon oxide or a low-k material, such as porous silicon oxide, fluorine-doped silicon oxide (SiOF). ), carbon-doped silicon oxide (SiOC), amorphous carbon (a-C and a-C:H), fluorinated amorphous carbon (a-C:F), etc., can be deposited through high-density plasma chemical vapor deposition ( HDP-CVD) process to avoid holes between the metal interconnect lines 102 . After the dielectric layer 104 is formed, a chemical mechanical planarization (CMP) process may be performed to planarize its surface. The planarized surface of the dielectric layer 104 is higher than the top surface of the metal interconnection line 102 .

In the prior art, the high-density plasma chemical vapor deposition process has good hole-filling properties, but the low-stress property of the resulting layer structure cannot improve the wafer warpage problem. In this regard, the present invention intends to form an additional layer structure to solve this problem. Referring to FIG. 3, after the dielectric layer 104 is formed, Next, a first highly stressed tetraethyl orthosilicate (TEOS) layer 106 is formed on the surface of the dielectric layer 104, which can be formed by a plasma-assisted chemical vapor deposition (PECVD) process. After the first high stress tetraethoxysilane layer 106 is formed, a chemical mechanical planarization process can be performed to planarize the surface and control the thickness thereof.

In an embodiment of the present invention, the stress of the first high-stress TEOS layer 106 varies with its deposition thickness. As shown in FIG. 4, which is a line graph of the ratio of the thickness of the first high stress TEOS layer 106 to the normalized value of the wafer warpage, the x-axis in the figure represents the first high stress TEOS layer A thickness ratio of 106, where POR represents a standard process that does not use a TEOS layer at all (thickness 0), 100% represents a case where the thickness of the TEOS layer is maximized, and so on. The y-axis represents the normalized warpage of the wafer on which the first high-stress TEOS layer 106 is formed, wherein a positive value represents the degree of downward warpage of the wafer, and a negative value represents the upward warpage of the wafer. degree. As can be seen from the figure, in the embodiment of the present invention, in the standard process (POR) in which the TEOS layer is not formed at all, the wafer will warp down due to the stress generated by the various layer structures formed thereon ( The normalized value is 1). In the case where the maximum thickness of the TEOS layer is formed, the stress causing the wafer to warp downwards is offset by the stress created by the first high stress TEOS layer 106, and the stress created is even too great to cause the wafer to warp downward. Warp up (normalized to -1.37). In the case of forming the first high stress TEOS layer 106 with a thickness of about 52.4%, the stress of the wafer warping down is just offset by the stress generated by the deposition of the first high stress TEOS layer 106, so that the wafer Best efficacy is achieved with almost no warpage in any direction (normalized value of -0.49). Therefore, in the embodiment of the present invention, forming the first high-stress TEOS layer 106 with a specific thickness on the gap-filled dielectric layer 104 can effectively improve the problem of wafer warpage.

Now, the flow of a method for improving wafer warpage according to another embodiment of the present invention will be described in sequence according to the cross-sectional structures of FIGS. 5 to 7 . In this embodiment, in addition to the first high stress TEOS layer 106 mentioned in the previous embodiments, before the dielectric layer 104 is formed, an additional high stress TEOS layer may be formed on the substrate. Referring to FIG. 5, after the metal interconnection lines 102 are formed, another second high stress TEOS layer 108 is firstly formed on the substrate 100, which can be formed by a plasma-assisted chemical vapor deposition (PECVD) process. formed, and its thickness can be controlled through a subsequent planarization process and/or an etch-back process. In the embodiment of the present invention, the surface of the second high stress TEOS layer 108 is lower than the top surface of the metal interconnection lines 102 and located between the metal interconnection lines 102 .

Please refer to Figure 6. After the second high stress TEOS layer 108 is formed, a dielectric layer 104 is then formed on the second high stress TEOS layer 108 and the metal interconnection lines 102 . The dielectric layer 104 can be an inter-metal dielectric layer, and its material can be silicon oxide or a low-k material, such as porous silicon oxide, silicon oxide doped with fluoride (SiOF), silicon oxide doped with carbon (SiOF). SiOC), amorphous carbon (a-C and a-C:H), fluorinated amorphous carbon (a-C:F), etc., can be formed by a high-density plasma chemical vapor deposition (HDP-CVD) process. In the embodiment of the present invention, since the second high stress TEOS layer 108 does not have good hole filling capability, after the dielectric layer 104 is formed, there will be holes between the dielectric layer 104 and the second high stress TEOS layer 108 110 is formed. However, since the dielectric layer 104 is formed by high-density plasma chemical vapor deposition (HDP-CVD) with good hole-filling capability, the formed holes 110 are limited to a portion close to the second high-stress TEOS layer 108 . Its top does not exceed the top surface of the metal interconnection line 102, so that the holes can be prevented from affecting subsequent processes.

Referring to FIG. 7 , after the dielectric layer 104 is formed, a chemical mechanical planarization (CMP) process is then performed to planarize the surface of the dielectric layer 104 . The planarized surface of the dielectric layer 104 is higher than the metal interconnection line 102 top. Afterwards, as in the previous embodiment, a first high stress TEOS layer 106 is formed on the surface of the dielectric layer 104, which may be formed by a plasma-assisted chemical vapor deposition (PECVD) process. After the first high stress TEOS layer 106 is formed, a chemical mechanical planarization process can be performed to planarize the surface and control the thickness thereof.

In the embodiment of the present invention, the stress of the second high-stress TEOS layer 108 formed on the substrate 100 varies with its deposition thickness, which also has the effect of improving wafer warpage. As shown in Figure 8, where POR represents a standard process that does not use a TEOS layer at all (thickness is 0), percentage represents the thickness ratio of the formed TEOS layer, and so on. The y-axis represents the normalized warpage of the wafer on which the second high-stress TEOS layer 108 is formed, wherein the positive value represents the degree of wafer warpage downward, and the negative value represents the wafer warpage upward. degree. As can be seen from the figure, in the embodiment of the present invention, the TEOS layer is not formed at all. In standard process (POR), the wafer will warp down (normalized to a value of 1) due to the stress generated by the various layer structures formed on it. In the case where the second high stress TEOS layer 108 is formed on the substrate 100, the portion of the stress that causes the wafer to warp down is offset by the stress created by the deposition of the second high stress TEOS layer 108 (normalized down to 0.64) to improve the problem of wafer warpage.

Please refer now to FIG. 9, which is a flow chart of a method according to the above-described embodiment of the present invention. First, in step S1, a second high stress TEOS layer 108 is deposited on the substrate 100 (as shown in FIG. 5). Next, in step S2, a dielectric layer 104 is deposited on the second high stress TEOS layer 108 using a high density plasma chemical vapor deposition (HDP-CVD) process (as shown in FIG. 6). Next, in step S3, a CMP process is performed to planarize the dielectric layer 104 (as shown in FIG. 7). Next, in step S4, a first high stress TEOS layer 106 is deposited on the dielectric layer 104 (as shown in FIG. 7). Next, in step S5, a CMP process is performed to planarize the first high stress TEOS layer 106 (as shown in FIG. 7). After the above process is completed, the next step S6 can measure the warpage of the wafer, for example, through a special optical measuring machine or a pressure measuring machine, which can measure the warpage of the wafer is within the allowable range. After passing the wafer warpage measurement, in step S7, the wafer can be sliced to confirm whether the holes formed between the metal interconnect lines exceed the top surface. Go to step S1, reset the thicknesses of the first high-stress TEOS layer 106 and the second high-stress TEOS layer 108 to be deposited, and repeat the above steps S1-S7 until the measurement of wafer warpage and the detection of hole slices All passed, so that the thickness of the two high-stress TEOS layers can be set at the optimal value to ensure the quality of the final actual product after the line. If not, the flow ends S8.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

S1-S8: Steps

Claims (7)

A method of improving wafer warpage, comprising: providing a substrate on which a plurality of metal interconnects are formed; using a high-density plasma chemical vapor deposition process to form a space between the substrate and the metal interconnects an electrical layer, wherein the surface of the dielectric layer is higher than the top surface of the metal interconnects; a chemical mechanical planarization process is performed to planarize the dielectric layer, and the surface of the planarized dielectric layer is higher than the the top surface of the metal interconnection line; and forming a first high stress tetraethoxysilane layer on the dielectric layer, wherein the stress of the first high stress tetraethoxysilane layer follows the first high stress tetraethoxysilane layer. The thickness of the ethoxysilane layer varies, and the stress of the first high stress tetraethoxysilane layer is set to offset the inherent stress of the substrate. The method for improving wafer warpage as described in claim 1 of the claimed scope further comprises forming a second high stress tetraethoxysilane layer on the substrate before forming the dielectric layer, wherein the second high stress tetraethoxysilane layer is formed on the substrate. The surface of the stressed tetraethoxysilane layer is lower than the top surfaces of the metal interconnects and between the metal interconnects, and the dielectric layer is formed on the second high-stressed tetraethoxysilane layer. The method for improving wafer warpage as described in claim 2, wherein a hole is formed between the dielectric layer and the second high stress tetraethoxysilane layer, and the top of the hole is lower than the metals The top surface of the interconnect. The method for improving wafer warpage as described in claim 2, wherein the second high stress tetraethoxysilane layer is formed using a plasma-assisted chemical vapor deposition process. The method for improving wafer warpage as described in claim 2, wherein the second highest The stress of the stressed tetraethoxysilane layer varies with its thickness, and the stress of the second highly stressed tetraethoxysilane layer is set to offset the inherent stress of the substrate. The method for improving wafer warpage as described in claim 1, wherein the first high stress tetraethoxysilane layer is formed using a plasma-assisted chemical vapor deposition process. The method for improving wafer warpage as described in item 1 of the claimed scope further comprises performing another chemical mechanical planarization process after the first high stress tetraethoxysilane layer is formed to planarize the first high stress tetraethoxysilane layer. Ethoxysilane layer.

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