TWI775000B - Method for generating a layout of integrated circuit and method for processing layout of integrated circuit - Google Patents

Abstract

A method of generating an integrated circuit layout diagram includes arranging first cells having a first cell height in a first row and arranging second cells having a second cell height less than the first cell height in a second row abutting the first row. The first row and the second row extend along a first direction and are laid out relative to a routing grid including first routing tracks along the first direction and second routing tracks along a second direction perpendicular to the first direction. First cell pins are placed within each first cell extending along second routing tracks. Second cell pins are placed over selected via placement points in each second cell. At least one second cell pin extends along a corresponding second routing track across a boundary of a corresponding second cell and into a corresponding first cell abutting the corresponding second cell.

Description

Method for generating an integrated circuit layout diagram and for processing the same System of integrated circuit layout diagrams

This case relates to a method of generating an integrated circuit layout, and more particularly, to a method of generating an integrated circuit layout with pins of different cell heights and a system for processing the integrated circuit layout.

Over the past few decades, the scaling of semiconductor components has followed Moore's Law. Due to lithography and integration constraints, advances in manufacturing processes cannot independently keep pace with constant device scaling trends, so layout design techniques also aid in further scaling of semiconductor devices.

According to an embodiment of the present application, it is directed to a method of generating a layout of an integrated circuit, the method comprising arranging a plurality of first cells having a first cell height in a first column; arranging in a second column adjacent to the first column A plurality of second cells with the height of the second cell, the height of the second cell is smaller than the height of the first cell degrees, and the first and second columns extend in a first direction and are arranged relative to a routing grid comprising a plurality of first routing traces extending in the first direction and a plurality of second routing traces extending in the second direction routing traces, the second direction is perpendicular to the first direction; placing a plurality of first cell pins within each first cell of the plurality of first cells, each of the plurality of first cell pins along the plurality of first cells Corresponding second routing traces of the two routing traces extend; and placing a plurality of second cell leads over a plurality of selected via placement points in each second cell of the plurality of second cells, the plurality of second cell leads At least one second cell pin of the pins extends across the boundary of the corresponding second cell of the plurality of second cells and to a plurality of the second cells adjacent to the corresponding second cell along a corresponding second wiring trace of the plurality of second wiring traces. in the corresponding first unit of a unit.

An embodiment according to the present application relates to a method for generating a layout diagram of an integrated circuit, comprising: arranging a plurality of first cells having a first cell height in a plurality of first columns; arranging in a plurality of second columns a plurality of second cells having a second cell height, the second cell height being smaller than the first cell height, wherein the first and second columns are arranged according to a wiring grid, the wiring grid including extending in a first direction a plurality of first wiring traces and a plurality of second wiring traces extending in a second direction, the second direction being perpendicular to the first direction; a plurality of selected first vias in each of the first cells A plurality of first cell pins are placed over the layout points, wherein each first cell pin of the first cell pins extends along a corresponding second routing trace of the second routing traces and has a within the top and bottom boundaries of a respective first cell; and placing a plurality of second cell pins over a plurality of selected via placement points in each second cell of the second cells, wherein the At least A second cell pin extends across a boundary of a corresponding second cell of the second cell along a corresponding second one of the second routing traces and to a corresponding first cell of the first cell adjacent to the corresponding second cell in the unit.

An embodiment according to the present application relates to a system for processing layouts of integrated circuits, comprising: a non-transitory computer-readable storage medium for storing a plurality of instructions thereon; and connecting to the non-transitory computer A processor of a readable storage medium, wherein the processor is used to execute instructions to: obtain a first unit from a database stored in a non-transitory computer-readable storage medium, wherein the first unit has a first height; obtain a second unit from the database, wherein the second unit has a second height different from the first height; arrange the first unit in a first row extending in a first direction; in a row adjacent to the first row Arranging the second cells in a second column, wherein the second column extends in the first direction; placing a plurality of first cell pins within the first cell, wherein each of the first cell pins extends perpendicular to the first direction and placing a plurality of second cell pins on a plurality of selected via layout points within the second cell, wherein the second cell extends in the second direction, and at least a first The two cell leads extend beyond a boundary of the second cell and into the first cell.

100, 300: Method for generating an integrated circuit layout diagram

102, 104, 106, 108, 110, 112, 302, 304, 306, 308, 310: Steps

200A, 200B, 200C, 200D, 200E, 200F, 400A, 400B, 400C: Layout

202: Unit 1

204: Unit Two

206a~206e: Power rail

212A, 214A: Top border

212B, 214B: Bottom border

212C, 214C: Side borders

220: First Conductive Thread

222, 224, 226, 228: the first conductive line

232, 234, 236: the second conductive line

240, 240(1)~240(5): The first unit pin

242: first through hole

250, 250(1)~250(6): Through-hole layout points

260: Second unit pin

260': unit pin

260(1), 260(2): Second unit pins

262: second through hole

270: First Via Layout Point

500: Electronic Design Automation (EDA) Systems

502: Processor

504: Non-transitory computer-readable storage medium

506: Computer code (instruction)

507: Standard Cell Library

508: Busbar

510: I/O interface

512: Network interface

514: Internet

542: User Interface

600: IC Manufacturing Systems

620: Design Studio

622: IC Design Layout

630: Mask Room

632: Data preparation

644: Mask Making

645:Mask

650: IC Manufacturer/Manufacturer/fab

652: Wafer Fabrication

653: Wafer

660: Device

Aspects of an embodiment of the present case are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

FIG. 1 is a flowchart of a method of generating a layout of an integrated circuit (IC) according to an embodiment; FIGS. 2A to 2F are depictions of layouts at various stages of generating an IC layout according to an embodiment. ; Figure 3 is a flowchart of a method for generating a layout diagram of an IC according to an embodiment; Figure 4A to Figure 4C are a depiction of a layout diagram of each stage of generating an IC layout diagram according to an embodiment; Figure 5 is a block diagram of an electronic design automation (EDA) system according to an embodiment; and FIG. 6 is a block diagram of an IC manufacturing system and an IC manufacturing process associated therewith, according to an embodiment.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components, materials, values, steps, operations, materials, arrangements, or the like are described below to simplify an embodiment of the present case. Of course, these are only examples and are not intended to be limiting. Covers other components, values, operations, materials, arrangements or the like. For example, in the description below, the formation of a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments that may be formed on the first feature Embodiments in which additional features are formed with the second feature such that the first feature and the second feature may not be in direct contact. Additionally, an embodiment of the present case may repeat reference numerals and/or letters in each instance. this repeat It is for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

Additionally, for ease of description, spatially relative terms such as "below," "below," "lower," "above," "upper," and the like may be used herein to describe an element illustrated in the figures or The relationship of a feature to another element(s) or feature(s). In addition to the orientation depicted in the figures, spatially relative terms are intended to encompass different orientations of elements in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and thus the spatially relative descriptors used herein may be interpreted similarly.

Some integrated circuit (IC) designs are based on a collection of cells selected from a library. A layout includes at least one logical block customized for a specific purpose. A logic block is an arrangement of cells placed in a routing grid of vertical and horizontal routing traces. Conductive structures such as metal lines are placed on the routing traces to provide connections between cells. The design of the IC layout is performed by an automatic placement and routing (APR) tool, which includes a placer and a router, by selecting standard cells from a standard cell library and placing and routing the cells according to a number of design rules . The placer decides the best position of each standard cell of the integrated circuit, and the placer optimizes the routing of the input/output lines and the connection between the standard cells so that the IC layout is not changed by the input/output and other wiring. Overcrowded.

Placers and routers use many design rules to decide where to place cells and how to generate wires to connect all cells. Design rules include, for example, minimum lengths of lines, minimum spacing between lines, and the like. in some In some cases, failure to meet design rules sometimes leads to process-related problems, such as shorts between metal lines due to optical proximity.

The height of the cell is determined by the number of horizontal tracks extending between the top and bottom edges of the cell. Cells with smaller cell heights are used to achieve high integration and low power consumption, while cells with higher cell heights are used for high-speed operation. In some logic blocks, standard cells have the same cell height to facilitate cell placement and routing.

As the demand for high speed and low power integrated circuits suitable for portable electronic applications has increased, logic blocks have been modified to include standard cells of different cell heights. In this type of hybrid cell design, standard cells are arranged in multiple columns, and only standard cells with the same height are placed in one column.

A mixed cell design using standard cells of different cell heights in one logic block helps achieve both high speed and low power in an integrated circuit layout design. However, in hybrid cell designs, cell pins used to transmit signals between cells, such as input and output pins, suffer from a substantial reduction in end-to-end spacing and pin access area. Therefore, cell routing is performed using an extra cut mask. The use of additional cut masks often results in increased manufacturing costs.

In some embodiments, a layout design method for implementing cell pin placement and routing for cells of different cell heights is provided. The layout design method allows pin placement and routing of high-speed cells and low-power cells in the same logic block without the use of additional cut masks to comply with existing design rules. Therefore, the layout design method of an embodiment of the present application helps in the traditional uniform The same process cost is maintained when the cell height design is changed to a mixed cell height design.

FIG. 1 is a flowchart of a method 100 of generating an integrated circuit (IC) layout 200F according to an embodiment. In various embodiments, the operations of method 100 are performed in the order depicted in FIG. 1 or in one or more orders other than the order depicted in FIG. 1 . In some embodiments, one or more additional operations are performed before, during, during, and/or after one or more operations of method 100 are performed. The method 100 is described below in conjunction with FIGS. 2A-2F, which include views of various stages of generating the layout 200F.

Some or all of the operations of method 100 can be performed as part of an automatic place and route (APR) tool. In some embodiments, some or all of the method 100 is performed by a processor of a computer. In some embodiments, some or all of method 100 is performed by processor 502 of electronic design automation (EDA) system 500 discussed below with respect to FIG. 5 . In some embodiments, some or all of the operations of method 100 can be performed as part of a design program executed in a design studio, eg, design studio 620 discussed below with respect to FIG. 6 .

Referring to FIGS. 1 and 2A, the method 100 includes step 102, wherein a plurality of first conductive lines 220-228 for the plurality of first cells 202 are placed along corresponding horizontal wiring traces of the plurality of horizontal wiring traces HT1-HT21 and For the plurality of conductive lines 232˜236 of the plurality of second cells 204, the first cell 202 has a first cell height CH1 and the second cell 204 has a second cell height CH2, and the second cell height CH2 is smaller than the first cell height CH1; Arrange the first unit 202 and the second unit 204 in plural columns. 2A is a layout diagram of an IC after placing a plurality of first conductive lines 220 - 228 and a plurality of second conductive lines 232 - 236 along respective ones of the plurality of horizontal wiring traces HT1 - HT21 according to an embodiment 200A.

Referring to FIG. 2A , a layout diagram 200A includes a plurality of cells of different cell heights arranged in respective columns, such as a first cell 202 of a first cell height CH1 and a second cell 204 of a second cell height CH2 . To simplify the description, the layout diagram 200A includes four columns, namely, a first column (Column 1), a second column (Column 2), a third column (Column 3), and a fourth column (Column 4). In some embodiments, the floor plan 200A includes many columns other than four. Each of the plurality of columns column 1 to column 4 extends in the X direction. In some embodiments, the X direction is the horizontal direction of the floor plan 200A. In some embodiments, the X direction is a direction other than horizontal. The columns of the plurality of columns column 1 to column 4 are adjacent to each other in the Y direction, which is perpendicular to the X direction. In some embodiments, the Y direction is the vertical direction of the floor plan 200A. In some embodiments, the Y direction is a direction other than vertical.

A plurality of columns, such as columns 1 to 4, are arranged relative to a wiring grid defined by a plurality of horizontal wiring traces HT1-HT21 and a plurality of vertical wiring traces VT1-VT20. Horizontal wiring traces HT1 to HT21 are arranged in parallel along the X direction. Each horizontal routing trace HT1~HT21 represents a potential routing path of the IC along the X direction. In some embodiments, each of the horizontal wiring traces HT1 - HT21 is spaced an equal distance from the adjacent horizontal wiring traces HT1 - HT21 . The vertical wiring traces VT1 to VT20 are arranged in parallel along the Y direction. Each vertical wiring trace VT1~VT20 represents the IC along the Y direction Potential routing paths. In some embodiments, each of the vertical wiring traces VT1-VT20 is spaced an equal distance from adjacent vertical wiring traces VT1-VT20. In some embodiments, two adjacent vertical routing traces of the plurality of vertical routing traces VT1-VT20 are separated by a nominal minimum distance to form a sharp pattern with a single exposure of a single photomask at a given technology node (without using double patterning techniques). Therefore, two vertical second wiring traces of the plurality of vertical wiring traces VT1 to VT20 are designated to have the same color (not shown). In some embodiments, odd vertical routing traces VT1, VT3, . double patterning technique), while the even vertical routing traces VT2, VT4, ..., VT20 are spaced a minimum distance from each other to form a clear pattern at a given technology node with a single exposure of a single photomask (without using double patterning technique). Therefore, the distance (ie, the pitch P) between two adjacent vertical wiring traces of the plurality of second wiring traces VT1 to VT20 is smaller than the minimum distance allowed by a single patterning lithography. In Figure 2A, a first color, such as color A, or a second color, such as color B, is assigned to each of the vertical wiring traces VT1-VT20. Starting from vertical wiring trace VT1, each vertical wiring trace VT1 to VT20 is assigned either color A or color B so that two adjacent vertical wiring traces do not have the same color. In Fig. 2A, every other vertical wiring trace VT1 to VT20 are assigned the same color. For example, odd-numbered vertical wiring traces VT1, VT3, . . . , VT19 are designated as color A, and even-numbered second wiring traces VT2, VT4, . color (eg, Color A, Color B) indicates that features of the same color will be formed on the same mask of multiple mask sets, and features of different colors will be formed on different masks of multiple mask sets.

During the layout stage, cells 202 and 204 are placed adjacent to each other by the APR tool. In some embodiments, cells 202 and 204 are arranged such that cells placed in the same column have the same cell height, but the widths of cells 202 or 204 in the same column vary. In some embodiments, the first cells 202 and the second cells 204 are alternately placed in a plurality of columns Column 1 to Column 4 . In Figure 2A, the first cells 202 with the first cell height CH1 are placed in odd columns, such as columns 1 and 3, and the second cells 204 with the second cell height CH2 are placed in the even columns, For example, column 2 and column 4. In some embodiments, the first cell height CH1 is set to be greater than the second cell height CH2. The cell height CH of a cell (eg, cell 202 or 204 ) is determined by the number of horizontal wiring traces HT1 to HT21 surrounding between the uppermost edge and the lowermost edge of the cell 202 or 204 . In some embodiments, each first cell 202 has a track height of seven (7) and each second cell 204 has a track height of five (5). The first cell 202 with a relatively large cell height CH1 operates at higher speeds and is therefore suitable for high speed applications. The second cell 204 with a relatively small cell height CH2 operates at less power and thus can be used for low power applications. Although cells in adjacent columns in Figure 2A have different cell heights, cells in adjacent columns with the same height are encompassed in one embodiment of the present case. In some embodiments and in Figure 2A, the number of columns in the plurality of columns used to place the first cell 202 is equal to the number of columns in the plurality of columns (eg, column 2 and column 4) used to place the second cell 204 number of columns (for example, column 1 and column 3). Those skilled in the art will understand that, in some embodiments, the number of columns in the plurality of columns used to place the first cells 202 is different from the number of columns in the plurality of columns used to place the second cells 204 (not shown). Show).

In some embodiments, cells 202 and 204 are standard cells. Standard cells include but are not limited to not (INV), and (AND), or (OR), inverse and (NOR), inverse or (XOR), exclusive or (AOI), or and not (OAI), multiplexer , buffers, adders, fillers, flip-flops, latches, delays, clock units or the like. Alternatively, units 202 and 204 are custom units. During the layout stage, cells 202 and 204 are placed by the APR tool.

Each of the first cells 202 has a substantially rectangular shape, including a top boundary 212A, a bottom boundary 212B, and opposing side boundaries 212C. The top boundary 212A and the bottom boundary 212B are parallel to the X direction. The side boundary 212C is parallel to the Y direction. The height of each first cell 202, ie, cell height CH1, is defined between the top boundary 212A and the bottom boundary 212B. Likewise, each of the second cells 204 has a substantially rectangular shape, including a top boundary 214A, a bottom boundary 214B, and opposing side boundaries 214C. The top boundary 214A and the bottom boundary 214B are parallel to the X direction. Side boundary 214C is parallel to the Y direction. The height of each second cell 204, ie, cell height CH2, is defined between the top boundary 214A and the bottom boundary 214B. When a first cell 202 in a column (eg, column 1 or column 3) abuts a second cell 204 in an adjacent column (eg, column 2 or column 4), the top and bottom boundaries 214A, 214B of the second cell 204 Merged with the respective top and bottom boundaries 212A, 212B of the first cells 202 in adjacent columns Column 1-4. For example, in Figure 2A, the top boundary 214A of the second cell 204 in column 2 is merged with the bottom boundary 212B of the first cell 202 in column 1, the bottom boundary 214B of the second cell 204 in column 2 is merged with the top boundary 212A of the first cell 202 in column 3, and the second cell in column 4 The top boundary 214A of 204 merges with the bottom boundary of the first cell 202 in column 3.

The layout diagram 200A further includes a plurality of power rails, such as 206a-206e, which extend along the boundaries of the plurality of columns 1-4. In Figure 2A, power rail 206b exists at the common boundary of columns 1 and 2, power rail 206c exists at the common boundary of columns 2 and 3, and power rail 206d exists at the common boundary of columns 3 and 4 place. Each of the power rails 206a-206e is used to provide one of the supply voltage potential Vdd and the ground voltage potential Vss to the cell 202 or 204 in the corresponding row 1-4. The power rails 206a-206e are rectangular with long axes substantially aligned with corresponding horizontal routing traces (eg, HT1, HT7, HT11, HT17, and HT21). In some embodiments, the top boundary 212A of each first cell 202 is defined in the middle of the respective power rail 206a or 206c, and the bottom boundary 212B of each first cell 202 is defined in the middle of the respective power rail 206b or 206b. Additionally, the top boundary 214A of each second cell 204 is defined in the middle of the respective power rail 206b or 206d, and the bottom boundary 214B of each second cell 204 is defined in the middle of the respective power rail 206c or 206e.

Each of the first cells 202 includes a plurality of first conductive lines 220, 222, 224, 226 and 228 within the top and bottom boundaries 212A, 212B. The first conductive lines 220, 222, 224, 226, and 228 in each of the first cells 202 are arranged substantially parallel to each other along the X-direction and aligned with respective horizontal wiring traces (eg, HT2~HT6 and HT12~ HT16). Each of the second cells 204 includes a plurality of second conductive lines 232, 234, and 236 within the top and bottom boundaries 214A, 214B. The second conductive lines 232, 234, and 236 in each of the second cells 204 are arranged substantially parallel to each other along the X-direction and aligned with the respective horizontal wiring traces (eg, HT8-HT10 and HT18-HT20).

In some embodiments, power rails 206a-206e and conductive lines 220-228 and 232-236 are formed within a first metal layer (ie, M1 layer), which is close to the substrate in which cells 202 are formed and active components of 204, such as transistors or the like. During the routing phase, power rails 206a-e and conductive lines 220-228 and 232-236 are arranged with respect to respective horizontal routing traces HT1-HT21 by an APR tool.

Referring to FIGS. 1 and 2B, the method 100 proceeds to step 104, wherein a plurality of first cell pins 240 for each first cell 202 are placed along respective vertical wiring traces of the plurality of vertical wiring traces VT1-VT20. 2B is a layout diagram 200B of a layout diagram 200A after placing a plurality of first cell pins 240 for each first cell 202 along respective vertical routing traces of the plurality of vertical routing traces VT1 - VT20 , according to an embodiment.

Cell leads described herein refer to the conductive wires that carry input or output signals for the cell. In some embodiments and in Figure 2B, the plurality of first cell pins 240 within each first cell 202 include at least one input pin or at least one output pin, the at least one input pin being adapted to An input signal is received into the unit, and the at least one output pin is adapted to pass an output signal from the unit. Adjust each first cell 202 according to actual circuit requirements The number of input pins and output pins within. For example, the leftmost first cell 202 in column 1 includes three first cell pins 240(1)-240(3), wherein the first cell pins 240(1) and 240(2) are used as input pins and use the first cell pin 240(3) as an output pin; while the leftmost first cell 202 in column 3 includes two first cell pins 240(4) to 240(5), where the first cell Pin 240(4) is used as an input pin and first cell pin 240(5) is used as an output pin.

Each of the first cell pins 240 extends in the Y direction and is aligned with a corresponding vertical wiring trace of the plurality of vertical wiring traces VT1 to VT20. Each of the first unit pins 240 is rectangular and has a length in the Y direction and a width in the X direction. The length of the first cell lead 240 is equal to or greater than the minimum length, which is specified by the first design rule of the specific manufacturing process, and thus meets the design rule line length requirements. As used herein, the minimum length of a fabrication process is the minimum length at which conductive lines can be fabricated while still satisfying corresponding design rules to avoid erroneous circuit function. In some embodiments, the second design rule imposes a minimum boundary offset between the end of the first cell pin 240 and the top and bottom boundaries 212A, 212B of the first cell 202 . Accordingly, the first cell pins 240 are located at the top and bottom boundaries 212A, 212B such that no first cell pins 240 terminate at the top or bottom edge 212A or 212B of the first cell 202 to satisfy the minimum boundary excursion criterion. In some embodiments, the first cell pins 240 extend across the entire set of first conductive lines 220 - 228 enclosed in the first cell 202 .

Each first unit pin 240 is assigned a color, and this color is the same as the color of the corresponding vertical wiring traces VT1 to VT20. Feet 240 extend along this vertical routing trace. In some embodiments, the first set of first cell pins 240 extending along odd vertical routing traces VT1, VT3, . , VT4, . The two masks form a second set of first unit pins 240, and the second mask is different from the first mask.

In some embodiments, the first cell lead 240 is located within the second metal layer (ie, the M2 layer) overlying the M1 layer. The first unit pins 240 are electrically coupled to the corresponding first conductive lines 220 ˜ 228 through a plurality of first through holes 242 arranged below the first unit pins 240 . Each of the first through holes 242 is at an intersection between the first unit pin 240 and the corresponding first conductive lines 220 to 228 .

Referring to FIGS. 1 and 2C , the method 100 proceeds to step 106 where a plurality of via layout points 250 are identified for each of the second cells 204 . Figure 2C is a layout 200C of the layout 200B after identifying a plurality of via layout points 250 for each of the second cells 204, according to an embodiment.

Via layout points 250 correspond to possible locations for placing vias 262 (FIG. 2E), electrically connecting second conductive lines 232-236 in the M1 layer to second cell pins 260 (FIG. 2D) to form In the overlying M2 layer, the signal transmission of the components is enabled. The via layout points 250 are located on the corresponding vertical wirings in the second conductive lines 232-236 and the vertical wiring traces VT1-VH20 the intersection of the trajectories. For example, for the leftmost second cell 204 in column 2, two exemplary via layout points 250(1) and 250(2) are identified for use over the second conductive line 232 placed on the horizontal routing trace HT8 Possible locations for via placement, two exemplary via placement points 250(3) and 250(4) are identified as possible locations for placement of vias over second conductive line 234 placed on horizontal routing trace HT9 , and two exemplary via placement points 250(5) and 250(6) are identified as possible locations for placing vias over the second conductive line 236 placed on the horizontal routing trace HT9.

Referring to FIGS. 1 and 2D , the method 100 proceeds to step 108 where a plurality of second cell leads 260 for each second cell 204 are placed over the plurality of selected via layout points 250 . 2D is a layout 200D of a layout 200C after placing a plurality of second cell pins 260 over a plurality of selected via layout points 250 for each second cell 204, according to an embodiment.

In some embodiments, the third design rule imposes a minimum end-to-end spacing requirement specifying that facing ends of adjacent cell pins on the same vertical routing trace must be separated by a minimum distance. The minimum end-to-end separation is a process technology node-specific parameter. In step 108, the via placement point 250 identified in step 106 is checked to determine if there is sufficient space available for placing the second cell pin 260 over the via placement point 250 such that the second cell pin 260 The adjacent first cell pins 240 are separated from the adjacent first cell pins 240 by a minimum end-to-end interval, and the adjacent first cell pins 240 are located on the same vertical wiring traces VT1 to VT20 as the second cell pins 260 . After inspection, a subset of via layout points 250 suitable for placement of second cell pins 260 for second cell 204 is selected. Exemplary second cell pins 260(1)-260(3) and example via layout points 250(1)-250(6) identified for column 2 leftmost second cell 204 are illustrated and described below for The via placement point 250 is chosen to place the second cell pin 260 to meet the criteria of minimum end-to-end spacing requirements. The second cell pin 260(1) may be placed over via placement point 250(3) or over via placement point 250(6) along vertical routing trace VT2 without causing minimum end-to-end spacing violations. This is because in a row, that is, in row 1 and row 3 immediately adjacent to row 2, only the leftmost first cell 202 in row 3 includes the first cell pin 240(4) along the same vertical wiring trace VT2, while row 1 A part of the vertical wiring trace VT2 in the middle is not occupied. Thus, the second cell pin 260(1) may extend across the top boundary 214A of the second cell 204 and onto the unoccupied portion of the vertical routing trace VT2 in the leftmost first cell 202 of column 1 to ensure the first One end of the second unit lead 260(1) is spaced from the adjacent end of the first unit lead 240(4) by a distance equal to or greater than the minimum end-to-end separation. Similarly, along vertical routing trace VT5, second cell pin 260(2) can be placed over via placement point 250(2) without causing minimum end-to-end spacing violations. This series is because the leftmost first cell 202 in both column 1 and column 3 does not include the first cell pin 240 along the same vertical routing trace VT5 to trigger a minimum end-to-end spacing conflict in order to prevent the second cell pin 260 (2 ) is placed over via placement point 250(2). In some embodiments, the second cell lead 260( 2 ) may be formed to have both ends terminating at opposing top and bottom boundaries 214A and 214B of the leftmost second cell 204 in row 2 . In other embodiments, the second cell lead 260(2) may be formed to have one end terminating within the leftmost second cell 204 in column 2 and to extend across the corresponding boundary 214A or 214B and extends to opposite ends on a portion of vertical wiring trace VT5 in column 1 or on a portion of vertical wiring trace VT5 in column 3, since neither portion of vertical wiring trace VT5 in column 1 and column 3 is occupied. Conversely, placement of cell pin 260' above via placement point 250(1) along vertical routing trace VT4 is prohibited by the minimum end-to-end spacing requirement, as indicated by the cross symbol, because the leftmost row in columns 1 and 3 Each of a cell 202 includes a first cell pin 240(2) or 240(5) along the same vertical routing trace VT4, and there is not enough space available to accommodate the cell pin therebetween without causing a minimum end-to-end End interval conflict. Placing cell pin 260' between the two first cell pins 240(2) and 240(5) in column 1 and column 3 along the same vertical routing trace VT4 will trigger a minimum end-to-end spacing violation because column 1 The distance D1 between the cell pin 260' and the facing end of the first cell pin 240(2) in column 3 or the facing end of the cell pin 260' in column 3 and the first cell pin 240(5) The distance D2 between them is less than the minimum end-to-end separation. Placing cell lead 260' above via layout point 250(1) along vertical routing trace VT4 increases the risk of faulty circuits resulting from fabrication of ICs from layout 200F (FIG. 2F).

Next, the second cell pins 260 for inputting and outputting signals to the second cell 204 are placed over the selected via layout point 250 so as to extend along the corresponding vertical wiring traces VT1 - VT21 where the selected via layout point 250 is located. Therefore, in some embodiments, the second cell pin 260 for the second cell 204 may be formed to have one end terminating within the respective top or bottom boundary 214A or 214B and extending across the respective top or bottom boundary 214A or 214B, in accordance with minimum end-to-end spacing requirements. The top or bottom boundary 214A or 214B to the opposite end in the adjacent first cell 202 on the same vertical routing trace VT1 The first cell pin 240 is not included on ~VT20. In this case, the second cell lead 260 may be formed of any length, such that in some embodiments the second cell lead 260 has a length equal to or greater than the minimum wire length. In this case, the second unit lead 260 has a length less than the minimum wire length. In the case where the adjacent vertical traces VT1 to VT20 are assigned different colors, the second unit pins 260 on the adjacent vertical wiring traces VT1 to VT20 are also assigned different colors, either color A or color B, which indicates that the adjacent second unit pins 260 are also assigned different colors. Cell pins 260 are fabricated from different masks.

Referring to FIGS. 1 and 2E, the method 100 proceeds to step 110, wherein a plurality of second vias 262 are placed to couple the plurality of second unit pins 260 to the plurality of second conductive lines 232-236. 2E is the layout 200D after placing the second vias 262 to couple the second cell pins 260 to the second conductive lines 232 - 236 according to an embodiment.

The second unit pins 260 are electrically coupled to the corresponding lower-layer second conductive lines 232 ˜ 236 through the second through holes 262 . The second vias 262 are placed at the locations of their via layout points 250 selected in step 108 .

Referring to FIGS. 1 and 2F, the method 100 proceeds to step 112, wherein at least one second cell lead 260 and/or at least one first cell lead 240 are elongated. FIG. 2F is a layout diagram 200F of the layout diagram 200F after the first cell lead 240 and the second cell lead 260 are elongated according to an embodiment.

In step 112, at least one second cell pin 260 in the second cell pins 260 is elongated in the Y direction, so that all the second cell pins 260 has a length equal to or greater than the minimum wire length. The elongation of the second cell pins 260 helps improve pin accessibility, thereby helping to provide better routing efficiency and routing density for the second cell 204 . Also, in some embodiments, at least one of the first cell pins 240 is elongated in the Y direction so as to span a corresponding boundary of the first cell 202 where the at least one first cell pin 240 is located 212A or 212B. The elongation of the first cell lead 240 helps improve lead accessibility, thereby helping to provide better routing efficiency and routing density for the first cell 202 . Each of the first cell pin 240 and the second cell pin 260 may be elongated to any length as long as the adjacent first cell pins on the same vertical routing traces VT1~VT30 after pin elongation The minimum end-to-end spacing requirement is met between the facing ends of 240 and the second unit pins 260 .

FIG. 3 is a flowchart of a method 300 of generating a floor plan 200F according to one embodiment. In various embodiments, the steps of method 300 are performed in the order depicted in FIG. 3 or in one or more orders other than the order depicted in FIG. 3 . In some embodiments, one or more additional operations are performed before, between, during, and/or after performing one or more steps of method 300 . The method 300 is described below in conjunction with FIGS. 4A-4C, which illustrate the various stages of generating the floor plan 200F. Unless otherwise stated, components in Figures 4A-4C are identified by the same reference numerals as shown in Figures 2A-2F, and components in Figures 4A-4C are the same as those in Figures 2A-4C. The same parts in the 2F diagram are basically the same.

Similar to method 100, some or all of the operations of method 300 can be performed as part of an APR tool. In some embodiments, Some or all of method 300 is performed by a processor of a computer. In some embodiments, some or all of the method 300 is performed by the processor 502 of the EDA system 500 discussed below with respect to FIG. 5 . In some embodiments, some or all of the operations of method 300 can be performed as part of a design program executed in a design studio, eg, design studio 620 discussed below with respect to FIG. 6 .

Referring to FIG. 3, method 300 includes operation 302, wherein a plurality of first conductive lines 220-228 for a plurality of first cells 202 of a first cell height are placed along corresponding horizontal wiring traces HT1-HT21 of a wiring grid and for The plurality of conductive lines 232-236 of the plurality of second cells 204 of the second cell height CH2, the second cell height CH2 is smaller than the first cell height CH1; the first cells 202 and the second cells 204 are arranged in a plurality of columns. Step 302 is substantially the same as step 102, and after step 302, the layout diagram 200A is generated.

Referring to FIGS. 3 and 4A , method 300 proceeds to operation 304 where a plurality of first via layout points 270 are identified for each of first cells 202 and for each of second cells 204 A plurality of second via layout points 250 . 4A is a layout diagram 200A identifying a plurality of first via layout points 270 for each of the first cells 202 and a plurality of second vias for each of the second cells 204, according to an embodiment Layout 400A after hole layout point 250.

The first via layout point 270 corresponds to a possible position for placing the first via 242 (FIG. 4C), and the first via 242 is used to electrically connect the first conductive lines 220-228 in the M1 layer to the first via Unit pin 240 (section 4B Fig. ) is formed in the overlying M2 layer, thereby enabling the signal transmission of the first unit 202. The first via layout point 270 is located at the intersection of the first conductive lines 220 ˜ 228 and corresponding vertical wiring traces of the vertical wiring traces VT1 ˜ VT20 .

Likewise, the second via layout point 250 corresponds to a possible location (FIG. 4C) for placing the second via 262 for electrically connecting the second conductive lines 232-236 in the M1 layer to the The second cell leads 260 (FIG. 4B) are formed in the overlying M2 layer to enable signal transmission of the second cell 204. The second via layout point 250 is located at the intersection of the second conductive lines 232 ˜ 236 and corresponding ones of the vertical wiring traces VT1 ˜ VT20 .

Referring to FIGS. 3 and 4B, the method 300 proceeds to step 306, wherein a plurality of first cell pins 240 are placed over the selected first via layout point 270 along the corresponding vertical routing traces VT1-VT20 and routed along the corresponding vertical The traces VT1 to VT20 place a plurality of second cell pins 260 above the selected second via layout point 250 . FIG. 4B is a layout diagram 400A where a plurality of first cell pins 240 are placed over selected first via layout points 270 along corresponding vertical wiring traces VT1 - VT20 and a plurality of first cell pins 240 are placed on selected second vias along corresponding vertical wiring traces VT1 - VT20 The layout diagram 400B after placing a plurality of second cell pins 260 above the layout points 250 .

An algorithm is performed iteratively over all via placement points 270 and 250 to evaluate the free space available around the first via placement point 270 and the second via placement point 250 . Based on the available free space, some of the first via layout points 270 and the second via layout points 250 are selected such that the first cell pin 240 and the second cell pin 270 are placed at the corresponding selected via layout points 270 and 250 250 does not cause any conflict of minimum end-to-end spacing requirements because the first cell pin 240 and second cell pin 260 for adjacent first cell 202 and second cell 204 are placed on the same vertical routing trace VT1~ on VT20.

Those first via layout points 270 suitable for placing the first cell pin 240 and those suitable for placing the second cell pin 260 are selected based on different design constraints applied to the first cell pin 240 and the second cell pin 260 250 of those second via layout points. For example, since the first cell 202 has a relatively large cell height CH1 that allows the first cell 202 to accommodate cell pins having a length equal to or greater than the minimum length, the first cell pins 240 can be formed to meet both minimum length requirements and minimum boundary offset requirements. Accordingly, each first cell lead 240 is formed to have both ends terminated within the top and bottom boundaries 212A and 212B of the first cell 202 . Conversely, since the second cell 204 has a relatively small cell height CH2 that only allows the second cell 204 to accommodate cell leads having a length less than the minimum length, the second cell leads 260 cannot be formed to conform to Minimum length requirements and minimum boundary offset requirements. Therefore, each second cell pin 260 is used to have both ends terminated in the second cell 204 when there is no first cell pin 240 on the same vertical wiring traces VT1 to VT20 in adjacent columns Column 1 and 3 at the top and bottom boundaries 214A and 214B, or to have termination within the top and bottom boundaries 214A and 214B when there is only one first cell pin 240 on the same vertical routing trace VT1-VT20 in column 1 or column 3 one end and extends across the corresponding top or bottom boundary 214A or 214B of the second cell 204 to the other end of the adjacent column column 1 or column 3 . By imposing different design constraints on the first cell pin 240 and the second cell The pin 260 can place the first unit pin 240 and the second unit pin 260 so that the two adjacent first unit pins 240 and the second unit pins 260 on the same vertical wiring traces VT1 to VT20 face each other end to meet the minimum end-to-end spacing requirement.

Next, the first cell pins 240 for inputting and outputting signals to the first cell 202 are placed above the selected first via layout point 270 to be along the corresponding vertical wiring traces VT1~ where the selected first via layout point 270 is located. VT21 extension. Also, the second cell pins 260 for inputting and outputting signals to the second cell 204 are placed above the selected second via layout point 250 to be along the corresponding vertical wiring traces VT1~ where the selected second via layout point 250 is located VT21 extension.

Referring to FIGS. 3 and 4C, the method 300 proceeds to step 308, wherein a plurality of first vias 242 are placed to couple the plurality of first cell leads 240 to the plurality of first conductive lines 220-228 and The plurality of second vias 262 are placed to couple the plurality of second cell leads 260 to the plurality of second conductive lines 232-236. FIG. 4C is a layout diagram 400B of placing a plurality of first vias 242 to couple a plurality of first cell pins 240 to a plurality of first conductive lines and placing a plurality of second vias 262 to The layout diagram 400C after the plurality of second unit pins 260 are coupled to the plurality of second conductive lines 232 - 236 .

The first unit pins 240 are electrically coupled to the corresponding lower-layer first conductive lines 220 - 228 through the first through holes 242 . The first vias 242 are placed at the locations of their via layout points 270 selected in step 306 . Likewise, the second cell pins 260 are electrically coupled to the corresponding lower layer second vias 262 Conductive wires 232~236. The second vias 262 are placed at the locations of the via layout points 250 selected in step 308 .

Referring to FIGS. 3 and 2F, the method 300 proceeds to step 310, wherein at least one second cell lead 260 and/or at least one first cell lead 240 are elongated. Step 310 is substantially the same as step 112, and after step 310 the floorplan 200F is generated.

In one embodiment of the present case, by using different design constraints in the placement of cell pins for cells of different cell heights, routing for cells of different heights in a mixed cell design can be performed under the same design block without pushing Extrude existing design rules. As a result, a 10% increase in pin routing utilization is achieved.

FIG. 5 is a block diagram of an electronic design automation (EDA) system 500 according to one embodiment.

In some embodiments, EDA system 500 includes an APR tool. According to some embodiments, the methods described herein for designing a layout representing a wire routing arrangement according to one or more embodiments may be implemented, for example, using EDA system 500 .

In some embodiments, the EDA system 500 is a general-purpose computing device including a hardware processor 502 and a non-transitory computer-readable storage medium 504 . The storage medium 504 is encoded with the computer code 506, that is, the storage medium stores the computer code, wherein the computer code 506 is a set of computer-executable instructions. Execution of computer code 506 by processor 502 represents (at least in part) an APR tool implemented, for example, according to one or more some or all of the methods described herein (hereinafter the processes and/or methods).

The processor 502 is electrically coupled to the computer-readable storage medium 504 via the bus bar 508 . Processor 502 is also electrically coupled to I/O interface 510 by bus 508 . The network interface 512 is also electrically connected to the processor 502 via the bus bar 508 . Connecting the network interface 512 to the network 514 enables the processor 502 and the computer-readable storage medium 504 to connect to external components via the network 514 . Processor 502 is used to execute computer code 506 encoded in computer-readable storage medium 504 to cause EDA system 500 to be operable to perform some or all of the processes and/or methods. In one or more embodiments, the processor 502 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and/or Appropriate processing unit.

In one or more embodiments, computer-readable storage medium 504 is an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or device or device). For example, the computer-readable storage medium 504 includes semiconductor or solid-state memory, magnetic tape, removable computer disc, random access memory (RAM), read-only memory (ROM), Rigid disks and/or CDs. In one or more embodiments using optical discs, the computer-readable storage medium 504 includes compact disc-read only memory (CD-ROM), compact disc-read/write ( compact disk-read/write, CD-R/W) and/or digital video disc (DVD).

In one or more embodiments, the storage medium 504 stores computer code 506 for causing the EDA system 500 (wherein such execution (at least in part) to represent an APR tool) may be used to execute the process and/or or some or all of the methods. In one or more embodiments, storage medium 504 also stores information that facilitates performing some or all of the processes and/or methods. In one or more embodiments, storage medium 504 stores standard cell library 507, including such standard cells corresponding to the cells disclosed herein.

EDA system 500 includes I/O interface 510 . The I/O interface 510 is coupled to external circuitry. In one or more embodiments, I/O interface 510 includes a keyboard, keypad, mouse, trackball, trackpad, screen, and/or cursor direction keys for communicating information and commands to processor 502 .

The EDA system 500 also includes a network interface 512 coupled to the processor 502 . Network interface 512 allows EDA system 500 to communicate with network 514 to which one or more other computer systems are connected. The network interface 512 includes a wireless network interface such as Bluetooth, WIFI, WIMAX, GPRS or WCDMA; or a wired network interface such as Ethernet, USB or IEEE-1364. In one or more embodiments, some or all of the processes and/or methods are implemented in two or more systems 500 .

The EDA system 500 is used to receive information via the I/O interface 510 . Information received via I/O interface 510 includes one or more of the following: instructions, data, design rules, standard cell libraries, and/or by processor 502 Additional parameters for processing. Information is transmitted to processor 502 via bus 508 . The EDA system 500 is used for receiving UI-related information through the I/O interface 510 . The information is stored in the computer readable medium 504 as a user interface (UI) 542 .

In some embodiments, some or all of the processes and/or methods are implemented as stand-alone software applications executed by a processor. In some embodiments, some or all of the processes and/or methods are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the processes and/or methods are implemented as plug-ins in a software application. In some embodiments, at least one of the processes and/or methods is implemented as a software application that is part of an APR tool. In some embodiments, some or all of the processes and/or methods are implemented as software applications used by the EDA system 500 . In some embodiments, a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc. or another suitable layout generation tool is used to generate a layout diagram including standard cells.

In some embodiments, these processes are implemented as functions of programs stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external/removable and/or internal/internal storage or memory units, such as one or more of the following: optical discs, such as DVDs; magnetic Disks, such as hard disks; semiconductor memories, such as ROM, RAM, memory cards, and the like.

FIG. 6 is a block diagram of an IC manufacturing system 600 and an IC manufacturing flow associated therewith, according to an embodiment.

In some embodiments, based on the layout, IC fabrication system 600 is used to fabricate at least one of: (A) one or more semiconductor masks or (B) at least one component of a layer of a semiconductor integrated circuit.

In FIG. 6, IC manufacturing system 600 includes entities such as design room 620, mask room 630, and IC manufacturers/fabs that interact with each other in the design, development, and manufacturing cycle and/or services related to manufacturing IC devices 660 ("fab") 650. Entities in system 600 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. Communication networks include wired and/or wireless communication channels. Each entity interacts with and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design room 620, mask room 630, and IC fab 650 are owned by a single larger company. In some embodiments, two or more of design room 620, mask room 630, and IC fab 650 coexist in a common facility and use common resources.

A design house (or design team) 620 generates an IC design layout 622 . IC design layout 622 includes various geometric patterns designed for IC device 660 . The geometric pattern corresponds to the pattern of metal, oxide, or semiconductor layers that make up the various components of the IC device 660 to be fabricated. The individual layers combine to form individual IC features. For example, a portion of the IC design layout 622 includes various IC features to be formed in a semiconductor substrate, such as a silicon wafer, such as active regions, gate electrodes, source and drain electrodes, conductive lines or vias for interlayer interconnects, and Openings for bond pads, and individual materials placed on semiconductor substrates material layer. Design office 620 implements appropriate design procedures to form IC design layout 622 . Design programs include one or more of logical design, physical design, or place and route. The IC design layout 622 is presented in one or more data files with geometric pattern information. For example, the IC design layout 622 may be represented in the GDSII file format or the DFII file format.

Mask chamber 630 includes data preparation 632 and mask fabrication 644 . Mask chamber 630 uses IC design floorplan 622 to fabricate one or more masks 645 for fabricating various layers of IC device 660 according to IC design floorplan 622 . Mask room 630 performs mask data preparation 632, in which IC design layout 622 is converted into a representative data file (RDF). Mask data preparation 632 provides RDF to mask fabrication 644 . Mask fabrication 644 includes a mask writer. The mask writer converts the RDF to an image on a substrate, such as a mask (master mask) 645 or semiconductor wafer 653 . The design layout 622 is manipulated by the mask data preparation 632 to meet the specific characteristics of the mask writer and/or the needs of the IC fab 650. In Figure 6, mask data preparation 632 and mask fabrication 644 are shown as separate elements. In some embodiments, mask data preparation 632 and mask fabrication 644 may be collectively referred to as mask data preparation.

In some embodiments, mask data preparation 632 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as may be caused by diffraction, interference, other process effects, and the like image error. OPC Adjustment IC Design Layout 862. In some embodiments, mask data preparation 632 includes further resolution enhancement techniques techniques, RET), such as off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, and the like or combinations of the above. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

In some embodiments, the mask data preparation 632 includes a mask rule checker (MRC) that utilizes a set of mask generation rules to check the IC design layout 622 going through the process in OPC. Mask generation rules include certain geometric and/or connection constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes and the like. In some embodiments, the MRC refines the IC design layout 622 to compensate for constraints during mask fabrication 644, which may disable a portion of the refinement performed by OPC in order to meet mask generation rules.

In some embodiments, mask data preparation 632 includes lithography process checking (LPC), which simulates the process to be performed by IC fab 650 to manufacture IC device 660 . The LPC simulates this process based on the IC design floorplan 622 to produce a simulated fabrication element, such as the IC device 660 . Process parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and/or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like or combinations thereof. In some embodiments, after the LPC has produced the simulated fabrication elements, if the simulated If the components are not close enough in shape to meet the design rules, the OPC and/or MRC are repeated to further refine the IC design layout 622 .

It should be understood that the above description of mask data preparation 632 has been simplified for clarity. In some embodiments, data preparation 632 includes additional features, such as logic operations (LOPs), to refine IC design layout 622 according to manufacturing rules. Additionally, the processes applied to IC design floorplan 622 during data preparation 632 may be performed in various different orders.

After mask data preparation 632 and during mask fabrication 644, a mask 645 or set of masks 645 is fabricated based on the modified IC design layout 622. In some embodiments, mask fabrication 644 includes performing one or more lithographic exposures based on IC design layout 622 . In some embodiments, an electron beam (electron beam) or mechanisms of multiple electron beams are used to form a pattern on the mask (reticle or master) 645 based on the modified IC design layout 622 . Mask 645 may be formed by various techniques. In some embodiments, the mask 645 is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. A beam of radiation, such as an ultraviolet (UV) beam, used to expose a layer of image-sensitive material (eg, photoresist) that has been coated on the wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, the binary mask version of mask 645 includes a transparent substrate (eg, fused silica) and an opaque material (eg, chrome) coated in the opaque regions of the binary mask. In another example, the mask 645 is formed using phase shifting techniques. In the phase shift mask (PSM) version of the mask 645, each feature in the pattern formed on the phase shift mask is used to have a suitable phase difference to enhance resolution and imaging quality. In various instances, the phase shift mask may is decaying PSM or alternating PSM. The masks produced by the mask fabrication 644 are used in various processes. For example, such masks are used in an ion implant process to form various doped regions in semiconductor wafer 653, in an etch process to form various etch regions in semiconductor wafer 653, and/or in other suitable processes used in.

IC fab 650 includes wafer fabrication 652 . IC fab 650 is an IC manufacturing operation that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC fab 650 is a semiconductor factory. For example, there may be a fabrication facility for the front-end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second fabrication facility may provide interconnection and packaging for IC products. Back-end manufacturing (back-end-of-line (BEOL) manufacturing), as well as tertiary manufacturing facilities, may provide other services for factory operations.

IC fab 650 uses mask 645 fabricated by mask chamber 630 to manufacture IC device 660 . Thus, IC fab 650 uses IC design floorplan 622 at least indirectly to manufacture IC device 660 . In some embodiments, semiconductor wafer 653 is fabricated by IC foundry 650 using mask 645 to form IC device 660 . In some embodiments, IC fabrication includes performing one or more lithographic exposures based at least indirectly on the IC design floorplan 622 . Semiconductor wafer 653 includes a silicon substrate or other suitable substrate on which material layers are formed. Semiconductor wafer 653 further includes one or more of various doped regions (formed in subsequent fabrication steps), dielectric features, multi-level interconnects, and the like.

Details regarding an integrated circuit (IC) manufacturing system (eg, system 600 of FIG. 6 ) and the IC manufacturing process associated therewith can be found, for example, at US Patent No. 9,256,709 issued on February 9, 2016, US Pre-Grant Publication No. 20150278429 published on October 1, 2015, US Pre-Grant Publication No. 20140040838 and 2007 published on February 6, 2014 7,260,442, issued August 21, 2008, each of which is incorporated herein by reference in its entirety.

According to an embodiment of the present application, it is directed to a method of generating a layout of an integrated circuit, the method comprising arranging a plurality of first cells having a first cell height in a first column; arranging in a second column adjacent to the first column A plurality of second cells of a second cell height, the second cell height being less than the first cell height, and the first and second columns extending along a first direction and arranged relative to a wiring grid, the wiring grid including along the first direction A plurality of first wiring traces extending and a plurality of second wiring traces extending along a second direction, the second direction being perpendicular to the first direction; placing a plurality of first cells in each of the plurality of first cells pins, each of the plurality of first cell pins extending along respective second routing traces of the plurality of second routing traces; and the plurality of selected pass-throughs in each second cell of the plurality of second cells A plurality of second cell pins are placed over the hole layout points, at least one second cell pin of the plurality of second cell pins extending across the plurality of second cells along respective second routing traces of the plurality of second routing traces The boundaries of the respective second cells of and extend into respective first cells of the plurality of first cells adjacent to the respective second cells. In some embodiments, the method further includes identifying a plurality of via placement points in each second cell of the plurality of second cells at respective intersections between the plurality of first routing traces and the plurality of second routing traces. The plurality of via placement points are possible locations for placing the plurality of second cell pins. In some embodiments, The method further includes identifying the plurality of selected via placement points from the plurality of via placement points for each second cell of the plurality of second cells such that the plurality of second cell pins are placed over the plurality of selected via placement points Thereafter, facing ends of adjacent first and second cell pins on the same routing trace are separated by a distance equal to or greater than a minimum end-to-end separation according to a set of design rules. In some embodiments, each of the plurality of first cell pins is placed such that opposite ends of each of the plurality of first cell pins terminate on top of a corresponding first cell of the plurality of first cells and within the bottom boundary. In some embodiments, at least one second cell pin of the plurality of second cell pins is positioned such that one end of the at least one second cell pin of the plurality of second cell pins terminates in the plurality of second cell pins within the top and bottom boundaries of the respective second cells, and the opposite ends of at least one second cell pin of the plurality of second cell pins terminate within a corresponding first cell of the plurality of first cells, the plurality of first cells A corresponding first cell of a cell is adjacent to a corresponding second cell of a plurality of second cells. In some embodiments, at least another second cell pin of the plurality of second cell pins is positioned such that opposite ends of the at least another second cell pin of the plurality of second cell pins terminate in the plurality of second cell pins At the top and bottom boundaries of the respective second cells of the second cells. In some embodiments, the method further includes elongating at least one first cell lead of the plurality of first cell pins to span the at least one first cell pin along respective second routing traces of the plurality of second routing traces The boundary of the corresponding first cell where it is located. In some embodiments, the method further includes elongating at least one second cell lead of the plurality of second cell pins along respective second routing traces of the plurality of second routing traces. At least one of the plurality of second unit pins is elongated The distance between the second cell pin and the facing end of the adjacent first cell pin on the same second routing trace as the at least one elongated second cell pin is equal to or greater than the minimum end according to a set of design rules end-to-end interval. In some embodiments, the method further includes placing the plurality of first conductive lines along the first set of the first wiring traces of the plurality of first wiring traces for the plurality of first cells, and along the plurality of the first wiring traces for the plurality of second cells A second set of first routing traces of a routing trace places a plurality of second conductive lines. In some embodiments, the method further includes placing the plurality of first vias to couple the plurality of first conductive lines with the plurality of first cell pins. In some embodiments, the method further includes placing a plurality of second vias to couple the plurality of second conductive lines with the plurality of second cell pins.

Another embodiment according to the present application relates to a method of generating an integrated circuit layout diagram, comprising arranging a plurality of first cells having a first cell height in a plurality of first columns; arranging a plurality of second columns having a first cell height; A plurality of second units with a height of two units, the height of the second unit is smaller than the height of the first unit. A plurality of first columns and a plurality of second columns are arranged according to a wiring grid, the wiring grid includes a plurality of first wiring traces extending in the first direction and a plurality of second wiring traces extending in the second direction, the first The two directions are perpendicular to the first direction; a plurality of first unit pins are placed over a plurality of selected first through hole layout points in each of the plurality of first units, and each of the plurality of first unit pins the first cell pins extend along respective second routing traces of the plurality of second routing traces and have both ends terminated within the top and bottom boundaries of the respective first cells of the plurality of first cells; and, in the plurality of the first cells Place a complex over a plurality of selected via placement points in each second cell of the two-cell a plurality of second cell pins, at least one second cell pin of the plurality of second cell pins extending across a corresponding second cell of the plurality of second cells along a corresponding second wiring trace of the plurality of second wiring traces and extend into respective first cells of the plurality of first cells adjacent to the respective second cells. In some embodiments, the method further includes identifying a plurality of first via placement points within each first cell of the plurality of first cells and a plurality of second via placement points within each second cell of the plurality of second cells A hole placement point, each of the plurality of first via placement points and the plurality of second via placement points is at a corresponding first wiring trace of the plurality of first wiring traces and a corresponding second one of the plurality of second wiring traces At the intersection of the routing traces. In some embodiments, the method further includes identifying a plurality of selected first via layout points from the plurality of first via layout points and identifying a plurality of selected second via layout points from the plurality of second via layout points, such that Phases placed along the same second routing trace after placing the plurality of first cell pins on the plurality of selected first via placement points and placing the plurality of second cell pins on the plurality of selected second via placement points The facing ends of the adjacent first and second cell leads are separated by a distance equal to or greater than a minimum end-to-end separation according to a set of design rules. In some embodiments, placing the plurality of first cell pins includes placing the plurality of first cell pins having a length equal to or greater than a minimum length according to a set of design rules. In some embodiments, placing the plurality of second cell pins includes placing the plurality of second cell pins having a length that is less than a minimum length according to a set of design rules. In some embodiments, the method further includes fabricating the integrated circuit based on the layout.

Another embodiment in accordance with the present case relates to a system for processing an integrated circuit layout diagram. The system includes at least one processor and a computer-readable storage medium coupled to the at least one processor. At least one processor is used to execute the instructions stored on the computer-readable storage medium to arrange a plurality of first cells having a first cell height in a plurality of first columns; at least one processor is used to execute the instructions stored in the computer-readable storage medium. Fetching an instruction on the storage medium to further arrange a plurality of second cells having a second cell height in a plurality of second columns, the second cell height being smaller than the first cell height, arranging the plurality of first columns and a plurality of second columns, the wiring grid comprising a plurality of first wiring traces extending in a first direction and a plurality of second wiring traces extending in a second direction, the second direction being perpendicular to the first direction; at least one processing a device for executing instructions stored on a computer-readable storage medium to place a plurality of first cell pins, each of the plurality of first cell pins, within each first cell of the plurality of first cells extending along respective second wiring traces of the plurality of second wiring traces; at least one processor for executing instructions stored on the computer-readable storage medium between the plurality of first wiring traces and the plurality of second wiring traces A plurality of through-hole layout points in each of the plurality of second units are further identified at corresponding intersection points of the plurality of second units; at least one processor is used for executing instructions stored on the computer-readable storage medium to automatically The plurality of via placement points further selects a subset of via placement points, wherein the subset of via placement points corresponds to a set of second routing traces of the plurality of second routing traces along which placement of the plurality of second routing traces A plurality of second unit pins of each second unit of the unit, if none or only one first unit of a pair of first units of the plurality of first units includes the first unit Meta pins, such first cells immediately adjacent to opposite boundaries of corresponding second cells of the plurality of second cells, may be on the same second routing trace as the adjacent first cell pins of the plurality of first cell pins A plurality of second cell pins are placed on the second cell pins; at least one processor is configured to execute instructions stored on a computer-readable storage medium to place the plurality of second cell pins over the subset of through-hole layout points. In some embodiments, each first cell pin of the plurality of first cell pins has an opposite end terminating within a boundary of a corresponding first cell of the plurality of first cells. In some embodiments, at least one second cell pin of the plurality of second cell pins has one end extending across the respective common boundary between the respective first cell and the second cell.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of an embodiment of the present application. Those skilled in the art will appreciate that one embodiment of the present disclosure may readily be used as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of an embodiment of the present invention, and that various types of structures may be implemented herein without departing from the spirit and scope of an embodiment of the present invention. Changes, Substitutions and Modifications.

100: Method of generating an integrated circuit layout diagram

102, 104, 106, 108, 110, 112: Steps

Claims (10)

A method of generating an integrated circuit layout, the method comprising the steps of: arranging a plurality of first cells having a first cell height in a first column; arranging in a second column adjacent to the first column a plurality of second cells of a second cell height, wherein the second cell height is smaller than the first cell height, and the first row and the second row extend along a first direction and are arranged relative to a wiring grid, The wiring grid includes a plurality of first wiring traces extending along the first direction and a plurality of second wiring traces extending along a second direction, the second direction being perpendicular to the first direction; in the first cells A plurality of first cell pins are placed within each first cell of the first cell, wherein each of the first cell pins extends along a corresponding second wiring trace of the second wiring traces; and A plurality of second cell pins are placed over the plurality of selected via layout points in each second cell of the two cells, wherein at least one of the second cell pins is routed along the second cell pins A respective second wiring trace of the trace extends across a boundary of a respective second cell of the second cells and into a respective first cell of the first cells adjacent to the respective second cell. The method of claim 1, further comprising: identifying a plurality of each of the plurality of second cells at respective plurality of intersections between the first wiring traces and the second wiring traces Pass hole layout points, wherein the through hole layout points are a plurality of possible locations for placing the second unit pins. The method of claim 1, further comprising: elongating at least one of the first cell pins to span the at least one along a corresponding second one of the second wiring traces A boundary of a corresponding first cell where the first cell pin is located. The method of claim 1, further comprising: elongating at least one of the second cell pins along a corresponding second wiring trace of the second wiring traces, wherein the second cell pins Between the at least one elongated second unit lead among the unit leads and the facing end of an adjacent first unit lead on the same second wiring trace as the at least one elongated second unit lead The distance is equal to or greater than a minimum end-to-end separation according to a set of design rules. The method of claim 1, further comprising: placing a plurality of first conductive lines for the first cells along a first set of first wiring traces of the first wiring traces, and for the second cells A plurality of second conductive lines are placed along a second set of first wiring traces of the first wiring traces. A method of generating a layout diagram of an integrated circuit, comprising: A plurality of first cells having a first cell height are arranged in a plurality of first columns; a plurality of second cells having a second cell height are arranged in a plurality of second columns, the second cell height being smaller than the first cell height A cell height in which the first columns and the second columns are arranged according to a routing grid that includes a plurality of first routing traces extending in a first direction and extending in a second direction a plurality of second wiring traces of the plurality of second wiring traces, the second direction being perpendicular to the first direction; placing a plurality of first cell leads over a plurality of selected first via layout points in each of the first cells pins, wherein each of the first cell pins extends along a corresponding second wiring trace of the second wiring traces and has a corresponding first cell both ends terminating in the first cells within the top and bottom boundaries of the cells; and placing a plurality of second cell pins over a plurality of selected second via layout points in each of the second cells, wherein the second cell pins At least one of the second cell pins extends across a boundary of a corresponding second cell of the second cells and extends to a border adjacent to the corresponding second cell along a corresponding second wiring trace of the second wiring traces. in a corresponding first unit of the first units. The method of claim 6, further comprising: identifying a plurality of first via layout points in each of the first cells and a plurality of first via layout points in each of the second cells The second via layout points, the first via layout points and the second via layout points Each is at an intersection of a respective first routing trace of the first routing traces and a respective second routing trace of the second routing traces. The method of claim 6, further comprising: identifying the selected first via layout points from a plurality of first via layout points and identifying the selected second via layout points from a plurality of second via layout points point so that after placing the first cell pins on the selected first via layout points and placing the second cell pins on the selected second via layout points, along a same second wiring The facing ends of adjacent first and second cell leads of the trace placement are separated by a distance equal to or greater than a minimum end-to-end separation according to a set of design rules. A system for processing an integrated circuit layout diagram, comprising: a non-transitory computer-readable storage medium for storing a plurality of instructions thereon; and a processor connected to the non-transitory computer-readable storage medium a processor, wherein the processor is configured to execute the instructions to: obtain a first unit from a database stored in the non-transitory computer-readable storage medium, wherein the first unit has a first height; from the The database obtains a second unit, wherein the second unit has a second height different from the first height; arranges the first unit in a first row extending in a first direction; adjoins the first row arranging the second cells in a second row, wherein the second row extends in the first direction; placing a plurality of first cell pins within the first cell, wherein each of the first cell pins extends in a second direction perpendicular to the first direction; and a plurality of first cell pins within the second cell A plurality of second cell leads are placed on selected via layout points, wherein the second cells extend in the second direction, and at least one second cell lead of the second cell leads extends beyond the second cell lead A boundary of the unit extends into the first unit. The system of claim 9, wherein the processor is further configured to execute the instructions to: extend at least one of the second unit pins, wherein the extended at least one of the second unit pins extend beyond this boundary.

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