TWI773986B - Nonvolatile memory device and related driving method - Google Patents

Abstract

A driving method of a nonvolatile memory device including multiple memory planes includes following operations: precharging at least one word line and at least one bit line of a first plane; if the at least one word line and the at least one bit line of the first plane have been precharged for a first time length or to respective voltage thresholds, precharging at least one word line and at least one bit line of a second plane; conducting a first data operation to at least one memory cell disposed at an intersection of the at least one word line and the at least one bit line of the first plane; conducting a second data operation to at least one memory cell disposed at an intersection of the at least one word line and the at least one bit line of the second plane.

Description

Non-volatile memory device and related driving method

The present disclosure relates to a driving method of a non-volatile memory device, and more particularly, to a driving method of a non-volatile memory device capable of reducing inrush current.

NAND flash memory is widely used in solid-state hard disks, mobile devices and handheld game consoles. It has the advantages of shock resistance and high transmission speed. The physical structure of NAND flash memory can be classified into memory chip, memory plane, block and physical page hierarchically according to the storage capacity. Current technology accesses multiple memory planes synchronously to speed up data transfer, but this creates large inrush currents in the memory chips, which may damage the associated power modules.

The present disclosure provides a driving method of a non-volatile memory device, the non-volatile memory device includes a plurality of memory planes, and the driving method includes the following process: performing at least a first memory plane of the plurality of memory planes One word line and at least one bit line are precharged; if at least one word line and at least one bit line of the first memory plane have been precharged for a first time length or reach their corresponding voltage thresholds, then Precharging at least one word line and at least one bit line of a second memory plane among the plurality of memory planes; performing a first data operation on at least one memory cell of the first memory plane, wherein the first memory plane at least one memory cell of the first memory plane is arranged at the intersection of at least one word line and at least one bit line of the first memory plane; the second data operation is performed on at least one memory cell of the second memory plane, wherein the second memory At least one memory cell of the plane is disposed at the intersection of at least one word line and at least one bit line of the second memory plane.

The present disclosure provides a driving method of a non-volatile memory device, the non-volatile memory device includes a plurality of memory planes, and the driving method includes the following process: performing at least a first memory plane of the plurality of memory planes One word line and at least one bit line are precharged; if at least one word line and at least one bit line of the first memory plane have been precharged for a second time length shorter than the first time length, then precharging at least one word line and at least one bit line of a second memory plane of the plurality of memory planes, and continuing to precharge at least one word line and at least one bit line of the first memory plane; When the first memory plane has been precharged for a first time length, the first data operation is performed on at least one memory cell of the first memory plane, wherein at least one memory cell of the first memory plane is disposed in the first memory plane the intersection of at least one word line and at least one bit line of the body plane; when at least one memory cell of the second memory plane has been precharged for a first time length, the second memory plane is subjected to the second data operation, wherein at least one memory cell of the second memory plane is disposed at the intersection of at least one word line and at least one bit line of the second memory plane.

The present disclosure provides a non-volatile memory device including a memory chip and a control circuit. A memory chip contains multiple memory planes. The control circuit is coupled to the memory chip and configured to perform the following operations: precharge at least one word line and at least one bit line of the first memory plane among the plurality of memory planes; At least one word line and at least one bit line of the body plane are precharged for a first time length or reach a corresponding voltage threshold, then at least one word line of the second memory plane of the plurality of memory planes is charged Precharging with at least one bit line; performing a first data operation on at least one memory cell of the first memory plane, wherein at least one memory cell of the first memory plane is disposed on at least one word line of the first memory plane an intersection with at least one bit line; performing a second data operation on at least one memory cell of the second memory plane, wherein at least one memory cell of the second memory plane is arranged on at least one character of the second memory plane The intersection of the line with at least one bit line.

The above-mentioned driving method and non-volatile memory device can reduce inrush current.

The embodiments of the present disclosure will be described below in conjunction with the relevant drawings. In the drawings, the same reference numbers refer to the same or similar elements or method flows.

FIG. 1 is a simplified functional block diagram of a non-volatile memory device 100 according to an embodiment of the present disclosure. The non-volatile memory device 100 includes an input/output circuit 110, a control circuit 120, an address register 130, a bias voltage configuration circuit 140, a command register 150, a report circuit 160, and a memory chip MC, wherein the memory chip MC includes a plurality of memory planes 170-1 to 170-n. Memory plane 170 includes memory array 172 , column decoders 174 , row decoders 176 , and sense amplifiers and data input structures 178 . In order to make the drawings concise and easy to describe, other components and connection relationships in the non-volatile memory device 100 are not shown in the first figure.

The indices 1 to n in the element numbers used in the description and drawings of the present application are only for the convenience of referring to individual elements, and are not intended to limit the number of the foregoing elements to a specific number. In the description and drawings of the present application, if an element number is used without specifying the index of the element number, it means that the element number refers to any unspecified element in the element group to which it belongs. For example, the object referred to by the element number 170-1 is the memory plane 170-1, and the object referred to by the element number 170 is an unspecified arbitrary memory plane among the memory planes 170-1 to 170-n. For another example, the object referred to by the element number 172-1 is the memory array 172-1, and the object referred to by the element number 172 is any unspecified memory array in the memory arrays 172-1 to 172-n.

The I/O circuit 110 is used to determine whether to read the command input CI and the data input DI into the non-volatile memory device 100 , and to determine whether to output the data from the sense amplifier and data input structure 178 . For example, the I/O circuit 110 may determine whether to write the command input CI into the command register 150 according to the command latch (Command Latch Enable) signal CLE. For another example, the input/output circuit 110 may determine whether to read the data input DI and whether to output the data according to the write enable signal WE and the read enable signal RE, respectively.

In addition, the I/O circuit 110 is also used for writing one or more addresses AD1 ˜ ADn in the command input CI into the address register 130 , and the address register 130 is used for allocating the addresses AD1 ˜ ADn to the address register 130 . The column decoder 174 and the row decoder 176 of the corresponding one or more memory planes 170 . The input-output circuit 110 is also used for converting the data input DI into one or more data SD1-SDn to be written, and assigning the data SD1-SDn to be written to the corresponding one or more sense amplifiers and the data input structure 178 .

The control circuit 120 is coupled to the bias configuration circuit 140, the command register 150, the report circuit 160 and the memory planes 170-1~170-n. The control circuit 120 is used to perform data operations (eg, programming, reading and/or erasing) on the memory plane 170 according to the command input CI. The control circuit 120 is also used for controlling the output voltage of the bias voltage configuration circuit 140 according to the command input CI, wherein the bias voltage configuration circuit 140 is used for setting the plurality of word lines WL and the plurality of bit lines BL of the memory plane 170 to correspond to Appropriate voltages for current data operation on memory plane 170 .

The column decoder 174 and the row decoder 176 are coupled to the memory array 172 through a plurality of word lines WL and a plurality of bit lines BL, respectively. The column decoder 174 and the row decoder 176 are used to receive one or more of the addresses AD1 ˜ADn from the address register 130 , and to perform data operations on the memory array 172 according to the received addresses. In this embodiment, the memory array 172 may include multiple blocks, each block may include multiple physical pages, and each physical page may include multiple memory cells Ce. Each memory cell Ce is disposed at the intersection of a corresponding word line WL and a corresponding bit line BL, that is, the control gate of each memory cell Ce is composed of a corresponding word line WL and a corresponding one Defined by the overlapping portion of the bit line BL. In addition, the memory array 172 can be implemented as a two-dimensional memory array or a three-dimensional memory array.

FIG. 2 is a flowchart of a driving method 200 according to an embodiment of the present disclosure. FIG. 3 is a schematic diagram of waveforms of part of the word line WL and the bit line BL during the precharging process according to an embodiment of the present disclosure. FIG. 4 is a schematic diagram illustrating the operation timing of the memory planes 170 - 1 to 170 - n according to an embodiment of the present disclosure. The term precharge in this disclosure refers to pre-setting the corresponding word lines and bit lines to voltages close to those required for read, program, or erase operations before they are used for read, program, or erase operations. operating voltage. As the size of the memory array 172 increases, longer bitlines and wordlines may be required, and precharging can be used to offset some of the increased RC delays on the wordlines and bitlines and to speed up the memory array 172 Speed of voltage setting. Please refer to FIG. 2 first, the non-volatile memory device 100 can execute the driving method 200 to perform data operations such as reading, programming, and erasing. For the convenience of description, the following will take the programming operation as an example for description. In the process S202, the control circuit 120 determines whether the command input CI is a multi-plane operation command. If the command input CI is a multi-memory plane operation command, the non-volatile memory device 100 will then execute the processes S204 - S216 . On the contrary, the non-volatile memory device 100 will execute the processes S218-S222.

In the process S204, the control circuit 120 may select a corresponding one of the memory planes 170-1 to 170-n according to a target parameter to precharge at least one word line BL and at least one bit line WL thereof, The target parameters may be stored in the non-volatile memory device 100 in advance. For example, when the target parameter is 1, the control circuit 120 may control the bias configuration circuit 140 to precharge the memory plane 170-1. In this disclosure, precharging refers to setting the corresponding word line WL and bit line BL to an appropriate and stable voltage before performing data operations, so as to avoid parasitics on the word line WL and the bit line BL. The component caused the data operation to fail. For example, as shown in FIG. 3 , when the memory plane 170 is precharged, the control circuit 120 can raise at least one word line WL and at least one bit line BL of the memory plane 170 to corresponding voltages. For the sake of brevity, FIG. 3 only exemplarily shows the voltage waveforms of an unselected bit line Usel_BL, a selected bit line Sel_BL, an unselected word line Usel_WL, and a selected word line Sel_WL . Wherein, the unselected bit line Usel_BL is applied with an inhibit voltage (eg, 3V), the selected bit line Sel_BL is first applied with an inhibit voltage and then is applied with a ground voltage (eg, 0V), and the unselected word line Usel_WL is applied through voltage (passing voltage, eg, 10V), and a programming voltage (eg, 20V) is applied to the selected word line Sel_WL.

The voltage waveforms of the word line WL and the bit line BL may be a staircase wave as shown in FIG. 3 or a square wave. In some embodiments, the control circuit 120 may first use an external power source (not shown) with a relatively high power to charge the word line WL and the bit line BL to the first order voltage of the staircase wave to speed up the charging speed. Then, the bias voltage configuration circuit 140 is used to charge the word line WL and the bit line BL to the second order voltage of the staircase wave, but the present disclosure is not limited to this. In other embodiments, the control circuit 120 can also use the bias voltage configuration circuit 140 to charge the word line WL and the bit line BL during the entire precharge process without using an external power source.

Referring to FIG. 2 , in the process S206 , the control circuit 120 determines whether the memory plane 170 currently being precharged (eg, the memory plane 170 - 1 ) has been precharged for a first time length LA. When the memory plane 170 currently being precharged has been precharged for the first time length LA, the control circuit 120 will determine that the precharge is complete, and the non-volatile memory device 100 will then execute the process S208 to complete the programming precharge At least one memory cell Ce at the intersection of at least one word line WL and at least one bit line BL of the memory plane 170 (eg, memory plane 170 - 1 ) of the memory plane 170 . Otherwise, the non-volatile memory device 100 can perform the process S204 again.

In the process S210, the control circuit 120 determines whether all the memory planes 170-1 to 170-n have been programmed, for example, to determine whether the target parameter is less than the total number of the memory planes 170-1 to 170-n. If the programming of all the memory planes 170 has not been completed, the non-volatile memory device 100 will execute the process S212 to accumulate the value of the target parameter, for example, the target parameter is set as the target parameter plus 1. The non-volatile memory device 100 may execute the process S204 again after the process S212 ends. At this time, the control circuit 120 will select another corresponding one of the memory planes 170-1 to 170-n (for example, the memory plane 170- 2), to precharge at least one word line WL and at least one bit line BL.

In this embodiment, the process S208 may be executed simultaneously with the processes S210 to S212 and other processes after the process S212. Referring to FIG. 4, when the memory plane 170-1 is precharged and programmed, the control circuit 120 can control the memory plane 170-2 to start precharging. When programming is performed when the memory plane 170-2 is precharged, the control circuit 120 can control the memory plane 170-1 while the memory plane 170-1 and/or the memory plane 170-2 are still being programmed. 3Start precharging.

In other words, the driving method 200 helps to reduce the inrush current in the non-volatile memory device 100 since the memory planes 170 - 1 - 170 - n are not precharged at the same time.

In addition, the programming operations of many of the memory planes 170-1 to 170-n can be performed in parallel, that is, many of the programming periods TP1 to TPn corresponding to the programming of the memory planes 170-1 to 170-n. may overlap at least partially. Therefore, the driving method 200 helps to accelerate the programming speed of the non-volatile memory device 100 .

Referring to FIG. 2 again, in the process S214, the control circuit 120 determines whether each of the memory planes 170-1 to 170-n has been programmed successfully. For example, in some embodiments, the non-volatile memory device 100 is programmed using the Incremental-Step-Pulse Programming (ISPP) technique. The control circuit 120 can determine whether the programming is successful according to the total number of programming pulses provided to the target word line WL. If the control circuit 120 determines that the memory planes 170-1 to 170-n are all successfully programmed, the control circuit 120 can use the reporting circuit 160 to output a signal representing the successful programming to an external processor or external logic circuit (not shown), and the process ends The driving method 200 is performed. Otherwise, the non-volatile memory device 100 may execute the process S216 to reset the target parameter, and execute the process S204 again. For example, the non-volatile memory device 100 may reset the target parameter to 1 in the process S216, so as to start reprogramming the memory planes 170-1 to 170-n from the memory plane 170-1 in the next process.

When the command input CI is not a multi-memory plane operation command, the non-volatile memory device 100 executes the process S218 to precharge at least one word line WL and at least one word line of one of the memory planes 170-1 to 170-n. One-bit line BL. Next, when the precharge reaches the first time length LA, the non-volatile memory device 100 executes the process S220 to program at least one memory cell Ce of the one of the memory planes 170-1 to 170-n.

The process S222 is similar to the process S214. In the process S222, the control circuit 120 determines whether one of the memory planes 170-1 to 170-n has been programmed successfully. If the control circuit 120 determines that one of the memory planes 170 - 1 to 170 - n is successfully programmed, the non-volatile memory device 100 ends the driving method 200 . Otherwise, the non-volatile memory device 100 can perform the process S218 again.

In some embodiments, when the non-volatile memory device 100 uses the driving method 200 to read the memory chip MC, the non-volatile memory device 100 may perform a reading operation without performing a programming operation in the process S208 and the process S220. Similarly, in other embodiments, when the non-volatile memory device 100 uses the driving method 200 to erase the memory chip MC, the non-volatile memory device 100 may perform the erasing operation in the process S208 and the process S220 without Perform programming operations.

FIG. 5 is a flowchart of a driving method 500 according to another embodiment of the present disclosure. FIG. 6 is a schematic diagram illustrating the operation timing of the memory planes 170 - 1 to 170 - n according to another embodiment of the present disclosure. Referring to FIG. 5 first, the non-volatile memory device 100 can execute the driving method 500 to perform data operations such as reading, programming, and erasing. For the convenience of description, the following will take the programming operation as an example for description. The non-volatile memory device 100 will first execute the aforementioned process S202, wherein if the command input CI is a multi-memory plane operation command, the non-volatile memory device 100 will then execute the processes S504-S522. On the contrary, the non-volatile memory device 100 will execute the aforementioned processes S218-S222.

In the process S504, the control circuit 120 may select a corresponding one of the memory planes 170-1 to 170-n according to the target parameter to precharge at least one word line BL and at least one bit line WL thereof. Next, in the process S506, the control circuit 120 determines whether the memory planes 170-1 to 170-n are all precharged, for example, to determine whether the target parameter is less than the total number of the memory planes 170-1 to 170-n. If all the memory planes 170 have not been precharged, the non-volatile memory device 100 executes the processes S508 - S514 . Otherwise, the non-volatile memory device 100 will execute the process S516.

In the process S508 , the control circuit 120 determines whether the at least one word line WL and the at least one bit line BL in the memory plane 170 (eg, the memory plane 170 - 1 ) being precharged have reached their corresponding voltage thresholds. . For example, the control circuit 120 can determine whether each of the at least bit lines BL reaches a voltage threshold (eg, 2.8V) close to the inhibit voltage, and can also determine whether a certain word line WL reaches a voltage threshold close to the programming voltage. The voltage threshold (eg, 18V) can also be used to determine whether other word lines WL reach the voltage threshold (eg, 8V) close to the pass voltage. If the control circuit 120 determines that the at least one word line WL and the at least one bit line BL in the memory plane 170 being precharged have reached their corresponding voltage thresholds, the non-volatile memory device 100 will execute the process S510 . Otherwise, the non-volatile memory device 100 may repeatedly perform the process S508.

In the process S510, the control circuit 120 accumulates the target parameter, for example, the target parameter is set as the target parameter plus one. The non-volatile memory device 100 may execute the process S504 again after the process S510 ends. At this time, the control circuit 120 will select another corresponding one of the memory planes 170-1 to 170-n (for example, the memory plane 170- 2), to precharge at least one word line WL and at least one bit line BL.

When the non-volatile memory device 100 executes the processes S508 ˜ S510 and other processes after the process S510 , the non-volatile memory device 100 can simultaneously execute the processes S512 ˜ S514 . Please refer to FIG. 5 and FIG. 6 at the same time, in the process S512, the control circuit 120 determines whether the memory plane 170 currently being precharged (eg, the memory plane 170-1) has been precharged for a first time length LA. When the memory plane 170 currently being precharged has been precharged for the first time length LA, the control circuit 120 will determine that the precharge is completed, and the non-volatile memory device 100 will then execute the process S514 to program the precharged At least one memory cell Ce at the intersection of at least one word line WL and at least one bit line BL of the memory plane 170 (eg, memory plane 170-1). Otherwise, the non-volatile memory device 100 can repeatedly perform the process S512.

As shown in FIG. 6 , when at least one word line WL and at least one bit line BL of a certain memory plane 170 (eg, memory plane 170 - 1 ) reach their corresponding voltage thresholds at the first time point PTa , the control circuit 120 not only controls the bias configuration circuit 140 to continue to precharge the memory plane 170, the control circuit 120 also controls the bias configuration circuit 140 to start charging the next memory plane 170 (for example, the memory plane 170). 170-2) at least one word line WL and at least one bit line BL are precharged without waiting until the precharging of the certain memory plane 170 is completed. Similarly, when at least one word line WL and at least one bit line BL of the next memory plane 170 (eg, memory plane 170-2) reach their corresponding voltage thresholds at the second time point PTb, control the In addition to controlling the bias configuration circuit 140 to continue to precharge the next memory plane 170, the circuit 120 also controls the bias configuration circuit 140 to start precharging the next memory plane 170 (eg, the memory plane 170- 3) at least one word line WL and at least one bit line BL are precharged.

Since the precharge process is nearly complete when the at least one word line WL and the at least one bit line BL of the memory plane 170 reach their corresponding voltage thresholds, the bias configuration circuit 140 provides the memory The current in the body plane 170 has dropped considerably since the beginning of the precharge. Therefore, even if multiple memory planes 170 are precharged at the same time, it will not cause excessive inrush current.

As can be seen from the above, when the non-volatile memory device 100 executes the driving method 500, the memory planes 170-1 to 170-n will start to be precharged in sequence. Therefore, the driving method 500 helps reduce inrush current in the non-volatile memory device 100 .

In addition, many of the memory planes 170-1 to 170-n can be precharged at the same time without causing excessive inrush current. Therefore, the driving method 500 can further speed up the programming speed of the non-volatile memory device 100 .

Referring to FIG. 5 again, when the control circuit 120 determines in the process S506 that the target parameter is greater than or equal to the total number of the memory planes 170-1 to 170-n, the non-volatile memory device 100 will perform a process similar to the process S512 S516. When the control circuit 120 determines that the memory plane 170 currently being precharged (eg, the memory plane 170-n) has been precharged for the first time length LA, the control circuit 120 determines that the precharge is completed and executes the process S518 to program the precharge. At least one memory cell Ce of the memory plane 170 after charging is completed. Otherwise, the non-volatile memory device 100 may execute the process S516 again to continue to precharge the memory plane 170 .

The process S520 is similar to the process S214 in FIG. 2 . When the control circuit 120 determines that the memory planes 170 - 1 to 170 - n have all been successfully programmed, the non-volatile memory device 100 can end the driving method 500 . On the contrary, the non-volatile memory device 100 may perform a process S522 similar to the process S216 in FIG. 2 to reset the target parameter. The non-volatile memory device 100 may execute the process S504 again after the process S522 ends.

In some embodiments, as shown in FIG. 7 , in the process S508 , the control circuit 120 determines whether the memory plane 170 currently being precharged has been precharged for a second time length LB, wherein the aforementioned first time length LA is greater than the second time length LB. When the memory plane 170 currently being precharged has been precharged for the second time length LB, the non-volatile memory device 100 will execute the process S510. Otherwise, the non-volatile memory device 100 will execute the process S508 again to continue to precharge the memory plane 170 . The second time length LB can be pre-stored in the non-volatile memory device 100, wherein by selecting an appropriate second time length LB, many of the memory planes 170-1 to 170-n can be precharged simultaneously It will not cause excessive inrush current.

In other embodiments, when the non-volatile memory device 100 executes the driving method 500 to read the memory chip MC, the non-volatile memory device 100 may perform the read operation without programming in the process S514 and the process S518 operate. Similarly, in still other embodiments, when the non-volatile memory device 100 uses the driving method 500 to erase the memory chip MC, the non-volatile memory device 100 may perform the erasing operation in the process S514 and the process S518 without Perform programming operations.

Although FIG. 1 only shows one memory chip MC, the present disclosure is not limited to this. In practice, the non-volatile memory device 100 may include a plurality of memory chips MC to increase storage density, and the non-volatile memory device 100 may execute the driving method 200 or 500 for each memory chip MC.

Certain terms are used in the specification and claims to refer to particular elements. However, those of ordinary skill in the art should understand that the same elements may be referred to by different nouns. The description and the scope of the patent application do not use the difference in name as a way of distinguishing elements, but use the difference in function of the elements as a basis for distinguishing. The "comprising" mentioned in the description and the scope of the patent application is an open-ended term, so it should be interpreted as "including but not limited to". In addition, "coupled" herein includes any direct and indirect means of connection. Therefore, if it is described in the text that the first element is coupled to the second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection such as wireless transmission or optical transmission, or through other elements or connections. The means are indirectly electrically or signally connected to the second element.

As used herein, the description "and/or" includes any combination of one or more of the listed items. In addition, unless otherwise specified in the specification, any term in the singular also includes the meaning in the plural.

The above are only preferred embodiments of the present disclosure, and all equivalent changes and modifications made according to the claims of the present disclosure shall fall within the scope of the present disclosure.

100: Non-volatile memory device 110: Input and output circuit 120: Control circuit 130: Address register 140: Bias voltage configuration circuit 150: Command scratchpad 160: Return Circuit 170-1~170-n: Memory plane 172-1~172-n: Memory array 174-1~174-n: Column decoder 176-1~176-n: Line decoder 178-1~178-n: Sense Amplifier and Data Input Structure MC: memory chip Ce: memory cell DI: data input CI: command input CLE: command latch signal WE: write enable signal RE: read enable signal SD1~SDn: Data to be written AD1~ADn: address WL: word line Sel_WL: selected word line Usel_WL: no word line selected BL: bit line Sel_BL: selected bit line Usel_BL: bit line not selected 200,500: Drive Method S202~S222, S504~S522: Process LA: first time length LB: second time length TP1~TPn: programming period PTa: The first point in time PTb: Second time point

FIG. 1 is a simplified functional block diagram of a non-volatile memory device according to an embodiment of the present disclosure. FIG. 2 is a flowchart of a driving method according to an embodiment of the present disclosure. FIG. 3 is a schematic diagram of waveforms of some word lines and bit lines in a memory plane during a precharge process according to an embodiment of the present disclosure. FIG. 4 is a schematic diagram illustrating an operation timing of a plurality of memory planes according to an embodiment of the present disclosure. FIG. 5 is a flowchart of a driving method according to another embodiment of the present disclosure. FIG. 6 is a schematic diagram illustrating the operation timing of a plurality of memory planes according to another embodiment of the present disclosure. FIG. 7 is a schematic diagram illustrating an operation timing of a plurality of memory planes according to yet another embodiment of the present disclosure.

200: Drive Method

S202~S222: Process

Claims (10)

A driving method of a non-volatile memory device, the non-volatile memory device includes a plurality of memory planes, and the driving method includes: at least one character of a first memory plane of the plurality of memory planes line and at least one bit line are precharged; if the at least one word line and the at least one bit line of the first memory plane have been precharged for a predetermined first time length or to a voltage corresponding to each threshold, precharge at least one word line and at least one bit line of a second memory plane of the plurality of memory planes, wherein two of the at least one word line of the first memory plane The word lines have different voltage thresholds; a first data operation is performed on at least one memory cell of the first memory plane, wherein the at least one memory cell of the first memory plane is disposed in the first memory the intersection of the at least one word line and the at least one bit line of the plane; and performing a second data operation on at least one memory cell of the second memory plane, wherein the at least one memory cell of the second memory plane The memory cells are disposed at the intersection of the at least one word line and the at least one bit line of the second memory plane. The driving method of claim 1, wherein the first data operation is performed in a first period, the second data operation is performed in a second period, and the start point of the first period is earlier than the second period the starting point, And the first period and the second period at least partially overlap. The driving method of claim 2, wherein when the at least one word line and the at least one bit line of the first memory plane have been precharged for the first time length, the first memory plane is The at least one word line and the at least one bit line of the two memory planes are precharged, and the driving method further includes: if the at least one word line and the at least one bit line of the second memory plane have been precharged When the word line is precharged for the first time length, at least one word line and at least one bit line of a third memory plane of the plurality of memory planes are precharged. The driving method of claim 1, wherein when the at least one word line and the at least one bit line of the first memory plane reach the respective corresponding voltage thresholds, the second memory The at least one word line and the at least one bit line of the plane are precharged, and the at least one word line and the at least one bit line of the first memory plane continue to be precharged, wherein the first memory The process of performing the first data operation on the at least one memory cell of the body plane includes: when the at least one word line and the at least one bit line of the first memory plane have been precharged for the first time length , performing the first data operation on the at least one memory cell of the first memory plane. The driving method as described in claim 4, further comprising: If the at least one word line and the at least one bit line of the second memory plane reach a corresponding voltage threshold, then at least one word of a third memory plane among the plurality of memory planes line and at least one bit line are precharged, and continue to precharge the at least one word line and the at least one bit line of the second memory plane; wherein the at least one memory of the second memory plane The process of performing the second data operation on the cell includes: when the at least one word line and the at least one bit line of the second memory plane have been precharged for the first time length, the second memory The at least one memory cell of the plane performs the second data operation. The driving method of claim 1, wherein when the at least one word line and the at least one bit line of the first memory plane are precharged, the at least one word line of the first memory plane The line and the at least one bit line have stepped voltage waveforms. A driving method of a non-volatile memory device, the non-volatile memory device includes a plurality of memory planes, and the driving method includes: at least one character of a first memory plane of the plurality of memory planes line and at least one bit line are precharged; if the at least one word line and the at least one bit line of the first memory plane have been precharged for a predetermined second time shorter than a first time length length, the length to the second memory plane of the plurality of memory planes One less word line and at least one bit line are precharged, and the at least one word line and the at least one bit line of the first memory plane continue to be precharged; when the first memory plane has been precharged When the at least one word line and the at least one bit line are precharged for the first time length, a first data operation is performed on at least one memory cell of the first memory plane, wherein the The at least one memory cell is disposed at the intersection of the at least one word line and the at least one bit line of the first memory plane; and when the at least one word line and the at least one word line of the second memory plane are When at least one bit line is precharged for the first time length, a second data operation is performed on at least one memory cell of the second memory plane, wherein the at least one memory cell of the second memory plane is disposed in the The intersection of the at least one word line and the at least one bit line of the second memory plane. The driving method of claim 7, wherein the first data operation is performed in a first period, the second data operation is performed in a second period, and the start point of the first period is earlier than the second period , and the first period and the second period at least partially overlap. The driving method of claim 8, further comprising: if the at least one word line and the at least one bit line of the second memory plane have been precharged for the second time length, then Precharging at least one word line and at least one bit line of a third memory plane in the memory plane, and continuing to precharge the at least one word line and the at least one bit line in the second memory plane Charge. A non-volatile memory device comprising: a memory chip including a plurality of memory planes; and a control circuit coupled to the memory chip and configured to perform the following operations: for the plurality of memory planes At least one word line and at least one bit line of a first memory plane are precharged; if the at least one word line and at least one bit line of the first memory plane are precharged by a predetermined At least one word line and at least one bit line of a second memory plane among the plurality of memory planes are precharged for the first time length or when a corresponding voltage threshold is reached, wherein the first memory plane two word lines in the at least one word line of the plane have different voltage thresholds; perform a first data operation on at least one memory cell of the first memory plane, wherein the at least one memory cell is disposed at the intersection of the at least one word line and the at least one bit line of the first memory plane; and a second data operation is performed on at least one memory cell of the second memory plane, The at least one memory cell of the second memory plane is disposed at the intersection of the at least one word line and the at least one bit line of the second memory plane.

Images