TWI772989B - Board information analyzing system and method - Google Patents

Abstract

The present invention provides a board information analysis system for analyzing a board. The substrate information analysis system comprises at least one sensing device, an image measurement module, and a characteristic analysis module. The sensing device detects a target area of the board to obtain a circuit image. The image measurement module is coupled to the at least one sensing device, and generates wire size information according to a wire image. The characteristic analysis module generates circuit characteristic information based on the wire size information.

Description

Substrate information analysis system and method

The present invention relates to a substrate information analysis system and method, in particular to an analysis system and method for detecting circuit information on a substrate.

With the development of fully automated industry, Automatic Optical Inspection (AOI) is a common representative method in industrial processes. To detect defects such as foreign objects or abnormal patterns, non-contact inspection is used, so it can be used to inspect semi-finished products during the production line. Based on the advantages of automatic optical recognition system detection, it has been widely used in the appearance inspection of circuit board assembly lines in the electronics industry and replaced the previous manual visual inspection.

The high-frequency technology required by today's 5G technology presents significant challenges in the manufacture of substrates, and likewise, the ever-shrinking physical size of electronic devices makes these challenges even more difficult to overcome. The high-density interconnect (HDI) designs of these compact devices require thinner lines to dramatically increase I/O while minimizing system form factors. However, thin lines may increase the risk of signal degradation. Once the physical characteristics of the line (such as the width of the top and bottom) are changed from the original design, there will be a delay of several milliseconds in the transmission of the RF signal, which will affect the signal chain when the signals are not synchronized.

High-density signal integrity depends on tight impedance control in the narrower geometry of the PCB traces. Circuits formed using conventional subtractive etch processes typically exhibit trapezoidal cross-sections, resulting in numerous impedance anomalies. Improvements in semi-additive process (mSAP) can improve this problem, resulting in higher precision formed traces, and straighter trace walls can improve impedance control.

Although the existing technology can obtain the surface defects of the line through the image, but some types of defects cannot be effectively identified, there is a high correlation between the line type and impedance matching and noise generation. Identifying differences that are difficult to detect may also create a risk of impedance mismatch or EMI noise, which clearly has yet to be overcome.

On the other hand, the traditional 3D inspection of lines mainly uses Confocal microscopy, triangular reflection technology, and white light interference technology. The time is too slow, which makes it difficult to carry out a large number of inspections. Due to the limitation of point measurement, only local height information can be obtained, and it is difficult to combine it into complete line cross-sectional area information.

The main purpose of the present invention is to provide a substrate information analysis system for analyzing a substrate. The substrate information analysis system includes at least one sensing device, an image measurement module, and a characteristic analysis module. The sensing device detects a target area of the substrate to obtain a line image. The image measurement module is coupled to the at least one sensing device, and the image measurement module generates a line size information according to the line image. The characteristic analysis module generates circuit characteristic information according to the circuit dimension information.

Another object of the present invention is to provide a substrate information analysis method, comprising: Through the sensing device, a target area of the substrate is detected to obtain a circuit image; according to the circuit image, a circuit size information is generated; and according to the circuit size information, a circuit characteristic information is generated.

Therefore, the present invention can obtain the circuit dimension information of the substrate (for example, including the upper width of the circuit, the lower width of the circuit, the height of the circuit, the length of the circuit, the cross-sectional area of the circuit, etc.) through image detection, and further obtain the circuit size information by using the information. Line characteristic information to realize the function of obtaining line characteristics through images.

The detailed description and technical content of the present invention are described below with reference to the drawings. Furthermore, the drawings in the present invention are not necessarily drawn according to the actual scale for the convenience of description. These drawings and their scales are not intended to limit the scope of the present invention, and are described here in advance.

One embodiment of the present invention will be described below. Please refer to FIG. 1 , which is a block diagram of the substrate information analysis system of the present invention.

The present embodiment discloses a substrate information analysis system 100. The substrate information analysis system 100 is mainly used for detecting the substrate B, confirming the circuit information of the substrate B or the integrated circuit through machine vision, and analyzing the circuit information of the substrate B from the circuit information. Various data to confirm whether the substrate B includes defects. The substrate B can be, for example, a single-layer (Single-Layer PCB), a double-layer (Double-Layer PCB), a multi-layer board (Multi-layer board), etc., or any other substrate provided with circuits. be restricted.

The substrate information analysis system 100 mainly includes at least one sensing device 10 and a computer device 20 connected or coupled to the sensing device 10 .

The sensing device 10 is used for detecting a target area of the substrate B to obtain a line image. The sensing device 10 mainly acquires the circuit image of the substrate B by means of image capturing. Specifically, the sensing device 10 may include an area scan camera or a line scan camera, and the line images are captured by these cameras. In one embodiment, the sensing device 10 may include, for example, a laser 3D scanning device, such as a Time of Fight (TOF), a triangulation, a binocular camera, and the like. By acquiring three-dimensional images of the substrate B and the circuit on the substrate, various information of the circuit can be accurately measured. The target area refers to any area on the substrate B that includes lines.

The image captured by the sensing device 10 will be transmitted to the computer equipment 20 (such as a computer or a server), loaded into the storage unit by the processor of the computer equipment 20, and then accessed to the image processing program, and processed through the image The program performs an image processing operation on the obtained line image, generates line size information according to the result of image processing of the line image, and generates line detection results, line measurement results, and line characteristic information according to the line size information. The storage unit may be, but is not limited to, a cache memory, a dynamic random access memory (DRAM), a persistent memory (Persistent Memory), etc. that can be used as a device for storing and retrieving data or The combination thereof is not limited in the present invention.

In order to allow the sensing device 10 to easily obtain the region of interest of the circuit image on the substrate B to further obtain circuit size information, the substrate information analysis system 100 can be configured with an appropriate light source so that the computer equipment 20 can easily obtain the circuit size information on the substrate B.

The following is a detailed description of the hardware configuration of the substrate information analysis system 100 according to an embodiment of the present invention. Please also refer to FIG. 2 , which is a schematic diagram of the appearance of an apparatus according to an embodiment of the present invention.

In this embodiment, the sensing device 10 includes a top-view image capturing device 11 and a side-view image capturing device 12; the top-view image capturing device 11 is disposed on the top-view direction side of the target area to obtain the line image of the line image. The top-view image; the side-view image capturing device 12 is arranged on the side of the target area in the side-view direction to obtain the side-view image of the line image. In a specific embodiment, the side in the side view direction refers to the positive lateral position on the left and right sides of the substrate B (equivalent to the left or right direction of the substrate B in FIG. The upper left side or the upper right side direction of the middle substrate B), so that the shooting direction of the side view image capturing device 12 and the circuit on the substrate B maintain a proper inclination angle. In one embodiment, there is a photographing angle α between the optical axis direction L of the side-view image capturing device 20 and the plane of the substrate B, and the photographing angle α is between 0 degrees and 90 degrees.

Through the above configuration, the top-view image capturing device 11 and the side-view image capturing device 12 will obtain the top-view image and the side-view image (hereinafter referred to as the circuit image) of the substrate B, and the computer equipment 20 will be able to Get the circuit size information of the circuit on the substrate B. In an optional embodiment, in addition to the above-mentioned optical configuration, the present invention can also be used for other three-dimensional measurements such as Time of Fight (TOF), Triangulation, and binocular cameras. The device generates the line size information. Since the algorithms for obtaining the line size information by these devices are not within the scope of the present invention, they will not be described in detail here.

The computer device 20 and its algorithm will be described in detail below, please refer to FIG. 1 again. In order to generate line size information from the line image, and generate line detection results, line measurement results, and line characteristic information according to the line size information, the processor of the computer device 20 analyzes the line image through a program loaded into the storage unit. Specifically, the computer device 20 can be divided into an image measurement module F1, a characteristic analysis module F2, a three-dimensional image generation module F3, and a line detection module F4 according to the functions performed. It must be noted here that these modules may be executed by a single device, or may be executed separately or cooperatively by a plurality of devices, which is not limited in the present invention.

The following describes the calculation programs executed by the image measurement module F1, the characteristic analysis module F2, the 3D image generation module F3, and the line detection module F4, respectively. Please refer to "Fig. 3" to "Fig. 7" together.

The computer equipment 20 is connected or coupled to the sensing device 10 through the communication port 21 to obtain the line image. The processor 22 of the computer equipment 20 and the storage unit 23 are executed in cooperation to access the programs in the storage unit 23 for execution. corresponding algorithm. After obtaining the circuit image, the computer device 20 first generates circuit dimension information through the circuit image, and obtains the detection result, the measurement result, and the electrical measurement result through the circuit dimension information. In one embodiment, the computer device 20 further includes an image processing program for performing image processing functions. , growth compensation, etc.), machine learning system (Machine Learning), deep learning system (Deep Learning), etc., which are not limited in the present invention.

For the function of the image measurement module F1, please refer to "Figure 1" first. The image measurement module F1 is coupled to the at least one sensing device 10, and generates a line size information according to the line image. Specifically, when the computer device 20 executes the program of the image measurement module F1, it analyzes the line image to obtain the first region image feature (upper width) and the second region image feature (sidewall width) in the line image. Specifically, the image measurement module F1 can perform image preprocessing procedures (such as image enhancement, noise removal, contrast enhancement, edge enhancement, feature capture, image compression, image conversion, etc.), and The image is segmented, or the boundary is extracted, to divide the region of interest (ROI). The method of capturing the region of interest can be, for example, binarization, or through a neural network such as a machine learning system, a deep learning system, etc., after being trained by the system and the image of the first region. The feature and the second region image feature are segmented from the image, which are not limited in the present invention. It should be noted that the circuit image described herein is not necessarily a single image, and may also be two or more circuit images, through a plurality of circuit images for subsequent analysis of circuit distribution information in three-dimensional space.

After acquiring the image features of the first area and the image features of the second area, the image measurement module F1 analyzes the image features of the first area and the image features of the second area to obtain the circuit width of the substrate B (for example, including the width of the circuit and the circuit width). Line size information such as the width of the lower width, etc.), line height or line cross-sectional area, the following describes how to obtain the line size information.

，並經由該等資訊計算並獲得線路截面積。 Take the circuit on the substrate B as an example, and take the aforementioned embodiment of the dual-lens (top-view image capture device 11 and side-view image capture device 12 ) as an example, as shown in FIG. 3 , through the front optical configuration, the image measurement module F1 can obtain the upper width UW1 of the line, the lower width UW2 of the line, and the height of the line through two sets of images shot in different directions.

, and calculate and obtain the cross-sectional area of the line through this information.

In addition to obtaining the line size information through the top-view image and side-view image, the line can also be generated through 3D scanning technology (such as Time of Fight (TOF), Triangulation, and stereo vision). Dimension information, and these methods of obtaining line dimension information are not intended to be limited by the present invention.

In addition to the above-mentioned embodiments, the measurement results can also include, but are not limited to, various measurement data of the substrate circuit, such as the upper width of the circuit, the lower width of the circuit, the height of the circuit, the length of the circuit, the cross-sectional area of the circuit, and line volume. The line volume can be calculated from the line cross-sectional area and line length. In a more accurate calculation method, the line volume can be obtained by calculating the cross-sectional area of each sampled line and the length of each sampled line.

； For the function of the characteristic analysis module F2, please refer to "Figure 4" to "Figure 5". The characteristic analysis module F2 can generate corresponding line characteristic information according to the previously obtained line dimension information. The line characteristic information may include line resistance value information or line impedance value information. The characteristic analysis module F2 can generate the line resistance value information according to the line cross-sectional area and the line length. Specifically, the line resistance value information can be obtained, for example, by the following equation:

;

為電阻係數，L為線路長度，A為線路截面積。請參閱「圖4」基於前面線路尺寸資訊所獲得的截面積，可以獲得至多最大解析度中線路每一區段SG ₁-SG _N的截面積數據，經由前面的方程式將每一小區段長度L ₁-L _N截面積所對應的阻值加總後，最終可以獲得整個區段線路的線路電阻值資訊。 where R is the resistance value,

is the resistivity, L is the length of the line, and A is the cross-sectional area of the line. Please refer to "Fig. 4" based on the cross-sectional area obtained based on the previous line size information, the cross-sectional area data of each section SG ₁ -SG _N of the line in the maximum resolution can be obtained, and the length L of each small section can be calculated by the previous equation. After adding up the resistance values corresponding to the ₁ -L _N cross-sectional area, the line resistance value information of the entire section line can be finally obtained.

； In an alternative embodiment, please refer to FIG. 5 , taking a microstrip line as an example, the characteristic analysis module F2 can be based on the line width, the line height, and the dielectric layer of the target area. The height and dielectric layer coefficients generate information on the impedance value of the line. Specifically, the characteristic analysis module F2 includes, but is not limited to, for example, the following equation can be applied to obtain the line impedance value information:

;

為單端阻抗值，

為相對介電常數，

為線路寬度，

為線路高度，

為介電層高度。相對介電常數

為預知數值；線路寬度

以及線路高度

可以由前述的影像測量模組F1經由影像分析後獲得。介電層高度

於一實施例中，在介電層於線路影像中未被遮蔽的情況下，可以由前述的影像測量模組F1經由影像分析後獲得；於另一實施例中，在基板B的尺寸精度相對穩定的情況下，介電層高度

則可以預設為固定的數值或是預先測量時獲得，於本發明中不予以限制。 in,

is the single-ended impedance value,

is the relative permittivity,

is the line width,

is the line height,

is the height of the dielectric layer. Relative permittivity

is a predicted value; line width

and line height

It can be obtained by the aforementioned image measurement module F1 through image analysis. Dielectric layer height

In one embodiment, when the dielectric layer is not shielded in the circuit image, it can be obtained by the aforementioned image measurement module F1 through image analysis; in another embodiment, the dimensional accuracy of the substrate B is relatively In stable cases, the dielectric height

Then, it can be preset as a fixed value or obtained during pre-measurement, which is not limited in the present invention.

The shape of the cross-sectional area of the circuit in the above-mentioned embodiment is exemplified by a rectangle, but it can also be a trapezoid or other polygonal shapes, which is not intended to limit the present invention. The above formula calculation can also be other calculation methods that can be referred to and comply with the relevant standards such as IPC issued by the International Electronic Industry Connection Association, including but not limited to, such as IPC-2221, IPC-2222, IPC-2223, IPC-2224, IPC-2225, IPC-2226, IPC-2227 and other related specifications. In another feasible embodiment, the characteristic analysis module F2 can also obtain the impedance/resistance through a look up table. In the look-up table, the values that do not appear in the look-up table can be calculated by the K-Nearest Neighbor or Insertion Method, depending on the design requirements.

In the above embodiment, the electrical defect detection includes, but is not limited to, for example, short circuit detection, open circuit detection, and leakage detection. Short circuit detection can be measured by whether each line in the line image includes a connected area. The open circuit detection can be determined by the obtained line cross-sectional area and line volume. When the line cross-sectional area and line volume are lower than the set threshold, it is determined that the line is open circuit. In another feasible embodiment, the circuit can also be detected through the substrate circuit. The 3D images are determined by visual inspection or machine vision. Leakage detection can be measured by the state of the insulation layer in the line image.

In the above-mentioned embodiment, the electromagnetic interference (EMI) detection, including but not limited to, can input the three-dimensional model of the circuit to the wave field simulation system (such as HFSS) through the three-dimensional image generation module F3 to output the wave field simulation diagram. , and further evaluate the possibility of electromagnetic interference through the wave field simulation map.

In the above embodiment, the impedance matching detection, including but not limited to, can analyze whether the line resistance value information and line impedance value information of each line conform to the set reasonable range by obtaining the line resistance value information and line impedance value information. Inside, confirm the result of impedance matching by analyzing the result of line resistance value information.

In another possible embodiment, please refer to FIG. 6 and FIG. 7 together, and the impedance matching state can also be determined by visual inspection or machine vision through the three-dimensional image of the substrate circuit. By analyzing the cross-sectional area and volume of the line to be tested through image analysis, when the cross-sectional area and volume of the line have abnormal patterns/features, such as line concave or convex, it can quickly determine that the line impedance is abnormal.

As shown in "Fig. 6", the depression DF1 above the line is difficult to confirm the defect from the image (for example, the top view image) in the two-dimensional image captured by the general camera, but it can be quickly confirmed from the cross-sectional area of the line and the volume of the line whether the abnormal type is included. state/characteristics, and further quickly determine that the line impedance is abnormal.

As shown in "Fig. 7", the depressions DF2 and DF3 on both sides of the line are difficult to confirm the defects in the two-dimensional image captured by the general camera (such as the top-view or side-view image), but can also be determined by the line cross-sectional area, The volume of the line can be quickly confirmed whether there is an abnormal pattern/feature, and the abnormality of the line impedance can be further quickly determined.

The above-mentioned embodiments of "FIG. 4" to "FIG. 7" are taken as an example for testing a single-layer substrate. The present invention also achieves the whole-board electrical testing of a multi-layer substrate. Please refer to "FIG. 8". The same or repeated parts of the foregoing embodiment and this embodiment will not be repeated. For example, for the single-layer substrate disclosed in the foregoing embodiment, the circuit impedance information or the calculation example of the circuit resistance information will not be repeated.

In this embodiment, it is disclosed to perform electrical testing on the multi-layer substrate. The multi-layer substrate A in this embodiment is formed by laminating five-layer substrates A1-A5. There are circuits on the independent substrates A1-A5 respectively, the substrate A1 includes a circuit L1; the substrate A2 includes a circuit L2; the substrate A3 includes a circuit L3; the substrate A4 includes a circuit L3; Line L4; includes a line L5 on the substrate A5.

In order to electrically connect each layer of circuits (circuits L1-L5), the substrate A2 has a via hole TH2, the substrate A3 has a via hole TH3, the substrate A4 has a via hole TH4, and the substrate A5 There is a via TH5 on it, and the circuit L1 of the substrate A1 and the circuit L2 of the substrate A2 are electrically connected through the through hole TH2; the circuit L2 of the substrate A2 and the circuit L3 of the substrate A3 are electrically connected through the through hole TH3; The circuit L3 of the substrate A3 and the circuit L4 of the substrate A4 are electrically connected; the circuit L4 of the substrate A4 and the circuit L5 of the substrate A5 are electrically connected through the via hole TH5. It should be noted here that, in this embodiment, in order to simplify the description, each circuit board only includes a single circuit, but the multi-layer substrate usually has multiple or more circuits on each layer of the substrate. The circuits can be classified into individual circuits by means of image recognition and pre-stored circuit layout, so as to confirm the electrical connection relationship between the circuits. Since the type of the line is not within the intended scope of the present invention, it will not be described in detail here.

、線路L2的阻抗值為

、線路L3的阻抗值為

、線路L4的阻抗值為

、線路L5的阻抗值為

、過孔TH2的阻抗值為

、過孔TH3的阻抗值為

、過孔TH4的阻抗值為

、過孔TH5的阻抗值為

，則所述線路的總體阻抗值(

)將等於上面的阻抗值的疊加:

； Through the aforementioned embodiments, the resistance value or resistance value information of the lines L1-L5 of the substrates A1-A5 of each layer can be obtained individually. In addition, the impedance of the via holes TH2-TH5 can be obtained according to the via hole information such as the via hole inner diameter, the via hole outer diameter, the via hole height, the reference plane via hole cutout diameter, and the via hole plating thickness. Finally, the impedance values of the multiple lines L1-L5 and the via holes can be superimposed and calculated to obtain the impedance value of the entire line. For example, the impedance value of the line L1 obtained through the result of the impedance calculation is

, the impedance of line L2 is

, the impedance of line L3 is

, the impedance of line L4 is

, the impedance of line L5 is

, the impedance of the via TH2 is

, the impedance of the via TH3 is

, the impedance of the via TH4 is

, the impedance of the via TH5 is

, then the overall impedance value of the line (

) will be equal to the superposition of the impedance values above:

;

In addition to the impedance value, the resistance value also conforms to the above-mentioned superposition formula, and by using the above-mentioned method, the impedance characteristic information of the entire board circuit of the multilayer substrate A can be obtained.

In addition to the above-mentioned detection methods, the present invention can also perform electrical detection on lines across layers, please refer to FIG. 9 together, as shown in the figure. The same or repeated parts of the foregoing embodiment and this embodiment will not be repeated. For example, for the single-layer substrate disclosed in the foregoing embodiment, the circuit impedance information or the calculation example of the circuit resistance information will not be repeated.

In this embodiment, it is disclosed to perform electrical testing on the lines across the layers, and the multilayer substrate B' in this embodiment is formed by laminating five-layer substrates B1-B5. There are circuits on the substrate B2 and the substrate B4 respectively, the substrate B2 includes a circuit K2; the substrate B4 includes a circuit K4; in order to bridge the circuit K2 of the substrate B2 and the circuit K4 of the substrate B4, the substrate B3 There is a via hole YH3 thereon, the substrate B4 has a via hole YH4, and the circuit K2 of the substrate B2 is electrically connected through the via hole YH3; the via hole YH3 of the substrate B3 and the circuit K4 of the substrate B4 are electrically connected through the via hole YH4.

、線路K4的阻抗值為

、過孔YH3的阻抗值為

、過孔YH4的阻抗值為

，則所述線路的總體阻抗值(

)將等於上面的阻抗值的疊加:

； According to the above-mentioned embodiment, the impedance value or resistance value information of the lines K2 and K4 of the substrates B1-B5 of each layer and the via holes YH3-YH4 can be obtained individually, and finally the impedance values of a plurality of lines and the impedance of the via holes YH3-YH4 can be obtained. Value superposition calculation to obtain impedance value information for the entire line. For example, the impedance value of the line K2 obtained individually through the aforementioned single-layer board detection is

, the impedance of line K4 is

, the impedance of via YH3 is

, the impedance of via YH4 is

, then the overall impedance value of the line (

) will be equal to the superposition of the impedance values above:

;

In addition to the impedance value, the resistance value also conforms to the above superposition formula. The circuit characteristic information of the multilayer substrate can be obtained by the above method.

The three-dimensional image generation module F3 can obtain the three-dimensional model of the circuit of the substrate B according to the circuit information obtained above. Taking dual cameras as an example, please refer to "Figure 10" to "Figure 15" for the three-dimensional image generation method, as shown in the figure.

First, please refer to FIG. 10 , after receiving the first image and the second image of the substrate B, the three-dimensional image generation module F3 sets a plurality of consecutive coordinates based on the boundary of one side of the first image and the second image Position M1(X1, Y2, Z3)...Mn(Xn, Yn, Zn)...MN(XN, YN, ZN), the coordinate position can be set through the stereo vision method (Stereo Vision Algorithm), the image pixel coordinates The system (u, v) is converted to the world coordinate system (Xw, Yw, Zw) and the calibration of the target coordinate position in the image is completed. In another feasible embodiment, the plurality of coordinate positions can also be sampled at the other side boundary, the centerline or other easily identifiable reference features, which are not limited in the present invention. In another feasible embodiment, especially in the embodiment of the line scanning camera, the coordinate position can be confirmed by feedback from the data of the transfer device.

Continuing, please refer to FIG. 11 together. After the coordinate positions are set, the 3D image generation module F3 obtains the upper line width UW1 and the lower line width UW2 in the first image. The relative position between the upper line width UW1 and the lower line width UW2 can be determined by the first sidewall width W1, the second sidewall width W2 or the first sidewall width W1, the second sidewall width W2 in the first image The ratio between is obtained.

Next, please refer to FIG. 12 together. After receiving the second image of the circuit, the 3D image generation module F3 analyzes the side wall width W3 of the circuit in the circuit image in the second image.

時，同時記錄等參數所屬的座標位置Mn(Xn, Yn, Zn)。 After the above two steps, the 3D image generation module F3 will obtain the upper width UW1 of the line, the lower width UW2 of the line, the width W1 of the first side wall, and the width W2 of the second side wall, and obtain through the above line information calculation. line height

At the same time, record the coordinate position Mn(Xn, Yn, Zn) to which the other parameters belong.

的參數條件確認的情況下，可以確認梯形截面的底長、頂長、高度、第一側斜邊、第二側斜邊，並由上述參數決定截面區域上的二維型態，進一步可以構成一二維影像截面圖ST。 Continuing, please refer to "Fig. 13" together, when the upper width UW1 of the line, the lower width UW2 of the line, the height T of the line, and the corresponding coordinate position Mn (Xn, Yn, Zn) are obtained, the 3D image generation module F3 establishes the target cross-sectional image according to the upper width UW1 of the line, the lower width UW2 of the line and the height T of the line. In this step, first confirm the relative positional relationship between the upper width UW1 and the lower width UW2 of the line through the width W1 of the first side wall and the width W2 of the second side wall.

When the parameter conditions are confirmed, the bottom length, top length, height, first side hypotenuse, and second side hypotenuse of the trapezoidal cross-section can be confirmed, and the two-dimensional pattern on the cross-sectional area can be determined by the above parameters. A two-dimensional image cross-sectional view ST.

Finally, please refer to "Fig. 14" and "Fig. 15" together, and sample the coordinate positions M1(X1, Y1, Z1)...Mn(Xn, Yn, Zn)...MN(XN, YN, ZN), and two-dimensional image cross-sectional views ST1-STn-STN corresponding to coordinate positions M1(X1, Y1, Z1)...Mn(Xn, Yn, Zn)...MN(XN, YN, ZN) , to create an image stack STK. After completing the image stacking STK, between the coordinate positions of the image intervals (M1(X1, Y1, Z1)...Mn(Xn, Yn, Zn)...MN(XN, YN, ZN)) through the interpolation method (Interpolation ) to supplement, thereby outputting a three-dimensional image of the circuit board as shown in "Fig. 15".

The circuit detection module F4 obtains the detection result of the surface defect of the substrate B according to the circuit image.

In the above-mentioned embodiment, the surface defect detection results include, but are not limited to, for example, any visible defects on the structure, such as surface quality and circuit defect information. In one embodiment, the line inspection module F4 can directly acquire non-structural defects (such as ink, dirt, etc.) through the first image and the second image, and directly mark the defects in the images through machine vision. . Surface structural defects (such as breakage, copper leakage, etc.) can be contrasted with the adjacent surface through optical configuration, or through the 3D image generation module F3, after the 3D image is reconstructed through the substrate circuit, it can pass the visual inspection. Or find the flaw by setting the threshold of the cross-sectional area (Threshold), through the above method, you can effectively find the flaw and output the detection result.

The following describes the substrate information analysis method of the present invention, please refer to FIG. 16 , which is a schematic flowchart of the substrate information analysis method of the present invention.

In one embodiment of the present invention, a method for analyzing substrate information is disclosed, which includes the following steps:

In terms of hardware configuration, a sensing device is first provided to one side of the substrate to detect a target area of the substrate to obtain a line image (step S01 ); in an embodiment, a top-view image capturing device can be provided to the top-view direction side of the substrate, and a side-view image capturing device is provided to the side-view direction side of the substrate, so as to obtain a first image of the substrate through the top-view image capturing device and the side-view image capturing device, respectively; A second image.

Then, after receiving the circuit image, the computer device generates a circuit size information according to the circuit image (step S02); the circuit size information includes circuit width, circuit height or circuit cross-sectional area; in another embodiment, the circuit size information It further includes the width of the upper web of the line, the width of the lower web of the line, and the volume of the line.

Finally, the computer device generates a line characteristic information according to the line size information (step S03). In one embodiment, the above-mentioned line characteristic information includes, but is not limited to, for example, line resistance value information or line impedance value information.

Through the above steps, the substrate information analysis method of the present invention can obtain the detection result, measurement result, and electrical measurement result of the substrate circuit through the captured circuit image. Among them, the test results include surface quality and line defect information; the measurement results include line width, line width, line height, line length, line cross-sectional area, line resistance value information, and line volume; electrical measurement results include Electrical defects, electromagnetic interference, and impedance matching, and finally realize the data detection of the substrate.

To sum up, the present invention can obtain the five-dimensional circuit information of the substrate (including the upper width of the circuit, the lower width of the circuit, the height of the circuit, the length of the circuit, the cross-sectional area of the circuit, and the information of the circuit resistance value) of the substrate through image detection. The line information realizes the functions of line detection, line measurement, and electrical detection.

The present invention has been described in detail above, but the above is only one of the preferred embodiments of the present invention, and should not limit the scope of the present invention, that is, all claims made according to the scope of the present invention are equal. Changes and modifications should still fall within the scope of the patent of the present invention.

線路寬度

線路高度

介電層高度 步驟S01-步驟S03 100 Substrate information analysis system 10 Sensing device 11 Top view image capture device 12 Side view image capture device 20 Computer equipment 21 Communication port 22 Processor 23 Storage unit B Substrate L Optical axis direction α Shooting angle F1 Image measurement module F2 Feature Analysis Module F3 3D Image Generation Module F4 Line Detection Module DF1 Concave Above the Line Substrate B1-B5 Substrate K2, K4 Line YH3-TH4 Via SG ₁ -SG _N Section L ₁ -L _N Section Length UW1 Line Upper Width UW2 Line Lower Width W1 First Side Sidewall Width W2 Second Sidewall Width W3 Line sidewall side view width ST 2D image cross-section ST1-STn-STN 2D image cross-section STK Image stack

Line width

line height

Dielectric Layer Height Step S01 - Step S03

FIG. 1 is a block diagram of the substrate information analysis system of the present invention.

FIG. 2 is a schematic diagram of the appearance of a device according to an embodiment of the present invention.

FIG. 3 is a schematic side view of the substrate circuit in the present invention.

FIG. 4 is a schematic diagram showing the division of a plurality of cross-sections of the circuit of the substrate of the present invention.

FIG. 5 is a schematic side view of the microstrip line in the present invention.

FIG. 6 is a schematic diagram of line defects (1).

FIG. 7 is a schematic diagram of a line defect (2).

FIG. 8 is a schematic exploded view (1) of the structure of the multi-layer substrate.

FIG. 9 is a schematic exploded view (2) of the structure of the multi-layer substrate.

FIG. 10 is a coordinate position positioning diagram of the substrate circuit in the present invention.

FIG. 11 is a schematic top view image of the substrate circuit in the present invention.

FIG. 12 is a schematic side view image of the substrate circuit in the present invention.

FIG. 13 is a schematic diagram (1) of imaging a three-dimensional image image of a substrate circuit in the present invention.

FIG. 14 is a schematic diagram (2) of imaging a three-dimensional image image of a substrate circuit in the present invention.

Fig. 15 is a schematic diagram (3) of imaging a three-dimensional image image of a substrate circuit in the present invention.

FIG. 16 is a schematic flowchart of a method for analyzing substrate information in the present invention.

100 Substrate information analysis system 10 Sensing device 20 Computer equipment 21 Communication port 22 processors 23 storage units F1 Image Measurement Module F2 Characteristic Analysis Module F3 3D image generation module F4 Line detection module B Substrate

Claims (23)

A substrate information analysis system for analyzing a substrate, comprising: at least one sensing device detects a target area of the substrate to obtain a line image; an image measurement module, coupled to the at least one sensing device, to generate a line size information according to the line image; and A characteristic analysis module generates circuit characteristic information according to the circuit dimension information. The substrate information analysis system according to claim 1, wherein the line characteristic information includes line resistance value information or line impedance value information. The substrate information analysis system according to claim 2, wherein the line dimension information includes a line width, a line height, a line length or a line cross-sectional area. The substrate information analysis system according to claim 3, wherein the line width includes a line upper width and a line lower width. The substrate information analysis system of claim 3, wherein the characteristic analysis module generates the line resistance value information according to the line cross-sectional area and the line length. The substrate information analysis system according to claim 3 or 4, wherein the characteristic analysis module generates the line impedance value information according to the line width, the line height, and the dielectric layer height and the dielectric layer coefficient of the target area . The substrate information analysis system according to claim 3 or 4, wherein the characteristic analysis module determines that the line impedance is abnormal according to the line cross-sectional area or the line volume. The substrate information analysis system of claim 1, wherein the at least one sensing device comprises: a top-view image capturing device for obtaining a top-view image of the line image on the side of the target area in the top-view direction; and A side-view image capturing device obtains a side-view image of the line image on the side of the target area in the side-view direction. The substrate information analysis system as claimed in claim 8, wherein a photographing angle is formed between the optical axis direction of the side-view image capturing device and the plane of the substrate, and the photographing angle is between 0 degrees and 90 degrees. The substrate information analysis system according to claim 1, wherein the sensing device comprises a laser three-dimensional scanning device, and the circuit dimension information is measured by acquiring a three-dimensional image of the substrate and the circuit on the substrate. The substrate information analysis system according to claim 1, further comprising a three-dimensional image generation module, the three-dimensional image generation module obtains the circuit three-dimensional model of the substrate according to the circuit size information. The substrate information analysis system according to claim 1, further comprising a circuit detection module, the circuit detection module obtains a surface defect detection result of the substrate according to the circuit image. The substrate information analysis system of claim 1, wherein the circuit characteristic information includes electrical defects, electromagnetic interference, or impedance matching. A substrate information analysis method, comprising: Detecting a target area of the substrate through the sensing device to obtain a line image; generating a line size information based on the line image; and According to the line size information, a line characteristic information is generated. The substrate information analysis method of claim 14, wherein the circuit characteristic information includes circuit resistance value information or circuit impedance value information. The substrate information analysis method according to claim 15, wherein the circuit dimension information includes a circuit width, a circuit height, a circuit length or a circuit cross-sectional area. The substrate information analysis method as claimed in claim 16, wherein the line width includes a line upper width and a line lower width. The substrate information analysis method according to claim 16, wherein the step of generating the circuit characteristic information according to the circuit dimension information comprises generating the circuit resistance value information according to the circuit cross-sectional area and the circuit length. The method for analyzing substrate information according to claim 15 or 16, wherein the step of generating the circuit characteristic information according to the circuit size information includes the step of generating the circuit characteristic information according to the circuit width, the circuit height, and the dielectric layer height and the dielectric layer of the target area. The coefficients generate information about the impedance value of the line. The substrate information analysis method according to claim 15 or 16, comprising determining that the line impedance is abnormal according to the line cross-sectional area or the line volume. The substrate information analysis method of claim 14, further comprising obtaining a three-dimensional circuit model of the substrate according to the circuit dimension information. The method for analyzing substrate information according to claim 14, further comprising obtaining a surface defect detection result of the substrate according to the circuit image. The substrate information analysis method of claim 14, wherein the circuit characteristic information includes electrical defects, electromagnetic interference, and impedance matching.

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