TWI771095B - Control chip, control circuit, and control method for sensing panels - Google Patents

Abstract

A control circuit of a sensing panel is provided. The control circuit includes a first, a second, and a third control chips. The first control chip includes a first clock input pin, a clock output pin, a primary data pin, and a first secondary data pin. The control circuit sends a clock through the clock output pin and sends a command through the primary data pin. The second control chip includes a second clock input pin configured to receive the clock, and a second secondary data pin configured to receive the command. The third control chip includes a third clock input pin configured to receive the clock, and a third secondary data pin configured to receive the command. After receiving the command, the second control chip sends or receives a first data according to the clock and a first target value. After receiving the command, the third control chip sends or receives a second data according to the clock and a second target value. The target value is different from the second target value.

Description

Control chip, control circuit and control method of induction panel

The present invention relates to an induction panel, in particular to a control circuit and a control method of the induction panel.

The induction panel can sense contact operation or non-contact operation. The panel that can sense the touch operation is, for example, a capacitive or resistive touch panel, which can know the position of the touch operation by detecting the magnitude of the voltage on the panel. The panel that can sense the non-contact operation is, for example, an electromagnetic induction panel, which can know the position of the non-contact operation by detecting the magnitude of the electromagnetic field on the surface of the panel.

A sensor panel usually requires a plurality of detection chips, and a main control chip connected to the detection chips. The detection chip is responsible for detecting the voltage or electromagnetic field in the selected range and generating the detection result, and the main control chip calculates the position of the contact/non-contact operation according to the detection result.

The larger the size of the sensor panel, the more detection chips are required, so the main control chip needs to have more pins to connect with all the detection chip signals. This increases the cost of the master chip and increases the complexity of the wiring of the panel.

In view of the deficiencies of the prior art, one object of the present invention is to provide a control chip, a control circuit and a control method for a sensing panel to improve the deficiencies of the prior art.

An embodiment of the present invention provides a control chip for an induction panel. The sensing panel includes a sensing circuit. The control chip includes: a clock input pin; a first data pin; a detection circuit coupled to the sensing circuit for detecting a characteristic value on the sensing circuit; a memory for storing a plurality of programs code or program instructions; and a computing circuit coupled to the clock input pin, the first data pin, the detection circuit and the memory for executing the code or program instructions to perform the following steps: A clock is received through the clock input pin; a command is received through the first data pin; and the characteristic value is transmitted through the first data pin according to the clock and a target value. The target value determines a point in time when the control chip transmits the characteristic value.

Another embodiment of the present invention provides a control circuit for a sensing panel, which includes a first control chip, a second control chip, and a third control chip. The first control chip includes a first clock input pin, a first clock output pin, a first main data pin and a first secondary data pin for connecting through the first clock output The pin transmits a clock, and transmits a command through the first main data pin. The second control chip includes: a second clock input pin coupled to the first clock output pin for receiving the clock; and a second secondary data pin coupled to the first primary data pin to receive the command. The third control chip includes: a third clock input pin coupled to the first clock output pin for receiving the clock; and a third secondary data pin coupled to the first primary data pin to receive the command. After receiving the command, the second control chip transmits or receives a first data according to the clock and a first target value; after receiving the command, the third control chip transmits or receives a first data according to the time The pulse and a second target value transmit or receive a second data; the first target value is not equal to the second target value.

Another embodiment of the present invention provides a control circuit for a sensing panel, which includes a first control chip, a second control chip, and a third control chip. The first control chip includes a first clock input pin, a first clock output pin, a first main data pin and a first secondary data pin for connecting through the first clock output The pin transmits a clock, and transmits a command through the first main data pin. The second control chip includes: a second clock input pin, coupled to the first clock output pin, for receiving the clock; a second clock output pin for transmitting the clock; a The second secondary data pin is coupled to the first primary data pin for receiving the command; and a second primary data pin is used for transmitting the command. The third control chip includes: a third clock input pin coupled to the second clock output pin for receiving the clock; and a third secondary data pin coupled to the second primary data pin to receive the command.

With regard to the features, implementations and effects of the present invention, embodiments are described in detail as follows in conjunction with the drawings.

100, 210, 220, 230, 240, 250, 710, 720, 730, 740, 750, 1210, 1220, 1230, 1240, 1250, 1260, 1270, 1280, 1290, 1291, 1292: Control wafer

110: Detection circuit

120: Computational Circuits

130: Memory

CLK_TX, CLK_TX1, CLK_TX2, CLK_TX3, CLK_TX4: Clock output pins

CLK_RX, CLK_RX1, CLK_RX2, CLK_RX3, CLK_RX4, CLK_RX5: Clock input pins

DAT_TX, DAT_TX1, DAT_TX2, DAT_TX3, DAT_TX4: Main data pins

DAT_RX, DAT_RX1, DAT_RX2, DAT_RX3, DAT_RX4, DAT_RX5: Secondary data pins

200, 700, 1200: induction panel

201, 202, 203, 204, 205, 701, 702, 703, 704, 705: Induction circuits

208,708,1208: Control Circuits

CLK: Clock

T: period

t0,t1,t2,t3,t4,t5,t6,t7,t8,t9,t10,t11,t12,t13,t14,t15,t16,t17,t18,t19: time points

CMD_W: write command

DAT_210_220,DAT_210_230,DAT_210_240,DAT_210_250,DAT_220_210,DAT_230_210,DAT_240_210,DAT_250_210,DAT_710_720,DAT_710_730,DAT_710_740,DAT_710_750,DAT_720_710,DAT_730_710,DAT_740_710,DAT_750_710:資料

CMD_R: read command

Steps

1 is a functional block diagram of an embodiment of a control chip of the present invention; FIG. 2 shows a sensing panel and its control circuit according to an embodiment of the present invention; 4A shows the flow chart of the write operation of the control wafer 210; FIG. 4B shows the flow chart of the write operation of the control wafer 220~250; 5 shows the timing arrangement of read commands and data in the read operation of the control circuit; FIG. 6A shows the flow chart of the read operation of the control chip 210; FIG. 6B shows the flow chart of the read operation of the control chips 220 to 250 7 shows a sensor panel and its control circuit according to another embodiment of the present invention; Flow chart; FIG. 9B shows the flow chart of the write operation of the control chips 720-740; FIG. 10 shows the timing arrangement of read commands and data in the read operation of the control circuit; FIG. 11A shows the read operation of the control chip 710 11B shows a flow chart of the read operation of the control chips 720-740; and FIG. 12 shows a sensor panel and its control circuit according to another embodiment of the present invention.

The technical terms used in the following description refer to the common terms in the technical field. If some terms are described or defined in this specification, the interpretation of these terms is subject to the descriptions or definitions in this specification.

The disclosure of the present invention includes a control chip, a control circuit and a control method of a sensing panel. Since some components included in the control chip and the control circuit of the sensing panel of the present invention may be known components individually, without affecting the full disclosure and practicability of the invention of the device, the following description describes the known components details will be omitted. In addition, part or all of the process of the control method of the sensor panel of the present invention can be in the form of software and/or firmware, and can be executed by the control chip of the present invention or its equivalent device, without affecting the sufficiency of the invention of the method. On the premise of disclosure and enforceability, The following description of the method invention will focus on the steps rather than the hardware.

FIG. 1 is a functional block diagram of an embodiment of a control chip of the present invention. The control chip 100 is used to detect a contact operation or a non-contact operation on the sensing panel. The control chip 100 includes a detection circuit 110 , a calculation circuit 120 , a memory 130 and four pins: a clock output pin CLK_TX, a clock input pin CLK_RX, a main data pin DAT_TX and a secondary data pin DAT_RX. The detection circuit 110 is coupled to a sensing circuit (eg, a capacitor array, a resistor array or an antenna array) for detecting characteristic values (eg, at least one of voltage, electric field, and magnetic field) on the sensing circuit. The memory 130 stores a plurality of program codes or program instructions. The calculation circuit 120 is coupled to the detection circuit 110 , the memory 130 and the four pins. The computing circuit 120 may be a circuit or electronic component with program execution capability, such as a central processing unit, a microprocessor, a micro-processing unit, a digital signal processor, an application specific integrated circuit (ASIC), or the like effective circuit. The computing circuit 120 implements the functions of controlling the chip 100 (including but not limited to processing characteristic values) by executing the program codes or program instructions. In other words, the program codes or program instructions can be regarded as firmware or software for controlling the chip 100 .

The clock output pin CLK_TX and the clock input pin CLK_RX are unidirectional pins, that is, the computing circuit 120 receives the clock through the clock input pin CLK_RX, and transmits the clock through the clock output pin CLK_TX. The primary data pin DAT_TX and the secondary data pin DAT_RX are bidirectional pins, that is, the computing circuit 120 can transmit and receive data through the primary data pin DAT_TX, and can also transmit and receive data through the secondary data pin DAT_RX .

FIG. 2 shows a sensing panel and its control circuit according to an embodiment of the present invention. The sensing panel 200 includes a sensing circuit 201 , a sensing circuit 202 , a sensing circuit 203 , a sensing circuit 204 , a sensing circuit 205 and a control circuit 208 . The control circuit 208 includes a control chip 210, a control chip 220, a control chip 230, There are five control wafers including the control wafer 240 and the control wafer 250 . Each control chip detects a designated area of the sensing panel 200 through the sensing circuit; more specifically, the control chips 210, 220, 230, 240 and 250 (coupled to or electrical connection) to detect a certain area of the sensing panel 200 through the sensing circuits 201 , 202 , 203 , 204 and 205 respectively. The control chips 210 , 220 , 230 , 240 and 250 can all be implemented by the control chip 100 . Please note that the 5 control wafers are for example only, and are not intended to limit the present invention. In other embodiments, more or less control wafers may be disposed on the sensing panel 200 .

The clock output pin CLK_TX1 of the control chip 210, the clock input pin CLK_RX2 of the control chip 220, the clock input pin CLK_RX3 of the control chip 230, the clock input pin CLK_RX4 of the control chip 240 and the clock input pin CLK_RX4 of the control chip 250 The input pin CLK_RX5 is coupled or electrically connected. That is, the control chip 210 can transmit the clock CLK to the control chip 220 , the control chip 230 , the control chip 240 and the control chip 250 . In some embodiments, the clock CLK can be generated by an oscillator (not shown) on the control circuit 208, and the control chip 210 receives the clock CLK through the clock input pin CLK_RX1.

The main data pin DAT_TX1 of the control chip 210, the secondary data pin DAT_RX2 of the control chip 220, the secondary data pin DAT_RX3 of the control chip 230, the secondary data pin DAT_RX4 of the control chip 240, and the secondary data pin of the control chip 250 The pin DAT_RX5 is coupled or electrically connected. That is, the control chip 210 can transmit data to the control chips 220, 230, 240 and 250 through the primary data pin DAT_TX1, and receive the control chips 220, 230, 240 and 250 through the primary data pin DAT_TX1 (respectively through the secondary data Data transmitted by pin DAT_RX2, secondary data pin DAT_RX3, secondary data pin DAT_RX4 and secondary data pin DAT_RX5). In some embodiments, the control chip 210 can transmit data to other devices through the secondary data pin DAT_RX1 (For example, a processor (not shown) of an electronic device that includes or integrates the sensing panel 200).

The write operations (FIGS. 3, 4A, and 4B) and read operations (FIGS. 5, 6A, and 6B) of the control circuit 208 are discussed below.

3 shows the timing arrangement of write commands and data in the write operation of the control circuit 208 , FIG. 4A shows the flow chart of the write operation of the control chip 210 , and FIG. 4B shows the flow chart of the write operation of the control chips 220 to 250 . picture.

The calculation circuit 120 of the control chip 210 transmits the clock CLK through the clock output pin CLK_TX1 (step S410 ), and sequentially transmits the write command CMD_W (time point t0 ), the data DAT_210_220 ( Time point t1), data DAT_210_230 (time point t2), data DAT_210_240 (time point t3), and data DAT_210_250 (time point t4) (step S420). "Data DAT_X_Y" means that the source of the data is the control chip X, and the destination of the data is the control chip Y. In some embodiments, the lengths of the write command and the data are the same; for example, in the example of FIG. 3 , both are three periods T of the clock CLK (but not limited thereto).

The calculation circuit 120 of the control chips 220, 230, 240 and 250 receives the clock CLK through the clock input pins CLK_RX2, CLK_RX3, CLK_RX4 and CLK_RX5 respectively (step S460), and respectively through the secondary data pins DAT_RX2, DAT_RX3, DAT_RX4 and DAT_RX5 Receive the write command CMD_W (step S470 ), and receive data through the secondary data pins DAT_RX2 , DAT_RX3 , DAT_RX4 and DAT_RX5 respectively according to the clock CLK and the target value Px (step S480 ). In some embodiments, the computing circuit 120 of the control chips 220 , 230 , 240 and 250 stores the data in the memory 130 .

The control chips 220, 230, 240 and 250 each store a target value Px (x=2, 3, 4, 5) (stored in the memory 130). For example, P2=0T, P3=3T, P4=6T and P5=9T; In this way, the calculation circuit 120 of the control chips 220, 230, 240 and 250 waits for 0T, 3T, 6T and 9T respectively after receiving the write command CMD_W (time point t1) before starting to receive data (that is, at the time point respectively). t1, t2, t3 and t4 start to receive data DAT_210_220, data DAT_210_230, data DAT_210_240 and data DAT_210_250). In some embodiments, the target value Px can be the number of the control chip (eg, P2=2, P3=3, P4=4, and P5=5), and each control chip can know the waiting time according to the number and the length of the data. Time (eg, time to wait = (Px-2)*3T).

5 shows the timing arrangement of read commands and data in the read operation of the control circuit 208 , FIG. 6A shows the flow chart of the read operation of the control chip 210 , and FIG. 6B shows the flow of the read operation of the control chips 220 to 250 . picture.

The computing circuit 120 of the control chip 210 transmits the clock CLK through the clock output pin CLK_TX1 (step S610 ), and transmits the read command CMD_R (time point t0 ) through the main data pin DAT_TX1 according to the clock CLK (step S620 ).

The calculation circuit 120 of the control chips 220, 230, 240 and 250 receives the clock CLK through the clock input pins CLK_RX2, CLK_RX3, CLK_RX4 and CLK_RX5 respectively (step S660), and respectively through the secondary data pins DAT_RX2, DAT_RX3, DAT_RX4 and DAT_RX5 Receive the read command CMD_R (step S670 ), and transmit data through the secondary data pins DAT_RX2 , DAT_RX3 , DAT_RX4 and DAT_RX5 respectively according to the clock CLK and the target value Px (step S680 ). For example, as shown in FIG. 5 , after receiving the read command CMD_R, the computing circuit 120 of the control chip 220 waits for P2=0T before transmitting the data DAT_220_210 (ie, starts to transmit at the time point t1 ), and the computing circuit of the control chip 230 120 waits for P3=3T to transmit the data DAT_230_210 after receiving the read command CMD_R (ie, starts to transmit at time t2), and the calculation circuit 120 of the control chip 240 waits for P4=6T to transmit the data after receiving the read command CMD_R DAT_240_210 (ie, Transmission starts at time t3 ), the computing circuit 120 of the control chip 250 waits for P5 = 9T to transmit the data DAT_250_210 after receiving the read command CMD_R (ie, starts transmission at time t4 ). In some embodiments, the data DAT_220_210, the data DAT_230_210, the data DAT_240_210 and the data DAT_250_210 are the aforementioned characteristic values on the sensing circuit.

FIG. 7 shows a sensing panel and its control circuit according to another embodiment of the present invention. The sensing panel 700 includes a sensing circuit 701 , a sensing circuit 702 , a sensing circuit 703 , a sensing circuit 704 , a sensing circuit 705 and a control circuit 708 . The control circuit 708 includes five control chips including a control chip 710 , a control chip 720 , a control chip 730 , a control chip 740 , and a control chip 750 . Each control chip detects a designated area of the sensing panel through the sensing circuit; for example, the control chips 710, 720, 730, 740 and 750 (coupled or electrically connected to the sensing circuits 701, 702, 703, 704 and 705, respectively) ) respectively detect a certain area of the sensing panel 700 through the sensing circuits 701 , 702 , 703 , 704 and 705 . The control chips 710 , 720 , 730 , 740 and 750 can all be implemented with the control chip 100 .

The clock output pin CLK_TX1 of the control chip 710 is coupled or electrically connected to the clock input pin CLK_RX2 of the control chip 720 , and the clock output pin CLK_TX2 of the control chip 720 is coupled or electrically connected to the clock input pin of the control chip 730 CLK_RX3, the clock output pin CLK_TX3 of the control chip 730 are coupled or electrically connected to the clock input pin CLK_RX4 of the control chip 740, and the clock output pin CLK_TX4 of the control chip 740 is coupled or electrically connected to the clock of the control chip 750 Input pin CLK_RX5. That is, the control chips 710 to 750 transmit the clock CLK in series. In some embodiments, the clock CLK may be generated by an oscillator (not shown) on the control circuit 708, and the control chip 710 receives the clock CLK through the clock input pin CLK_RX1.

The main data pin DAT_TX1 of the control chip 710 is coupled or electrically connected to the secondary data pin DAT_RX2 of the control chip 720 , and the main data pin DAT_TX2 of the control chip 720 is coupled to Or electrically connected to the secondary data pin DAT_RX3 of the control chip 730 , the main data pin DAT_TX3 of the control chip 730 is coupled to or electrically connected to the secondary data pin DAT_RX4 of the control chip 740 , and the main data pin DAT_TX4 of the control chip 740 is coupled It is connected or electrically connected to the secondary data pin DAT_RX5 of the control chip 750 . That is, the control chips 710-750 transmit and receive data in a serial manner. More specifically, the control chip 710 can transmit data to and receive data from the control chip 720; the control chip 720 can transmit data to and receive data from the control chip 730; and so on. In some embodiments, the control chip 710 can transmit data to other devices through the secondary data pin DAT_RX1.

The write operations (FIGS. 8, 9A, and 9B) and read operations (FIGS. 10, 11A, and 11B) of the control circuit 708 are discussed below.

8 shows the timing arrangement of write commands and data in the write operation of the control circuit 708 , FIG. 9A shows the flow chart of the write operation of the control chip 710 , and FIG. 9B shows the flow chart of the write operation of the control chips 720 to 740 . picture.

The computing circuit 120 of the control chip 710 transmits the clock CLK through the clock output pin CLK_TX1 (step S910 ), and sequentially transmits the write command CMD_W (time point t0 ), the data DAT_710_750 ( Time point t3), data DAT_710_740 (time point t6), data DAT_710_730 (time point t9), and data DAT_710_720 (time point t12) (step S920).

The computing circuit 120 of the control chip 720 receives the write command CMD_W through the secondary data pin DAT_RX2 from the time point t0, and starts to transmit the write command CMD_W through the main data pin DAT_TX2 in the next cycle (starting from the time point t1). After the control chip 720 receives and processes the write command CMD_W (that is, after knowing that the command is a write command, time point t3), the control chip 720 The calculation circuit 120 of the slice 720 receives the data DAT_710_720 according to the clock CLK and the target value P2=9T. More specifically, the calculation circuit 120 of the control chip 720 starts to obtain the data DAT_710_720 after counting the time of 9T from the time point t3, and transmits the intermediate data (ie, the data DAT_710_750, the data DAT_710_740 and the data DAT_710_730) through the main data pin DAT_TX2 Transfer to the next stage of the control wafer (ie, control wafer 730).

Similarly, the computing circuit 120 of the control chip 730 starts to transmit the write command CMD_W through the main data pin DAT_TX3 at the time point t2. After the control chip 730 receives and processes the write command CMD_W (ie, after learning that the command is a write command at the time point t4 ), the calculation circuit 120 of the control chip 730 transmits the intermediate data (ie, the data DAT_710_750 and the data DAT_710_740 ) through the The main data pin DAT_TX3 is transmitted to the next-level control chip (ie, the control chip 740 ), and starts to obtain the data DAT_710_730 at the time point t10 (ie, t4+6T (6T is the target value P3 of the control chip 730 )).

Similarly, the computing circuit 120 of the control chip 740 starts to transmit the write command CMD_W through the main data pin DAT_TX4 at the time point t3. After the control chip 740 receives and processes the write command CMD_W (ie, after learning that the command is a write command at the time point t5), the calculation circuit 120 of the control chip 740 transfers the intermediate data (ie, the data DAT_710_750) through the main data connection The pin DAT_TX4 is transmitted to the next-level control chip (ie, the control chip 750 ), and starts to obtain the data DAT_710_740 at the time point t8 (ie, t5+3T (3T is the target value P4 of the control chip 740 )).

Because the control wafer 750 is the last control wafer, the control wafer 750 does not need to transmit the write command CMD_W. After the control chip 750 receives and processes the write command CMD_W (ie, after learning that the command is a write command at the time point t6 ), the calculation circuit 120 of the control chip 750 at the time point t6 (ie, t6 + OT ( OT is the control chip The target value of 750 P5)) began to obtain data DAT_710_740.

Based on the above discussion, the operation of the control wafers 720, 730, and 740 can be represented by the flowchart of FIG. 9B, including the following steps.

Step S960: The calculation circuit 120 of the control chips 720, 730 and 740 receives the clock CLK through the clock input pins CLK_RX2, CLK_RX3, CLK_RX4 and CLK_RX5, respectively.

Step S970: The computing circuit 120 of the control chips 720, 730 and 740 receives the write command CMD_W, the first data and the second data through the secondary data pins DAT_RX2, DAT_RX3 and DAT_RX4, respectively. For the control chip 720, the first data includes data DAT_710_750, data DAT_710_740 and data DAT_710_730, and the second data includes data DAT_710_720. For the control chip 730, the first data includes data DAT_710_750 and DAT_710_740, and the second data includes data DAT_710_730. For the control chip 740, the first data includes data DAT_710_750, and the second data includes data DAT_710_740.

Step S980: The computing circuit 120 of the control chips 720, 730 and 740 transmits the write command CMD_W and the first data through the main data pins DAT_TX2, DAT_TX3 and DAT_TX4, respectively.

Step S990: The calculation circuit 120 of the control chips 720, 730 and 740 obtains the second data according to the clock CLK and the target values P2, P3 and P4, respectively. In some embodiments, the computing circuit 120 of the control chips 720 , 730 and 740 stores the second data in the memory 130 .

10 shows the timing arrangement of read commands and data in the read operation of the control circuit 708 , FIG. 11A shows the flow chart of the read operation of the control chip 710 , and FIG. 11B shows the flow of the read operation of the control chips 720 to 740 . picture.

The calculation circuit 120 of the control chip 710 transmits through the clock output pin CLK_TX1 The clock CLK (step S1110 ), and the read command CMD_R (time point t0 ) is transmitted through the main data pin DAT_TX1 according to the clock CLK (step S1120 ).

The computing circuit 120 of the control chip 720 starts to receive the read command CMD_R through the secondary data pin DAT_RX2 at the time point t0, and starts to transmit the read command CMD_R through the main data pin DAT_TX2 at the time point t1. The computing circuit 120 of the control chip 730 starts to receive the read command CMD_R through the secondary data pin DAT_RX3 at the time point t1, and starts to transmit the read command CMD_R through the main data pin DAT_TX3 at the time point t2. The computing circuit 120 of the control chip 740 starts to receive the read command CMD_R through the secondary data pin DAT_RX4 at the time point t2, and starts to transmit the read command CMD_R through the main data pin DAT_TX4 at the time point t3. The computing circuit 120 of the control chip 750 starts to receive the read command CMD_R through the secondary data pin DAT_RX5 at the time point t3. Since the control wafer 750 is the last control wafer, the control wafer 750 does not need to transmit the read command CMD_R.

After the control chip 750 receives and processes the read command CMD_R (ie, after learning that the command is a read command at the time point t6 ), the calculation circuit 120 of the control chip 750 at the time point t6 (ie, t6 + 0T (0T is the control chip The target value of 750 P5)) starts to transmit data DAT_750_710 through the secondary data pin DAT_RX5.

The computing circuit 120 of the control chip 740 starts to receive the data DAT_750_710 through the primary data pin DAT_TX4 at the time point t6, starts to transmit the data DAT_750_710 through the secondary data pin DAT_RX4 at the time point t7, and starts at the time point t10 (ie t7+3T(3T For the target value P4)) of the control chip 740, the data DAT_740_710 starts to be transmitted through the secondary data pin DAT_RX4.

The computing circuit 120 of the control chip 730 starts to pass through the main data pins at time t7 DAT_TX3 receives data DAT_750_710 and data DAT_740_710 in sequence, starts to transmit data DAT_750_710 and data DAT_740_710 sequentially through secondary data pin DAT_RX3 at time point t8, and at time point t14 (ie t8+6T (6T is the target value of control chip 730) P3)) starts to transmit data DAT_730_710 through the secondary data pin DAT_RX3.

The computing circuit 120 of the control chip 720 starts to receive the data DAT_750_710, the data DAT_740_710 and the data DAT_730_710 through the main data pin DAT_TX2 at the time point t8, and sequentially transmits the data DAT_750_710 and the data DAT_740_710 through the secondary data pin DAT_RX2 at the time point t9. and the data DAT_730_710, and the data DAT_720_710 is transmitted through the secondary data pin DAT_RX2 at the time point t18 (ie, t9+9T (9T is the target value P2 of the control chip 720 )).

Based on the above discussion, the operation of the control wafers 720, 730, and 740 can be represented by the flowchart of FIG. 11B, including the following steps.

Step S1160: The calculation circuit 120 of the control chip 720 (730 or 740) receives the clock CLK through the clock input pin CLK_RX2 (CLK_RX3 or CLK_RX4).

Step S1170: The computing circuit 120 of the control chip 720 (730 or 740) receives the read command CMD_R through the secondary data pin DAT_RX2 (DAT_RX3 or DAT_RX4).

Step S1180: The computing circuit 120 of the control chip 720 (730 or 740) transmits the read command CMD_R through the main data pin DAT_TX2 (DAT_TX3 or DAT_TX4).

Step S1190: The computing circuit 120 of the control chip 720 (730 or 740) receives the first data through the main data pin DAT_TX2 (DAT_TX3 or DAT_TX4). For the control chip 740, the first data includes data DAT_750_710. For the control chip 730, the first data includes data DAT_750_710 and data DAT_740_710. For the control chip 720, the first data Contains data DAT_750_710, data DAT_740_710 and data DAT_730_710.

Step S1195: The computing circuit 120 of the control chip 720 (730 or 740) transmits the first data and the second data through the secondary data pin DAT_RX2 (DAT_RX3 or DAT_RX4). For the control chip 740, the second data includes data DAT_740_710. For the control chip 730, the second data includes data DAT_730_710. For the control chip 720, the second data includes data DAT_720_710.

In some embodiments, the data received by the control wafer 210 and the control wafer 710 may include the coordinates of the position of the contact/non-contact operation, which coordinates are obtained by other control wafers (eg, 220, 230, 240, 250, 720). , 730, 740 or 750) are calculated from the measured eigenvalues.

In the embodiment of FIG. 2, the control chips are connected in parallel, while in the embodiment of FIG. 7, the control chips are connected in series. Other embodiments may be combined with the embodiments of FIG. 2 and FIG. 7 . FIG. 12 shows a sensing panel and its control circuit according to another embodiment of the present invention. The control circuit 1208 of the sensing panel 1200 includes a control chip 1210, a control chip 1220, a control chip 1230, a control chip 1240, a control chip 1250, a control chip 1260, a control chip 1270, a control chip 1280, a control chip 1290, a control chip 1291 and a control chip 11 control wafers such as 1292. For the sake of brevity, the pins of the control chip are omitted in FIG. 12 and only data connections (ie, clock connections are omitted) are shown. The control chips 1210, 1220, 1230, 1240 and 1250 are connected in parallel; the control chips 1220, 1260, 1270 and 1280 are connected in series; the control chips 1250, 1290, 1291 and 1292 are connected in series. As long as the target value Px is pre-specified for each control chip, each control chip can operate according to the flowcharts of FIGS. 4A-4B, 6A-6B, 9A-9B, and 11A-11B. Because of the combination of series and parallel, the control circuit 1208 is more flexible in layout and can be more easily applied to sensing panels of various sizes.

To sum up, based on the customized communication specification (refer to the timing diagrams of FIG. 3, FIG. 5, FIG. 8 and FIG. 10, and FIG. 4A, FIG. 4B, FIG. 11B is the flow chart) The control chip of the present invention can be dynamically set to master mode according to software or firmware (transmitting and receiving data through the main data pin DAT_TX, such as the aforementioned control chips 210, 710, 720, 730 and 740) or slave mode (transmitting and receiving data through the secondary data pin DAT_RX, such as the aforementioned control chips 220, 230, 240, 250, 720, 730, 740 and 750). Note that the control chips 720, 730 and 740 switch between master mode and slave mode. Furthermore, since each sensing chip can execute a sensing algorithm, even if the size of the sensing panel increases, the computing requirement of a certain control chip will not be increased. That is to say, the control circuit proposed by the present invention is a distributed and/or decentralized structure, which not only helps to simplify the complexity of the wiring and makes the circuit layout more flexible, but also does not cause the operation of a single chip. Overburdened.

Since a person with ordinary knowledge in the technical field can understand the implementation details and changes of the method invention in this application through the disclosure content of the device invention in this application, in order to avoid redundant repetition, the disclosure requirements and practicability of the method invention are not affected. On the premise, repeated explanations are omitted here. Please note that the shapes, sizes and ratios of the components in the preceding figures are only schematic representations, which are for those skilled in the art to understand the present invention, and are not intended to limit the present invention. In addition, in some embodiments, the steps mentioned in the aforementioned flowcharts can be adjusted in their sequence according to the actual operation, and can even be executed simultaneously or partially simultaneously.

Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. Those skilled in the art can change the technical features of the present invention according to the explicit or implicit contents of the present invention. All such changes may belong to the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope of the patent application in this specification.

200: Induction panel

201, 202, 203, 204, 205: Induction circuits

208: Control circuit

210, 220, 230, 240, 250: Control chip

CLK_TX, CLK_TX1, CLK_TX2, CLK_TX3, CLK_TX4: Clock output pins

CLK_RX, CLK_RX1, CLK_RX2, CLK_RX3, CLK_RX4, CLK_RX5: Clock input pins

DAT_TX, DAT_TX1, DAT_TX2, DAT_TX3, DAT_TX4: Main data pins

DAT_RX, DAT_RX1, DAT_RX2, DAT_RX3, DAT_RX4, DAT_RX5: Secondary data pins

Claims (13)

A control chip of an induction panel, the induction panel includes an induction circuit, and the control chip includes: A clock input pin; a first data pin; a detection circuit, coupled to the induction circuit, for detecting a characteristic value on the induction circuit; a memory that stores a plurality of code or program instructions; and A computing circuit, coupled to the clock input pin, the first data pin, the detection circuit and the memory, is used for executing the program codes or program instructions to perform the following steps: Receive a clock through the clock input pin; receiving a command through the first data pin; and transmit the characteristic value through the first data pin according to the clock and a target value; The target value determines a time point when the control chip transmits the characteristic value. As claimed in claim 1, the control chip further comprises a second data pin, which is coupled to the computing circuit, and the computing circuit further performs the following steps: The command is sent through the second data pin. The control chip of claim 2, wherein the characteristic value is a first characteristic value, and the calculation circuit further performs the following steps: receiving a second characteristic value through the second data pin; and The second characteristic value is transmitted through the first data pin. A control circuit of an induction panel, comprising: a first control chip, comprising a first clock input pin, a first clock output pin, a first main data pin and a first secondary data pin for transmitting the first clock The output pin transmits a clock, and transmits a command through the first main data pin; a second control chip, comprising: a second clock input pin coupled to the first clock output pin for receiving the clock; and a second secondary data pin coupled to the first primary data pin for receiving the command; and a third control chip, comprising: a third clock input pin coupled to the first clock output pin for receiving the clock; and a third secondary data pin coupled to the first primary data pin for receiving the command; The second control chip transmits or receives a first data according to the clock and a first target value after receiving the command, and the third control chip sends or receives a first data according to the clock and a second after receiving the command The target value transmits or receives a second data, and the first target value is not equal to the second target value. The control circuit of claim 4, wherein the command is a write command, the first control chip transmits the first data and the second data through the first main data pin, and the second control chip receives the After the write command, wait for N cycles of the clock and then receive the first data through the second secondary data pin, where N is an integer greater than or equal to zero. The control circuit of claim 5, wherein the second target value is greater than the first target value, and the first control chip transmits the first data first and then transmits the second data. The control circuit of claim 4, wherein the command is a read command, the second control chip waits for N cycles of the clock after receiving the read command, and then transmits the first through the second secondary data pin a data, and the first control chip receives the first data through the first main data pin, and N is an integer greater than or equal to zero. The control circuit of claim 7, wherein the second target value is greater than the first target value, and the first control chip receives the first data first and then the second data through the first main data pin. A control circuit of an induction panel, comprising: a first control chip, comprising a first clock input pin, a first clock output pin, a first main data pin and a first secondary data pin for transmitting the first clock The output pin transmits a clock, and transmits a command through the first main data pin; a second control chip, comprising: a second clock input pin coupled to the first clock output pin for receiving the clock; a second clock output pin for transmitting the clock; a second secondary data pin coupled to the first primary data pin for receiving the command; and a second main data pin for transmitting the command; and a third control chip, comprising: a third clock input pin coupled to the second clock output pin for receiving the clock; and A third secondary data pin is coupled to the second primary data pin for receiving the command. The control circuit of claim 9, wherein the command is a write command, the first control chip outputs a first data and a second data through the first main data pin, the second control chip outputs a first data and a second data through the second control chip The secondary data pin receives the first data and the second data, and obtains the first data according to the clock, the second control chip transmits the second data through the second main data pin, and the third data The control chip receives the second data through the third secondary data pin. The control circuit of claim 10, wherein the first control chip transmits the second data first and then transmits the first data. The control circuit of claim 9, wherein the command is a read command, the third control chip generates a first data according to the read command, and the third control chip generates the first data through the third secondary data pin A data is sent to the second control chip, the second control chip generates a second data according to the read command, and the second control chip receives the first data through the second main data pin, and through the second control chip The secondary data pin transmits the first data and the second data to the first control chip. The control circuit of claim 12, wherein the second control chip transmits the first data first and then transmits the second data.

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