TWI769056B - Storage device and data accessing method using multi-level cell - Google Patents

Abstract

A storage device and a data accessing method are disclosed, wherein the storage device includes a memory circuit and a control circuit. The memory circuit includes a plurality of multi-level cells, and each of the multi-level cells is configured to store at least a first bit, a second bit and a third bit in at least a first page, a second page and a third page. The control circuit is configured to read the first bits according to a one-time reading operation related to the first bits, read the second bits according to M-times reading operations related to the second bits, and read the third bits according to N-times reading operations related to the third bits, wherein the difference between M and N is less than or equal to one.

Description

Storage device and data access method using multi-level memory cells

The present disclosure relates to a storage device and a data access method, and more particularly, to a storage device and data access method using multi-level memory cells.

With the evolution of semiconductor technology, memory structures with multi-level cells (MLCs) have been widely used. The multi-level memory cell is used as the storage unit of the memory, and each multi-level memory cell can store multi-bit data, so it can greatly increase the storage capacity of the memory.

However, due to the multi-bit characteristics of the multi-level memory cells, when reading each bit of the multi-level memory cells, multiple read operations may be required to apply read voltages in different voltage ranges. The more reading operations required, the easier it is to cause data reading errors. Therefore, under the condition that the number of read operations of the multi-level memory cells is relatively large, an error correction mechanism (eg, encoding with an error correction code (ECC)) is also required to correct possible data read errors. When the number of read operations is too many and a more complex error correction code must be used, the amount of additional data added after encoding will be greatly increased, resulting in a decrease in data storage efficiency of the memory.

From the above, how to minimize the number of read operations of multi-level memory cells, so as to simplify the error correction mechanism of the stored data of the multi-level memory cells, so as to reduce the amount of extra data added by the error correction mechanism, is a subject in the technical field. Important issues that related industries are working on.

An embodiment of the present disclosure provides a storage device including a memory circuit and a control circuit. The memory circuit includes a plurality of multi-level memory cells, and each multi-level memory cell is used for storing at least a first bit and a second bit in at least a first page, a second page, and a third page , and a third bit. The control circuit is configured to read the first bit according to one read operation related to the first bit, read the second bit according to M times of read operations related to the second bit, and read the second bit according to M times of read operations related to the second bit. The third bit is read by N read operations of three bits, wherein the difference between M and N is less than or equal to 1.

Another embodiment of the present disclosure provides a data access method applied to a memory circuit including a plurality of multi-level memory cells, each of which is used for at least a first page, a second page, And a third page stores at least a first bit, a second bit, and a third bit, the data access method includes the following steps. A plurality of multi-bit data are stored in the first bit, the second bit and the third bit of the multi-level memory cell, the first bit corresponds to the first page, the second bit corresponds to the second page, and the first bit corresponds to the second page. The three digits correspond to the third page. The first cell is read according to a read operation associated with the first cell of the multi-level memory cell. The second bit is read according to M read operations associated with the second bit of the multi-level memory cell. And, the third bit is read according to N times of read operations related to the third bit of the multi-level memory cell, wherein the difference between M and N is less than or equal to 1.

Other aspects and advantages of the present invention will become apparent upon reading the following drawings, detailed description, and claims.

The technical terms in this specification refer to the common terms in the technical field. If some terms are described or defined in this specification, the interpretation of this part of the terms is subject to the descriptions or definitions in this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, those skilled in the art can selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

FIG. 1 is a block diagram of a storage device 100 according to a first embodiment of the present disclosure. Referring to FIG. 1 , the storage device 100 of the first embodiment includes a memory circuit 102 and a control circuit 104 . The memory circuit 102 includes a plurality of multi-level memory cells, and each multi-level memory cell is used to store at least one first bit B1 in at least a first page, a second page, and a third page respectively , a second bit B2, and a third bit B3. The first page is a low page, the second page is a middle page, and the third page is a high page.

In addition, the control circuit 104 is configured to read the first bit B1 according to one read operation related to the first bit B1 of the multi-level memory cells, and read the first bit B1 according to M times of read operations related to the second bit B2 The second bit B2 is taken, and the third bit B3 is read according to N read operations related to the third bit B3, where the difference between M and N is less than or equal to one. One of the technical effects of the technical solution of the present disclosure is that the read times M of the second bit B2 and the read times N of the third bit B3 are evenly distributed, so that the read times of the second bit B2 and the third bit B3 are evenly distributed. The fetch times M is the same as or close to N, which can prevent the read times of a certain bit (or several bits) of the multi-level memory cell from increasing too much, which leads to an increase in the read error rate of these bits.

In the first embodiment of the present disclosure, the multi-level memory cell line is a triple-level memory cell (TLC), and each third-level memory cell has three bits, which are the first bit B1, the third bit Two bits B2 and third bits B3. The first to third bits B1~B3 are stored in the first to third pages respectively, and are used to store a three-bit data (b1 b2 b3) ₂ , where b1 is the binary logic value of the first bit B1, b2 is the binary logic value of the second bit B2, and b3 is the binary logic value of the third bit B3. The third-order memory cells storing three-bit data (b1 b2 b3) ₂ with different logic values have different threshold voltage distributions, for example, the third-order memory cells storing three-bit data (0 0 0) ₂ have a threshold voltage distribution Vt (0,0,0), the third-order memory cell storing three-bit data (0 0 1) ₂ has a threshold voltage distribution Vt(0,0,1). The three-bit metadata for different logical values are (1 1 1) ₂ , (1 0 1) ₂ , (1 0 0) ₂ , (1 1 0) ₂ , (0 1 0) ₂ , (0 1 1) ₂ , (0 0 1) ₂ , or (0 0 0) ₂ corresponding to the threshold voltage distributions Vt(1,1,1), Vt(1,0,1), Vt(1,0,0), Vt(1,1,0), Vt(0,1,0), Vt(0,1,1), Vt(0,0,1), and Vt(0,0,0). Among them, the threshold voltage distribution Vt(1,1,1), Vt(1,0,1), Vt(1,0,0), Vt(1,1,0), Vt(0,1,0), Vt(0,1,1), Vt(0,0,1), and Vt(0,0,0) are arranged in order from low voltage to high voltage.

More specifically, the memory circuit 102 can be various types of two-dimensional memory, such as: two-dimensional NAND flash memory (2D NAND flash memory), two-dimensional phase change memory (2D Phase Change Memory, 2D memory) PCM), two-dimensional resistive random access memory (2D Resistive Random Access Memory, 2D RRAM), or two-dimensional magnetoresistive random access memory (2D Magnetoresistive Random Access Memory, 2D MRAM). The memory circuit 102 can also be various types of three-dimensional memory, such as: three-dimensional NAND flash memory (3D NAND flash memory), three-dimensional phase-change memory (3D PCM), three-dimensional resistive random access memory ( 3D RRAM), or three-dimensional magnetoresistive random access memory (3D MRAM). The memory circuit 102 includes a plurality of multi-level cells (MLCs), each multi-level memory cell has a plurality of bits, and the multi-level memory cells may be two-dimensional memory cells or three-dimensional memory cells.

On the other hand, the control circuit 104 is electrically connected to the memory circuit 102 . The control circuit 104 is used for performing a read operation to read the three-bit data ( b1 b2 b3 ) ₂ stored in the third-order memory cells in the memory circuit 102 . The control circuit 104 can apply read voltages Vr with different voltage values according to the threshold voltage distribution of the third-order memory cells to read the first bit B1 , the second bit B2 and the third bit B3 of the third-order memory cells, respectively. Details are described below.

2A to 2C are schematic diagrams of the threshold voltage distribution and the read voltage Vr of the third-order memory cells of the present disclosure. Referring first to FIG. 2A, the three-bit data (1 1 1) ₂ , (1 0 1) ₂ , (1 0 0) ₂ , (1) of different logic values stored in the third-order memory cells in the memory circuit 102 1 0) ₂ , (0 1 0) ₂ , (0 1 1) ₂ , (0 0 1) ₂ and (0 0 0) ₂ correspond to the threshold voltage distributions Vt(1,1,1), Vt(1, respectively ,0,1), Vt(1,0,0), Vt(1,1,0), Vt(0,1,0), Vt(0,1,1), Vt(0,0,1) and Vt(0,0,0) (ordered from low voltage to high voltage).

As shown in FIG. 2A, the voltage range R1 is between the threshold voltage distribution Vt(1, 1, 0) and the threshold voltage distribution Vt(0, 1, 0). When the read voltage Vr applied by the control circuit 104 to the third-order memory cells is set within the voltage range R1, there are threshold voltage distributions Vt(1,1,1), Vt(1,0,1), Vt(1, The threshold voltage Vt of the third-order memory cells of 0,0) or Vt(1,1,0) is smaller than the read voltage Vr, so there are threshold voltage distributions Vt(1,1,1), Vt(1,0,1 ), Vt(1,0,0) or the third-order memory cells of Vt(1,1,0) can be turned on, and the logic values stored in the memory cells can be read out through other circuits (such as sense amplifiers). The third-order memory cells that can be turned on store three-bit data (1 1 1) ₂ , (1 0 1) ₂ , (1 0 0) ₂ or (1 1 0) ₂ respectively, and these third-order memory cells that are turned on The logic value b1 of the first bit B1 of the memory cell is read as "1".

On the other hand, the threshold of a third-order memory cell with threshold voltage distribution Vt(0,1,0), Vt(0,1,1), Vt(0,0,1) or Vt(0,0,0) The voltages Vt are all greater than the read voltage Vr, so there is a threshold voltage distribution of Vt(0,1,0), Vt(0,1,1), Vt(0,0,1) or Vt(0,0,0) Third-order memory cells cannot be turned on. The third-order memory cells that cannot be turned on store three bits of metadata (0 1 0) ₂ , (0 1 1) ₂ , (0 0 1) ₂ or (0 0 0) ₂ respectively, and cannot be turned on. The logic value b1 of the first bit B1 of the third-order memory cells is determined to be "0".

From the above, when the read voltage Vr applied by the control circuit 104 is set to be within a voltage range R1, the first element B1 of the third-order memory cells with different threshold voltage distributions can be read as a logic value “1” or a judgment is the logical value "0". Therefore, the read operation related to the first cell B1 of the third-order memory cell is a read operation, and the read voltage Vr of this read operation is between the threshold voltage distribution Vt(1,1,0) and Vt (0,1,0).

Next, referring to FIG. 2B, the voltage range R2 is between the threshold voltage distribution Vt(1,1,1) and the threshold voltage distribution Vt(1,0,1), and the threshold voltage distribution Vt(1,0,0) and The voltage range R3 is between the threshold voltage distribution Vt(1,1,0), and the voltage range R4 is between the threshold voltage distribution Vt(0,1,1) and the threshold voltage distribution Vt(0,0,1).

For the third-order memory cells with the threshold voltage distribution Vt(1,1,1), the threshold voltages of the third-order memory cells are all smaller than the voltage value of the voltage range R2. When the read voltage Vr is set within the voltage range R2 (to be the read voltage Vr2 ), the read voltage Vr2 is greater than the threshold voltage of the third-order memory cells, so the third-order memory cells can be turned on by the read voltage Vr2 while reading. These third-order memory cells store three bits of data (1 1 1) ₂ , and the logic value b2 of the second bit B2 is "1". In other words, the read voltage Vr2 can read the logic value b2 of the second bit B2 stored in the third-order memory cell of the threshold voltage distribution Vt(1,1,1) as "1".

On the other hand, for the third-order memory cells of the threshold voltage distribution Vt(1,0,1) and the third-order memory cells of the threshold voltage distribution Vt(1,0,0), the threshold voltages of these third-order memory cells Both are greater than the voltage value of the voltage range R2, and are less than the voltage value of the voltage range R3. Therefore, these third-order memory cells cannot be turned on by the read voltage Vr2, and thus cannot be read. However, if the voltage value of the read voltage Vr is increased, and the read voltage Vr is set to be within the voltage range R3 (to be the read voltage Vr3), the third-order memory cells can be turned on by the read voltage Vr3 and can be read read, the logic value b2 of the second bit B2 stored in the third-order memory cells can be read as "0".

In other words, the third-order memory cells of the threshold voltage distributions Vt(1,0,1) and Vt(1,0,0) cannot be turned on by the read voltage Vr2, but can be turned on by the read voltage Vr3. Therefore, for the second bit B2 of these third-order memory cells, it is the intersection of the bit read by the read voltage Vr2 and the bit read by the read voltage Vr3. The logic value b2 of the second bit B2 of this intersection is "0".

On the other hand, for the third-order memory cells of the threshold voltage distributions Vt(1,1,0), Vt(0,1,0) and Vt(0,1,1), the thresholds of the third-order memory cells The voltages are all greater than the voltage value of the voltage range R3 and less than the voltage value of the voltage range R4. The read voltage Vr3 cannot turn on the third-order memory cells, but if the read voltage Vr is increased to within the voltage range R4 (to become the read voltage Vr4 ), the third-order memory cells can be turned on. That is to say, for the third-order memory cells of the threshold voltage distribution Vt(1,1,0), Vt(0,1,0) and Vt(0,1,1), the value read by the reading voltage Vr3 The intersection of the bit and the bit read by the read voltage Vr4 is the second bit B2, and the logic value b2 of the second bit B2 is "1".

In addition, for the third-order memory cells of the threshold voltage distribution Vt(0,0,1), Vt(0,0,0), the read voltage Vr4 cannot turn on these third-order memory cells, and these third-order memory cells The logic value b2 of the second bit B2 of the cell is judged to be "0".

From the above, if the control circuit 104 reads the second bit B2 of the third-order memory cell, the read voltage Vr is set to be located in the three voltage ranges R2, R3, and R4 in sequence (the read voltage Vr2, R3, and R4). Vr3, Vr4), and sequentially read or determine the second bit B2 of the third-order memory cells with different threshold voltage distributions as a logic value "1" or a logic value "0". Therefore, the read operation related to the second bit B2 of the third-order memory cell is three read operations. The read voltages Vr of the three read operations are respectively set to be between the threshold voltage distributions Vt(1,1,1) and Vt(1,0,1) and between the threshold voltage distributions Vt(1,0 ,0) and Vt(1,1,0), and between the threshold voltage distributions Vt(0,1,1) and Vt(0,0,1).

Similar to the reading method of the second bit B2, please refer to FIG. 2C for the reading method of the third bit B3. The voltage range R5 is between the threshold voltage distribution Vt(1,0,1) and Vt(1,0,0), and the threshold voltage distribution between Vt(0,1,0) and Vt(0,1,1) It is the voltage range R6, and the threshold voltage distribution between Vt(0,0,1) and Vt(0,0,0) is the voltage range R7. The control circuit 104 sequentially sets the read voltage Vr to be within the three voltage ranges R5, R6, R7, and sequentially reads or determines the third bit B3 of the third-order memory cells with different threshold voltage distributions as a logic value "1" or logical value "0". Therefore, the read operation related to the third bit B3 is also three read operations, and the read voltages Vr of these three read operations are respectively set to be between the threshold voltage distributions Vt(1,0,1) and Vt (1,0,0), between the threshold voltage distributions Vt(0,1,0) and Vt(0,1,1), and between the threshold voltage distributions Vt(0,0,1) and Between Vt(0,0,0).

To sum up, for the first bit B1 of the third-order memory cell, the read voltage Vr is set within a voltage range R1 to perform a read operation; for the second bit B2, the read voltage Vr is set to be within a voltage range R1. The voltage Vr is set to be located in the three voltage ranges R2, R3, R4 in sequence to perform three read operations; for the third bit B3, the read voltage Vr is set to be located in the three voltage ranges R5 in sequence , R6, R7 to perform three read operations. From the above, the configuration of the threshold voltage distribution and the read voltage Vr of the third-order memory cells in the first embodiment is a "1-3-3 configuration", wherein the number of read times of the first cell B1 is one. In addition, the read times of the second bit B2 and the third bit B3 are evenly distributed, so that the read times of the second bit B2 and the third bit B3 are the same or close to each other. In the "1-3-3 configuration" of the first embodiment, the read times of the second bit B2 and the third bit B3 are both three times.

In the "1-3-3 configuration", the read times of the second bit B2 and the third bit B3 are evenly distributed, which can prevent the read error rate from increasing due to excessive read times of a certain bit. For example, in a comparative example, four read operations are required for the third bit B3 of the third-order memory cell of the "1-2-4 configuration", so that the third bit of the "1-2-4 configuration" The B3 read error rate increases, so the stored data in the "1-2-4 configuration" must be protected with a more complex error correction mechanism. For example, for the error correction code used to encode the stored data of "1-2-4 configuration", it is necessary to insert more parity bits outside the stored data, resulting in the additional parity bits inserted outside the stored data. The amount of additional data (overhead) increases, resulting in a loss of data storage efficiency.

FIG. 3 and FIG. 4 are schematic diagrams illustrating an example of the application of the storage device 100 according to the first embodiment of the present disclosure. Referring first to FIG. 3, the storage device 100 having a third-order memory cell in a "1-3-3 configuration" can be used to store weight data 302 and normal data 304, wherein the weight data 302 can be applied to multiply-add (Multiply and Accumulate, MAC) operations, such as bit-wise multiply-add operations. The weight data 302 of the bitwise multiply-add operation has a single-bit data format, so the weight data 302 is stored in the first bit B1 (corresponding to the lower page) of the third-order memory cell of the "1-3-3 configuration" ); on the other hand, the general data 304 is general data or general data stored in the memory circuit 102 , and the general data 304 is not limited to a specific purpose. In this embodiment, the normal data 304 is other general data or normal data other than the weight data 302 . In other words, the normal data 304 does not include the weight data 302 used for the multiplication and addition operations, and the normal data 304 is not limited to be used for the multiplication and addition operations. Normally data 304 is stored in the second bit B2 (corresponding to the middle page) and the third bit B3 (corresponding to the upper page) of the third-level memory cell. The first cell B1 of the third-order memory cell of the "1-3-3 configuration" of the present disclosure only needs to perform one read operation, so it is suitable for storing data of any type of bitwise operations. In contrast, in the “2-3-2 configuration” of a comparative example, the first bit B1 needs to be read twice, so the third-order memory cell of the “2-3-2 configuration” cannot be used for storing Bitwise operation data.

Next, referring to FIG. 4 , before the weight data 402 is stored in the first bit B1 of the third-order memory cell, the weight data 402 can be encoded through the error correction code, and the data fields W1 and W2 of the weight data 402 are encoded. , W3, W4. ． . After that, a plurality of parity bits P are inserted. When applied to the bitwise multiply-add operation, the data format of the normal data 404 and the weight data 402 must be the same, and the normal data 404 is correspondingly extended to the data fields N1 , N2 , N3 of the normal data 404 , N4. . . Afterwards, padding bits (such as bits with logical value "0") are placed to correspond to the parity bits P of the weight data 402.

In the above-mentioned first embodiment, the multi-level memory cell is a third-level memory cell, while the multi-level memory cell of the second embodiment of the present disclosure is a quad-level memory cell (Quad-Level Cell, QLC). Each fourth-level memory cell has four bits, which are the first bit B1, the second bit B2, the third bit B3 and the fourth bit B4 to store the four-bit data (b1 b2 b3 b4) ₂ , the four-bit data (b1 b2 b3 b4) ₂ of different logical values are (1 1 1 1) ₂ , (1 1 1 0) ₂ , (1 1 0 0) ₂ , (1 0 0 0) ₂ , (1 0 1 0) ₂ , (1 0 1 1) ₂ , (1 0 0 1) ₂ , (1 1 0 1) ₂ , (0 1 0 1) ₂ , (0 0 0 1) ₂ , (0 0 0 0) ₂ , (0 0 1 0) ₂ , (0 0 1 1) ₂ , (0 1 1 1) ₂ , (0 1 1 0) ₂ or (0 1 0 0) ₂ and corresponding to different The threshold voltage distribution of , from low voltage to high voltage is the threshold voltage distribution Vt(1,1,1,1), Vt(1,1,1,0), Vt(1,1,0,0), Vt (1,0,0,0), Vt(1,0,1,0), Vt(1,0,1,1), Vt(1,0,0,1), Vt(1,1,0 ,1), Vt(0,1,0,1), Vt(0,0,0,1), Vt(0,0,0,0), Vt(0,0,1,0), Vt( 0,0,1,1), Vt(0,1,1,1), Vt(0,1,1,0) and Vt(0,1,0,0). According to the above threshold voltage distribution, the control circuit 104 applies the read voltage Vr with different voltage values to read the four-bit data (b1 b2 b3 b4) ₂ stored in the fourth-order memory cells, as described in detail below.

FIGS. 5A to 5E are schematic diagrams of the threshold voltage distribution and the read voltage Vr of the fourth-order memory cell of the present disclosure. Referring first to FIG. 5A, for the read operation of the first bit B1 of the fourth-order memory cell , there is a voltage range R1 between the threshold voltage distribution Vt(1,1,0,1) and Vt(0,1,0,1); when the read voltage Vr applied by the control circuit 104 is set to be within the voltage range R1, Then there are critical voltage distributions Vt(1,1,1,1), Vt(1,1,1,0), Vt(1,1,0,0), Vt(1,0,0,0), Vt (1,0,1,0), Vt(1,0,1,1), Vt(1,0,0,1), Vt(1,1,0,1) threshold voltage of fourth-order memory cells Vt is smaller than the read voltage Vr, these fourth-order memory cells can be turned on, and the logic value "1" of the first element B1 is read out. On the other hand, there are threshold voltage distributions Vt(0,1,0,1), Vt(0,0,0,1), Vt(0,0,0,0), Vt(0,0,1,0 ), Vt(0,0,1,1), Vt(0,1,1,1), Vt(0,1,1,0) and fourth-order memory cells of Vt(0,1,0,0) The first cell B1 of the fourth-order memory cells that cannot be turned on is judged to be a logic value "0". Since the read voltage Vr is set within a voltage range R1, the read operation related to the first cell B1 of the fourth-order memory cell is a read operation.

For the read operation of the second bit B2 of the fourth-order memory cell, see Fig. 5B, between the threshold voltage distributions Vt(1,1,0,0) and Vt(1,0,0,0) is the voltage range R2, between the threshold voltage distribution Vt(1,0,0,1) and Vt(1,1,0,1) is the voltage range R3, the threshold voltage distribution Vt(0,1,0 ,,1) and Vt(0,0,0,1) is the voltage range R4, between the threshold voltage distribution Vt(0,0,1,1) and Vt(0,1,1,1) is the voltage range R5. When the read voltage Vr applied by the control circuit 104 is set to be within the four voltage ranges R2, R3, R4, and R5 in sequence, the second bit B2 of the fourth-order memory cells with different threshold voltage distributions can be sequentially determined as Logical value "1" or logical value "0". Therefore, the read operation related to the second bit B2 of the fourth-order memory cell is four read operations.

Similarly, referring to Figure 5C, for the read operation of the third bit B3 of the fourth-order memory cell, the threshold voltage distributions Vt(1,1,1,0) and Vt(1,1,0,0 ) is the voltage range R6, between the threshold voltage distribution Vt(1,0,0,0) and Vt(1,0,1,0) is the voltage range R7, the threshold voltage distribution Vt(1, The voltage range R8 is between 0,1,1) and Vt(1,0,0,1), and the threshold voltage distribution Vt(0,0,0,0) and Vt(0,0,1,0) The voltage range R9 is between them, and the voltage range R10 is between the threshold voltage distributions Vt(0,1,1,0) and Vt(0,1,0,0). When the read voltage Vr applied by the control circuit 104 is sequentially set to be within the five voltage ranges R6, R7, R8, R9, and R10, the third bits B3 of the fourth-order memory cells with different threshold voltage distributions can be sequentially set It is judged as a logical value "1" or a logical value "0". Therefore, the read operation related to the third bit B3 of the fourth-order memory cell is five read operations.

Similarly, referring to Fig. 5D, for the read operation of the fourth bit B4 of the fourth-order memory cell, the threshold voltage distributions Vt(1,1,1,1) and Vt(1,1,1,0 ) is the voltage range R11, and between the threshold voltage distribution Vt(1,0,1,0) and Vt(1,0,1,1) is the voltage range R12, and the threshold voltage distribution Vt(0, The voltage range R13 is between 0,0,1) and Vt(0,0,0,0), and the threshold voltage distribution between Vt(0,0,1,0) and Vt(0,0,1,1) The voltage range R14 is between them, and the voltage range R15 is between the threshold voltage distributions Vt(0,1,1,1) and Vt(0,1,1,0). When the read voltage Vr applied by the control circuit 104 is sequentially set to be within the five voltage ranges R11 , R12 , R13 , R14 , and R15 , the fourth bit B4 of the fourth-order memory cells with different threshold voltage distributions can be sequentially set It is judged as a logical value "1" or a logical value "0". Therefore, the read operation related to the fourth bit B4 of the fourth-order memory cell is five read operations.

To sum up, and referring to FIG. 5E, when the control circuit 104 of the second embodiment reads the first cell B1 of the fourth-order memory cell, the read voltage Vr is set within a voltage range R1 for one time read operation. When reading the second bit B2, the reading voltage Vr is set in the four voltage ranges R2, R3, R4, and R5 in sequence to perform four reading operations. When the third bit B3 is read, the read voltage Vr is sequentially set within five voltage ranges R6, R7, R8, R9, and R10 to perform five read operations. When the fourth bit B4 is read, the read voltage Vr is sequentially set within five voltage ranges R11 , R12 , R13 , R14 , and R15 to perform five read operations. Therefore, the configuration of the threshold voltage distribution and the read voltage Vr of the fourth-order memory cells in the second embodiment is a "1-4-5-5 configuration", in which the number of times of reading the first bit B1 is once, and The read times of the second to fourth bits B2-B4 are evenly distributed, so that the read times of the second to fourth bits B2-B4 are the same or close to avoid excessive concentration of the read operations on a certain bit Yuan. For example, for the fourth bit B4 of the fourth-order memory cell in the “1-2-4-8 configuration” of another comparative example, eight read operations are required to read the fourth bit B4. As the error rate increases, so does the amount of additional data required for error correction codes for the data stored in the fourth-order memory cells of the "1-2-4-8 configuration."

FIG. 6 is a schematic diagram of an example of the application of the storage device 100 according to the second embodiment of the present disclosure. Referring to FIG. 6 , the storage device 100 with the fourth-order memory cells having the "1-4-5-5 configuration" is used for storing weight data 602 and normal data 604 of the bitwise multiply-add operation. The first cell B1 of the fourth-order memory cell in the "1-4-5-5 configuration" only needs to perform one read operation, so it is suitable for storing the weight data 602 of the bitwise multiplication and addition operation, while the fourth-order memory cell has The second to fourth bits B2-B4 are used to store the normal data 604 of the bitwise multiply-add operation. In contrast, for the first cell B1 of the fourth-order memory cell in the “3-4-4-4 configuration” of another comparative example, three read operations are required, so it is not suitable for storing bitwise operations. information.

As in the first embodiment and the second embodiment, the control circuit 104 reads the first cell B1 according to a read operation related to the first cell B1 of the multi-level memory cell, and reads the first cell B1 according to the first read operation related to the multi-level memory cell. The M read operations of the two-bit B2 to read the second bit B2, according to the N read operations of the third bit B3 related to the multi-level memory cell to read the third bit B3; and, if If the multi-level memory cell is a memory cell of more than four levels, the fourth bit B4 is read according to P times of read operations related to the fourth bit B4 of the multi-level memory cell. Wherein, the number of readings is evenly distributed among the second to fourth bits B1 ˜ B4 , so that the difference between any two of M, N, and P is less than or equal to 1. For example, in the "1-3-3 configuration" of the third-order memory cells of the first embodiment, both M and N are three, and the difference between M and N is equal to zero. In the "1-4-5-5 configuration" of the fourth-order memory cells of the second embodiment, M is four, N is five, P is five, and the difference between M, N, and P is any two. The value is equal to one or equal to zero.

FIG. 7 is a flow chart of a data access method according to a first embodiment of the present disclosure. The data access method of the first embodiment is applied to the storage device 100 of the first embodiment for data stored in a third-order memory cell. For access, the data access method of the first embodiment is implemented in accordance with the setting range of the read voltage Vr shown in FIGS. 2A to 2C.

First, in step 702, a plurality of three-bit data (b1 b2 b3) ₂ are stored in the first bit B1, the second bit B2 and the third bit of the plurality of third-order memory cells in the memory circuit 102 B3. The first bit B1 corresponds to the first page (low page), the second bit B2 corresponds to the second page (middle page), and the third bit B3 corresponds to the third page (high page). In one example, the data access method of the first embodiment can be used to store the weight data 602 of the multiply-add operation and the normal data, wherein the weight data 602 is stored in the first bit B1 of the third-order memory cell, and the normal data is The second bit B2 and the third bit B3 are stored in the third-order memory cells.

Next, in step 704, the read voltage Vr is set within the voltage range R1 to perform a read operation to read the first bit B1 of the third-order memory cell. Among them, the voltage range R1 is between the threshold voltage distribution Vt(1,1,0) and Vt(0,1,0)

Next, in step 706, the read voltage Vr is set within the voltage ranges R2, R3, and R4 in sequence to perform three read operations, and the second bit B2 of the third-order memory cell is read. Among them, the voltage range R2 is between the threshold voltage distributions Vt(1,1,1) and Vt(1,0,1), and the voltage range R3 is between the threshold voltage distributions Vt(1,0,0) and Vt(1 , 1, 0), and the voltage range R4 is between the threshold voltage distributions Vt(0,1,1) and Vt(0,0,1).

Next, in step 708 , the read voltage Vr is set within the voltage ranges R5 , R6 , and R7 in sequence to perform three read operations, and the third bit B3 of the third-order memory cell is read. The voltage range R5 is between the threshold voltage distributions Vt(1,0,1) and Vt(1,0,0), and the voltage range R6 is between the threshold voltage distributions Vt(0,1,0) and Vt(0 , 1, 1), and the voltage range R7 is between the threshold voltage distributions Vt(0,0,1) and Vt(0,0,0).

FIG. 8 is a flowchart of a data access method according to a second embodiment of the present disclosure. The data access method of the second embodiment is applied to the storage device 100 of the second embodiment for data stored in a fourth-order memory cell. For access, the data access method of the second embodiment is implemented in accordance with the setting range of the read voltage Vr shown in FIGS. 5A to 5D.

First, in step 802, a plurality of four-bit data (b1 b2 b3 b4) ₂ are stored in the first bit B1, the second bit B2, the third bit of the plurality of fourth-order memory cells in the memory circuit 102 Byte B3 and the fourth bit B4. In one example, the data access method of the second embodiment can be used to store the weight data and normal data of the multiply-add operation, wherein the weight data is stored in the first bit B1 of the fourth-order memory cell, and the normal data is stored in the The second bit B2, the third bit B3 and the fourth bit B4 of the fourth-order memory cell.

Next, in step 804, the read voltage Vr is set within the voltage range R1 to perform a read operation to read the first bit B1 of the fourth-order memory cell. Among them, the voltage range R1 is between the threshold voltage distribution Vt(1,1,0,1) and Vt(0,1,0,1)

Next, in step 806 , the read voltage Vr is set within the voltage ranges R2 , R3 , R4 , and R5 in sequence to perform four read operations to read the second bit B2 of the fourth-order memory cell. Among them, the voltage range R2 is between the threshold voltage distribution Vt(1,1,0,0) and Vt(1,0,0,0), and the voltage range R3 is between the threshold voltage distribution Vt(1,0,0, 1) and Vt(1,1,0,1), the voltage range R4 is between the threshold voltage distribution Vt(0,1,0,1) and Vt(0,0,0,1), the voltage range R5 is between the threshold voltage distribution Vt(0,0,1,1) and Vt(0,1,1,1).

Next, in step 808, the read voltage Vr is set within the voltage ranges R6, R7, R8, R9, and R10 in sequence to perform five read operations, and the third bit B3 of the fourth-order memory cell is read. Among them, the voltage range R6 is between the threshold voltage distribution Vt(1,1,1,0) and Vt(1,1,0,0), and the voltage range R7 is between the threshold voltage distribution Vt(1,0,0, 0) and Vt(1,0,1,0), the voltage range R8 is between the threshold voltage distribution Vt(1,0,1,1) and Vt(1,0,0,1), the voltage range R9 is between the threshold voltage distribution Vt(0,0,0,0) and Vt(0,0,1,0), and the voltage range R10 is between the threshold voltage distribution Vt(0,1,1,0) and Vt (0,1,0,0).

Next, in step 810 , the read voltage Vr is set within the voltage ranges R11 , R12 , R13 , R14 , and R15 in sequence to perform five read operations to read the fourth bit B4 of the fourth-order memory cell. The voltage range R11 is between the threshold voltage distribution Vt(1,1,1,1) and Vt(1,1,1,0), and the voltage range R12 is between the threshold voltage distribution Vt(1,0,1, 0) and Vt(1,0,1,1), the voltage range R13 is between the threshold voltage distribution Vt(0,0,0,1) and Vt(0,0,0,0), the voltage range R14 is between the threshold voltage distribution Vt(0,0,1,0) and Vt(0,0,1,1), and the voltage range R15 is between the threshold voltage distribution Vt(0,1,1,1) and Vt (0,1,1,0).

FIG. 9 is a flow chart of the data updating method according to the present disclosure. If some bits of the multi-level memory cells of the storage device 100 need to be read multiple times, which is likely to cause read errors, the control circuit 104 can execute the data Update method to correct errors. The data update method shown in FIG. 9 can also be implemented in conjunction with the data access method shown in FIG. 7 and FIG. 8 . Referring to FIG. 9, in step 902, a first threshold is set, and the first threshold is a threshold of fail bit count (FBC _th ). In this embodiment, the first threshold is the threshold of the number of error bits of normal data. The first threshold must be within the correction capability of the error correction code, in other words, the first threshold must be less than the maximum number of bits that the error correction code can correct.

Next, in step 904, it is checked whether the data stored in the multi-level memory cells in the memory circuit 102 has an error (whether there is an error bit); if an error occurs, the number of error bits is calculated. In this embodiment, the weight data stored in the lower page (the first cell of the third-order memory cell) of the memory circuit 102 is substantially constant and stored in the memory circuit 102 , and the weight data is rarely read to the external circuit or changed by the user. In addition, the reading operation of the weight data is a one-time reading, and the number of readings is less, so data damage is less likely to occur. Therefore, the data update method of this embodiment does not check the weight data.

In contrast, the normal data stored in the middle page and the upper page (the second and third bits of the third-order memory cells) of the memory circuit 102 are general data, and the normal data may be frequently read to the outside circuit. In addition, the reading operation of normal data is multiple readings (at least three times), which may easily cause data corruption. Therefore, the data updating method of this embodiment checks the error bits of the normal data, and calculates the normal data. The number of error bits.

Next, in step 906, the number of error bits in the normal data is compared with the first threshold. If the number of error bits in the normal data is greater than the first threshold, data update needs to be performed, and at this time, step 908 is performed. On the other hand, if the number of error bits in the normal data is less than or equal to the first threshold, no data update is required.

In step 908, the data of the memory circuit 102 is updated as a whole. In other words, not only the normal data but also the weight data are updated together. The control circuit 104 reads weight data and normal data from all the pages (low page, middle page, and high page) in the memory circuit 102 . In other words, the weight data is read from the first bit of the multi-level memory cell, and the normal data is read from the second bit, the third bit and/or the fourth bit of the multi-level memory cell.

Next, in step 910, the control circuit 104 decodes the read normal data with the error correction code, and then corrects the erroneous bits of the normal data. And, the control circuit 104 updates the read weight data.

Next, in step 912, the control circuit 104 writes the updated weight data and the corrected normal data into the first bit to the third bit and/or the fourth bit of the multi-level memory cells, respectively.

Although the present invention has been disclosed above in detail in terms of preferred embodiments and examples, it is to be understood that such examples are intended to be illustrative and not restrictive. It is contemplated that various modifications and combinations will occur to those of ordinary skill in the art, which are within the spirit of the inventions and the scope of the appended claims.

100: storage device 102: memory circuit 104: control circuit B1: first bit B2: second bit B3: third bit B4: fourth bit Vr: read voltage Vt: threshold voltage R1~R15: Voltage range (b1 b2 b3) ₂ : three-bit data (1 1 1) ₂ , (1 0 1) ₂ , (1 0 0) ₂ , (1 1 0) ₂ : three-bit data (0 1 0) ₂ ,(0 1 1) ₂ ,(0 0 1) ₂ ,(0 0 0) ₂ : three-bit data (b1 b2 b3 b4) ₂ : four-bit data (1 1 1 1) ₂ ,(1 1 1 0) ₂ ,(1 1 0 0) ₂ ,(1 0 0 0) ₂ : four-bit data (1 0 1 0) ₂ ,(1 0 1 1) ₂ ,(1 0 0 1) ₂ ,( 1 1 0 1) ₂ : four-bit data (0 1 0 1) ₂ , (0 0 0 1) ₂ , (0 0 0 0) ₂ , (0 0 1 0) ₂ : four-bit data (0 0 1 1) ₂ ,(0 1 1 1) ₂ ,(0 1 1 0) ₂ ,(0 1 0 0) ₂ : four-bit data Vt(1,1,1),Vt(1,0,1) , Vt(1,0,0): threshold voltage distribution Vt(1,1,0), Vt(0,1,0), Vt(0,1,1): threshold voltage distribution Vt(0,0,1 ), Vt(0,0,0): threshold voltage distribution Vt(1,1,1,1), Vt(1,1,1,0), Vt(1,1,0,0): threshold voltage distribution Vt(1,0,0,0), Vt(1,0,1,0), Vt(1,0,1,1): threshold voltage distribution Vt(1,0,0,1), Vt(1 ,1,0,1),Vt(0,1,0,1): threshold voltage distribution Vt(0,0,0,1), Vt(0,0,0,0), Vt(0,0, 1,0): threshold voltage distribution Vt(0,0,1,1), Vt(0,1,1,1), Vt(0,1,1,0): threshold voltage distribution Vt(0,1, 0,0): threshold voltage distribution P: parity bit 302, 402, 602: weight data 304, 404, 604: normal data W1~W4: data fields N1~N4: data fields 702~708: steps 802~810: steps 902~912: step

FIG. 1 is a block diagram of a storage device according to a first embodiment of the disclosure. 2A to 2C are schematic diagrams of the threshold voltage distribution and read voltage of the third-order memory cells of the present disclosure. FIG. 3 and FIG. 4 are schematic diagrams of an example of the application of the storage device according to the first embodiment of the disclosure. 5A to 5E are schematic diagrams of the threshold voltage distribution and read voltage of the fourth-order memory cells of the present disclosure. FIG. 6 is a schematic diagram of an example of the application of the storage device according to the second embodiment of the disclosure. FIG. 7 is a flow chart of the data access method according to the first embodiment of the disclosure. FIG. 8 is a flowchart of the data access method according to the second embodiment of the disclosure. FIG. 9 is a flowchart of the disclosed data updating method.

B1: first digit

Vr: read voltage

Vt: threshold voltage

R1: Voltage range

Vt(1,1,1), Vt(1,0,1), Vt(1,0,0): threshold voltage distribution

Vt(1,1,0), Vt(0,1,0), Vt(0,1,1): threshold voltage distribution

Vt(0,0,1), Vt(0,0,0): critical voltage distribution

Claims (20)

A storage device, comprising: A memory circuit includes a plurality of multi-level memory cells, each of the multi-level memory cells is used to store at least one first bit, a first bit in at least a first page, a second page, and a third page two bits, and a third bit; and a control circuit for reading the first bits according to one read operation associated with the first bits, and reading the first bits according to M read operations associated with the second bits The second bits are read, and the third bits are read according to N read operations related to the third bits, wherein the difference between M and N is less than or equal to 1. The storage device of claim 1, wherein each of the multi-level memory cells is a third-order memory cell, the first page is a low page, the second page is a middle page, and the third page is a high page. The storage device of claim 1, wherein each of the multi-level memory cells is a third-order memory cell and is used to store one three-dimensional data, wherein the three-dimensional data are (1 1 1) ₂ , (1 0 1) ₂ , (1 0 0) ₂ , (1 1 0) ₂ , (0 1 0) ₂ , (0 1 1) ₂ , (0 0 1) ₂ , or (0 0 0) ₂ respectively corresponding to Threshold voltage distribution Vt(1,1,1), Vt(1,0,1), Vt(1,0,0), Vt(1,1,0), Vt(0,1,0), Vt( 0,1,1), Vt(0,0,1), and Vt(0,0,0), the threshold voltage distributions from low voltage to high voltage are Vt(1,1,1), Vt( 1,0,1), Vt(1,0,0), Vt(1,1,0), Vt(0,1,0), Vt(0,1,1), Vt(0,0,1 ), and Vt(0,0,0). The storage device of claim 3, wherein M=3 and N=3, and the read voltage of the one read operation with respect to the first bits is between Vt(1,1,0) and Vt (0,1,0), the read voltages of the M times of read operations related to the second bits are respectively between Vt(1,1,1) and Vt(1,0,1) between, between Vt(1,0,0) and Vt(1,1,0), and between Vt(0,1,1) and Vt(0,0,1), and related The read voltages of the N times of read operations on the third bits are respectively between Vt(1,0,1) and Vt(1,0,0) and between Vt(0,1, 0) and Vt(0,1,1), and between Vt(0,0,1) and Vt(0,0,0). The storage device according to claim 1, wherein the memory circuit is a two-dimensional NAND flash memory (2D NAND flash memory), a two-dimensional phase change memory (2D phase change memory, 2D PCM), two 2D resistive random access memory (2D RRAM), or two-dimensional magnetoresistive random access memory (2D magnetoresistive random access memory, 2D MRAM), and these multi-level memory cells are two-dimensional memory cells. The storage device according to claim 1, wherein the memory circuit is a three-dimensional NAND flash memory (3D NAND flash memory), a three-dimensional phase change memory (3D phase change memory, 3D PCM), a three-dimensional resistive type Random access memory (3D resistive random access memory, 3D RRAM), or three-dimensional magnetoresistive random access memory (3D magnetoresistive random access memory, 3D MRAM), and these multi-level memory cells are three-dimensional memory cells. The storage device of claim 1, wherein the first bits of the multi-level memory cells are used to store a weight data, the second bits of the multi-level memory cells and the third bits The bits are used to store a normal data, and the weight data is used for a multiply-add operation. The storage device of claim 1, wherein each of the multi-level memory cells is a fourth-level memory cell, each of the fourth-level memory cells is further used to store a fourth bit in a fourth page, and the control circuit is further The fourth bits are read according to P read operations associated with the fourth bits, wherein the difference between any of P, M, and N is less than or equal to one. The storage device of claim 8, wherein each of the multi-level memory cells is used to store a four-bit data, and the four-bit data is (1 1 1 1) ₂ , (1 1 1 0) ₂ , ( 1 1 0 0) ₂ , (1 0 0 0) ₂ , (1 0 1 0) ₂ , (1 0 1 1) ₂ , (1 0 0 1) ₂ , (1 1 0 1) ₂ , (0 1 0 1) ₂ , (0 0 0 1) ₂ , (0 0 0 0) ₂ , (0 0 1 0) ₂ , (0 0 1 1) ₂ , (0 1 1 1) ₂ , (0 1 1 0 ) ₂ , or (0 1 0 0) ₂ corresponding to the threshold voltage distributions Vt(1,1,1,1), Vt(1,1,1,0), Vt(1,1,0,0) , Vt(1,0,0,0), Vt(1,0,1,0), Vt(1,0,1,1), Vt(1,0,0,1), Vt(1,1 ,0,1), Vt(0,1,0,1), Vt(0,0,0,1), Vt(0,0,0,0), Vt(0,0,1,0), Vt(0,0,1,1), Vt(0,1,1,1), Vt(0,1,1,0), and Vt(0,1,0,0), these threshold voltage distributions The sequence from low voltage to high voltage is Vt(1,1,1,1), Vt(1,1,1,0), Vt(1,1,0,0), Vt(1,0,0,0 ), Vt(1,0,1,0), Vt(1,0,1,1), Vt(1,0,0,1), Vt(1,1,0,1), Vt(0, 1,0,1), Vt(0,0,0,1), Vt(0,0,0,0), Vt(0,0,1,0), Vt(0,0,1,1) , Vt(0,1,1,1), Vt(0,1,1,0), and Vt(0,1,0,0). The storage device of claim 9, wherein M=4, N=5, and P=5, and the read voltage of the one read operation with respect to the first bits is between Vt(1,1, 0,1) and Vt(0,1,0,1), the read voltages of the M times of read operations related to the second bits are respectively between Vt(1,1,0,0 ) and Vt(1,0,0,0), between Vt(1,0,0,1) and Vt(1,1,0,1), between Vt(0,1,0 ,1) and Vt(0,0,0,1), and between Vt(0,0,1,1) and Vt(0,1,1,1), relative to these third The read voltages of the N times of read operations of the bit are respectively between Vt(1,1,1,0) and Vt(1,1,0,0) and between Vt(1,0,0) ,0) and Vt(1,0,1,0), between Vt(1,0,1,1) and Vt(1,0,0,1), between Vt(0,0 ,0,0) and Vt(0,0,1,0), and between Vt(0,1,1,0) and Vt(0,1,0,0), and are related to the The read voltages of the P read operations of the fourth bits are respectively between Vt(1,1,1,1) and Vt(1,1,1,0) and between Vt(1, 0,1,0) and Vt(1,0,1,1), between Vt(0,0,0,1) and Vt(0,0,0,0), between Vt( 0,0,1,0) and Vt(0,0,1,1), and between Vt(0,1,1,1) and Vt(0,1,1,0). According to the storage device of claim 8, the first bits of the multi-level memory cells are used to store a weight data, the second bits of the multi-level memory cells, the third bits of the multi-level memory cells The bit and the fourth bits are used to store a normal data, and the weight data is used for a multiply-add operation. A data access method is applied to a memory circuit including a plurality of multi-level memory cells, each of which is used for storing in at least a first page, a second page, and a third page At least one first bit, one second bit, and one third bit, the data access method includes: reading the first bits according to a read operation associated with the first bits; reading the second bits according to M read operations associated with the second bits; and the third bits are read according to N read operations associated with the third bits, Wherein, the difference between M and N is less than or equal to 1. The data access method of claim 12, wherein each of the multi-level memory cells is a third-order memory cell and is used to store one three-dimensional data, and the three-dimensional data is (1 1 1) ₂ , ( 1 0 1) ₂ , (1 0 0) ₂ , (1 1 0) ₂ , (0 1 0) ₂ , (0 1 1) ₂ , (0 0 1) ₂ , or (0 0 0) ₂ respectively Corresponding to the threshold voltage distribution Vt(1,1,1), Vt(1,0,1), Vt(1,0,0), Vt(1,1,0), Vt(0,1,0), Vt(0,1,1), Vt(0,0,1), and Vt(0,0,0), the threshold voltage distributions from low voltage to high voltage are Vt(1,1,1), Vt(1,0,1), Vt(1,0,0), Vt(1,1,0), Vt(0,1,0), Vt(0,1,1), Vt(0,0 , 1), and Vt(0,0,0). The data access method according to claim 13, wherein M=3 and N=3, the data access method comprises: setting a read voltage between Vt(1,1,0) and Vt(0,1,0) to perform the one read operation associated with the first bits; Set the read voltage to be between Vt(1,1,1) and Vt(1,0,1) and between Vt(1,0,0) and Vt(1,1,0), respectively time, and between Vt(0,1,1) and Vt(0,0,1) to perform the M read operations associated with the second bits; and Set the read voltage to be between Vt(1,0,1) and Vt(1,0,0) and between Vt(0,1,0) and Vt(0,1,1), respectively time, and between Vt(0,0,1) and Vt(0,0,0) to perform the N read operations related to the third bits. The data access method as described in claim 12, further comprising: storing a weight data in the first bits of the multi-level memory cells; and storing a normal data in the second bits and the third bits of the multi-level memory cells, The weight data is applied to a multiply-add operation. The data access method as described in claim 15, further comprising: setting a first threshold, the first threshold being less than the maximum number of correctable bits of an error correction code; checking whether the normal data has at least one error bit, and calculating the number of the at least one error bit; comparing the number of the at least one error bit of the normal data with the first threshold; If the number of the at least one error bit is greater than the first threshold, read the weight data from the first bits of the multi-level memory cells, and read the weight data from the second bits of the multi-level memory cells and the third bits to read the normal data; correcting the at least one erroneous bit of the normal data with the error correction code, and updating the weight data; and Write the updated weight data into the first bits of the multi-level memory cells, and write the corrected normal data into the second bits and the third bits of the multi-level memory cells Yuan. The data access method of claim 12, wherein each of the multi-level memory cells is a fourth-level memory cell, and each of the fourth-level memory cells has the first bit, the second bit, and the third bit , and a fourth bit for storing a four-bit data, the data access method further includes: The fourth bits are read according to P read operations associated with the fourth bits of the fourth-order memory cells, where the difference between any of P, M, and N is less than or equal to one. The data access method of claim 17, wherein the four-bit data is (1 1 1 1) ₂ , (1 1 1 0) ₂ , (1 1 0 0) ₂ , (1 0 0 0) ₂ , (1 0 1 0) ₂ , (1 0 1 1) ₂ , (1 0 0 1) ₂ , (1 1 0 1) ₂ , (0 1 0 1) ₂ , (0 0 0 1) ₂ , (0 0 0 0) ₂ , (0 0 1 0) ₂ , (0 0 1 1) ₂ , (0 1 1 1) ₂ , (0 1 1 0) ₂ or (0 1 0 0) ₂ respectively At the threshold voltage distribution Vt(1,1,1,1), Vt(1,1,1,0), Vt(1,1,0,0), Vt(1,0,0,0), Vt( 1,0,1,0), Vt(1,0,1,1), Vt(1,0,0,1), Vt(1,1,0,1), Vt(0,1,0, 1), Vt(0,0,0,1), Vt(0,0,0,0), Vt(0,0,1,0), Vt(0,0,1,1), Vt(0 ,1,1,1), Vt(0,1,1,0), and Vt(0,1,0,0), these threshold voltage distributions are Vt(1,1, 1,1), Vt(1,1,1,0), Vt(1,1,0,0), Vt(1,0,0,0), Vt(1,0,1,0), Vt (1,0,1,1), Vt(1,0,0,1), Vt(1,1,0,1), Vt(0,1,0,1), Vt(0,0,0 ,1), Vt(0,0,0,0), Vt(0,0,1,0), Vt(0,0,1,1), Vt(0,1,1,1), Vt( 0,1,1,0), and Vt(0,1,0,0). The data access method of claim 18, wherein M=4, N=5 and P=5, the data access method comprises: setting a read voltage between Vt(1,1,0,1) and Vt(0,1,0,1) to perform the one read operation associated with the first bits; Set the read voltage to be between Vt(1,1,0,0) and Vt(1,0,0,0) and between Vt(1,0,0,1) and Vt(1, respectively ,1,0,1), between Vt(0,1,0,1) and Vt(0,0,0,1), and between Vt(0,0,1,1) and between Vt(0, 1, 1, 1) to perform the M read operations related to the second bits; The read voltage is set to be between Vt(1,1,1,0) and Vt(1,1,0,0) and between Vt(1,0,0,0) and Vt(1, respectively ,0,1,0), between Vt(1,0,1,1) and Vt(1,0,0,1), between Vt(0,0,0,0) and Vt (0,0,1,0), and between Vt(0,1,1,0) and Vt(0,1,0,0) to perform the N read operations; and The read voltage is set to be between Vt(1,1,1,1) and Vt(1,1,1,0) and between Vt(1,0,1,0) and Vt(1, respectively ,0,1,1), between Vt(0,0,0,1) and Vt(0,0,0,0), between Vt(0,0,1,0) and Vt (0,0,1,1), and between Vt(0,1,1,1) and Vt(0,1,1,0) to perform the P read operations. The data access method as described in claim 17, further comprising: storing a weight data in the first bits of the multi-level memory cells; and storing a normal data in the second bits, the third bits, and the fourth bits of the multi-level memory cells, The weight data is applied to a multiply-add operation.

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