TWI768222B - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

A semiconductor device includes a substrate and a first III-V compound layer disposed on the substrate. The first III-V compound layer includes a plurality of crystal lattices and each of the crystal lattices has a prism plane. The semiconductor device further includes a second III-V compound layer disposed on the first III-V compound layer. The semiconductor device includes a source electrode, a drain electrode and a gate electrode disposed on the second III-V compound layer. The source electrode and the drain electrode define a channel region that has a plurality of channels of charge carriers in the first III-V compound layer. The normal direction of the prism plane defines an m-axis, and each of the channels of the charge carriers is parallel with the m-axis.

Description

Semiconductor device and method of manufacturing the same

Embodiments of the present disclosure relate to a semiconductor device, and more particularly, to a semiconductor device for high electron mobility transistors (HEMT) devices.

In the semiconductor industry, gallium nitride (GaN) is often used to form various integrated circuit components due to its characteristics, such as high electron mobility transistor (HEMT) components. High electron mobility transistors, also known as heterostructure FETs (HFETs) or modulation-doped FETs (MODFETs), are composed of different energy gaps. The composition of semiconductor materials. A two dimensional electron gas (2 DEG) layer is created adjacent to the formed interface of different semiconductor materials. Due to the high electron mobility of the two-dimensional electron gas, high electron mobility transistors can have the advantages of high breakdown voltage, high electron mobility, and low input capacitance, so they are suitable for high-power components.

However, although the existing high electron mobility transistors generally meet the requirements, they are not satisfactory in every aspect, and further improvements are still required to improve performance and have wider applications.

Embodiments of the present disclosure include a semiconductor device. The semiconductor device includes a substrate and a first III-V group compound layer, and the first III-V group compound layer is disposed on the substrate. The first group III-V compound layer includes a plurality of crystal lattices and each crystal lattice has an apex face. The semiconductor device further includes a second III-V group compound layer, and the second III-V group compound layer is disposed on the first III-V group compound layer. The semiconductor device includes a source electrode, a drain electrode and a gate electrode, which are arranged on the second III-V group compound layer. The source electrode and the drain electrode define a channel region in the first III-V group compound layer, and the channel region has a plurality of carrier channels. The direction of the normal line of the plane defines an m-axis, and each carrier channel is parallel to the m-axis.

Embodiments of the present disclosure include a semiconductor device. The semiconductor device includes a substrate and a first III-V group compound layer, and the first III-V group compound layer is disposed on the substrate. The first III-V compound layer includes a plurality of lattices and each lattice has an m-plane. The semiconductor device further includes a second III-V group compound layer, and the second III-V group compound layer is disposed on the first III-V group compound layer. The semiconductor device includes a source electrode, a drain electrode and a gate electrode, which are arranged on the second III-V group compound layer. The source electrode and the drain electrode define a channel region in the first III-V group compound layer, and the channel region has a plurality of carrier channels. Each carrier channel is parallel to the normal direction of the m-plane.

Embodiments of the present disclosure include a method for fabricating a semiconductor device. The manufacturing method includes forming and providing a substrate. The manufacturing method further includes forming a first III-V compound layer on the substrate. The first group III-V compound layer includes a plurality of crystal lattices and each crystal lattice has an apex face. The manufacturing method includes forming a second III-V compound layer on the first III-V compound layer. The manufacturing method further includes forming a source electrode, a drain electrode and a gate electrode on the second III-V compound layer. The source electrode and the drain electrode define a channel region in the first III-V group compound layer, and the channel region has a plurality of carrier channels. The direction of the normal line of the plane defines an m-axis, and each carrier channel is parallel to the m-axis.

The following disclosure provides many different embodiments or examples for implementing different features of the present invention. The following disclosure describes specific examples of various components and their arrangements to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the embodiment of the present disclosure describes that a first feature part is formed on or above a second feature part, it means that it may include an embodiment in which the first feature part and the second feature part are in direct contact. Embodiments may be included in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

It should be understood that additional operational steps may be performed before, during, or after the method, and in other embodiments of the method, some of the operational steps may be substituted or omitted.

In addition, it may use spatially related terms such as "below", "below", "lower", "above", "above", "higher" and similar terms, These spatially relative terms are used for convenience in describing the relationship between one element(s) or feature(s) and another element(s) or feature(s) in the figures, and these spatially relative terms include differences between devices in use or operation Orientation, and the orientation depicted in the drawings. When the device is turned in a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used therein will also be interpreted according to the turned orientation.

In the specification, the terms "about", "approximately" and "approximately" usually mean within 20%, or within 10%, or within 5%, or within 3% of a given value or range, or within 2%, or within 1%, or within 0.5%. The quantity given here is an approximate quantity, that is, the meanings of "about", "approximately" and "approximately" can still be implied without the specific description of "about", "approximately" and "approximately".

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be construed to have meanings consistent with the relevant art and the context or context of the present disclosure, and not in an idealized or overly formal manner interpretation, unless there is a special definition in the embodiments of the present disclosure.

Different embodiments disclosed below may reuse the same reference symbols and/or labels. These repetitions are for the purpose of simplicity and clarity and are not intended to limit the specific relationship between the various embodiments and/or structures discussed.

The on-resistance (R _on ) is an important factor affecting the power consumption of the semiconductor device, and its resistance value is proportional to the power consumption of the semiconductor device. Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, which are particularly suitable for high electron mobility transistor (HEMT) devices. In the semiconductor device of the disclosed embodiment, the charge carrier channel (or the source electrode and the drain electrode) of the semiconductor device is relatively opposite to the III-V compound layer (eg, gallium nitride (GaN)) The lattice is arranged in a specific direction, which can effectively reduce the on-resistance of the semiconductor device. The following description will be made with reference to the embodiments shown in the drawings.

FIGS. 1 to 4 are partial cross-sectional views illustrating different process stages of forming the semiconductor device 1 shown in FIG. 4 according to some embodiments of the present disclosure. It should be noted that, in order to show the features of the embodiments of the present disclosure more clearly, some elements may be omitted in FIGS. 1 to 4 .

Referring to FIG. 1, a substrate 10 is provided. In some embodiments, the substrate 10 may be a semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, or a similar semiconductor substrate. In some embodiments, the substrate 10 may be a semiconductor-on-insulator substrate, such as a silicon on insulator (SOI) substrate. In some embodiments, the substrate 10 may be a glass substrate or a ceramic substrate, such as a silicon carbide (SiC) substrate, an aluminum nitride (AlN) substrate, or a sapphire (Sapphire) substrate. However, the embodiments of the present disclosure are not limited thereto.

In some embodiments, the substrate 10 is a QST substrate. Here, the QST substrate refers to a substrate produced by Qromis Technology, Inc. in the United States. For example, the QST substrate may include a core, a barrier layer, a bonding layer and a single crystalline layer. In some embodiments, the barrier layer may encapsulate the core, the bonding layer may be disposed on the barrier layer, and the growth layer may be disposed on the bonding layer, but the embodiments of the present disclosure are not limited thereto.

In some embodiments, the material of the core may include a polycrystalline ceramic material, such as polycrystalline aluminum nitride (AlN), polycrystalline gallium nitride (GaN), polycrystalline gallium nitride (AlGaN) ), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (zinc oxide, ZnO), polycrystalline gallium trioxide (gallium(III) trioxide, Ga ₂ O ₃ ), other suitable materials or a combination of the foregoing, but The embodiments of the present disclosure are not limited thereto. In some embodiments, the polycrystalline ceramic material may include a bonding material such as yttrium oxide (ie, yttria).

In some embodiments, the material of the barrier layer may be an amorphous material, such as silicon nitride, silicon carbonitride (SiCN), silicon oxynitride (SiON), aluminum nitride (aluminum nitride, AlN), silicon carbide (SiC), other suitable materials, or a combination of the foregoing, but the embodiments of the present disclosure are not limited thereto. In some embodiments, the barrier layer may be formed by a low-pressure chemical vapor deposition (LPCVD) process, but the embodiments of the present disclosure are not limited thereto. In some embodiments, the barrier layer may be one or more layers including one or more materials laminated in a composite manner, but the embodiments of the present disclosure are not limited thereto.

In some embodiments, the barrier layer may be used to prevent diffusion and/or release of components in the core (eg, yttrium oxide, oxygen, metal impurities, other trace elements, etc.) into the environment of the semiconductor processing chamber. In a semiconductor processing chamber, QST substrates may be epitaxially grown, for example, at high temperatures (eg, 1,000°C).

In some embodiments, the material of the bonding layer may include silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a combination of the foregoing. In some embodiments, the bonding layer may be formed on (part of) the top surface of the barrier layer by chemical vapor deposition (CVD), atomic layer deposition (ALD), or spin coating. For example, the aforementioned chemical vapor deposition method may be low pressure chemical vapor deposition (LPCVD), low temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (rapid thermal chemical vapor deposition) deposition, RTCVD) or plasma-assisted chemical vapor deposition (plasma enhanced chemical vapor deposition, PECVD).

In some embodiments, the material of the growth layer may include silicon (Si), aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), silicon carbide (SiC), other suitable materials or The aforementioned combinations are formed, but the embodiments of the present disclosure are not limited thereto. The growth layer can be a single-layer or multi-layer structure. In some embodiments, the growth layer may be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam It is formed by epitaxy (molecular beam epitaxy, MBE), other suitable methods, or a combination of the foregoing, but the embodiment of the present disclosure is not limited thereto.

In some embodiments, the substrate 10 may further include a plurality of adhesion layers and a conductive layer. The adhesive layer and the conductive layer can be disposed between the core and the barrier layer. For example, the adhesive layer may be disposed between the core and the conductive layer, and the adhesive layer may be disposed between the conductive layer and the barrier layer, but the embodiment of the present disclosure is not limited thereto.

In some embodiments, the material of the adhesive layer may include tetraethyl orthosiliate (TEOS), silicon oxide _{(Six O y )} , other suitable materials, or a combination of the foregoing, but the embodiments of the present disclosure are not limited to This is limited. In some embodiments, the adhesion layer may be formed around the core by chemical vapor deposition (CVD), atomic layer deposition (ALD), or spin coating.

In some embodiments, the conductive layer may include a doped (eg, boron doped) highly conductive material. In some embodiments, the doping concentration may be between 1×10 ¹⁹ cm ⁻³ to 1×10 ²⁰ cm ⁻³ to provide high conductivity. Other dopants of different doping concentrations (eg, phosphorous, arsenic, bismuth, etc., with doping concentrations between 1x1016 cm ^-3 and ^5x1018 cm ^{-3 )} can also be used to provide materials suitable for use in conductive layers. N-type or P-type semiconductor materials, but the embodiments of the present invention are not limited thereto.

For the detailed structure of the QST substrate, please refer to US Patent Application No. 15/621,335 filed on June 13, 2017 and US Patent Application No. 15/621,335 filed on June 13, 2017, which will not be repeated here. . However, the embodiments of the present disclosure are not limited thereto.

Referring to FIG. 2 , a first III-V group compound layer 20 is formed on the substrate 10 . In some embodiments, the material of the first group III-V compound layer 20 may include one or more group III-V compound semiconductor materials, eg, group III nitrides. In some embodiments, the material of the first III-V group compound layer 20 may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium gallium nitride (InGaN), Aluminum (indium gallium aluminium nitride, InGaAlN), similar materials or a combination of the foregoing. In some embodiments, the thickness of the first III-V compound layer 20 may be between 0.01 μm and 10 μm. In some embodiments, the first III-V compound layer 20 may have dopants, such as n-type dopants or p-type dopants. The first III-V compound layer 20 can be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), and other suitable method or a combination of the foregoing. For example, the first III-V compound layer 20 may be epitaxially grown by metal organic chemical vapor deposition (MOCVD) using a gallium-containing precursor and a nitrogen-containing precursor. Gallium-containing precursors may include trimethylgallium (TMG), triethylgallium (TEG), or other suitable chemicals; nitrogen-containing precursors include ammonia (NH3), tertiarybutylamine (tertiarybutylamine) , TBAm), phenyl hydrazine or other suitable chemicals. However, the embodiments of the present disclosure are not limited thereto.

Referring to FIG. 3 , a second III-V group compound layer 30 is formed on the first III-V group compound layer 20 . In some embodiments, the material of the second group III-V compound layer 30 may include one or more group III-V compound semiconductors, eg, group III nitrides. In some embodiments, the material of the second III-V compound layer 30 may include aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium aluminum nitride (InGaAlN), and the like material or a combination of the foregoing. In some embodiments, the thickness of the second III-V compound layer 30 may be between 1 nm and 500 nm. In some embodiments, the second III-V compound layer 30 may have dopants, such as n-type dopants or p-type dopants. The second III-V compound layer 30 can be formed by an epitaxial growth process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), and other suitable method or a combination of the foregoing. For example, the second III-V compound layer 30 may be epitaxially grown by metal organometallic vapor phase epitaxy (MOCVD) using an aluminum-containing precursor, a gallium-containing precursor, and a nitrogen-containing precursor. Aluminum-containing precursors include trimethylaluminum (TMA), triethylaluminum (TEA), or other suitable chemicals; gallium-containing precursors include trimethylgallium (TMG), triethyl Gallium (TEG) or other suitable chemicals; nitrogen containing precursors include ammonia (NH3), tert-butylamine (TBAm), phenyl hydrazine or other suitable chemicals. However, the embodiments of the present disclosure are not limited thereto.

Referring to FIG. 4 , a source electrode 41 , a drain electrode 43 and a gate electrode 45 are formed on the second III-V group compound layer 30 to form the semiconductor device 1 . In the disclosed embodiment, the source electrode 41 , the drain electrode 43 and the gate electrode 45 may be arranged in a specific manner, which will be described in detail later with reference to the drawings.

In some embodiments, the material of the source electrode 41 may include a conductive material, such as a metal, a metal silicide, a semiconductor material, other suitable materials, or a combination of the foregoing. The metal can be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper ( Cu), a combination of the foregoing, an alloy of the foregoing, or a multilayer of the foregoing. The semiconductor material may be polycrystalline silicon or polycrystalline germanium. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the material of the drain electrode 43 may be the same as or similar to the material of the source electrode 41 , and details are not repeated here.

The steps of forming the source electrode 41 and the drain electrode 43 may include depositing a conductive material on the second III-V compound layer 30 and performing a patterning process on the conductive material to form the source electrode 41 and the drain electrode The electrode 43 is on the top surface 30T of the second III-V compound layer 30 . Deposition processes for forming the conductive material may include atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD) (eg, sputtering), other suitable processes, or combinations thereof. Pay special attention. Although FIG. 4 shows that the source electrode 41 and the drain electrode 43 are formed on the top surface 30T of the second III-V group compound layer 30 , the embodiment of the present disclosure is not limited thereto. In some embodiments, part of the source electrode 41 and part of the drain electrode 43 may also be formed in the second III-V group compound layer 30, or may be connected to the first III-V group compound layer 20, depending on the actual demand adjustment.

In some embodiments, the material of the gate electrode 45 may include a conductive material, such as a metal, a metal silicide, a semiconductor material, other suitable materials, or a combination of the foregoing. The metal can be gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper ( Cu), a combination of the foregoing, an alloy of the foregoing, or a multilayer of the foregoing. The semiconductor material may be polycrystalline silicon or polycrystalline germanium. However, the embodiments of the present disclosure are not limited thereto.

The step of forming the gate electrode 45 may include depositing a conductive material on the second III-V compound layer 30 and performing a patterning process on the conductive material to form the gate electrode 45 on the second III-V compound layer on top surface 30T of layer 30 . The deposition process to form the conductive material may include atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD) (eg, sputtering), other suitable processes, or a combination of the foregoing.

In some embodiments, the semiconductor device 1 may further include a doped compound semiconductor layer (not shown), and the doped compound semiconductor layer may be formed between the second III-V group compound layer 30 and the gate electrode 45 . In some embodiments, the doped compound semiconductor layer may include a p-type doped III-V compound, eg, p-type doped gallium nitride. The p-type doped gallium nitride can be doped with at least one of magnesium (Mg), calcium (Ca), zinc (Zn), beryllium (Be), and carbon (C), and other dopants are additionally added. (For example, selected from the group consisting of strontium (Sr), barium (Ba), and radium (Ra)), but the embodiment of the present disclosure is not limited thereto. In some embodiments, the doped compound semiconductor layer may be formed by metal organic chemical vapor deposition (MOCVD) or other suitable deposition processes, lithography patterning processes, and etching processes. In some embodiments, the thickness of the doped compound semiconductor layer may be between about 1 nm and about 100 nm, but the embodiments of the present disclosure are not limited thereto.

Referring to FIG. 4, the band gap discontinuity and the piezoelectric effect between the first III-V compound layer 20 and the second III-V compound layer 30 are in the first III- A carrier channel with highly mobile conduction electrons, called a two-dimensional electron gas (2-DEG), is generated near the interface between the group V compound layer 20 and the second group III-V compound layer 30, such as This is shown by the dotted line in Figure 4. The semiconductor device 1 shown in FIG. 4 may be high electron mobility transistors (HEMT) using two-dimensional electron gas (2DEG) as conductive carriers.

FIG. 5A shows a partial top view of the substrate 10 and the first III-V compound layer 20 . In FIG. 5A , the first III-V compound layer 20 is arranged in a plurality of lattices 21 , but the size of each lattice 21 shown in FIG. 5A is only for illustration, and the size of the lattice 21 relative to the substrate 10 Actual size is not as shown in Figure 5A. In the embodiment shown in FIG. 5A , the material of the first III-V group compound layer 20 is gallium nitride (GaN), and the crystal lattice 21 of gallium nitride belongs to the hexagonal crystal system. . FIG. 5B shows an enlarged schematic top view of the single crystal lattice 21 . FIG. 6 shows a schematic perspective view of a single crystal lattice 21 . FIG. 7 is a schematic top view of a part of the semiconductor device 1 according to an embodiment of the present disclosure.

It should be noted that, in order to show the features of the embodiments of the present disclosure more clearly, some elements may be omitted in FIGS. 5A to 7 . For example, FIG. 7 only shows the source electrode 41 , the drain electrode 43 , the gate electrode 45 and the channel region 47 defined by the source electrode 41 and the drain electrode 43 of the semiconductor device 1 . In addition, FIG. 4 can be, for example, a cross-sectional view taken along the line A-A' in FIG. 7, but the embodiment of the present disclosure is not limited thereto.

Referring to FIGS. 5A , 5B and 6 simultaneously, the lattice 21 has a prism plane. In the present disclosure, the H-plane refers to the rectangular plane on the side of the hexagonal column of the lattice 21 of the hexagonal crystal system, that is, the m-plane (m-plane) 21m of the lattice 21, which is a person with ordinary knowledge in the technical field to which the present invention pertains. Understandable. The high plane (m plane 21 m) belongs to the plane family {1-100}. For example, the high plane may be represented as a plane (10-10), but the embodiment of the present disclosure is not limited to this. In other embodiments, the plane may also be represented as Plane(-1010), Plane(1-100), Plane(-1100), Plane(01-10), or Plane(0-110).

As shown in Fig. 5A and Fig. 5B, the normal direction of the plane can define an m-axis (ie, the symbol m in Fig. 5A and Fig. 5B). For example, when the plane is a plane (10-10), the m-axis is [10-10]; when the plane is a plane (-1010), the m-axis is [-1010]; when the plane is a plane (1- 100), the m-axis is [1-100]; when the plane is a plane (-1100), the m-axis is [-1100]; when the plane is a plane (01-10), the m-axis is [01-10]; When the plane is the plane (0-110), the m-axis is [0-110].

5A and 7 simultaneously, the source electrode 41 and the drain electrode 43 may define a channel region 47 in the first III-V group compound layer 20 , and the channel region 47 may have a plurality of carrier channels. In the disclosed embodiment, each carrier channel is parallel to the m-axis. In other words, in the disclosed embodiment, each carrier channel is parallel to the normal direction of the m-plane of the lattice.

In some embodiments, the extension direction of the source electrode 41 and the drain electrode 43 may be perpendicular to the m-axis (perpendicular to the normal direction of the m-plane), that is, the source electrode 41 and the drain electrode 43 are along the lines of FIG. 5A and FIG. 5A . The direction of the a-axis (symbol a) shown in Fig. 7 extends. In some embodiments, the source electrode 41 and the drain electrode 43 are separated from each other along the direction of the m-axis (the normal direction of the m-plane). In more detail, as shown in FIG. 7 , in some embodiments, the source electrode 41 and the drain electrode 43 are arranged opposite and parallel to each other, and a sidewall of the source electrode 41 facing the drain electrode 43 is on the substrate 10 The projection is one side 41S, and the side 41S is perpendicular to the m-axis (perpendicular to the normal direction of the m plane); or, the projection of the side wall of the drain electrode 43 facing the source electrode 41 on the substrate 10 is one side Side 43S, side 43S is perpendicular to the m-axis (perpendicular to the normal direction of the m-plane).

In the embodiment of the present disclosure, the carriers (electrons or holes) moving in the channel region 47 defined by the source electrode 41 and the drain electrode 43 can have a higher value than that of the conventional semiconductor device. The carrier mobility can have a favorable effect on the on-resistance (R _on ) of the semiconductor device 1 .

However, it should be noted that the arrangement of the source electrode 41 , the drain electrode 43 and the gate electrode 45 in the present disclosure is not limited to that shown in FIG. 7 . As long as each carrier channel in the channel region 47 is parallel to the m-axis, the carriers moving in the channel region 47 defined by the source electrode 41 and the drain electrode 43 can have a higher carrier mobility. .

Table 1 is a performance comparison result of the semiconductor device 1 of the disclosed embodiment and a semiconductor device of a comparative example. The structure of the semiconductor device 1 of the disclosed embodiment can be referred to FIG. 4 to FIG. 7, and each carrier channel in the channel region 47 of the semiconductor device 1 of the disclosed embodiment is parallel to the m-axis (eg [10-10 ]). The semiconductor device of the comparative example has a structure similar to that of the semiconductor device 1 of the embodiment of the present disclosure, except that each carrier channel in the channel region of the semiconductor device of the comparative example is parallel to the a-axis (that is, the The normal direction of the a-plane (a-plane) 21a, for example, [11-20]) (refer to FIGS. 5A and 5B ).

Table I performance Example Comparative example R _on (mΩ) 20.5 115 Area (mm ² ) 10.38 5.18 R _on,sp (mΩ) 2.13 5.96

In Table 1, R _on is the on-resistance, and R _on,sp is the characteristic on-resistance. The characteristic on-resistance R _on,sp is defined as the on-resistance distributed per square unit. As shown in Table 1, the characteristic on-resistance R on,sp of the semiconductor device 1 of the embodiment is reduced by 64% compared to the characteristic on-resistance R _{on ,sp} of the semiconductor device 1 of the comparative example. That is, by arranging each carrier channel in the channel region 47 of the semiconductor device 1 in a specific direction relative to the lattice 21 of the first III-V compound layer 20 (GaN), the conduction of the semiconductor device 1 can be effectively reduced resistance.

To sum up the above, in the semiconductor device of the present disclosure, each carrier channel in the channel region of the semiconductor device is parallel to the m-axis (that is, the method of forming the high plane of the crystal lattice of the first group III-V compound layer) line direction), which can effectively reduce the on-resistance of the semiconductor device.

The foregoing summary outlines the features of many of the embodiments so that those skilled in the art may better understand various aspects of the disclosed embodiments. It should be understood by those skilled in the art that other processes and structures can be easily designed or modified based on the disclosed embodiments to achieve the same purpose and/or to achieve the embodiments described herein. the same advantages. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the disclosed embodiments. Various changes, substitutions or modifications can be made to the embodiments of the present disclosure without departing from the inventive spirit and scope of the embodiments of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the scope of the appended claims. In addition, although the present disclosure has been disclosed above with several preferred embodiments, it is not intended to limit the present disclosure, and not all advantages have been described in detail herein.

Each claim of this disclosure may be a separate embodiment, and the scope of this disclosure includes each claim and each embodiment of this disclosure in combination with each other.

1: Semiconductor device 10: Substrate 20: The first III-V compound layer 21: Lattice 21a:a plane 21m:m plane 30: Second III-V compound layer 30T: Top surface 41: source electrode 41S: Side 43: drain electrode 43S: Side 45: Gate electrode 47: Passage area A-A’: hatch line a:a axis m:m axis

The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the elements may be enlarged or reduced to clearly represent the technical features of the embodiments of the present disclosure. FIGS. 1 to 4 are partial cross-sectional views illustrating different process stages of forming the semiconductor device shown in FIG. 4 according to some embodiments of the present disclosure. FIG. 5A shows a partial top view of the substrate and the first III-V compound layer. Figure 5B shows an enlarged schematic top view of a single lattice. Figure 6 shows a schematic perspective view of a single crystal lattice. FIG. 7 is a schematic top view of a portion of the semiconductor device according to an embodiment of the present disclosure.

1: Semiconductor device

10: Substrate

20: The first III-V compound layer

30: Second III-V compound layer

30T: Top surface

41: source electrode

43: drain electrode

45: Gate electrode

Claims (18)

A semiconductor device, comprising: a substrate; a first III-V group compound layer disposed on the substrate, the first III-V group compound layer includes a plurality of crystal lattices and each of the crystal lattices has a pyran face; a second III-V compound layer disposed on the first III-V compound layer; and A source electrode, a drain electrode and a gate electrode are disposed on the second III-V group compound layer, and the source electrode and the drain electrode define a channel region in the first III-V group compound layer , the channel region has a plurality of carrier channels; The direction of the normal line of the surface defines an m-axis, and each carrier channel is parallel to the m-axis. The semiconductor device of claim 1, wherein the substrate is a semiconductor substrate, a substrate with a semiconductor on an insulator, a glass substrate or a ceramic substrate. The semiconductor device according to claim 1, wherein the substrate is a QST substrate. The semiconductor device of claim 1, wherein the m-axis is [10-10], [-1010], [1-100], [-1100], [01-10] and [0-110 ] one of them. The semiconductor device as described in claim 1, wherein the source electrode and the drain electrode are opposite to each other, and the projection of a side wall of the source electrode facing the drain electrode on the substrate is perpendicular to the m-axis . The semiconductor device of claim 1, wherein the source electrode and the drain electrode are separated from each other along the m-axis direction. A semiconductor device, comprising: a substrate; a first III-V group compound layer disposed on the substrate, the first III-V group compound layer includes a plurality of lattices and each lattice has an m-plane; a second III-V compound layer disposed on the first III-V compound layer; and A source electrode, a drain electrode and a gate electrode are disposed on the second III-V group compound layer, and the source electrode and the drain electrode define a channel region in the first III-V group compound layer , the channel region has a plurality of carrier channels; Each of the carrier channels is parallel to the normal direction of the m-plane. The semiconductor device of claim 7, wherein the substrate is a semiconductor substrate, a substrate with a semiconductor on an insulator, a glass substrate or a ceramic substrate. The semiconductor device of claim 7, wherein the substrate is a QST substrate. The semiconductor device according to claim 7, wherein the m-plane is plane (10-10), plane (-1010), plane (1-100), plane (-1100), plane (01-10) and one of the planes (0-110). The semiconductor device as described in claim 7, wherein the source electrode and the drain electrode are opposite to each other, and the projection of a side wall of the source electrode facing the drain electrode on the substrate is perpendicular to the m The normal direction of the plane. The semiconductor device of claim 7, wherein the source electrode and the drain electrode are separated from each other along a normal direction of the m-plane. A method of manufacturing a semiconductor device, comprising: forming and providing a substrate; forming a first III-V group compound layer on the substrate, wherein the first III-V group compound layer includes a plurality of crystal lattices and each of the crystal lattices has a plane; forming a second III-V compound layer on the first III-V compound layer; and A source electrode, a drain electrode and a gate electrode are formed on the second III-V compound layer, wherein the source electrode and the drain electrode define a channel in the first III-V compound layer area, there are a plurality of carrier channels in the channel area; The direction of the normal line of the surface defines an m-axis, and each carrier channel is parallel to the m-axis. The manufacturing method according to claim 13, wherein the substrate is a semiconductor substrate, a substrate with a semiconductor on an insulator, a glass substrate or a ceramic substrate. The manufacturing method of claim 13, wherein the substrate is a QST substrate. The manufacturing method according to claim 13, wherein the m-axis is [10-10], [-1010], [1-100], [-1100], [01-10] and [0-110] ] one of them. The manufacturing method as described in claim 13, wherein the source electrode and the drain electrode are opposite to each other, and the projection of a side wall of the source electrode facing the drain electrode on the substrate is perpendicular to the m-axis . The manufacturing method as described in claim 13, wherein the source electrode and the drain electrode are separated from each other along the m-axis direction.

Images