TWI767875B - Memory device and operation method thereof - Google Patents

Abstract

A memory device and an operation method thereof are provided. The operation method includes: in a first phase, selecting a global signal line, selecting a first string select line, unselecting a second string select line, selecting a first word line, and unselecting a second word line; sensing during a second phase; in a third phase, keeping voltages of the global signal line, the selected first word line and the unselected second word line, unselecting the first string select line and selecting the second string select line to switch voltages of the first and the second string select lines; and sensing during a fourth phase.

Description

Memory device and method of operating the same

The present invention relates to a memory device with In-Memory-Computing (IMC) and an operation method thereof.

Artificial Intelligence (AI) has become a highly effective solution in many fields. The key operation of AI is to perform multiply-and-accumulation (MAC) operations on a large amount of input data (such as input feature maps) and weight values.

However, with the current AI architecture, it is easy to encounter an IO bottleneck and an inefficient MAC operation flow.

To achieve high accuracy, MAC operations with multi-bit inputs and multi-bit weight values can be performed. However, the I/O bottleneck becomes more severe and the efficiency will be lower.

In-Memory-Computing (IMC) can be used to accelerate MAC operations, because IMC can reduce the complex Arithmetic logic unit (ALU) required under the central processing architecture, and provide an in-memory MAC High parallelism of operations.

When doing IMC, it would be helpful for IMC performance to speed up the background setup time of the multiply operation.

According to an example of the present application, an operation method of a memory device is proposed, the memory device includes a plurality of memory cells, and the operation method of the memory device includes: in a first stage, selecting an integral signal line for the integral signal line The signal line is pulled up from a first reference voltage to a second reference voltage, a first string selection line is selected to be pulled up from the first reference voltage to a third reference voltage, and a first string selection line is selected A second string of select lines is maintained at the first reference voltage, a first word line is selected to be pulled up from the first reference voltage to a fourth reference voltage, and a second word line is not selected The word line is used to pull up the second word line from the first reference voltage to a fifth reference voltage; in a second stage, sensing is performed; in a third stage, the entire signal line is maintained at the The second reference voltage, the first string selection line is not selected, the first string selection line is pulled down from the third reference voltage to the first reference voltage, and the second string selection line is selected to use the second string selection line Pulling up the first reference voltage to the third reference voltage, maintaining the selected first word line at the fourth reference voltage, and maintaining the unselected second word line at the fifth reference voltage ; and induction in a fourth stage.

According to another example of the present application, an operation method of a memory device is proposed, the memory device includes a plurality of memory cells, and the operation method of the memory device includes: in a first stage, selecting an integral signal line to connect the The overall signal line is pulled up from a first reference voltage to a second reference voltage, and a first string selection line is selected to pull up the first string selection line from the first reference voltage to a third reference voltage. A second string of select lines is maintained at the first reference voltage, a first word line is selected to be pulled up from the first reference voltage to a fourth reference voltage, and a first word line is not selected Two word lines are used to pull up the second word line from the first reference voltage to a fifth reference voltage; in a second stage, sensing is performed; in a third stage, the entire signal line is maintained at The second reference voltage maintains the selected first string selection line at the third reference voltage, maintains the unselected second string selection line at the first reference voltage, and deselects the first word line with the the first word line is pulled up from the fourth reference voltage to the fifth reference voltage, and the second word line is selected to be pulled down from the fifth reference voltage to the fourth reference voltage; and sensing in a fourth stage.

According to another example of the present application, a memory device is proposed, comprising: a plurality of memory cells; a plurality of integral signal lines; a plurality of bit lines; a plurality of string select lines; and a plurality of word lines, coupled to the memories a body unit, the memory units are further coupled to the bit lines; a plurality of first switches are coupled to the string selection lines and the bit lines; and a plurality of second switches are coupled to the some integral signal lines and the bit lines; wherein, in a first stage, a first integral signal line of the integral signal lines is selected to pull up the first integral signal line from a first reference voltage to a second reference voltage, selects a first string selection line of the string selection lines to pull the first string selection line from the first reference voltage to a third reference voltage, and deselects one of the string selection lines A second string of select lines is maintained at the first reference voltage, and a first word line of the word lines is selected to pull up the first word line from the first reference voltage to a fourth reference voltage , and deselect a second word line of the word lines to pull up the second word line from the first reference voltage to a fifth reference voltage; sense in a second stage; in a In the third stage, the first overall signal line is maintained at the second reference voltage, the first string selection line is not selected, and the first string selection line is pulled down from the third reference voltage to the first reference voltage, selecting the second string select line to pull the second string select line from the first reference voltage to the third reference voltage, maintaining the selected first word line at the fourth reference voltage, and maintaining The unselected second word line is at the fifth reference voltage; and sensed in a fourth stage.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given and described in detail in conjunction with the accompanying drawings as follows:

The technical terms in this specification refer to the common terms in the technical field. If some terms are described or defined in this description, the interpretations of these terms are subject to the descriptions or definitions in this description. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, those skilled in the art can selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

FIG. 1 shows a schematic circuit diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 is, for example and without limitation, a three-dimensional (3D) memory device. As shown in FIG. 1, the memory device 100 includes a plurality of memory blocks B0-BQ (Q is a positive integer), a page buffer circuit 120, a common source line CSL, a plurality of A global source line (also called a global signal line) GSL0~GSLQ, a plurality of string select lines (string select lines) SSL0~SSLN (N is a positive integer), a plurality of word lines WL0~WLM (M is a positive integer), a plurality of bit lines BL0~BLP (P is a positive integer).

Each of the memory blocks B0 ˜ BQ includes a plurality of switches SW1 , a plurality of switches SW2 and a plurality of memory strings SS. Each memory string SS includes a plurality of memory cells MC. The memory cells MC are located at the intersections of the word lines WL0 ˜WLM and the bit lines BL0 ˜BLP. In the same memory block, the memory cells MC coupled to the same bit line form a memory string SS.

The switches SW1 are located at the intersections of the string select lines SSL0 ˜SSLN and the bit lines BL0 ˜BLP. When an associated memory string SS is selected, the associated switch SW1 will be turned on.

The switches SW2 are located at the intersections of the global source lines GSL0 ˜GSLQ and the bit lines BL0 ˜BLP. When an associated memory block is selected, the associated switch SW2 will be turned on.

A plurality of cell currents Id flowing through the memory strings SS will flow through the common source line CSL to the related circuits (such as, but not limited to, accumulation circuits) at the back end to perform related operations (such as but not limited to). Limited by, multiply and accumulate operation (Multiply Accumulate, MAC), data read, data write, etc.).

The page buffer circuit 120 includes a plurality of page buffers 121_0 to 121_P. The page buffers 121_0 ˜ 121_P are coupled to the bit lines BL0 ˜BLP.

FIG. 2 shows a schematic diagram and a waveform diagram of a memory operation method according to an embodiment of the present application. In FIG. 2, for the convenience of explanation, the memory cells MC coupled to the same word line (eg, WL0) are drawn to clearly show the operation when the string selection line is switched. In addition, when switching the string selection lines, although Figure 2 shows sequential switching (SSL0→SSL1...), it should be understood that the present case is not limited to this, and the switching sequence of the string selection lines may have other sequences, which also within the spirit of the case.

Below, the memory block B0 (the overall source line GSL0 ), the string selection lines SSL0 , SSL1 and the word lines WL0 , WL1 are taken as examples for description, but it should be understood that the present case is not limited to this. For the convenience of explanation, the data of other memory blocks was originally accessed, but after the address is decoded, for example, it is found that the next data is stored in the intersection of the string selection line SSL0 and the word line WL0 in the memory block B0 (ie, string select line SSL0 is the selected string select line, and word line WL0 is the selected word line).

Then in stage P21, select the overall source line GSL0 to be pulled up from the first reference voltage to the second reference voltage; select the string selection line SSL0 to be pulled up from the first reference voltage to the third reference voltage; unselect other strings Select the lines SSL1~SSLN to maintain the first reference voltage; select the word line WL0 to be pulled up from the first reference voltage to the fourth reference voltage; do not select other word lines WL1~WLM to be pulled up from the first reference voltage to the fourth reference voltage Five reference voltages (higher than the fourth reference voltage). Thereby, the memory cells MC in the area 150 can be selected (as shown in FIG. 1 and FIG. 2 ).

After that, induction is performed in stage P22.

Then, after the address is decoded, for example, it is found that the next data is stored in the memory cell MC at the intersection of the string selection line SSL1 and the word line WL0 in the memory block B0 (that is, the string selection line SSL1 is The selected string select line, and the word line WL0 is the selected word line). That is, the selected string select line is changed (from string select line SSL0 to string select line SSL1 ), but the selected word line is not changed (still word line WL0 ).

Then in stage P23, the selected global source line GSL0 is maintained at the second reference voltage; the string selection line SSL0 is not selected and pulled down from the third reference voltage to the first reference voltage; the other string selection lines SSL2~ are not selected. SSLN is maintained at the first reference voltage; the selection string selection line SSL1 is pulled up from the first reference voltage to the third reference voltage; the selected word line WL0 is maintained at the fourth reference voltage; the unselected word lines WL1~WLM are maintained at the fifth reference voltage. Thereby, the memory cells MC in the area 151 can be selected (as shown in FIG. 1 and FIG. 2 ).

After that, induction is performed in stage P24.

Similarly, after the address is decoded, to access the next data, the selected string selection line needs to be changed (for example, from the string selection line SSL1 to the string selection line SSL2), but the selected word line is not changed. In the next stage, the selected overall source line GSL0 is maintained at the second reference voltage; the unselected string selection line SSL1 is pulled down from the third reference voltage to the first reference voltage; the other unselected string selection lines SSL0 and SSL3~SSLN are maintained at the first reference voltage; the selection string selection line SSL2 is pulled up from the first reference voltage to the third reference voltage; the selected word line WL0 is maintained at the fourth reference voltage; other unselected words are maintained Lines WL1 ˜WLM are maintained at the fifth reference voltage.

Similarly, after the address is decoded, in order to access the next piece of data, if it is necessary to switch to a different memory block, the operation similar to the stage P21 needs to be performed again.

As shown in FIG. 2 , the memory device 100 further includes an accumulation circuit 130 coupled to the page buffer circuit 120 .

The data read from the selected memory cells MC are first input into the page buffer circuit 120, and then sent to the accumulation circuit 130 (this case is not limited to this) for MAC operation to obtain output data.

That is, in the operation method of FIG. 2, after the initialization stage (P21), when the data in the same memory block is read, when the string selection line needs to be switched, let the level of the entire source line be Maintain, maintain the level of the selected word line and the unselected word line, and switch the level of the next selected string selection line and the current selected string selection line (eg, stage P23). In this way, the background setting time of the memory device operation can be shortened (the stages P21 to P24 can be regarded as the multiplication bit line setting time and the word line setting time in the MAC operation).

In addition, in the embodiment of FIG. 2 of the present application, by switching the memory block and the string selection line, compared with the prior art, the word line setting time can be reduced, thereby speeding up the operation.

What’s more, in the embodiment of FIG. 2 of this application, if the memory device has multiple memory planes and each memory plane has its own accumulation circuit, the accumulation and output of the MAC operation can be pipelined. conduct.

FIG. 3 shows a schematic diagram and a waveform diagram of a memory operation method according to another embodiment of the present application. In FIG. 3, for the convenience of explanation, the memory cells MC coupled to the same string of select lines (eg, SSL0) are drawn to clearly show the operation of switching word lines. In addition, when switching word lines, although Figure 3 shows sequential switching (WL0→WL1...), it should be understood that this case is not limited to this, and the switching order of word lines can be in other sequences, which is also within the spirit of the case.

Below, the memory block B0 (the overall source line GSL0 ), the string selection lines SSL0 , SSL1 and the word lines WL0 , WL1 are taken as examples for description, but it should be understood that the present case is not limited to this. For the convenience of explanation, the data of other memory blocks was originally accessed, but after the address is decoded, for example, it is found that the next data is stored in the intersection of the string selection line SSL0 and the word line WL0 in the memory block B0 (ie, string select line SSL0 is the selected string select line, and word line WL0 is the selected word line).

Then in stage P31, select the overall source line GSL0 to be pulled up from the first reference voltage to the second reference voltage; select the string selection line SSL0 to be pulled up from the first reference voltage to the third reference voltage; do not select other strings The lines SSL1-SSLN are selected to be maintained at the first reference voltage; the word line WL0 is selected to be pulled up from the first reference voltage to the fourth reference voltage; the remaining word lines WL1-WLM are not selected to be pulled up from the first reference voltage to the fourth reference voltage Five reference voltages (higher than the fourth reference voltage). Thereby, the memory cells MC in the area 150 can be selected (as shown in FIG. 1 and FIG. 3 ).

After that, induction is performed in stage P32.

After that, after the address is decoded, for example, it is found that the next data is stored in the memory cell MC at the intersection of the string selection line SSL0 and the word line WL1 in the memory block B0 (that is, the string selection line SSL0 is still in the memory cell MC). line is selected for the selected string, and word line WL1 is the selected word line). That is, the selected string select line does not change (still the string select line SSL0), but the selected word line changes (from word line WL0 to WL1).

Then in phase P33, the selected global source line GSL0 is maintained at the second reference voltage; the selected string selection line SSL0 is maintained at the third reference voltage; the unselected string selection lines SSL1-SSLN are maintained at the first reference voltage ; unselect the word line WL0 is pulled up from the fourth reference voltage to the fifth reference voltage; maintain the other unselected word lines WL2~WLM at the fourth reference voltage; and select the word line WL1 from the fifth reference voltage The reference voltage is pulled down to the fourth reference voltage. Thereby, the memory cells MC in the area 160 can be selected (as shown in FIG. 1 and FIG. 3 ).

After that, induction is performed in stage P34.

Similarly, after address decoding, in order to access the next data, the selected word line needs to be changed (eg, from word line WL1 to word line WL2), but the selected string selection line is not changed. In the next stage, the selected overall source line GSL0 is maintained at the second reference voltage; the selected string selection line SSL0 is maintained at the third reference voltage; the unselected string selection lines SSL1 ˜SSLN are maintained at the first reference voltage; the unselected word line WL1 is pulled up from the fourth reference voltage to the fifth reference voltage; the other unselected word lines WL0 and WL3~WLM are maintained at the fifth reference voltage; and the word line WL2 is selected Pulled down from the fifth reference voltage to the fourth reference voltage.

The data read from the selected memory cells MC are first input into the page buffer circuit 120, and then sent to the accumulation circuit 130 (this case is not limited to this) for MAC operation to obtain output data.

That is, in the operation method of FIG. 3, after the initialization stage (P31), when reading the data in the same memory block, when the switching of the word line is required, the level of the entire source line is set. Maintain, maintain the level of the selected string selection line and the unselected string selection line, and switch the level of the next selected word line and the current selected word line (eg, stage P33). In this way, the background setting time of the memory device operation can be shortened (the stages P31 to P34 can be regarded as the multiplication bit line setting time and the word line setting time in the MAC operation).

In addition, in the embodiment shown in FIG. 3 of the present application, by switching the memory block, the string selection line and the word line, compared with the prior art, the time for setting the word line can be reduced, thereby speeding up the operation.

What's more, in the embodiment of Fig. 3 of this application, if the memory device has multiple memory planes and each memory plane has its own accumulation circuit, the accumulation and output of MAC operations can be performed in a pipelined manner.

In addition, in other possible embodiments of the present application, the operation methods of Fig. 2 and Fig. 3 can be combined arbitrarily, which are all within the scope of the present application. FIG. 4 and FIG. 5 show the operation method of the memory device according to still another embodiment of the present application.

In Fig. 4, stages P41-P44 are the same or similar to stages P21-P24 in Fig. 2, and stages P45-P46 are the same or similar to stages P33-P34 in Fig. 3, so their details are omitted here.

That is, in Figure 4, the string selection line is switched first (the selected string selection line is switched from the string selection line SSL0 to the string selection line SSL1, as in stage P43), and then the word line is switched (the selected word The word line is switched from word line WL0 to word line WL1, as in stage P45).

In Fig. 5, stages P51-P54 are the same or similar to stages P31-P34 in Fig. 3, and stages P55-P56 are the same or similar to stages P23-P24 in Fig. 2, so their details are omitted here.

That is, in FIG. 5, the switching of the word line is performed first (the selected word line is switched from the word line WL0 to the word line WL1, as in stage P53), and then the string selection line is switched (the selected string The selection line is switched from the string selection line SSL0 to the string selection line SSL1, as in stage P55).

FIG. 6 shows an operation method of a memory device according to yet another embodiment of the present application. The operation method of the memory device includes: (610) in a first stage, selecting an overall signal line to pull up the overall signal line from a first reference voltage to a second reference voltage, selecting a first string selection line to pull up the first string select line from the first reference voltage to a third reference voltage, deselect a second string select line to maintain the first reference voltage, select a first word line to The first word line is pulled up from the first reference voltage to a fourth reference voltage, and a second word line is not selected to be pulled up from the first reference voltage to a fifth reference voltage; (620) inducting in a second stage; (630) in a third stage, maintaining the overall signal line at the second reference voltage, not selecting the first string selection line The string selection line is pulled down from the third reference voltage to the first reference voltage, the second string selection line is selected to pull the second string selection line up from the first reference voltage to the third reference voltage, and maintained to be The selected first word line is at the fourth reference voltage, and the unselected second word line is maintained at the fifth reference voltage; and (640) sensing in a fourth stage.

FIG. 7 shows an operation method of a memory device according to yet another embodiment of the present invention. The operating method of the memory device includes: (710) in a first stage, selecting an overall signal line to pull up the overall signal line from a first reference voltage to a second reference voltage, selecting a first string select lines to pull up the first string of select lines from the first reference voltage to a third reference voltage, deselect a second string of select lines to maintain the first reference voltage, select a first word line to pulling up the first word line from the first reference voltage to a fourth reference voltage, and deselecting a second word line to pull up the second word line from the first reference voltage to a first five reference voltages; (720) inducting in a second stage; (730) in a third stage, maintaining the entire signal line at the second reference voltage, and maintaining the selected first string of select lines at The third reference voltage maintains the unselected second string of select lines at the first reference voltage, and the first word line is unselected and the first word line is pulled up from the fourth reference voltage to the fifth a reference voltage, and selecting the second word line to pull the second word line down from the fifth reference voltage to the fourth reference voltage; and (740) sensing in a fourth stage.

It can be seen from the above that in the above-mentioned embodiments of the present application, a faster operation speed (such as, but not limited to, faster MAC operation speed, faster data read/write speed, etc.) can be provided, because before induction is performed Background setup time can be reduced (eg, multiplication bit line setup time and word line setup time in MAC operations can be reduced).

The above embodiments of the present case can be applied to three-dimensional NAND-type flash memory, or memory devices sensitive to retention and thermal changes, such as, but not limited to, three-dimensional NOR-type flash memory, phase-change (PCM)-type flash memory Memory, magnetic random access memory (magnetic RAM) or resistive RAM, etc.

The above embodiments of this case can be applied to different artificial intelligence (AI) models that need to perform multiple MAC operations, such as, but not limited to, a fully connected layer, a convolution layer, a multi-layer perceptron perceptron), support vector machine, etc.

The above-mentioned embodiments of this case can be applied to accelerate MAC operations, read operations, write operations, and the like.

The above-mentioned embodiments of the present application can be applied to computing usage, and can also be applied to data search, analysis usage, clustering analysis, and the like.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

100: Memory device B0~BQ: memory block 120: Page Buffer Circuit CSL: Common Source Line GSL0~GSLQ: Overall source line SSL0~SSLN: String selection line WL0~WLM: word line BL0~BLP: bit lines SW1, SW2: switch SS: memory string 121_0~121_P: page buffer Id: current 150, 151, 160: Area 130: Cumulative circuit P21~P24, P31~P34, P41~P46, P51~P56: Stage 610-640, 710-740: Steps

FIG. 1 shows a schematic circuit diagram of a memory device according to an embodiment of the present invention. FIG. 2 shows a schematic diagram and a waveform diagram of a memory operation method according to an embodiment of the present application. FIG. 3 shows a schematic diagram and a waveform diagram of a memory operation method according to another embodiment of the present application. FIG. 4 and FIG. 5 show the operation method of the memory device according to still another embodiment of the present application. FIG. 6 shows an operation method of a memory device according to yet another embodiment of the present application. FIG. 7 shows an operation method of a memory device according to yet another embodiment of the present invention.

610-640: Procedure

Claims (10)

An operating method of a memory device, the memory device comprising a plurality of memory units, the operating method of the memory device comprising: In a first stage, an overall signal line is selected to be pulled up from a first reference voltage to a second reference voltage, and a first string of select lines is selected to be driven from the The first reference voltage is pulled up to a third reference voltage, a second string of select lines is not selected to maintain the first reference voltage, and a first word line is selected to pass the first word line from the first reference pulling up the voltage to a fourth reference voltage, and deselecting a second word line to pull up the second word line from the first reference voltage to a fifth reference voltage; induction in a second stage; In a third stage, the entire signal line is maintained at the second reference voltage, the first string selection line is not selected, and the first string selection line is pulled down from the third reference voltage to the first reference voltage, selecting the second string select line to pull the second string select line from the first reference voltage to the third reference voltage, maintaining the selected first word line at the fourth reference voltage, and maintaining deselecting the second word line at the fifth reference voltage; and Induction is performed in a fourth stage. The operation method of a memory device according to claim 1, wherein the memory device further comprises a page buffer circuit and an accumulation circuit, The data read from at least one selected memory cell of the memory cells is input into the page buffer circuit, and sent to the accumulating circuit for multiplying and accumulating to obtain output data. The operation method of a memory device as claimed in claim 1, wherein the memory device includes a plurality of memory planes and each of the memory planes includes an accumulation circuit, and the accumulation and output of a multiply-accumulate-add operation are pipelined. The operating method of the memory device as claimed in claim 1, further comprising: In a fifth stage, the entire signal line is maintained at the second reference voltage, the selected second string selection line is maintained at the third reference voltage, and the unselected first string selection line is maintained at the first selection line. a reference voltage, the first word line is not selected, the first word line is pulled up from the fourth reference voltage to the fifth reference voltage, and the second word line is selected for the second word line line is pulled down from the fifth reference voltage to the fourth reference voltage; and Induction is performed in a sixth stage. An operating method of a memory device, the memory device comprising a plurality of memory units, the operating method of the memory device comprising: In a first stage, an overall signal line is selected to be pulled up from a first reference voltage to a second reference voltage, and a first string of select lines is selected to be driven from the The first reference voltage is pulled up to a third reference voltage, a second string of select lines is not selected to maintain the first reference voltage, and a first word line is selected to pass the first word line from the first reference pulling up the voltage to a fourth reference voltage, and deselecting a second word line to pull up the second word line from the first reference voltage to a fifth reference voltage; induction in a second stage; In a third stage, the entire signal line is maintained at the second reference voltage, the selected first string of select lines is maintained at the third reference voltage, and the unselected second string of select lines is maintained at the first a reference voltage, the first word line is not selected, the first word line is pulled up from the fourth reference voltage to the fifth reference voltage, and the second word line is selected for the second word line line is pulled down from the fifth reference voltage to the fourth reference voltage; and Induction is performed in a fourth stage. The operating method of a memory device according to claim 5, wherein the memory device further comprises a page buffer circuit and an accumulation circuit, The data read from at least one selected memory cell of the memory cells is input into the page buffer circuit, and sent to the accumulating circuit for multiplying and accumulating to obtain output data. The operation method of a memory device as claimed in claim 5, wherein the memory device includes a plurality of memory planes and each of the memory planes includes an accumulation circuit, and the accumulation and output of a multiply-accumulate-add operation are pipelined. The operating method of the memory device as claimed in claim 5, further comprising: In a fifth stage, the entire signal line is maintained at the second reference voltage, the first string selection line is not selected, and the first string selection line is pulled down from the third reference voltage to the first reference voltage, selecting the second string select line to pull the second string select line from the first reference voltage to the third reference voltage, maintaining the selected second word line at the fourth reference voltage, and maintaining deselecting the first word line at the fifth reference voltage; and Induction is performed in a sixth stage. A memory device comprising: a plurality of memory cells; a plurality of integral signal lines; a plurality of bit lines; a plurality of string selection lines; a plurality of word lines coupled to the memory cells, the memory cells further coupled to the bit lines; a plurality of first switches coupled to the string select lines and the bit lines; and a plurality of second switches, coupled to the overall signal lines and the bit lines; in, In a first stage, a first overall signal line of the overall signal lines is selected to be pulled up from a first reference voltage to a second reference voltage, and one of the string selection lines is selected. A first string selection line to pull up the first string selection line from the first reference voltage to a third reference voltage, and a second string selection line of the string selection lines is deselected to maintain the first reference voltage, selecting a first word line of the word lines to pull up the first word line from the first reference voltage to a fourth reference voltage, and deselecting a second word line of the word lines word line to pull up the second word line from the first reference voltage to a fifth reference voltage; induction in a second stage; In a third stage, the first overall signal line is maintained at the second reference voltage, the first string selection line is not selected, and the first string selection line is pulled down from the third reference voltage to the first reference voltage, selecting the second string select line to pull the second string select line from the first reference voltage to the third reference voltage, maintaining the selected first word line at the fourth reference voltage, and , maintaining the unselected second word line at the fifth reference voltage; and Induction is performed in a fourth stage. The memory device of claim 9, wherein, In a fifth stage, the first overall signal line is maintained at the second reference voltage, the selected second string selection line is maintained at the third reference voltage, and the unselected first string selection line is maintained at For the first reference voltage, the first word line is not selected so that the first word line is pulled up from the fourth reference voltage to the fifth reference voltage, and the second word line is selected for the second the word line is pulled down from the fifth reference voltage to the fourth reference voltage; and Induction is performed in a sixth stage.

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