TWI765844B - Signal processing circuit and method for self-calibrating tdqsck - Google Patents

Abstract

A signal processing circuit includes a delay locked loop (DLL) circuit, a data output path circuit, and a first phase detector circuit. The DLL circuit is arranged to receive a memory clock signal, and generate a DLL output signal according to the memory clock signal and a DLL feedback signal. The data output path circuit is coupled to the DLL circuit, and is arranged to generate a DQS signal according to the DLL output signal. The first phase detector circuit is coupled to the data output path circuit, and is arranged to receive the memory clock signal and the DQS signal, and detect a phase difference between the memory clock signal and the DQS signal to generate a first phase detection result.

Description

Signal processing circuit and method for self-calibrating tDQSCK

The present invention relates to dynamic random access memory (DRAM), and more particularly to a method for self-calibrating a tDQSCK (which is a memory clock signal) during a read operation. A method for a skew between a rising edge and a rising edge of a data strobe (DQS) signal and a related signal processing circuit.

150皮秒(picosecond, ps)，則動態隨機存取記憶體的製造商可使得動態隨機存取記憶體的tDQSCK小於

150皮秒，理想上來說，動態隨機存取記憶體的tDQSCK應接近於0。 tDQSCK is defined in the DRAM specification, which limits the relative relationship between the rising edge of the memory clock signal and the rising edge of the data strobe signal during a read operation, that is, tDQSCK A maximum tolerance value and a minimum tolerance value representing a deviation between the rising edge of the memory clock signal and the rising edge of the data strobe signal during a read operation. DRAM manufacturers set the design target for tDQSCK to be smaller than the size of tDQSCK defined in the DRAM specification, for example, the DRAM specification The size of tDQSCK

150 picoseconds (picosecond, ps), the manufacturer of DRAM can make the tDQSCK of DRAM less than

150 picoseconds, ideally, the tDQSCK of DRAM should be close to 0.

In fact, the tDQSCK of DRAMs manufactured by DRAM manufacturers may be slightly different from each other, although they may all be smaller than those defined in the DRAM specifications. The size of tDQSCK, but the distribution of tDQSCK can be quite uneven. For example, suppose a tDQSCK distribution graph has a horizontal axis representing the value of tDQSCK and a vertical axis representing the number of DRAMs. If for each DRAM For memory access, if the settings of tDQSCK are the same, the distribution of the number of DRAMs may not be concentrated at tDQSCK=0, and may be quite scattered. The dynamic random access memory is derived from the method of calibrating tDQSCK and the related signal processing circuit.

Therefore, one of the objectives of the present invention is to provide a method for self-calibrating tDQSCK and a related signal processing circuit to solve the above problems.

According to an embodiment of the present invention, a signal processing circuit is provided. The signal processing circuit may include a delay locked loop circuit, a data output path circuit and a first phase detector circuit. The delay locked loop circuit can receive a memory clock signal, and generate a delay locked loop output signal according to the memory clock signal and a delay locked loop feedback signal, wherein the delay locked loop feedback signal is Obtained from the output signal of the delay-locked loop. The data output path circuit can be coupled to the PLL circuit, and can be used for generating a data strobe signal according to the DLL output signal. The first phase detector circuit can be coupled to the data output path circuit, and can be used for receiving the memory clock signal and the data strobe signal, and detecting a phase difference between the memory clock signal and the data strobe signal , to generate a first phase detection result, wherein a first delay amount is used by the delay-locked loop circuit, and the first delay amount is adjusted according to the first phase detection result.

According to an embodiment of the present invention, a method for self-calibrating a tDQSCK is provided. The method may include: entering a multi-function register mode, a read pre-training mode and a write equalization mode, and presetting a tDQSCK setting; providing a read command and recording a write equalization index signal a write equalization state, wherein the write equalization state of the write equalization index signal indicates the phase relationship between the memory clock signal and the data strobe signal; determine whether tDQSCK is a maximum setting of tDQSCK, wherein tDQSCK is not the maximum setting of tDQSCK , reduce a value of a delay amount to move the data strobe signal forward, provide the read command again, and record the write equalization state of the write equalization index signal again; and because tDQSCK is the maximum setting of tDQSCK, default again tDQSCK setting; judging whether tDQSCK is a minimum setting of tDQSCK, in which, since tDQSCK is not the minimum setting of tDQSCK, increase the value of the delay amount to shift the data strobe signal backward, provide the read command again, and record the write equalization index signal again and leave the multi-function register mode, read pre-training mode and write equalization mode because tDQSCK is the minimum setting of tDQSCK; update a tDQSCK setting code until the write equalization index signal changes state; And record the tDQSCK setup code.

One of the advantages of the present invention is that, through the method of the present invention for self-calibrating tDQSCK during a read operation, for a tDQSCK distribution graph (the horizontal axis represents different values of tDQSCK and the vertical axis represents the chip (eg, dynamic random access memory) ), the distribution of tDQSCK can be more concentrated, and furthermore, after the tDQSCK of each wafer is self-calibrated by the method of the present invention, a manual shift code can be added to the tDQSCK setup code for each wafer , so that the distribution of tDQSCK after self-calibration can be shifted to the left or right according to the design requirements, which greatly increases the design flexibility.

FIG. 1 is a block diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100, such as dynamic random access memory (DRAM), may include a command input interface 10, a command decoder 12, a memory cell circuit 14, a delay-locked phase A delay locked loop (DLL) circuit 16 , a data first input first output (FIFO) circuit 18 and a data input/output (I/O) interface 20 are provided. The command input interface 10 can receive a plurality of command signals COMMAND_SIGNAL, wherein the command signal COMMAND_SIGNAL can include a read command RE, a differential pair of memory clock signals (ie a true (true) clock signal CK_t and a complementary (complementary) clock signal CK_c), a clock enable signal CKE, a chip selection signal CS_n and a plurality of address signals (eg BG0, BG1, BA0, BA1 and A0~A13) and so on. The command decoder 12 can be coupled to the command input interface 10, and can receive and decode the command signal COMMAND_SIGNAL to generate a command address signal CAIR and a control signal CS, wherein the command address signal CAIR corresponds to the read command RE, And the control signal CS is generated by a plurality of address signals.

The memory cell circuit 14 can be coupled to the command decoder 12, and can have a plurality of memory banks (BANK_0~BANK_N), wherein the memory cell circuit 14 is controlled by the control signal CS, and the control signal CS can be used to determine A memory address in one of the memory banks BANK_0~BANK_N, and a read operation corresponding to the read command RE can be operated on the memory address to read a read from the memory address Get data RDATA. The delay-locked loop circuit 16 can be used to receive the command address signal CAIR and the memory clock signal of the differential pair (ie the real clock signal CK_t and the complementary clock signal CK_c), and according to the memory clock signal (eg the real clock signal CK_t and the complementary clock signal CK_c) clock signal CK_t) to generate a delay-locked loop output signal DLL_OUT. The data FIFO circuit 18 can be coupled to the memory cell circuit 14 and the PLL circuit 16, and can be used for receiving the read data RDATA and the PLL output signal DLL_OUT. The data input/output interface 20 can be coupled to the data FIFO circuit 18, and can be used to generate a plurality of data (data, DQ) signals DQ0-DQ7, a plurality of The data signals DQ8~DQ15, the upper data strobe signal of a differential pair (that is, an upper real data strobe signal UDQS_t and an upper complementary data strobe signal UDQS_c) and a lower data strobe signal of a differential pair (also That is, the real data strobe signal LDQS_t and the complementary data strobe signal LDQS_c), wherein the upper data strobe signal of the differential pair and the lower data strobe signal of the differential pair correspond to the data signals DQ8~DQ15 and the data signal DQ0 respectively ~DQ7, and the data signals DQ0~DQ7 and the data signals DQ8~DQ15 correspond to the read data RDATA.

FIG. 2 is a schematic diagram of a signal processing circuit 200 according to an embodiment of the present invention. The signal processing circuit 200 may include a delay locked loop circuit 22, a data output path circuit 24, a phase detector circuit 26, and a storage device 48, wherein the delay locked loop circuit 16 shown in FIG. The delay locked loop circuit 22 shown in FIG. 2 is implemented, and the data FIFO circuit 18 and the data input/output interface 20 shown in FIG. 1 can be implemented by the data output path circuit 24 shown in FIG. 2 To implement, therefore, the memory device 100 shown in FIG. 1 can be modified to include the phase detector circuit 26 and the storage device 48, in addition, since the double data rate (DDR) 3 memory And the DDR4 memory has a write leveling function (that is, both the DDR3 memory and the DDR4 memory can include a write leveling circuit), so the phase detector circuit 26 can use the write leveling circuit. A phase detector circuit is implemented, but the present invention is not limited to this.

The delay locked loop circuit 22 can receive the real clock signal CK_t, and generate the delay locked loop output signal DLL_OUT according to the real clock signal CK_t and a delay locked loop feedback signal DLL_FED, wherein the delay locked loop feedback signal DLL_FED is obtained from the delay-locked loop output signal DLL_OUT. The data output path circuit 24 can be coupled to the delay-locked loop circuit 22 and can be used to generate the real data strobe signal LDQS_t according to the delay-locked loop output signal DLL_OUT. The phase detector circuit 26 can be coupled to the data output path circuit 24 and the storage device 48, and can be used to receive the real clock signal CK_t and the lower real data strobe signal LDQS_t, and to detect the real clock signal CK_t and the lower real data A phase difference between the strobe signals LDQS_t to generate a first phase detection result FP_DR, wherein a first delay amount FDA can be used by the delay locked loop circuit 22, and the storage device 48 can be used to receive the first phase The detection result FP_DR, and the first delay amount FDA is adjusted according to the first phase detection result FP_DR.

As shown in FIG. 2 , the PLL circuit 22 may include a phase detector circuit 28 , a delay unit circuit 30 , a delay controller 32 and a tracking delay circuit 34 . The phase detector circuit 28 can receive the real clock signal CK_t and the delay-locked loop feedback signal DLL_FED, and detect a phase difference between the real clock signal CK_t and the delay-locked loop feedback signal DLL_FED to generate A second phase detection result SP_DR. The delay unit circuit 30 can be coupled to the phase detector circuit 28 and the data output path circuit 24, and can be used to apply a second delay amount SDA to the real clock signal CK_t to generate the delay locked loop output signal DLL_OUT. The delay controller 32 can be coupled to the phase detector circuit 28 and the delay unit circuit 30, and can be used to control the second delay amount SDA of the delay unit circuit 30 according to the second phase detection result SP_DR. The tracking delay circuit 34 can be coupled to the phase detector circuit 28 and the delay unit circuit 30 and can be used to apply the first delay amount FDA to the PLL output signal DLL_OUT to generate the PLL feedback signal DLL_FED.

Additionally, the phase detector circuit 28 may include an input buffer 36 , an input buffer 38 and a phase detector 40 . The input buffer 36 can be coupled to the delay unit circuit 30 and can be used for receiving and buffering the real clock signal CK_t. The input buffer 38 can be coupled to the tracking delay circuit 34 and can be used for receiving and buffering the delay-locked loop feedback signal DLL_FED. The phase detector 40 can be coupled to the input buffer 36 , the input buffer 38 and the delay controller 32 , and can be used to detect the real clock signal CK_t output from the input buffer 36 and the delay output from the input buffer 38 The phase-locked loop feedbacks the phase difference between the signals DLL_FED to generate and transmit the second phase detection result SP_DR to the delay controller 32 . Phase detector circuit 26 may include an input buffer 42 , an input buffer 44 and a phase detector 46 . The input buffer 42 can be coupled to the data output path circuit 24 and can be used for receiving and buffering the real data strobe signal LDQS_t. The input buffer 44 can be used to receive and buffer the real clock signal CK_t. The phase detector 46 can be coupled to the input buffer 42 , the input buffer 44 and the storage device 48 , and can be used to detect the lower real data strobe signal LDQS_t output from the input buffer 42 and the lower real data strobe signal LDQS_t output from the input buffer 44 The phase difference between the real clock signals CK_t is used to generate and transmit the first phase detection result FP_DR to the storage device 48 .

It should be noted that the memory device 100 (eg, dynamic random access memory), which includes the signal processing circuit 200, is operated in a multi-purpose register (MPR) mode with read pre- Training (read preamble training) mode and write in equalization mode. The first phase detection result FP_DR can be used as a write equalization index signal WL_INDEX, and a write equalization state WS of the write equalization index signal WL_INDEX indicates the phase between the real clock signal CK_t and the lower real data strobe signal LDQS_t In addition, the storage device 48 can be further used to generate and transmit a first delay adjustment signal FDA_CODE to the tracking delay circuit 34 according to the first phase detection result FP_DR to adjust the first delay FDA, for example, when When the write equalization state WS of the write equalization index signal WL_INDEX is equal to 1 (that is, the write equalization index signal WL_INDEX has a high level), the lower real data strobe signal LDQS_t lag behind the real clock signal CK_t, and tracks The delay circuit 34 can increase a value of the first delay amount FDA according to the first delay amount adjustment signal FDA_CODE, so as to shift the lower real data strobe signal LDQS_t backward. For another example, when the write equalization state of the equalization index signal WL_INDEX is written When WS is equal to 0 (that is, the write equalization index signal WL_INDEX has a low level), the lower real data strobe signal LDQS_t leads the real clock signal CK_t, and the tracking delay circuit 34 can adjust the signal FDA_CODE according to the first delay amount to reduce the value of the first delay amount FDA, so that the lower real data strobe signal LDQS_t FDA_CODE is shifted forward.

Therefore, the storage device 48 can support a plurality of candidate values for the first delay amount FDQ, and according to the write equalization state WS of the write equalization index signal WL_INDEX, the storage device 48 can also be used to select from the plurality of candidate values by The value of the first delay amount FDA is updated by a candidate value of the first delay amount FDA (that is, the first delay amount FDA is adjusted according to the first delay amount adjustment signal FDA_CODE), wherein a tDQSCK setting code of the candidate value can be updated at the same time.

In this embodiment, the storage device 48 can be coupled to the tracking delay circuit 34 and the phase detector circuit 26 (especially the phase detector 46 ), and can include (but not limited to): a plurality of electronic fuses ( electronic fuses, eFuse) 50_1~50_N (N>1), wherein the electronic fuses 50_1~50_N may have 2 ^N states, and the 2 ^N states respectively correspond to a plurality of candidate values for the first delay amount FDA. The storage device 48 can also be used for receiving a control signal SET_FDA, and when the write equalization index signal WL_INDEX toggles after the value of the first delay amount FDA is updated by the candidate value, the storage device 48 can also be used for recording tDQSCK setting code (which corresponds to the current setting of the first delay amount FDA), wherein the control signal SET_FDA can control the storage device 48 to transmit the first delay amount adjustment signal FDA_CODE to the tracking delay circuit 34, and the electronic fuses 50_1~50_N A programming operation can be performed above to store the tDQSCK setup code (which is an N-bit code). After the electronic fuses 50_1~50_N are programmed at the end of the self-calibration process, a tDQSCK setting code (which indicates a post-calibration setting of the first delay amount FDA) is recorded for subsequent use, that is, when When the memory device 100 operates in the normal mode, the storage device 48 can refer to the tDQSCK setting code to control the setting of the first delay amount FDA.

FIG. 3 is a timing diagram of the clock signal, the data strobe signal and the write equalization index signal obtained by the signal processing circuit 200 shown in FIG. 2 according to an embodiment of the present invention. As shown in Figure 3, a read command (labeled "READ"), such as a multi-function register (MPR) read command, is issued at time T0, and a read latency is is equal to 11 (ie, at time point T11, the read command is operated for the first time). The signals shown above the dotted line L1 (ie the real clock signal CK_t and the lower real data strobe signal LDQS_t) are the external signals of the signal processing circuit 200, and the signals shown below the dotted line L1 (ie a clock write equalization The signal CK_WL, the data strobe write equalization signal DQS_WL and the write equalization index signal WL_INDEX) are the internal signals of the signal processing circuit 200, wherein the real clock signal CK_t corresponds to the clock write equalization signal CK_WL, and the real data selection The communication signal LDQS_t corresponds to the data strobe write equalization signal DQS_WL. Since the lower real data strobe signal LDQS_t lags behind the real clock signal CK_t, the tDQSCK of the memory device 100 (eg, the dynamic random access memory) including the signal processing circuit 200 is greater than 0. In addition, close to the time point T11 and the time At an intermediate timing between points T12, after the data strobe write equalization signal DQS_WL is strobe clocked into the equalization signal CK_WL, the write equalization state WS of the write equalization index signal WL_INDEX is equal to 1.

In this embodiment, since the tDQSCK of the memory device 100 including the signal processing circuit 200 is greater than 0, the tracking delay circuit 34 of the signal processing circuit 200 can increase the value of the first delay amount FDA, so that the real data can be selected The communication signal LDQS_t is shifted backward. During the backward shift of the lower real data strobe signal LDQS_t, a plurality of candidate values for the first delay amount FDA can be supported by the tracking delay circuit 34, wherein in response to the write equalization state WS of the write equalization index signal WL_INDEX, The value of the first delay amount FDA is updated by a candidate value selected from the plurality of candidate values. In addition, in the process of backward displacement of the lower real data strobe signal LDQS_t, the rising edge of the current real data strobe signal LDQS_t ) crosses (cross) the rising edge of the real clock signal CK_t, the data strobe write equalization signal DQS_WL will also cross the rising edge of the clock write equalization signal CK_WL, therefore, the write equalization index signal WL_INDEX will change state ( That is, the write equalization state WS of the write equalization index signal WL_INDEX changes from 1 to 0). At this time, the tDQSCK of the memory device 100 is close to 0 and the tDQSCK setting code is stored in the storage device 48 . After the self-calibration process is performed, a programming operation may be performed on the electronic fuses 50_1 to 50_N to store the tDQSCK setting codes of the candidate values in the electronic fuses 50_1 to 50_N.

FIG. 4 is a timing diagram of a clock signal, a data strobe signal and a write equalization index signal obtained by the signal processing circuit 200 shown in FIG. 2 according to another embodiment of the present invention. The difference between FIG. 3 and FIG. 4 is that the lower real data strobe signal LDQS_t in FIG. 4 leads the real clock signal CK_t, and the tDQSCK of the memory device 100 including the signal processing circuit 200 is less than 0. In addition, Near the time point T11, after the data strobe write equalization signal DQS_WL strobe clock is written into the equalization signal CK_WL, the write equalization state WS of the write equalization index signal WL_INDEX is equal to 0. Similar descriptions are repeated.

In this embodiment, since the tDQSCK of the memory device 100 including the signal processing circuit 200 is less than 0, the tracking delay circuit 34 of the signal processing circuit 200 can reduce the value of the first delay amount FDA, so that the real data can be selected The communication signal LDQS_t is shifted forward. During the forward shift of the lower real data strobe signal LDQS_t, a plurality of candidate values for the first delay amount FDA can be supported by the tracking delay circuit 34, which corresponds to the write equalization state WS of the write equalization index signal WL_INDEX , the value of the first delay amount FDA is updated by a candidate value selected from the plurality of candidate values. In addition, in the process of moving forward the lower real data strobe signal LDQS_t, the rising edge of the current real data strobe signal LDQS_t crosses the When the real clock signal CK_t is on the rising edge, the data strobe write equalization signal DQS_WL will also cross the rising edge of the clock write equalization signal CK_WL. Therefore, the write equalization index signal WL_INDEX will change state (that is, the write equalization signal The write equalization state WS of the index signal WL_INDEX changes from 0 to 1). At this time, the tDQSCK of the memory device 100 is close to 0 and the tDQSCK setting code is stored in the storage device 48 . After the self-calibration process is performed, a programming operation may be performed on the electronic fuses 50_1 to 50_N to store the tDQSCK setting codes of the candidate values in the electronic fuses 50_1 to 50_N.

FIG. 5 is a flowchart of a method for self-calibrating tDQSCK according to an embodiment of the present invention. If the same result can be obtained, the steps do not have to be performed in sequence according to the process shown in FIG. 5. For example, the method shown in FIG. 5 can be performed by the signal processing circuit 200 (which can be the memory device 100). part) to be implemented.

In step S500, the memory device 100 including the signal processing circuit 200 (eg, dynamic random access memory) enters the multi-function register (MPR) mode, the read pre-training mode and the write equalization mode, and pre- Let tDQSCK of memory device 100 be set.

In step S502, a read command (eg, a multi-function register (MPR) read command) is provided to the signal processing circuit 200, and the write equalization state WS of the write equalization index signal WL_INDEX is recorded.

In step S504, it is determined whether tDQSCK is equal to one of the maximum settings of tDQSCK of the memory device 100, if yes, go to step S508; if not, go to step S506.

In step S506, since tDQSCK is not the maximum setting of tDQSCK of the memory device 100, the value of the first delay amount FDA is decreased to shift the lower real data strobe signal LDQS_t forward, and the process returns to step S502.

In step S508, since tDQSCK is the maximum setting of tDQSCK of the memory device 100, the tDQSCK setting of the memory device 100 is again preset.

In step S510, a read command (eg, a multi-function register (MPR) read command) is provided to the signal processing circuit 200 again, and the write equalization state WS of the write equalization index signal WL_INDEX is recorded again.

In step S512, it is determined whether tDQSCK is equal to one of the minimum settings of tDQSCK of the memory device 100, if yes, go to step S516; if not, go to step S514.

In step S514, since tDQSCK is not the minimum setting of tDQSCK of the memory device 100, the value of the first delay FDA is increased to shift the lower real data strobe signal LDQS_t backward, and the process returns to step S510.

In step S516, since tDQSCK is the minimum setting of tDQSCK of the memory device 100, the memory device 100 leaves the multi-function register (MPR) mode, the read pretraining mode and the write equalization mode.

In step S518, the tDQSCK setting code is updated according to the latest tDQSCK setting code selected from step S506 or step S514.

In step S520, it is determined whether the write equalization index signal WL_INDEX has changed state, if yes, go to step S522; if not, go back to step S518.

In step S522, after the self-calibration process is performed, the tDQSCK setting code is recorded and the tDQSCK setting code is stored in the electronic fuses 50_1 ˜ 50_N by performing a programming operation on the electronic fuses 50_1 ˜ 50_N.

Since those skilled in the art can easily understand the operation of each step shown in FIG. 5 through the description of the signal processing circuit 200 shown in FIG. 2, for the sake of brevity, similar content in this embodiment is not repeated here. Repeat.

FIG. 6 is a schematic diagram of the distribution of tDQSCK after self-calibration according to an embodiment of the present invention, wherein the horizontal axis of the schematic diagram represents different values of tDQSCK (in nanoseconds (ns)), and the vertical axis of the schematic diagram Represents different numbers of chips (eg dynamic random access memory). As shown in Figure 6, a curve A represented by a dashed line is an original tDQSCK distribution, and all wafers in curve A have the same tDQSCK setting code, however, in a curve B, the tDQSCK of each wafer is determined by this The inventive method is self-calibrated so that each wafer in curve B has a respective tDQSCK setting code (which is appropriate for each wafer), and the tDQSCK distribution of curve B can be more concentrated.

FIG. 7 is a schematic diagram of the displacement of the tDQSCK distribution shown in FIG. 6 after self-calibration according to an embodiment of the present invention. After the tDQSCK of each wafer is self-calibrated by the method of the present invention, a manual shift code can be added to the tDQSCK setup code for each wafer, for example, the manual shift code is used to The tDQSCK for each wafer is shifted to the left by 0.01, and an adder 702 is used to add the manual shift code to the tDQSCK setup code to generate an optimized tDQSCK setup code for each wafer by adding the respective An optimized tDQSCK setup code is applied to each wafer, and the tDQSCK distribution shown in Figure 6 after self-calibration is shifted to the left by 0.01. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: Memory device 10: Command input interface 12: Command Decoder 14: Memory cell circuit 16,22: Delay Locked Loop Circuit 18: Data FIFO circuit 20: Data input/output interface COMMAND_SIGNAL: command signal CS,SET_FDA: Control signal CAIR: command address signal CK_t: real clock signal CK_c: Complementary clock signal BANK_0~BANK_N: memory bank RDATA: read data DLL_OUT: Delay locked loop output signal DQ0~DQ7, DQ8~DQ15: Data signal LDQS_t: the real data strobe number LDQS_c: Lower complementary data strobe signal UDQS_t: Real data strobe number UDQS_c: Up complementary data strobe signal 200: Data processing circuit 24: Data output path circuit 26, 28: Phase Detector Circuit 30: Delay unit circuit 32: Delay Controller 34: Tracking delay circuit 36, 38, 42, 44: Input buffers 40, 46: Phase Detector 48: Storage device 50_1~50_N: Electronic fuse FDA: First Delay Quantity SDA: Second delay amount DLL_FED: Delay-locked loop feedback signal FP_DR: The first phase detection result SP_DR: The second phase detection result FDA_CODE: The first delay adjustment signal CK_WL: Clock write equalization signal DQS_WL: data strobe write equalization signal WL_INDEX: write equalization index signal S500~S522: Steps 702: Adder

FIG. 1 is a block diagram of a memory device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a signal processing circuit according to an embodiment of the present invention. FIG. 3 is a timing diagram of a clock signal, a data strobe signal and a write equalization index signal obtained by the signal processing circuit shown in FIG. 2 according to an embodiment of the present invention. FIG. 4 is a timing diagram of a clock signal, a data strobe signal and a write equalization index signal obtained by the signal processing circuit shown in FIG. 2 according to another embodiment of the present invention. FIG. 5 is a flowchart of a method for self-calibrating tDQSCK according to an embodiment of the present invention. FIG. 6 is a schematic diagram of tDQSCK distribution after self-calibration according to an embodiment of the present invention. FIG. 7 is a schematic diagram of the displacement of the tDQSCK distribution shown in FIG. 6 after self-calibration according to an embodiment of the present invention.

200: Data processing circuit

22: Delay-locked loop circuit

24: Data output path circuit

26, 28: Phase Detector Circuit

30: Delay unit circuit

32: Delay Controller

34: Tracking delay circuit

36, 38, 42, 44: Input buffers

40, 46: Phase Detector

48: Storage device

50_1~50_N: Electronic fuse

CK_t: real clock signal

LDQS_t: the real data strobe number

FDA: First Delay Quantity

SDA: Second delay amount

DLL_OUT: Delay locked loop output signal

DLL_FED: Delay-locked loop feedback signal

FP_DR: The first phase detection result

SP_DR: The second phase detection result

FDA_CODE: The first delay adjustment signal

SET_FDA: Control signal

Claims (16)

A signal processing circuit, comprising: a delay locked loop circuit for receiving a memory clock signal and generating a delay locked loop output signal according to the memory clock signal and a delay locked loop feedback signal, wherein the delay locked loop The feedback signal is obtained from the output signal of the delay-locked loop; a data output path circuit, coupled to the DLL circuit, and used for generating a data strobe signal according to the DLL output signal; and a first phase detector circuit, coupled to the data output path circuit, and used for receiving the memory clock signal and the data strobe signal, and detecting the memory clock signal and the data strobe signal a phase difference between them to generate a first phase detection result; A first delay amount is used by the delay-locked loop circuit, and the first delay amount is adjusted according to the first phase detection result. The signal processing circuit of claim 1, wherein the signal processing circuit self-calibrates a tDQSCK which is a rising edge between a rising edge of the memory clock signal and a rising edge of the data strobe signal deviation. The signal processing circuit as described in claim 1, wherein the delay-locked loop circuit comprises: a second phase detector circuit for receiving the memory clock signal and the PLL feedback signal, and detecting a difference between the memory clock signal and the PLL feedback signal phase difference to generate a second phase detection result; a delay unit circuit, coupled to the second phase detector circuit and the data output path circuit, and used for applying a second delay amount to the memory clock signal to generate the delay locked loop output signal ; a delay controller, coupled to the second phase detector circuit and the delay unit circuit, and used for controlling the second delay amount according to the second phase detection result; and a tracking delay circuit, coupled to the delay unit circuit and the second phase detector circuit, and used for applying the first delay amount to the PLL output signal to generate the PLL feedback signal. The signal processing circuit as described in claim 3, wherein the second phase detector circuit comprises: a first input buffer, coupled to the delay unit circuit, and used for receiving and buffering the memory clock signal; a second input buffer coupled to the tracking delay circuit and used for receiving and buffering the PLL feedback signal; and a phase detector, coupled to the first input buffer, the second input buffer and the delay controller, and used for detecting the memory clock signal output from the first input buffer and the automatic The phase difference between the PLL feedback signals output by the second input buffer is used to generate the second phase detection result. The signal processing circuit as described in claim 3, wherein the first phase detector circuit comprises: a first input buffer for receiving and buffering the memory clock signal; a second input buffer coupled to the data output path circuit and used for receiving and buffering the data strobe signal; and a phase detector, coupled to the first input buffer and the second input buffer, and used for detecting the memory clock signal output from the first input buffer and from the second input buffer The phase difference between the data strobe signals output by the device is determined to generate the first phase detection result. The signal processing circuit as described in claim 3, wherein the first phase detection result is used as a write equalization index signal, and a write equalization state of the write equalization index signal indicates the memory The phase relationship between the clock signal and the data strobe signal. The signal processing circuit of claim 6, wherein when the write equalization state of the write equalization index signal is equal to a first logic value, the tracking delay circuit increases a value of the first delay amount , so that the data strobe signal is shifted backward; and when the write equalization state of the write equalization index signal is equal to a second logic value, the tracking delay circuit reduces the value of the first delay amount to make The data strobe signal is moved forward. The signal processing circuit described in item 7 of the scope of the application further includes: A storage device, coupled to the first phase detector circuit and the tracking delay circuit, supports a plurality of candidate values for the first delay amount, and is used for generating and outputting a first phase detection result according to the first phase detection result A delay adjustment signal is applied to the tracking delay circuit to update the value of the first delay amount by a candidate value selected from the plurality of candidate values in response to the write equalization state of the write equalization index signal , wherein the first delay amount is adjusted according to the first delay amount adjustment signal. The signal processing circuit as described in claim 8, wherein the storage device is further configured to receive a control signal, and when the write equalization index signal occurs after the value of the first delay amount is updated by the candidate value During state transition, the storage device is further used for recording a setting code of the candidate value, wherein the control signal controls the storage device to transmit the first delay amount adjustment signal to the tracking delay circuit. The signal processing circuit of claim 9, wherein the storage device includes a plurality of electronic fuses. A method for self-calibrating a tDQSCK, wherein the tDQSCK is a deviation between a rising edge of a memory clock signal and a rising edge of a data strobe signal, and the method comprising: Enter a multi-function register mode, a read pre-training mode and a write equalization mode, and preset a tDQSCK setting; providing a read command and recording a write equalization state of a write equalization index signal, wherein the write equalization state of the write equalization index signal indicates the phase relationship between the memory clock signal and the data strobe signal; determining whether the tDQSCK is a maximum setting of the tDQSCK, wherein since the tDQSCK is not the maximum setting of the tDQSCK, reducing a value of a delay amount to shift the data strobe signal forward, providing the read command again, and recording the write equalization state of the write equalization index signal again; and presetting the tDQSCK setting again because the tDQSCK is the maximum setting of the tDQSCK; Determine whether the tDQSCK is a minimum setting of the tDQSCK, wherein since the tDQSCK is not the minimum setting of the tDQSCK, increase the value of the delay amount to shift the data strobe signal backward, provide the read command again, and again recording the write equalization state of the write equalization index signal; and leaving the multi-function register mode, the read pre-training mode, and the write equalization mode because the tDQSCK is the minimum setting of the tDQSCK; updating a tDQSCK setup code until the write equalization index signal transitions; and Record the tDQSCK setup code. The method of claim 11, wherein the read command is a multi-function register write command. According to the method described in claim 11, the delay amount has a plurality of candidate values, and the step of updating the tDQSCK setting code until the write equalization index signal transitions further comprises: The value of the delay amount is updated by a candidate value selected from the plurality of candidate values until the write equalization index signal transitions. The method described in item 13 of the claimed scope, wherein recording the tDQSCK setting code includes: The tDQSCK setting code corresponding to the candidate value causing the write equalization index signal to transition is recorded. The method of claim 11, wherein the tDQSCK is close to 0 due to the transition of the write equalization index signal. The method as described in item 11 of the claimed scope, wherein recording the tDQSCK setting code further comprises: A programming operation is performed on the plurality of electronic fuses to store the tDQSCK setting code in the plurality of electronic fuses.

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