TWI764662B - Semiconductor structure and package structure - Google Patents

Abstract

A semiconductor structure includes a base layer, semiconductor dies on the base layer, and an inter-die connection layer electrically connecting two adjacent semiconductor dies. Each of the semiconductor dies includes an active area and a seal ring area including a seal ring surrounding the active area. The inter-die connection layer extends over adjacent portions of the seal rings in the seal ring areas of the two adjacent semiconductor dies.

Description

Semiconductor structure and package structure

The present invention relates to the technical field of semiconductors, and in particular, to a semiconductor packaging structure and a packaging structure.

Semiconductor packaging not only provides protection for the semiconductor die from environmental contaminants, but also provides electrical power between the semiconductor die packaged therein and another device such as a printed circuit board (PCB). connect. For example, one or more semiconductor dies may be encapsulated in an encapsulating material and electrically connected to a substrate of the semiconductor package. The semiconductor package may then be electrically connected to the printed circuit board using a bonding process. For example, a semiconductor package may have bump structures on the bottom surface of the substrate, and the bump structures are mounted on and electrically coupled to a printed circuit board. Different package types of semiconductor packages have been developed to improve the electrical properties of the dies in the package.

Although existing packaging structures are adequate for their intended purpose, they are not entirely satisfactory in all respects. For example, signal loss and/or power loss may occur between the dies of the package structure. Therefore, there are still problems to be overcome with regard to semiconductor structures and packaging structures having dies obtained from semiconductor structures.

In view of this, the present invention provides a semiconductor packaging structure and a packaging structure to solve the above problems.

According to a first aspect of the present invention, a semiconductor structure is disclosed, comprising: basal layer; semiconductor dies, on the base layer, each of the semiconductor dies including an active region and a seal ring region including a seal ring surrounding the active region; and an inter-die connection layer that electrically connects two adjacent semiconductor die, and the inter-die connection layer extends on adjacent portions of the seal ring in the seal ring region of the two adjacent semiconductor die .

According to a second aspect of the present invention, a packaging structure is disclosed, comprising: a substrate having a first surface and a second surface opposite the first surface, wherein the substrate includes a redistribution layer; A multi-die component disposed over the first surface of the substrate and electrically coupled to a redistribution layer of the substrate, wherein the multi-die component includes: a base layer; a plurality of semiconductor dies on the base layer and spaced apart from each other; and an inter-die connection layer electrically connecting two adjacent semiconductor dies; wherein the inter-die connection layer extends over the seal ring in the seal ring region of the two adjacent semiconductor dies .

The semiconductor structure of the present invention includes: a base layer; semiconductor crystal grains, on the base layer, each of the semiconductor crystal grains includes an active area and a sealing ring area, and the sealing ring area includes a sealing ring surrounding the active area; and an inter-die connection layer that electrically connects two adjacent semiconductor die, and the inter-die connection layer is on adjacent portions of the seal ring in the seal ring region of the two adjacent semiconductor die extend. Therefore, the present invention can form a package structure by arranging a multi-die component including two or more semiconductor dies electrically connected to each other after the wafer sawing process is performed. The semiconductor dies of multi-die components provide fast and reliable signal transmission through the inter-die connection layer between the semiconductor dies, because the electrical communication between adjacent semiconductor dies through the inter-die connection layer can pass through the shortest path to fulfill. Therefore, since the signal loss (and/or power loss) between the semiconductor dies of the embodiment can be significantly reduced, the package structure including the multi-die device having a plurality of semiconductor dies in the embodiment is similar to that in the embodiment, and Compared with the package structure having a plurality of dies individually from a conventional wafer, it has better electrical performance.

The following description is of the best contemplated mode for carrying out the invention. This description is made to illustrate the general principles of the invention and should not be considered limiting. The scope of the present invention is determined by the appended claims.

Hereinafter, the inventive concept is fully described with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. Advantages and features of the inventive concept and methods for implementing them will become apparent from the following exemplary embodiments, which will be described in more detail with reference to the accompanying drawings. However, it should be noted that the inventive concept is not limited to the following exemplary embodiments, and may be implemented in various forms. Therefore, the exemplary embodiments are provided only to disclose the inventive concept and to make the class of the inventive concept known to those of ordinary skill in the art. Furthermore, the figures shown are only schematic and non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. In the practice of the present invention, dimensions and relative dimensions do not correspond to actual dimensions.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular terms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "contacting" another element, it can be directly connected or contacting the other element or intervening elements may be present.

Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In contrast, the term "directly" refers to the absence of intervening elements. It should be understood that the terms "comprising", and/or "comprising" when used herein specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or combinations thereof.

In addition, for the convenience of description, expressions such as "below", "under", "under", "above", "between" may be used herein. Spatially relative terms such as "on" are used to describe the relationship of an element or feature to it. another element or feature as shown. In addition to the orientation depicted in the figures, spatially relative terms are intended to encompass different orientations of the device in use or operation. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments could be termed a second element in other embodiments without departing from the teachings of the present invention. Exemplary embodiments of aspects of the inventive concepts explained and illustrated herein include their complementary equivalents. Throughout the specification, the same or similar reference numbers or reference numerals refer to the same or similar elements.

Some embodiments of the invention are described. It should be noted that additional operations may be provided before, during and/or after the stages described in these embodiments. Some of the stages described may be replaced or eliminated for different embodiments. Additional features can be added to the semiconductor device structure. Some of the features described below may be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a particular order, the operations may be performed in another logical order.

1A and 1B are top views of intermediate stages of a method for forming a semiconductor structure according to some embodiments of the present invention. The semiconductor structure may be a wafer including a plurality of semiconductor dies on the base layer 10 . 1A and 1B depict portions of semiconductor die 11 on base layer 10 for illustrating some embodiments. In some embodiments, each semiconductor die 11 includes an active area AA and _a seal ring R _S surrounding the active area _AA . Active area _AA includes active components such as integrated circuits and one or more transistors. The sealing ring R _S protects the active elements in the active area _AA from harmful contaminants such as moisture, moisture, particles and/or ionic impurities.

As shown in FIGS. 1A and 1B , the semiconductor die 11 on the base layer 10 may be arranged in a matrix pattern. In some embodiments, the semiconductor die on the base layer are separated from each other by the spacer patterns SP. The spacing pattern SP includes a plurality of first spaces SP1 extending in the first direction D1 (eg, the X direction) and second spaces SP2 extending in the second direction D2 (eg, the Y direction). The second direction D2 is different from the first direction D1. For example, the second direction D2 (eg, the Y direction) is perpendicular to the first direction D1 (eg, the X direction). The first spaces SP1 are spaced apart from each other in the second direction D2, and the second spaces SP2 are spaced apart from each other in the first direction D1.

According to embodiments of the present invention, several die features are formed after a wafer sawing process. Most of each die feature includes two or more semiconductor dies 11, so these die features may be referred to as multi-die features. Each multi-die component may include a sealing frame _FS outside the semiconductor die 11 , wherein the sealing frame _FS surrounds the semiconductor die 11 to define a die area. In some embodiments, the sealing frame _FS also provides an effective environmental barrier that protects the semiconductor die 11 from moisture, moisture, particulate or ionic impurities. As shown in FIG. 1B , as an example, four die regions 12 each including four semiconductor die 11 and two die regions 13 each including two semiconductor die 11 are shown. Furthermore, the semiconductor die 11 of the die regions 12/13 are electrically connected to each other through one or a plurality of inter-die connection layers L _IC .

In this example, as shown in FIG. 1B , the first sealing frame F _S1 on the base layer 10 surrounds the first group (eg, four) of semiconductor dies 11 to define the first die region 12 - 1 and the second The F _S2 on the sealing frame base layer 10 surrounds the second group (eg, four) of semiconductor dies 11 to define a second die region 12 - 2 . The third sealing frame F _S3 on the base layer 10 surrounds the third group (eg, four) of semiconductor dies 11 to define the third die region 12-3, and the fourth sealing frame F _S4 on the base layer 10 surrounds the fourth A set (eg, four) of semiconductor dies 11 to define a fourth die region 12-4, and a fifth sealing frame FS5 on the base layer 10 surrounds a fifth set (eg, two) of semiconductor dies 11 to define a fifth die region 12-4. Die region 13-1, and a sixth sealing frame F _S6 on base layer 10 surrounds a sixth group (eg, two) of semiconductor dies 11 to define sixth die region 13-2. The first die region 12-1, the second die region 12-2, the third die region 12-3, and the fourth die region 12-4 may be simply referred to as the die region 12, and the fifth die region 13 -1 and the sixth grain region 13 - 2 may be simply referred to as the grain region 13 . Similarly, the first sealing frame F _S1 , the second sealing frame F _S2 , the third sealing frame F _S3 , the fourth sealing frame F _S4 , the fifth sealing frame F _S5 and the sixth sealing frame F _S6 may be simply referred to as sealing frames F _S.

During wafer sawing, the scribe line LS passes through the space between the die regions _12/13 (defined by the sealing frame FS). In some embodiments, as shown in FIG. 1B , the scribe line LS between the die regions 12 / 13 includes a first scribe line LS1 extending in a first direction D1 (eg, the X direction) and a second direction D2 A second scribe line LS2 extending in (eg, the Y direction). As shown in FIG. 1B , the first scribe line LS1 passes through one of the first spaces SP1 , and the second scribe line LS2 passes through one of the second spaces SP2 . Specifically, according to some embodiments, each first scribe line LS1 overlaps with a portion of one first space SP1, and each second scribe line LS2 overlaps with a portion of one second space SP2.

In addition, as shown in FIG. 1B , the first scribe line LS1 is located between the fifth die region 13 - 1 and the sixth die region 13 - 2 (eg, passing through the space therebetween), and is located in the first die The region 12-1 and the third die region 12-3 are also located between the second die region 12-2 and the fourth die region 12-4. The second scribe line LS2 is located between (eg, through the space between) the first die region 12-1 and the second die region 12-2, and is also located between the third die region 12-3 and the fourth die region 12-3. Between the die regions 12-4. Another second scribe line LS2 is located between the first die area 12-1 and the fifth die area 13-1, and is also located between the third die area 12-3 and the sixth die area 13-2 . It should be noted that no inter-die connecting layer extends over the adjacent die regions to connect the semiconductor dies of the adjacent die regions. For example, no inter-die connecting layer extends on the first die region 12-1 and the second die region 12-2 to connect the semiconductor die of the first die region 12-1 and the second die region 12-2 grain. Therefore, according to embodiments of the present invention, the inter-die connection layer is not cut during the wafer sawing process.

2 is a top view of a semiconductor structure according to some embodiments of the present invention. In some embodiments, a wafer including several (several) semiconductor dies 11 is formed on the base layer 10 , and several sealing frames F _S are formed on the base layer 10 to define die regions (eg, die regions). 12, 13 and 14). In FIG. 2 , most of the die regions include two or more semiconductor die 11 . For example, the wafer in FIG. 2 includes nine die regions 12 , four die regions 13 and four die regions 14 . Each die region 12 includes four semiconductor die 11 , each die region 13 includes two semiconductor die 11 , and each die region 14 includes one semiconductor die 11 . It should be noted that the arrangement of the die regions and the number of semiconductor dies provide an exemplary exemplary example in each of the die regions shown in FIG. 2 , and the present invention is not limited thereto.

In addition, as shown in FIG. 2 , in some embodiments, a first scribe line LS1 (such as the X direction) extending in the first direction D1 and a second scribe line LS2 (such as the Y direction) extending in the second direction D2 pass through through the space between two adjacent die regions 12 , 13 and 14 . If the semiconductor die 11 in each of the die regions 12 and 13 fabricated on the base layer 10 has the same function, the die regions 12 and 13 may be referred to as multi-die feature regions. However, the semiconductor die 11 on the base layer 10 may have the same function or different functions.

Additionally, although FIG. 2 depicts the semiconductor die 11 in one of the die regions 12 or 13 as being spaced apart from each other, two adjacent semiconductor die 11 in one of the die regions 12 or 13 are electrically connected to each other , which can be realized by, for example, one or the other of the plurality of inter-die connection layers L _IC in FIG. 1B . According to some embodiments of the present invention, after performing a wafer sawing process, a package structure may be formed by arranging a multi-die component including two or more (eg, four) semiconductor dies 11 electrically connected to each other . The semiconductor dies 11 of the multi-die component provide fast and reliable signal transmission through the inter-die connection layers between the semiconductor dies 11 due to the electrical communication between adjacent semiconductor dies 11 (eg, through the dies 11 ). inter-connection layer) can be achieved through the shortest path. Therefore, since the signal loss (and/or power loss) between the semiconductor dies 11 of the embodiment (which are electrically connected to each other via the inter-die connection layer L _IC ) can be significantly reduced, the inclusion of a plurality of The package structure of a multi-die package of individual semiconductor dies 11 has better electrical performance than a package structure having a plurality of dies individually from a conventional wafer. As shown in FIG. 2 , the semiconductor structure in this embodiment includes: a first sealing frame on the base layer and surrounding a first group of semiconductor die (for example, including two or four or one semiconductor die), wherein the a first encapsulation frame defining a first die region; and a second encapsulation frame on the base layer and surrounding a second set of semiconductor dies (eg, including two or four or one semiconductor die), wherein the second encapsulation The frame defines a second die area, wherein the second die area is adjacent to the first die area, and a scribe line is located between the first die area and the second die area. Wherein, no inter-die connection layer extends over the first die region and the second die region. Wherein, the number of semiconductor crystal grains in the first crystal grain region (for example, including two semiconductor crystal grains) and the number of semiconductor crystal grains in the second crystal grain region (for example, including two or four or one semiconductor crystal grain) grains) same or different. The semiconductor structure further includes: a third sealing frame on the base layer and surrounding a third set of semiconductor dies, wherein the third sealing frame defines a third die region, and wherein the semiconductor dies in the third die region are The number is different from the number of semiconductor dies in the second die region. Wherein, the third die area is adjacent to the first die area or the second die area, and another scribe line is located between the third die area and the first die area or the second die area between regions.

For example, details of an inter-die connection layer used to connect adjacent semiconductor dies in a single die region are provided below.

3 is a top view of a die region of a semiconductor structure according to some embodiments of the present invention. FIG. 4 is a cross-sectional view taken along cross-sectional line 4 - 4 of the semiconductor structure in FIG. 3 . FIG. 5 is a cross-sectional view taken along cross-sectional line 5 - 5 of the semiconductor structure in FIG. 3 . A top view of two adjacent semiconductor dies within the die region in FIG. 3 , according to some embodiments of the present invention.

Features/components in Figures 3, 4, 5 and 6 that are similar or identical to features/components in Figures 1A, 1B and 2 are designated by similar or identical reference numerals, and these similar or identical features /Parts are not repeated here. Additionally, it should be noted that the structures in FIGS. 3, 4, 5, and 6 are provided to illustrate electrical connections between adjacent semiconductor dies in a die region, according to some embodiments of the present invention. An applicable design. The present invention is not limited to this.

As shown in FIG. 3 , in some embodiments, the die region 12 is on the base layer 10 , and the die region 12 includes four semiconductor dies 11 - 1 , 11 - 2 , 11 - 3 and 11 - 4 . The base layer 10 has a top surface 101 and a bottom surface 102 opposite the top surface 101 , wherein semiconductor die (eg, semiconductor die 11 - 1 and 11 - 2 ) are disposed on the top surface 101 of the base layer 10 . The semiconductor die 11-1 includes an active area A _A1 and a seal ring R _S1 surrounding the active area A _A1 . The semiconductor die 11-2 includes an active area A _A2 and a seal ring R _S2 surrounding the active area A _A2 . The semiconductor die 11-3 includes an active area A _A3 and a seal ring R _S3 surrounding the active area A _A3 . The semiconductor die 11-4 includes an active area A _A4 and a seal ring R _S4 surrounding the active area A _A4 . The sealing frame F _S on the base layer 10 surrounds the semiconductor die 11 - 1 , 11 - 2 , 11 - 3 and 11 - 4 to define the die region 12 . It should be noted in the present invention that the base layer 10 is made of a wafer, and the wafer may include monocrystalline silicon, polycrystalline silicon, or compound wafers (such as gallium arsenide, gallium nitride, etc., all of which can be used to produce electricity crystal wafers), and are silicon wafers. Therefore, the base layer 10 includes the material of the wafer, such as silicon, and the base layer 10 also includes transistors, as well as source/drain contacts, gate contacts, etc., and the base layer 10 does not include wiring or windings (such as copper layer, etc.). Therefore, the base layer 10 is completely different from the substrate or printed circuit board, including different materials (substrate or printed circuit board, etc., including resin, copper layer, etc.), different manufacturing processes, and different structures (the substrate or printed circuit board, etc. are The wiring layers such as copper are alternated with resin and the like, and the base layer 10 is formed on the original silicon wafer through photolithography, etching and other steps).

In addition, the semiconductor dies 11-1, 11-2, 11-3, and 11-4 may be arranged in a 2×2 matrix and spaced apart from each other. For example, the semiconductor die 11-1 is spaced apart from the semiconductor die 11-3 through the first space SP1, and is spaced apart from the semiconductor die 11-2 through the second space SP2. Similarly, the semiconductor die 11-4 is spaced apart from the semiconductor die 11-2 through the first space SP1, and is spaced apart from the semiconductor die 11-3 through the second space SP2. Also, the semiconductor die are electrically connected to each other through the inter-die connection layer L _IC . For example, the semiconductor die 11-1 is electrically connected to the semiconductor die 11-2 through the inter-die connection layer L _IC1 , and the semiconductor die 11-2 is electrically connected to the semiconductor die 11-4 through the inter-die connection layer L _IC2 . Similarly, the semiconductor die 11-1 is electrically connected to the semiconductor die 11-3 through the inter-die connection layer L _IC3 , and the semiconductor die 11-3 is electrically connected to the semiconductor die 11-3 through the inter-die connection layer L _IC4 4.

4 is a cross-sectional view taken along a cross-sectional line 4-4 of the semiconductor structure in FIG. 3, where the cross-sectional line 4-4 passes through a location between the inter-die connection layers L _IC1 . Thus, FIG. 4 depicts only the configuration of the seal ring for two adjacent semiconductor dies 11-1 and 11-2 without any inter-die connection layer L _IC1 , according to some embodiments of the present invention.

As shown in FIG. 4 , in some embodiments, the semiconductor die 11-1 includes a seal ring area A _R1 and an active area A _A1 , and the semiconductor die 11-2 includes a seal ring area A _R2 and an active area A _A2 . Active areas A _A1 and A _A2 may include active elements such as transistors and integrated circuits. Each of the seal ring areas A _R1 and A _R2 may include a plurality of interconnect stacks stacked vertically to provide mechanical protection and moisture protection for the active areas A _A1 and A _A2 .

In this example, three interconnect stacks on base layer 10 (eg, on top surface 101 of base layer 10 ) form a seal ring for the semiconductor die. As shown in FIG. 4 , the seal ring R _S1 of the semiconductor die 11 - 1 includes a first interconnect stack 211 over the base layer 10 and surrounding the active area A _A1 , on the first interconnect stack 211 and surrounding the active area The second interconnect stack 212 of the area A _A1 , and the third interconnect stack 213 on the second interconnect stack 212 and surrounding the active area A _A1 . The first interconnect stack 211 includes a plurality of first wires 211L and first conductive vias 211V connecting the first wires 211L. The second interconnect stack 212 includes a plurality of second wires 212L and second conductive vias 212V, wherein the second conductive vias 212V connect two adjacent second wires 212L and connect the lowermost second wire 212L and the uppermost of the first wire 211L. The third interconnect stack 213 includes at least one third wire 213L and several third conductive vias 213V, wherein the third conductive vias 213V connect the third wire 213L and the uppermost second wire 212L.

In some embodiments, the first wires 211L of the first interconnect stack 211, the second wires 212L of the second interconnect stack 212, and the third wires 213L of the third interconnect stack 213 are each formed of a first metal layer (eg, , M1 ), a second metal layer (eg, M2 ), and a third metal layer (eg, M3 ). For example, the first wire 211L and the second wire 212L are made of copper (Cu), and the third wire 213L is made of aluminum (Al). The outermost third wire 213L is made of aluminum (Al), which has better oxidation resistance and can protect internal structures such as copper layers. Additionally, in some embodiments wherein each first wire 211L has a first thickness t1, each second wire 212L has a second thickness t2, and each third wire 213L has a third thickness t3. The thickness t2 is greater than the first thickness t1, and the third thickness t3 is greater than the second thickness t2, but not limited thereto. In this embodiment, starting from the base layer 10, the metal layers or wires going up can be thicker and thicker to facilitate manufacturing, while the metal layers or wires with a lower thickness can be used to transmit signals, etc., while the upper layer has a larger thickness A metal layer or wire can be used to connect to power or ground. Therefore, in this embodiment, metal layers or wires with different functions are arranged separately to improve work efficiency and prevent crosstalk.

In addition, in this example, as shown in FIG. 4 , the active area A _A1 of the semiconductor die 11 - 1 includes a first conductive stack 311 over the base layer 10 , a second conductive stack 311 over the first conductive stack 311 312 and a third conductive stack 313 on the second conductive stack 312 for forming an integrated circuit of the semiconductor die 11-1. In some embodiments, the first conductive stack 311 includes a plurality of wires 311L and a plurality of conductive vias 311V, the second conductive stack 312 includes two wires 312L and a plurality of conductive vias 312V, and the third conductive stack 313 includes a Conductive wires 313L and a plurality of conductive vias 313V. The third conductive stack 313 is electrically connected to the second conductive stack 312 , and the second conductive stack 312 is electrically connected to the first conductive stack 311 . The first conductive stack 311 may be electrically connected to one or more active elements (eg, transistors) in the base layer 10 . In some embodiments, the wires 311L of the first conductive stack 311 , the wires 312L of the second conductive stack 312 , and the wires 313L of the third conductive stack 313 are composed of a first metal layer (eg, M1 ), a second metal layer, layer (eg M2) and a third metal layer (eg M3) are formed.

Similarly, in some embodiments, as shown in FIG. 4 , the seal ring _RS2 of the semiconductor die 11 - 2 includes a first interconnect stack 221 over the base layer 10 and surrounding the active area A _A2 , in the first A second interconnect stack 222 above the interconnect stack 221 and surrounding the active area A _A2 , and a third interconnect stack 223 above the second interconnect stack 222 and surrounding the active area A _A2 . The first interconnect stack 221 includes a plurality of first wires 221L and first conductive vias 221V connecting the first wires 221L. The second interconnect stack 222 includes a plurality of second wires 222L and second conductive vias 222V, wherein the second conductive vias 222V connect two adjacent second wires 222L and connect the lowermost second wires 222L and the uppermost of the first wire 221L. The third interconnect stack 223 includes at least one third wire 223L and a plurality of third conductive vias 223V, wherein the third conductive vias 223V connect the third wire 223L and the uppermost second wire 222L. In some embodiments, the first conductor 221L of the first interconnect stack 221, the second conductor 222L of the second interconnect stack 222, and the third conductor 223L of the third interconnect stack 223 are each composed of a first metal layer (eg, M1 ), a second metal layer (eg, M2 ), and a third metal layer (eg, M3 ) are formed.

Furthermore, in this example, as shown in FIG. 4 , the active area AA2 of the semiconductor die 11 - 2 includes a first conductive stack 321 located above the base layer 10 and a second conductive stack 322 located on the first conductive stack 321 and a third conductive stack 323 on the second conductive stack 322 for forming an integrated circuit of the semiconductor die 11-2. In some embodiments, the first conductive stack 321 includes a plurality of wires 321L and several conductive vias 321V, the second conductive stack 322 includes two wires 322L and several conductive vias 322V, and the third conductive stack 323 includes a Wire 323L and several conductive vias 323V. The third conductive stack 323 is electrically connected to the second conductive stack 322 , and the second conductive stack 322 is electrically connected to the first conductive stack 321 . The first conductive stack 321 may be electrically connected to one or more active elements (eg, transistors, not shown) in the base layer 10 . In some embodiments, the wires 321L of the first conductive stack 321 , the wires 322L of the second conductive stack 322 , and the wires 323L of the third conductive stack 323 are composed of a first metal layer (eg, M1 ), a second metal layer, layer (eg, M2) and a third metal layer (eg, M3) are formed.

In some embodiments, as shown in FIG. 4 , the semiconductor die 11 - 1 further includes a dummy area A _D1 between the seal ring area A _R1 and the active area A1 . Dummy area A _D1 may include several (plurality) wires _311D , 312D, 313D, wires 311D, 311D, The wires 312D and 313D may be formed on the same layer as the wires 311L, 312L and 313L, for example, in the same process. Also, the semiconductor die 11-2 further includes a dummy area A _D2 between the seal ring area A _R2 and the active area A _A2 . Dummy area A _D2 may include several (plurality) of wires 321D, _322D , 323D, wires 321D, 321D, The wires 322D and 323D may be formed on the same layer as the wires 321L, 322L and 323L, for example, in the same process. Dummy areas A _D1 and A _D2 are used as buffer areas, the wires in dummy areas A _D1 and A _D2 will enhance the conductive stack of the wafer after the sawing process along the scribe lines between the die areas (eg 311- 313) for the mechanical strength of wires (eg 311L-313L). The metal layers or wires in the dummy areas A _D1 and A _D2 may not be connected to other metal layers or wires, such as floating, and adding metal layers and wires in the above two areas can also protect the active area A _A1 the conductive stack in the semiconductor structure and increase the mechanical strength of the semiconductor structure as a whole.

5 is a cross-sectional view taken along a cross-sectional line 5-5 of the semiconductor structure in FIG. 3, wherein the cross-sectional line 5-5 passes through a position corresponding to the inter-die connection layer L _IC1 . Therefore, according to some embodiments of the present invention, FIG. 5 shows a plurality of inter-die connection layers L _IC1 passing through the seal ring region A _R1 of the semiconductor die 11-1 and the seal ring region A of the semiconductor die 11-2 _R2 . 6 shows a top view of semiconductor dies 11-1 and 11-2 in which the inter-die connection layer L _IC1 passes through the recess 21R of the seal ring R _S1 and the recess 22R of the seal ring R _S2 . As shown in FIG. 6 , the concave portions 21R of the seal ring R _S1 are arranged side by side in the second direction D2 (eg, the Y direction). The concave portions 22R of the seal ring R _S2 opposite to the concave portions 21R of the seal ring R _S1 are arranged in the second direction D2 (eg, the Y direction) and separated from each other. It should be noted that in Figures 5, 6 and 4, similar or identical reference numerals are used to denote similar or identical features/components, and details of similar or identical features/components (eg their construction and materials) are This will not be repeated. In this embodiment, the inter-die connection layers 421 , 422 and 433 are electrically insulated from the sealing ring (eg, the sealing ring R _S1 , the sealing ring R _S2 ). In the prior art, at the positions of the recesses 21R and 31R is the structure of the seal ring (for example, the structure of the seal ring formed by stacking metal layers), because there is no need here in the prior art (the positions of the recesses 21R and 31R) Spaces are reserved to provide connections between dies (in the prior art, dies are all cut into individual dies, and the individual dies after division are connected through a substrate or a redistribution layer structure). In the embodiment of the present invention, the structure of the sealing ring existing in the prior art is absent, or the sealing ring structure in the prior art is removed, thereby forming (or assuming to be formed) the concave portions 21R and 31R, which are used in this embodiment. Inter-die connection layers 421 , 422 and 433 are passed through and formed in the recesses 21R and 31R to electrically connect adjacent die. In addition, the inter-die connection layers 421 , 422 , and 433 in the embodiments of the present invention are different from the leads or wires in the prior art, which are drawn from the pads of one die to another. On the pad of a die, and the formation of the lead or wire is to use the lead or wire to connect outside the metal layer of the die; the inter-die connection layer in the present invention can be formed together with the metal layer in the die, The structure is obviously different, there is no need to reserve pads for inter-die connection, and the manufacturing process is also simpler and more convenient, while avoiding the shortcomings of the prior art that the wire bonding electrical connection is unstable and easily damaged.

As shown in FIGS. 5 and 6 , the adjacent portions of the seal rings RS1 and RS2 of the two adjacent semiconductor dies 11-1 and 11-2 have recesses 21R and 22R, and the inter-die connection layer L _IC1 passes through Recesses 21R and 22R. Each of the recesses 21R and 22R may correspond to one or both of the interconnected stacks of seal rings. In some embodiments, the second interconnect stack 212 of seal ring R _S1 has a first recess 211R, and the third interconnect stack 213 of seal ring R _S1 has a second recess 212R. The second recessed portion 212R communicates with the first recessed portion 211R. The first recessed portion 211R and the second recessed portion 212R form the recessed portion 21R of the seal ring R _S1 . Similarly, the second interconnect stack 222 of seal ring RS2 has a first recess _221R , and the third interconnect stack 223 of seal ring RS2 has a second recess 222R. The second recess 222R communicates with the first recess 221R. The first recessed portion 221R and the second recessed portion _222R form the recessed portion 22R of the seal ring RS2. The first concave portion 221R may have one or more inter-die connecting layers passing through it, the second concave portion 222R may have one or more inter-die connecting layers passing through it, and the concave portion 31R may have one or multiple crystal grains. The inter-connecting layer passes through, and the above can be freely set according to the design requirements.

In this example, three inter-die connection layers 421 , 422 and 423 (referred to as inter-die connection layers L _IC1 ) are constructed for electrically connecting two adjacent semiconductor dies. As shown in FIG. 5 , the inter-die connection layers 421 and 422 pass through the first concave portion 211R of the seal ring R _S1 and the first concave portion 221R of the seal ring R _S2 . In some embodiments, the inter-die connection layers 421 and 422, the second wire 212L of the second interconnect stack 212, and the second wire 222L of the second interconnect stack 222 are made of the same material (eg, a second metal layer (for example, M2)). Also, as shown in FIGS. 4 and 5 , the inter-die connection layers 421 and 422 are at the same level (same layer) as the second wires 212L and 222L. The inter-die connection layers 421 and 422 may connect the active elements of the semiconductor dies 11-1 and 11-2, and the inter-die connection layer 423 may also connect the active elements of the semiconductor dies 11-1 and 11-2. In addition, although there may be disconnections in the inter-die connecting layers 421, 422 and 423 in the figure, this is because the figure is a cross-sectional view, in fact, each of the inter-die connecting layers 421, 422 and 423 is are interconnected, not disconnected.

In addition, as shown in FIG. 5 , the inter-die connection layer 423 passes through the second concave portion 212R of the seal ring R _S1 and the second concave portion 222R of the seal ring R _S2 . In some embodiments, the inter-die connection layer 423 , the third wires 213L of the third interconnect stack 213 , and the third wires 223L of the third interconnect stack 223 are made of the same material (eg, a third metal layer (eg, M3) material). Also, as shown in FIGS. 4 and 5 , the inter-die connection layer 423 is at the same level (same layer) as the third wires 213L and 223L. The inter-die connection layer 423 may connect other active elements of the semiconductor die 11-1 and 11-2.

The first wires (eg, 211L and 221L) and the third wires (eg, 213L and 223L) may be made of different materials. The second wires (eg, 212L and 222L) and the third wires (eg, 213L and 223L) may be made of different materials. For example, the first wires (eg, 211L and 221L) and the second wires (eg, 212L and 222L) are made of copper (Cu), and the third wires (eg, 213L and 223L) are made of aluminum (Al). Additionally, in some embodiments, each of the first wires 211L and 221L has a first thickness t1, each of the second wires 212L and 222L has a second thickness t2, and each of the third wires 213L and 223L has a third thickness t3 , wherein the second thickness t2 is greater than the first thickness t1, and the third thickness t3 is greater than the second thickness t2. In some embodiments, each of the inter-die connection layers 421 , 422 , and 433 has a thickness (eg, t2 ) that is greater than a thickness (eg, t1 ) of each of the first wires 211L and 221L. Also, in some embodiments, the inter-die connection layer 423 , such as the inter-die connection layer formed by the third metal layer ( M3 ), has a third thickness t3 that is greater than the first conductive line 211L and the thickness of either of 221L (eg, t1). Additionally, in some embodiments, the third thickness t3 of the inter-die connection layer 423 is greater than the second thickness t2 of each of the inter-die connection layers 421 and 422 .

Additionally, in some embodiments, as shown in FIGS. 4 and 5 , each semiconductor die further includes a dummy area surrounding the active area and located between the seal ring area and the active area. For example, as described above, the dummy area A _D1 is formed between the seal ring area A _R1 and the active area AA1 of the semiconductor die 11-1, and the dummy area A _D2 is formed between the seal ring area A _R2 and the semiconductor die 11-2 between the active areas A and _A2 . In some embodiments, as shown in FIGS. 5 and 6 , the inter-die connection layer L _IC1 further passes through the concave portion 31R in the dummy area _AD1 and the concave portion 32R in the dummy area AD2 . As shown in FIG. 6 , the concave portions 31R in the dummy area A _D1 are arranged in the second direction D2 (eg, the Y direction) and separated from each other. The concave portions 32R in the dummy area A _D2 opposite to the concave portions 31R in the dummy area A _D1 are arranged in the second direction D2 (eg, the Y direction) and separated from each other.

It should be noted that the number of the inter-die connection layers L _IC1 may be varied and determined according to the design requirements of the semiconductor structure to be formed in the application. Some variations of the embodiments are provided below for illustration.

7A is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the present invention. 4 and 7A, two inter-die connection layers are formed as conductive bridges between adjacent semiconductor die. It should be noted that in Figures 7A and 4-5, similar or identical reference numerals are used to denote similar or identical features/components, and details of similar or identical features/components (eg, their construction and materials) are herein no more repetitions.

The difference between the semiconductor structure of FIG. 7A and the semiconductor structure of FIG. 5 lies in the number of inter-die connection layers L _IC1 for electrically connecting the semiconductor die 11 - 1 and 11 - 2 .

In FIG. 7A , two inter-die connection layers L _IC1 (including one inter-die connection layer 423 and one inter-die connection layer 422 ) are configured to electrically connect two adjacent semiconductor dies. As shown in FIG. 7A , in some embodiments, the inter-die connection layer 422 passes through the first recess 211R' of the seal ring _RS1 and the first recess _221R ' of the seal ring RS2. In addition, in this example, the inter-die connection layer 422 further penetrates the concave portion 31R in the dummy area _AD1 and the concave portion 32R in the dummy area AD2, as shown in FIG. 7A . In some embodiments, the inter-die connection layer 422 , the second wires 212L of the second interconnect stack 212 , and the second wires 222L of the second interconnect stack 222 are made of the same material (eg, the second metal layer (eg, M2 )) ) material). Also, the inter-die connection layer 422 is flush with one of the second conductive lines 212L or 222L. For example, the inter-die connection layer 422 is flush with the uppermost layers of the second wires 212L and 222L, as shown in FIG. 7A .

In addition, as shown in FIG. 7A , the inter-die connection layer 423 passes through the second recessed portion _212R of the seal ring RS1 and the second recessed portion _222R of the seal ring RS2. In addition, in this example, the inter-die connection layer 423 further passes through the concave portion 31R in the dummy area AD1 and the concave portion 32R in the dummy area AD2, as shown in FIG. 7A . In some embodiments, the inter-die connection layer 423 , the third wires 213L of the third interconnect stack 213 , and the third wires 223L of the third interconnect stack 223 are made of the same material (eg, a third metal layer (eg, M3))) made of material). Also, the inter-die connection layer 423 is flush with the third wires 213L and 223L, as shown in FIGS. 4 and 7A . The inter-die connection layer 422 may connect active elements of the semiconductor dies 11-1 and 11-2, and the inter-die connection layer 423 may connect other active elements of the semiconductor dies 11-1 and 11-2.

In addition, the concave portion 21R of the seal ring R _{S1 and the concave portion 22R of the seal ring R S2 in FIG. 5 are deeper than the concave portion 21R′ of the seal ring R S1 and the} concave portion 22R′ of the seal ring R _S2 in FIG. 7A , and the deeper depth can accommodate more Multi-layer inter-die connection layer. For example, the first recesses 211R and 221R in FIG. 5 (through which the two inter-die connection layers 421 and 422R pass) are larger than the first recesses 211R' and 221R' in FIG. 7A (through which the one inter-die connection layer 422 passes) Deeper.

7B is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the present invention. 4 and 7B, an inter-die connection layer is formed as a conductive bridge between adjacent semiconductor die, and a seal ring is formed from two interconnect stacks. It should be noted that in Figures 7B and 4-5, similar or identical reference numerals are used to denote similar or identical features/components, and details of similar or identical features/components (eg, their construction and materials) are herein no more repetitions.

Differences between the semiconductor structure of FIG. 7B and the semiconductor structure of FIG. 5 include the number of interconnect stacks of seal rings and the number of inter-die connection layers L _IC1 for electrically connecting semiconductor dies 11 - 1 and 11 - 2 .

In Figure 7B, two interconnect stacks on base layer 10 form a seal ring for the semiconductor die. For example, the seal ring R _S1 of the semiconductor die 11 - 1 includes a first interconnect stack 211 over the base layer 10 and a second interconnect stack 212 over the first interconnect stack 211 , wherein the first interconnect stack 211 and the second interconnect stack 212 surrounds the active area AA1. The first interconnect stack 211 includes a plurality of first wires 211L and first conductive vias 211V connecting the first wires 211L. The second interconnect stack 212 includes a plurality of second wires 212L and second conductive vias 212V, wherein the second conductive vias 212V connect two adjacent second wires 212L and connect the lowermost second wire 212L and the uppermost of the first wire 211L. In some embodiments, the first wires 211L of the first interconnect stack 211 are formed from a first metal layer (eg, M1 ), and the second wires 212L of the second interconnect stack 212 are formed from a second metal layer (eg, M2 ) )form.

In addition, as shown in FIG. 7B , the active area AA1 of the semiconductor die 11-1 includes a first conductive stack 311 located above the base layer 10 and a second conductive stack 312 located on the first conductive stack 311 for forming a semiconductor The integrated circuit of die 11-1. In some embodiments, the first conductive stack 311 includes several wires 311L and several conductive vias 311V. The second conductive stack 312 includes two conductive lines 312L and several conductive vias 312V. The second conductive stack 312 is electrically connected to the first conductive stack 311 . The first conductive stack 311 may electrically connect one or more active elements (eg, transistors) in the base layer 10 . In some embodiments, wires 311L of the first conductive stack 311 are formed from a first metal layer (eg, M1 ), and wires 312L of the second conductive stack 312 are formed from a second metal layer (eg, M2 ) form.

Similarly, in some embodiments, as shown in FIG. 7B , the seal ring RS2 of the semiconductor die 11 - 2 includes a first interconnect stack 221 over the base layer 10 and a second interconnect stack 221 over the first interconnect stack 221 An interconnect stack 222, wherein the first interconnect stack 221 and the second interconnect stack 222 surround the active area AA2. The first interconnect stack 221 includes a plurality of first wires 221L and first conductive vias 221V connecting the first wires 221L. The second interconnect stack 222 includes a plurality of second wires 222L and second conductive vias 222V, wherein the second conductive vias 222V connect two adjacent second wires 222L and connect the lowermost second wires 222L and the uppermost of the first wire 221L. In some embodiments, the first wires 221L of the first interconnect stack 221 are formed from a first metal layer (eg, M1 ), and the second wires 222L of the second interconnect stack 222 are formed from a second metal layer (eg, M2 ) )form.

Furthermore, in this example, as shown in FIG. 7B , the active area AA2 of the semiconductor die 11 - 2 includes a first conductive stack 321 over the base layer 10 and a second conductive stack 322 over the first conductive stack 321 , for forming the integrated circuit of the semiconductor die 11-2. In some embodiments, the first conductive stack 321 includes several wires 321L and several conductive vias 321V. The second conductive stack 322 includes two conductive lines 322L and several conductive vias 322V. The second conductive stack 322 is electrically connected to the first conductive stack 321 . The first conductive stack 321 may electrically connect one or more active elements (eg, transistors, not shown) in the base layer 10 . In some embodiments, the wires 321L of the first conductive stacks 321 of the first conductive stacks 321 are formed from a first metal layer (eg, M1 ), the wires of the second conductive stacks 322 322L is formed of a second metal layer (eg, M2).

In FIG. 7B, the inter-die connection layer 422 is configured to electrically connect two adjacent semiconductor die. For example, the power element of the semiconductor die 11-1 is electrically connected to the power element of the semiconductor die 11-2 through the inter-die connection layer 422. As shown in FIG. 7B, in some embodiments, the inter-die connection layer 422 passes through the recess 21R" of the seal ring RS1 and the recess 22R" of the seal ring RS2. In addition, in this example, the inter-die connection layer 422 further penetrates the concave portion 31R in the dummy area AD1 and the concave portion 32R in the dummy area AD2, as shown in FIG. 7B . In some embodiments, the inter-die connection layer 422 , the second wires 212L of the second interconnect stack 212 , and the second wires 222L of the second interconnect stack 222 are made of the same material (eg, the second metal layer (eg, M2 )) material) is made. Also, the inter-die connection layer 422 is flush (at the same layer, or at the same level) with one of the second conductive lines 212L or 222L. For example, the inter-die connection layer 422 is flush with the uppermost layers of the second wires 212L and 222L, as shown in FIG. 7B .

Although in some embodiments, the above-described inter-die connection layer is formed in the concave portion of the seal ring of the semiconductor die, the present invention is not limited thereto. In some other embodiments, an inter-die connection layer may be formed over the seal ring of two adjacent semiconductor dies in the die region without recessing any portion of the seal ring.

8 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention. It should be noted that in Figures 8 and 4, 5, 7A and 7B, similar or identical reference numerals are used to denote similar or identical features/components, and similar or identical features/components (eg, their structure and materials) are not repeated here.

As shown in FIG. 8 , each seal ring includes several interconnect stacks above the base layer 10 . For example, the seal ring R _S1 of the semiconductor die 11-1 includes a first interconnect stack 211 over the base layer 10 and surrounding the active area A _A1 , on the first interconnect stack 211 and surrounding the active area A _A1 A second interconnect stack 212, and a third interconnect stack 213 on the second interconnect stack 212 and surrounding the active area A _A1 . The seal ring _RS2 of the semiconductor die 11-2 includes a first interconnect stack 221 over the base layer 10 and surrounding the active area A _A2 , a second interconnect stack 221 on the first interconnect stack 221 and surrounding the active area A _A2 An interconnect stack 222, and a third interconnect stack 221 located on the second interconnect stack 222 and surrounding the active area A _A2 .

In some embodiments, as shown in FIG. 8, an inter-die connection layer 501 is formed over those interconnect stacks (eg, 211/212/213 and 221/222/223). Likewise, the inter-die connection layer 501 extends on adjacent portions of the seal ring RS1 in the seal ring region A _R1 and the seal ring RS2 in the seal ring region A _R2 of the semiconductor die 11-1 and 11-2. The inter-die connection layer 501 may connect the active elements of the semiconductor die 11-1 and 11-2 through the conductive via 501V, thereby serving as a bridge between the semiconductor die 11-1 and 11-2.

Additionally, in some embodiments, as shown in FIG. 8 , the inter-die connection layer 501 and the interconnect stack (eg, 211 - 213 and 221 - 223 of seal rings R _S1 and R _S2 ) are made of the same material. However, the present invention is not limited to this. The material of the inter-die connection layer 501 may be the same or different from that of the uppermost wires (eg, the third wires 213L and 223L) of the seal rings R _S1 and R _S2 .

9A is a top view of a multi-die component 120 in accordance with some embodiments of the invention. After a wafer sawing process along the scribe lines between the die regions on the wafer (as shown in Figure 2), several multi-die parts can be obtained. Each multi-die component may include two or more semiconductor dies. In this example, as shown in FIG. 9A, a multi-die component 120 including four semiconductor dies 11-1, 11-2, 11-3, and 11-4 is illustrated. It should be noted that in Figures 9A, IB and 3, similar or identical reference numerals are used to denote similar or identical features/components. The semiconductor dies 11-1, 11-2, 11-3, and 11-4 (eg, structures and materials) and related elements (eg, the sealing frame F _S , the first space SP1 , the second space SP2 , and the crystals) have been described above Details of the intergranular junction layers L _IC1 -L _IC4 and will not be repeated.

9B is a cross-sectional view of a package structure 120P including the multi-die feature 120 of FIG. 9A in accordance with some embodiments of the present invention. FIG. 9B only shows semiconductor dies 11 - 1 and 11 - 2 of multi-die component 120 in package structure 120P due to the cross-sectional view. Additionally, it should be noted that, depending on the design requirements of the application, two or more multi-die components may be arranged on the substrate of the package structure. To simplify the figure, one multi-die component 120 is disposed on the substrate 100 of the package structure 120P.

In some embodiments, the package structure 120P includes a substrate 100 and a multi-die feature 120 bonded to the substrate 100 . In this example, as shown in FIG. 9B, the substrate 100 has a first surface 100a and a second surface 100b opposite to the first surface 100a. The substrate 100 includes a redistribution pattern 100L having a redistribution layer (RDL) and other elements (eg, conductive vias and conductive pads). The arrangement of the redistribution patterns 100L is determined according to the substrate design of the present application. In some embodiments, the multi-die feature 120 is disposed on the first surface 100a of the substrate 100 , and the multi-die feature 120 is electrically coupled to the redistribution layer of the redistribution pattern 100L in the substrate 100 .

In some embodiments, the substrate 100 further includes an inter-metal dielectric (IMD) layer 100M, and the redistribution pattern 100L is embedded in the inter-metal dielectric layer 100M. In some embodiments, the IMD layer may be formed of organic materials including polymer base materials, non-organic materials including silicon nitride (SiNx), silicon oxide (SiOx), graphene, and the like. For example, the intermetal dielectric layer is made of a polymer base material. It should be noted that the numbers and configurations of IMD layers, conductive pads, conductive vias and redistribution layers shown in FIG. 9B are exemplary only and do not limit the present invention.

In some embodiments, multi-die feature 120 is on base layer 10 and includes a plurality of semiconductor die, such as semiconductor die 11-1, 11-2, 11-3, and 11-4 of FIG. 9A. Also, the semiconductor dies 11-1, 11-2, 11-3, and 11-4 are disposed on the top surface 101 of the base layer 10 (under the base layer 10 as seen in FIG. 9B), and are spaced apart from each other. In some embodiments, as shown in FIG. 9B , the package structure 120P further includes a plurality of conductive structures 113 , wherein the multi-die component 120 is bonded to the substrate 100 through the conductive structures 113 . As shown in FIG. 9B , the top surface 101 of the base layer 10 of the multi-die part 120 faces the first surface 100 a of the substrate 100 . The conductive structure 113 is disposed over the first surface 100a of the substrate 100 and under the first semiconductor dies 11-1 and 11-2.

In addition, an inter-die connection layer L _IC is formed to electrically connect two adjacent semiconductor die. For example, as shown in FIGS. 9A and 9B , the inter-die connection layer L _IC1 electrically connects the semiconductor die 11 - 1 and 11 - 2 as a conductive bridge between the semiconductor die 11 - 1 and 11 - 2 . Likewise, the inter-die connection layer L _IC extends over the seal rings (such as seal rings R _S1 and R _S2 ) of two adjacent semiconductor dies, as described in the above description. Likewise, the inter-die connection layer L _IC passes through the space between two adjacent semiconductor dies of the multi-die component 120 . For example, as shown in FIG. 9B, the inter-die connection layer L _IC1 passes through the second space SP2 between the first semiconductor die 11-1 and the second semiconductor die 11-2. Additionally, in some embodiments, as shown in FIG. 9B , when the multi-die component 120 is bonded to the substrate 100 , the inter-die connection layer L _IC is located between the top surface 101 and the first surface of the base layer 10 . Details such as the structure and material of the inter-die connection layer LIC have been described above, and will not be repeated here.

In some embodiments, as shown in FIG. 9B , the package structure 120P further includes a molding material 110 surrounding the semiconductor dies 11 - 1 , 11 - 2 , 11 - 3 , and 11 of the multi-die component 120 -4 and fill the space. The molding material 110 adjoins the sidewalls of the semiconductor dies 11-1, 11-2, 11-3, and 11-4. That is, the semiconductor dies 11 - 1 , 11 - 2 , 11 - 3 and 11 - 4 are separated from each other through the molding material 110 . Furthermore, the molding material 110 encapsulates the inter-die connection layer L _IC extending between the semiconductors, and the inter-die connection layer L _IC passes through the molding material 110 . For example, as shown in FIG. 9B , the semiconductor dies 11 - 1 and 11 - 2 are separated from each other through the molding material 110 . The inter-die connection layer L _IC1 between the semiconductor die 11 - 1 and 11 - 2 passes through the molding material 110 .

In some embodiments, molding material 110 includes a non-conductive material, such as epoxy, resin, moldable polymer, or another suitable molding material. In some embodiments, the molding material 110 is applied while being substantially liquid and then cured through a chemical reaction. In some other embodiments, the molding material 110 is an ultraviolet (UV) or thermally cured polymer applied as a gel or malleable solid and then cured by a UV or thermal curing process. The molding material 110 may be cured with a mold (not shown).

In some embodiments, the surfaces of the semiconductor die 11-1 and 11-2 facing away from the first surface 100a of the substrate 100 are exposed by the molding material 110 so that a heat sink (not shown) can be attached directly to the semiconductor die on the surface of grains 11-1 and 11-2. Therefore, the heat dissipation efficiency of the semiconductor package structure 120P can be improved, especially for a large semiconductor package structure, eg, 50 mm×50 mm, which is preferable for high power applications.

In some embodiments, as shown in FIG. 9B , the package structure 120P further includes a polymer material 115 disposed under the molding material 110 , the semiconductor dies 11 - 1 and 11 - 2 , and between the conductive structures 113 . Structure 120P may further include an underfill layer (not shown) disposed between first surface 100a of substrate 100 and polymer material 115 . In some embodiments, semiconductor dies 11-1 and 11-2 and molding material 110 are surrounded by an underfill layer. The polymer material 115 and/or the underfill layer are provided to compensate for the different coefficients of thermal expansion (CTE) between the substrate 100, the conductive structure 113, and the semiconductor die 11-1 and 11-2.

The package structure 120P of FIG. 9B may be mounted on a board (not shown). In some embodiments, the package structure 120P may be a system-in-package (SIP) structure. Also, the board may include a printed circuit board (PCB) and may be formed of polypropylene (PP). The package structure 120P can be mounted on the board through a bonding process. For example, the package structure 120P further includes bump structures (not shown) on the second surface 100b of the substrate 100 . The bump structures may be conductive ball structures (eg, ball grid array (BGA)), conductive post structures, or conductive paste structures, which are mounted on and electrically coupled to a board (eg, a PCB) through a bonding process.

According to some of the above-described embodiments, the semiconductor structure and the package structure having the multi-die components obtained from the semiconductor structure achieve a number of advantages. After performing the wafer sawing process, a plurality of multi-die components can be obtained. In some embodiments, each multi-die component includes several semiconductor dies. The semiconductor die of a multi-die component may have the same function. In addition, in some embodiments, two adjacent semiconductor dies of a multi-die component are electrically connected to each other through one or more inter-die connection layers L _IC (as shown in FIG. 1B , FIG. 3 , FIG. 5 , FIG. 6 , 7A, 7B and 8). According to some embodiments of the present invention, a package structure may be formed by bonding one or more multi-die components to a substrate. Through the inter-die connection layer L _IC , electrical communication between adjacent semiconductor die can be achieved through the shortest path. Thus, the semiconductor die of the multi-die component can provide fast and reliable signal transmission through the inter-die connection layer. The inter-die connection layer L _IC1 may extend over seal ring regions of adjacent semiconductor dies of the multi-die component. In some embodiments, the seal rings of adjacent semiconductor dies have recesses, and the one or more inter-die connection layers pass through the recesses of the seal rings. In some other embodiments, one or more inter-die connection layers extending over the seal ring region are formed over the interconnect stack of the seal ring. In a conventional package structure (or semiconductor package), dies are individually bonded on a substrate and can be electrically connected to each other through redistribution layers in the substrate. Also, each die obtained from a conventional wafer may comprise a single semiconductor die. According to some embodiments, each multi-die component obtained from a wafer may include two or more semiconductor dies, and the package structure uses on-die wiring (eg, inter-die connection layer L _IC ) to integrate multiple Grains of semiconductor grains. mold parts. Compared to package structures that include a plurality of dies from a conventional wafer (each die is a single semiconductor die), a package structure that includes a multi-die component with a plurality of loss and/or power for better electrical performance. Losses between semiconductor dies in multi-die components (multi-die components are electrically connected to each other through the inter-die connection layer L _IC ) can be significantly reduced.

It should be noted that the details of the structure of the embodiments are provided for the purpose of illustration, and the details of the description of the embodiments are not intended to limit the invention. It should be noted that not all embodiments of the invention are shown. Modifications and variations can be made to meet practical application requirements without departing from the spirit of the present invention. Accordingly, other embodiments of the invention not specifically shown may exist. Furthermore, the drawings are simplified to clearly illustrate the embodiments. Dimensions and proportions in the drawings may not be proportional to the actual product. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Although the embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made in the present invention without departing from the spirit of the invention and the scope defined by the scope of the claims. The described embodiments are in all respects for illustrative purposes only and are not intended to limit the invention. The protection scope of the present invention shall be determined by the scope of the appended patent application. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention.

10: base layer 11, 11-1, 11-2, 11-3, 11-4: semiconductor die 12, 13, 12-1, 12-2, 12-3, 12-4, 13-1, 13 -2: Die regions L _IC , L _IC1 , L _IC2 , L _IC3 , L _IC4 : Inter-die connection layer SP: Spacer pattern SP1: First space SP2: Second space F _S , F _S1 , F _S2 , F _S3 ,F _S4 ,F _S5 ,F _S6 : Sealing frame A _A1 ,A _A2 ,A _A3 ,A _A4 : Active area R _S1 ,R _S2 ,R _S3 ,R _S4 : Sealing ring 4-4,5-5: Section line LS1: first scribe line LS2: second scribe line A _D1 , A _D2 : dummy area A _R1 , A _R2 : seal ring area 211, 221, 311, 321: first interconnect stack 212, 222, 312, 322: second interconnect stack 213, 223, 313, 323: third interconnect Connected stacks 211V, 221V: first conductive vias 211L, 221L: first conductive vias 212V, 222V: second conductive vias 212L, 222L: second conductive vias 213V, 223V: third conductive vias 213L, 223L: third conductive line t1: first thickness t2: second thickness t3: third thickness 311V, 312V, 313V, 321V, 322V, 323V, 501V: conductive vias 321D, 322D, 323D: wires 211R, 211R', 221R: first recesses 212R, 212R', 222R: second recesses 21R, 21R';21R'', 22R, 22R', 22R'', 31R, 32R: recesses 421, 422, 423, 501: Inter-die connection layer 120: Multi-die component 120P: Package structure 102: Bottom surface 101: Top surface 115: Polymer material 100: Substrate 100a: First surface 100b: Second surface 100M: Intermetal dielectric layer 100L : Redistribution pattern

The present invention can be more fully understood by reading the ensuing detailed description and examples, which are given with reference to the accompanying drawings, wherein: 1A and 1B are top views of intermediate stages of a method for forming a semiconductor structure according to some embodiments of the present invention. 2 is a top view of a semiconductor structure according to some embodiments of the present invention. 3 is a top view of a die region of a semiconductor structure according to some embodiments of the present invention. FIG. 4 is a cross-sectional view taken along cross-sectional line 4 - 4 of the semiconductor structure in FIG. 3 . FIG. 5 is a cross-sectional view taken along cross-sectional line 5 - 5 of the semiconductor structure in FIG. 3 . 6 is a top view of two adjacent semiconductor dies within the die region of FIG. 3 in accordance with some embodiments of the present invention. 7A is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the present invention. 7B is a cross-sectional view of a semiconductor structure in accordance with some embodiments of the present invention. 8 is a cross-sectional view of a semiconductor structure according to some other embodiments of the present invention. 9A is a top view of a multi-die component according to some embodiments of the present invention. 9B is a cross-sectional view of a package structure including the multi-die component of FIG. 9A in accordance with some embodiments of the present invention.

10: Basal layer

11-1, 11-2, 11-3, 11-4: Semiconductor Die

12: Die area

L _IC , L _IC1 , L _IC2 , L _IC3 , L _IC4 : inter-die connection layer

SP: Spacer Pattern

SP1: First Space

SP2: Second space

F _S : Sealed frame

A _A1 ,A _A2 ,A _A3 ,A _A4 : Active area

R _S1 , R _S2 , R _S3 , R _S4 : seal ring

4-4,5-5: Section line

Claims (25)

A semiconductor structure comprising: a base layer; semiconductor die on the base layer, each of the semiconductor die including an active region and a seal ring region including a seal ring surrounding the active region; and a die an inter-die connection layer electrically connecting two adjacent semiconductor die, and the inter-die connection layer extends on adjacent portions of the seal ring in the seal ring region of the two adjacent semiconductor die; wherein the seal ring of each of the semiconductor die includes: a first interconnect stack over the base layer and surrounding the active region, wherein the first interconnect stack includes a first wire; and a second interconnect stack , above the first interconnect stack and surrounding the active region, wherein the second interconnect stack includes a second wire; wherein the second wire and the inter-die connection layer are formed together from the same material. The semiconductor structure of claim 1, wherein adjacent portions of the seal ring of the two adjacent semiconductor dies have recesses, and the inter-die connection layer passes through the recesses. The semiconductor structure of claim 1, wherein the inter-die connection layer and a conductive layer of the seal ring are at the same level. The semiconductor structure of claim 1, wherein the second interconnect stack has a first recess, and the inter-die connection layer passes through the first recess. The semiconductor structure of claim 4, wherein the inter-die connection layer is flush with one of the second wires. The semiconductor structure of claim 4, wherein the second wire and the inter-die connection layer are made of the same material. The semiconductor structure of claim 3, wherein the thickness of the inter-die connection layer is large on the thickness of one of the first wires. The semiconductor structure of claim 3, wherein the seal ring of each of the semiconductor die further comprises: a third interconnect stack on the second interconnect stack and surrounding the active region, wherein the third interconnect The stack includes a third wire, wherein the second interconnect stack has a first recess, the third interconnect stack has a second recess, and the second recess communicates with the first recess. The semiconductor structure of claim 8, wherein the inter-die connection layer passes through the first recess and/or the second recess. The semiconductor structure of claim 8, wherein the inter-die connection layer passes through the first recess, and the semiconductor structure further includes another inter-die connection layer that passes through the second inter-die connection layer recess. The semiconductor structure of claim 10, wherein the inter-die connection layer is flush with one of the second wires, and the other inter-die connection layer is flush with one of the third wires. The semiconductor structure of claim 10, wherein the third wire and the other inter-die connection layer are made of the same material. The semiconductor structure of claim 10, wherein the inter-die connection layer and the other inter-die connection layer are made of different materials. The semiconductor structure of claim 10, wherein the thickness of the inter-die connection layer is greater than that of one of the first wires, and the thickness of the other inter-die connection layer is greater than that of one of the second wires. The semiconductor structure of claim 10, wherein the thickness of the other inter-die connection layer is greater than the thickness of the inter-die connection layer. Such as the semiconductor structure of claim 1, also include: A sealing frame on the base layer, wherein the sealing frame surrounds the semiconductor die and defines a die area. The semiconductor structure of claim 16, wherein the semiconductor dies in the die region are spaced apart from each other. The semiconductor structure of claim 16, wherein the semiconductor die in the die region have the same function. The semiconductor structure of claim 1, wherein the semiconductor die on the base layer are separated from each other by a spacer pattern, the spacer pattern comprising: a first space extending in a first direction; and a second space extending in a second direction , wherein the first direction is different from the second direction. The semiconductor structure of claim 19, further comprising: a plurality of scribe lines passing through the first space and a portion of the second space. The semiconductor structure of claim 1, wherein the seal ring includes a plurality of interconnect stacks over the base layer, and the inter-die connection layer is formed over the plurality of interconnect stacks. The semiconductor structure of claim 21, wherein the uppermost conductive layer and the inter-die connection layer in the plurality of interconnect stacks are made of the same material. The semiconductor structure of claim 1, wherein the inter-die connection layer is electrically insulated from the seal ring. The semiconductor structure of claim 1, wherein the base layer includes active devices electrically connected to each semiconductor die. A package structure comprising: a substrate having a first surface and a second surface opposite the first surface, wherein the substrate includes a redistribution layer; a multi-die component disposed over the first surface of the substrate and electrically coupled Redistribution connected to the substrate a cloth layer, wherein the multi-die component comprises: a base layer; a plurality of semiconductor die on the base layer and spaced apart from each other; and an inter-die connection layer electrically connecting two adjacent semiconductor die; wherein , the inter-die connection layer extends on the seal ring in the seal ring region of two adjacent semiconductor die; wherein, the seal ring of each semiconductor die includes: a first interconnect stack, on the substrate a layer over and around the active region, wherein the first interconnect stack includes a first wire; and a second interconnect stack over and around the active region, wherein the second interconnect stack A second wire is included; wherein the second wire and the inter-die connection layer are formed together with the same material.

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