TWI764514B - Method of automatically selecting equalizer gear - Google Patents

Abstract

A method of automatically selecting equalizer gear applied to a display apparatus is disclosed. The display apparatus includes a display panel, a plurality of source driving circuits and a timing control circuit. The plurality of source driving circuits includes a plurality of equalizers respectively. The method includes steps of: coupling the timing control circuit to the plurality of source driving circuits and coupling the plurality of source driving circuits to the display panel; and the timing control circuit and the plurality of source driving circuits communicating training results of the plurality of equalizers with each other through at least one bidirectional control signal to realize the synchronization of display data transmission.

Description

How to automatically select the equalizer gear

The present invention relates to a display device, and more particularly, to a method for automatically selecting an equalizer gear position applied to a display device.

Generally speaking, as shown in FIG. 1 , the display device 1 includes a display panel PL, source driving circuits SD1 to SDN, and a timing control circuit TCON. The timing control circuit TCON is respectively coupled to the source driving circuits SD1 to SDN through wires. The source driving circuits SD1 ˜SDN are respectively coupled to different display regions of the display panel PL.

However, as the size of the display panel PL increases and its resolution increases, due to the positional difference between the source driver circuits SD1 to SDN, the timing control circuit TCON is coupled to the source driver circuits SD1 to SDN. The length of the line is different, and the channel loss (Channel loss) it produces will become non-negligible. Especially when the timing control circuit TCON outputs timing control signals to the source driver circuits SD1 to SDN, it is very likely that the source driver circuits SD1 to SDN will receive errors due to channel loss, which needs to be improved urgently.

In view of this, the present invention proposes a method for automatically selecting an equalizer gear for a display device, so as to effectively solve the above-mentioned problems encountered in the prior art.

One specific embodiment according to the present invention is a method for automatically selecting an equalizer gear. In this embodiment, the method for automatically selecting an equalizer gear is applied to a display device. The display device includes a display panel, a plurality of source driving circuits and a timing control circuit. The plurality of source driving circuits respectively include a plurality of equalizers. The method includes the following steps: coupling a timing control circuit to the plurality of source driving circuits and the plurality of source driving circuits to a display panel; and at least one bidirectional transmission between the timing control circuit and the plurality of source driving circuits The control signals communicate the training results of the plurality of equalizers with each other, so as to realize the synchronization of display data transmission.

In one embodiment, the iSP transmission mode is used for point-to-point data transmission between the timing control circuit and the plurality of source driving circuits.

In one embodiment, the timing control circuit transmits a training pattern with a specific frequency to the plurality of source driving circuits.

In one embodiment, when the plurality of source driving circuits respectively receive training patterns with a specific frequency, the plurality of source driving circuits are synchronized with the specific frequency and train the plurality of equalizers.

In one embodiment, when the plurality of source driving circuits respectively complete the training of the plurality of equalizers, the plurality of source driving circuits respectively feed back signals of the plurality of equalizers through the plurality of equalizers. The training result is sent to the timing control circuit.

In one embodiment, when the timing control circuit receives the feedback signals from the plurality of equalizers and determines that the training results of the plurality of equalizers are correct, the timing control circuit starts to transmit display data to the plurality of sources. Drive circuit.

In one embodiment, the at least one bidirectional control signal includes a lock signal including a training pattern having a specific frequency.

In one embodiment, the at least one bidirectional control signal includes an equalizer feedback signal including an equalizer training result.

In one embodiment, the timing control circuit includes a transmitter control unit, a clock generation unit, a parallel rotation sequence unit, a pre-emphasis unit, and a transmitter drive unit. The transmitting end control unit is used for controlling the data transmission process in the timing control circuit. The clock generating unit is coupled to the control unit for generating a clock signal with a specific frequency. The parallel-to-serial unit is coupled to the control unit and the clock generation unit, and is used for converting parallel data into serial data according to the clock signal. The pre-emphasis unit is coupled to the control unit for generating a pre-emphasis setting. The transmission-end driving unit is coupled to the parallel rotation sequence unit and the pre-emphasis unit, and is used for processing the sequence data according to the pre-emphasis setting and then outputting the sequence data through the transmission-end pins.

In one embodiment, each source driver circuit includes an equalizer, a clock data recovery (CDR) unit, a serial-to-parallel unit, and a receiver control unit, respectively. The equalizer receives serial data through the receiver pins. The clock data recovery unit is coupled to the equalizer and used for obtaining clock signals from the serial data. The serial-to-parallel unit is coupled to the equalizer and the clock data recovery unit, and is used for converting the serial data into parallel data according to the clock signal. The receiver control unit is coupled to the serial-to-parallel unit for controlling the data transmission process in the source driving circuit.

In one embodiment, the transmitting-end control unit and the receiving-end control unit communicate through the at least one bidirectional control signal, and the at least one bidirectional control signal determines its control direction according to different mode settings.

In one embodiment, the at least one bidirectional transmission control signal includes a lock signal including a training pattern having a specific frequency.

In one embodiment, the at least one bidirectional transmission control signal includes an equalizer feedback signal including an equalizer training result.

In one embodiment, the plurality of source driving circuits can be set at the same time or set in series.

In one embodiment, the at least one bidirectional control signal includes a lock signal and an equalizer feedback signal.

In one embodiment, when the lock signal and the equalizer feedback signal are both at low levels, the plurality of source driving circuits perform clock synchronization training to synchronize with the timing control circuit.

In one embodiment, when the lock signal changes from a low level to a high level and the equalizer feedback signal remains at a low level, the plurality of source driving circuits perform training of the plurality of equalizers.

In one embodiment, when the equalizer feedback signal changes from a low level to a high level and the lock signal remains at a high level, the plurality of source driving circuits train the plurality of equalizers through the equalizer feedback signal. The result is sent back to the timing control circuit.

In one embodiment, when the timing control circuit receives the training results of the plurality of equalizers, the timing control circuit determines whether the training results of the plurality of equalizers are correct.

In one embodiment, if the above determination result is yes, the timing control circuit changes the lock signal from a high level to a low level and maintains the equalizer feedback signal at a high level to start transmitting display data to the plurality of source drivers. circuit; if the above judgment result is no, the timing control circuit will change both the lock signal and the equalizer feedback signal to a low level, causing the plurality of source driving circuits to perform clock synchronization training again.

Compared with the prior art, the present invention provides a method for automatically selecting an equalizer gear for a display device, which utilizes at least one bidirectional control signal (eg, a lock signal Lock, an equalizer feedback signal EQFB) to control a source electrode The state setting of the equalizer (EQ) in the driver can improve the stability of selecting the equalizer gear, so it can effectively avoid the channel loss caused by the different lengths of the wiring between the timing controller and each source driver. cause a reception error.

The advantages and spirit of the present invention can be further understood from the following detailed description of the invention and the accompanying drawings.

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Elements/components using the same or similar numbers in the drawings and the embodiments are intended to represent the same or similar parts.

One specific embodiment according to the present invention is a method for automatically selecting an equalizer gear. In this embodiment, the method of automatically selecting the equalizer gear is applied to the display device, and the type of the display device is not particularly limited. The display device includes a display panel, a plurality of source driving circuits and a timing control circuit. The plurality of source driving circuits are respectively coupled to different display areas of the display panel. The plurality of source driving circuits respectively include a plurality of equalizers. The plurality of source driving circuits can be set at the same time or can be set continuously in series.

Please refer to FIG. 2 . FIG. 2 is a schematic diagram illustrating a structure of the present invention using a point-to-point iSP transmission method between a timing control circuit serving as a transmitting end and a plurality of source driving circuits serving as a receiving end.

As shown in FIG. 2 , the timing control circuit TCON as the transmitting end (TX) includes transmitters TX1 to TXK, a lock signal detector LD and an equalizer feedback signal detector ED, where K is a positive integer. The transmitters TX1 ˜TXK are respectively coupled to a plurality of source driving circuits SD1 ˜SDK serving as the receiving end (RX). The lock signal detector LD is coupled to the wire for transmitting the lock signal LOCK. The equalizer feedback signal detector ED is coupled to the wire used for transmitting the equalizer feedback signal EQFB.

。開關M12耦接用以傳輸等化器回饋訊號EQFB之導線且其閘極受控於反相等化器回饋訊號

。 For the source driver circuit SD1 in the plurality of source driver circuits SD1 ˜SDK, the source driver circuit SD1 includes a receiver RX1 and switches M11 ˜ M12 . The receiver RX1 is coupled to the transmitter TX1 and receives the signal transmitted by the transmitter TX1. The switch M11 is coupled to the wire for transmitting the lock signal LOCK and its gate is controlled by the inverting lock signal

. The switch M12 is coupled to the wire for transmitting the equalizer feedback signal EQFB and its gate is controlled by the inverse equalizer feedback signal

.

。開關MK2耦接用以傳輸等化器回饋訊號EQFB之導線且其閘極受控於反相等化器回饋訊號

。其餘可依此類推，於此不另行贅述。 For the source driver circuit SDK among the plurality of source driver circuits SD1 to SDK, the source driver circuit SDK includes a receiver RXK and switches MK1 to MK2. The receiver RXK is coupled to the transmitter TXK and receives the signal transmitted by the transmitter TXK. The switch MK1 is coupled to the wire for transmitting the lock signal LOCK and its gate is controlled by the inverse lock signal

. The switch MK2 is coupled to the wire for transmitting the equalizer feedback signal EQFB and its gate is controlled by the inverse equalizer feedback signal

. The rest can be deduced by analogy, and will not be repeated here.

Please refer to FIG. 3 . FIG. 3 shows a timing diagram of entering the normal display mode after completing the training mode and the feedback mode through the bidirectional control signal (the lock signal and the equalizer feedback signal) of the present invention.

As shown in FIG. 3, before time t2, it belongs to the stage of training mode MODE1 and feedback mode MODE2, between the timing control circuit TCON and the source driving circuits SD1~SDK in FIG. 2 through the lock signal LOCK and the equalizer feedback signal The two-way control signal of EQFB is used for clock training (Clock training), automatic equalizer training (AEQ training) and feedback (Feedback) equalizer training results and other procedures. During this period, the transmitters TX1 ˜TXK can respectively transmit a training pattern TP with a specific frequency to the corresponding receivers RX1 ˜RXK, but not limited thereto.

When the timing control circuit TCON confirms that the equalizer training results of the source drive circuits SD1 to SDK are correct at time t2, it starts to enter the normal display mode MODE3. At this time, the transmitters TX1~TXK in the timing control circuit TCON start to transmit the display data DD to the corresponding receivers RX1~RXK of the source driver circuits SD1~SDK respectively for display on the display panel.

Next, please refer to FIG. 4 , which is a flowchart of a method for automatically selecting an equalizer gear in this embodiment. As shown in FIG. 4 , the method for automatically selecting the equalizer gear in this embodiment includes the following steps:

Step S10: coupling the timing control circuit to the plurality of source driver circuits and the plurality of source driver circuits to the display panel; and

Step S12: The timing control circuit and the plurality of source driving circuits communicate with each other the training results of the plurality of equalizers through at least one bidirectional control signal, so as to realize the synchronization of display data transmission.

In practical applications, point-to-point data transmission can be performed between the timing control circuit and the plurality of source driving circuits by, for example, iSP transmission, but not limited thereto.

Regarding the training of the plurality of equalizers of the plurality of source driving circuits, an example is described as follows:

First, the timing control circuit can transmit a training pattern with a specific frequency to the plurality of source driving circuits through, for example, a lock signal LOCK. When the plurality of source driving circuits respectively receive a training pattern with a specific frequency, the plurality of source driving circuits are synchronized with the specific frequency and train the plurality of equalizers.

When the plurality of source driving circuits respectively complete the training of the plurality of equalizers, the plurality of source driving circuits respectively transmit the training results of the plurality of equalizers to the timing control through the plurality of equalizer feedback signals circuit. When the timing control circuit receives the feedback signals from the plurality of equalizers and determines that the training results of the plurality of equalizers are correct, the timing control circuit starts to transmit display data to the plurality of source driving circuits. In other words, if the timing control circuit determines that the training results of the plurality of equalizers are incorrect, the timing control circuit will not transmit display data to the plurality of source driving circuits.

In practical applications, the at least one bidirectional control signal described in step S12 may include a lock signal and an equalizer feedback signal, but is not limited thereto. Wherein, the locking signal may include a training pattern with a specific frequency, and the equalizer feedback signal may include the training result of the equalizer, but not limited thereto.

Please refer to FIG. 5 . FIG. 5 is a functional block diagram of a timing control circuit serving as a transmitting end (TX) and a source driving circuit serving as a receiving end (RX) in an embodiment.

As shown in FIG. 5 , the timing control circuit 30 as the transmitter (TX) may include a transmitter control unit 300 , a clock generation unit 301 , a parallel rotation sequence unit 302 , a pre-emphasis unit 303 and a transmitter driver unit 304, but not limited thereto.

In this embodiment, the transmitter control unit 300 is used to control the data transmission process in the timing control circuit 30 . The clock generating unit 301 is coupled to the transmitting-end control unit 300 for generating a clock signal CLK with a specific frequency. The parallel-to-serial unit 302 is coupled to the transmitter control unit 300 and the clock generation unit 301 for converting the parallel data PDT into the serial data SDT according to the clock signal CLK. The pre-emphasis unit 303 is coupled to the transmitting-end control unit 300 for generating a pre-emphasis setting PES. The transmission end driving unit 304 is coupled to the parallel rotation sequence unit 302 and the pre-emphasis unit 303, and is used for processing the sequence data SDT according to the pre-emphasis setting PES and then outputting it to the channel CH through the transmission end pin TXPN.

In this embodiment, the source driver circuit 32 serving as the receiver (RX) may include an equalizer 320 , a clock data recovery (CDR) unit 321 , a serial-to-parallel unit 322 and a receiver control unit 323 . The equalizer 320 receives the sequence data SDT from the channel CH through the receiver pin RXPN. The clock data recovery unit 321 is coupled to the equalizer 320 for obtaining the clock signal CLK from the serial data SDT. The serial-to-parallel unit 322 is coupled to the equalizer 320 and the clock data recovery unit 321 for converting the serial data SDT into parallel data PDT according to the clock signal CLK. The receiver control unit 323 is coupled to the serial-to-parallel unit 322 for controlling the data transmission process in the source driving circuit 32 .

It should be noted that, at least one bidirectional communication can pass between the transmitting end control unit 300 in the timing control circuit 30 serving as the transmitting end (TX) and the receiving end controlling unit 323 in the source driving circuit 32 serving as the receiving end (RX) Control signals (such as lock signal LOCK and equalizer feedback signal EQFB, but not limited thereto) are communicated, and the at least one bidirectional control signal (such as lock signal LOCK and equalizer feedback signal EQFB) can be set according to different modes Determines its control direction. In fact, the plurality of source driving circuits of the display device can be set at the same time or continuously set in series, and there is no specific limitation.

Next, please refer to FIG. 6 . FIG. 6 shows a timing diagram for automatically selecting the equalizer gear by the bidirectional control signal (the lock signal LOCK and the equalizer feedback signal EQFB).

As shown in FIG. 6 , before time t1, it belongs to training mode MODE1; between time t1 and t2, it belongs to the stage of feedback mode MODE2, and after time t2, it belongs to normal display mode MODE3.

In the training mode MODE1, the transmitter TX1 of the timing control circuit TCON can transmit the training patterns TP1-TP2 with specific frequencies to the receiver RX1 of the source driving circuit SD1 through the lock signal LOCK. Similarly, the transmitter TXK of the timing control circuit TCON can transmit the training patterns TP1 to TP2 with specific frequencies to the receiver RXK of the source driver circuit SDK through the lock signal LOCK. The rest can be deduced accordingly. The training pattern TP1 may be used for clock synchronization training and the training pattern TP2 may be used for equalizer synchronization training, but not limited thereto.

As shown in Figure 6, in the training mode MODE1, when the lock signal LOCK and the equalizer feedback signal EQFB are both at low levels, the source driver circuits SD1~SDK will perform clock synchronization training according to the training pattern TP1 to synchronize with the timing control circuit TCON. When the lock signal LOCK changes from a low level to a high level and the equalizer feedback signal EQFB remains at a low level, the source driver circuits SD1~SDK will perform synchronous training of their equalizers.

At time t1, the equalizer feedback signal EQFB changes from a low level to a high level and starts to enter the feedback mode MODE2. In the feedback mode MODE2, when the equalizer feedback signal EQFB changes from a low level to a high level and the lock signal LOCK remains at a high level, the source driver circuits SD1~SDK will pass the equalizer feedback signal EQFB to their respective The equalizer training results EQ1~EQK are sent back to the timing control circuit TCON.

When the sequence control circuit TCON receives the equalizer training results EQ1 to EQK respectively, the sequence control circuit TCON determines whether the equalizer training results EQ1 to EQK are correct.

If the above judgment result is yes, it means that the source driver circuits SD1~SDK have completed their equalizer synchronization training, then the timing control circuit TCON will change the lock signal LOCK from high level to low level and maintain the equalizer feedback signal EQFB at a high level to enter the normal display mode MODE3 at time t2. At this time, the transmitters TX1~TXK will start to transmit the display data DD to the source driving circuits SD1~SDK respectively.

If the above judgment result is no, it means that the source driver circuits SD1~SDK have not completed their equalizer clock synchronization training, then the timing control circuit TCON will turn the lock signal LOCK and the equalizer feedback signal EQFB to a low level, so as to Enter the training mode MODE1 again, causing the source driver circuits SD1~SDK to re-train their equalizer synchronization.

It should be noted that, in terms of the operation of the lock signal LOCK, as shown in Figure 6, in the training mode MODE1 and the feedback mode MODE2, the lock signal LOCK is transmitted from the timing control circuit TCON to the source driver circuits SD1~SDK, and also That is, the locking signal LOCK is controlled by the timing control circuit TCON; in the normal display mode MODE3, the locking signal LOCK is transmitted from the source driving circuits SD1~SDK to the timing control circuit TCON, that is, the locking signal LOCK is transmitted by the source driving circuit. Controlled by SD1~SDK.

In addition, in terms of the operation of the equalizer feedback signal EQFB, as shown in Figure 6, in the training mode MODE1, the equalizer feedback signal EQFB is transmitted from the timing control circuit TCON to the source driver circuits SD1~SDK, that is, The equalizer feedback signal EQFB is controlled by the timing control circuit TCON, and its EQ value is sequentially stepped from 0 to K; in the feedback mode MODE2 and the normal display mode MODE3, the equalizer feedback signal EQFB is driven by the source drive circuit. SD1~SDK is sent to the timing control circuit TCON, that is, the equalizer feedback signal EQFB is controlled by the source driver circuit SD1~SDK, and its EQ value is the best value Mi selected from 0~K and i=1~K .

It should be noted that, the source driver circuits SD1~SDK in this embodiment can inform the timing control of the equalizer gear selection after the source driver circuits SD1~SDK train their equalizers through the equalizer feedback signal EQFB. The circuit TCON enables the timing control circuit TCON to determine whether the pre-emphasis setting PES provided by the pre-emphasis unit 303 in FIG. 5 needs to be adjusted according to the returned equalizer gear selection for the next training.

Compared with the prior art, the present invention provides a method for automatically selecting an equalizer gear for a display device, which utilizes at least one bidirectional control signal (eg, a lock signal LOCK, an equalizer feedback signal EQFB) to control a source electrode The state setting of the equalizer (EQ) in the driver can improve the stability of selecting the equalizer gear, so it can effectively avoid the channel loss caused by the different lengths of the wiring between the timing controller and each source driver. cause a reception error.

:反相鎖定訊號

:反相等化器回饋訊號 MODE1:訓練模式 MODE2:回饋模式 MODE3:正常顯示模式 TP:訓練樣式 DD:顯示資料 t1~t2:時間 30:時序控制電路 32:源極驅動電路 300:傳送端控制單元 301:時脈產生單元 302:平行轉序列單元 303:預加強(Pre-emphasis)單元 304:傳送端驅動單元 320:等化器 321:時脈資料回復(CDR)單元 322:序列轉平行單元 323:接收端控制單元 CLK:時脈訊號 PDT:平行資料 SDT:序列資料 PES:預加強設定 TXPN:傳送端接腳 CH:通道 RXPN:接收端接腳 TP1:訓練樣式 TP2:訓練樣式 SET:設定訊號 EQ1~EQK:等化器訓練結果 S10~S12:步驟 1: Display device PL: Display panel SD1~SDN: Source drive circuit TCON: Timing control circuit TX1~TXK: Transmitter LD: Lock signal detector ED: Equalizer feedback signal detector SD1~SDK: Source Drive circuit DVDD: Working voltage R: Resistor GND: Ground terminal RX1~RXK: Receiver M11~M12: Switch MK1~MK2: Switch LOCK: Lock signal EQFB: Equalizer feedback signal

: Inverted lock signal

: Inverse equalizer feedback signal MODE1: Training mode MODE2: Feedback mode MODE3: Normal display mode TP: Training pattern DD: Display data t1~t2: Time 30: Timing control circuit 32: Source drive circuit 300: Transmitter control Unit 301: Clock generation unit 302: Parallel rotation sequence unit 303: Pre-emphasis unit 304: Transmitter drive unit 320: Equalizer 321: Clock data recovery (CDR) unit 322: Serial to parallel unit 323: Receiver control unit CLK: Clock signal PDT: Parallel data SDT: Serial data PES: Pre-emphasis setting TXPN: Transmitter pin CH: Channel RXPN: Receiver pin TP1: Training pattern TP2: Training pattern SET: Setting Signals EQ1~EQK: Equalizer training results S10~S12: Steps

The accompanying drawings of the present invention are described as follows: FIG. 1 is a schematic diagram illustrating that the lengths of the traces of the timing control circuit coupled to the source driving circuits are different due to the position difference between the source driving circuits in the prior art. FIG. 2 is a schematic structural diagram of a point-to-point iSP transmission method between the timing control circuit serving as the transmitting end and the source driving circuit serving as the receiving end according to the present invention. FIG. 3 is a timing diagram of the present invention entering the normal display mode after completing the training mode and the feedback mode by using the bidirectional control signal (the lock signal and the equalizer feedback signal). FIG. 4 is a flowchart illustrating a method for automatically selecting an equalizer gear according to a preferred embodiment of the present invention. FIG. 5 is a functional block diagram of a timing control circuit serving as a transmitting end and a source driving circuit serving as a receiving end in an embodiment. FIG. 6 is a timing chart showing the automatic selection of the equalizer gear by the bidirectional control signal (the lock signal and the equalizer feedback signal).

S10~S12: Steps

Claims (18)

A method for automatically selecting an equalizer gear position is applied to a display device, the display device includes a display panel, a plurality of source drive circuits and a timing control circuit, the plurality of source drive circuits respectively include a plurality of equalizers The method includes the following steps: coupling the timing control circuit to the plurality of source driving circuits and coupling the plurality of source driving circuits to the display panel; and connecting the timing control circuit and the plurality of source driving circuits The training results of the plurality of equalizers are communicated with each other through at least one bidirectional control signal to realize the synchronization of display data transmission; wherein, the at least one bidirectional control signal includes a locking signal including a training pattern with a specific frequency. The method of claim 1, wherein an iSP transmission method is used to perform point-to-point data transmission between the timing control circuit and the plurality of source driving circuits. The method of claim 1, wherein when the plurality of source driving circuits respectively receive the training pattern having the specific frequency, the plurality of source driving circuits are synchronized to the specific frequency and equalize the plurality of machine for training. The method of claim 3, wherein when the plurality of source driver circuits respectively complete the training of the plurality of equalizers, the plurality of source driver circuits respectively pass the plurality of equalizer feedback signals to the plurality of equalizers The training result of the equalizer is sent to the timing control circuit. The method of claim 4, wherein the timing control circuit starts to transmit display data only when the timing control circuit receives the feedback signals from the plurality of equalizers and determines that the training results of the plurality of equalizers are correct. to the plurality of source drive circuits. The method of claim 1, wherein the at least one bidirectional control signal includes an equalizer feedback signal including a training result of the equalizer. The method of claim 1, wherein the timing control circuit comprises: a transmitter control unit for controlling a data transmission process in the timing control circuit; a clock generation unit, coupled to the control unit, for generating a clock signal of the specific frequency; a parallel rotation sequence unit, coupled to the control unit and the clock generation unit, for converting a parallel data into a sequence data according to the clock signal; a pre-emphasis ) unit, coupled to the control unit, for generating a pre-emphasis setting; and a transmission-end driving unit, coupled to the parallel rotation sequence unit and the pre-emphasis unit, for processing the sequence data according to the pre-emphasis setting Output through a transmission terminal pin. The method of claim 7, wherein each source driver circuit comprises: the equalizer, which receives the sequence data through a receiver pin; and a clock data recovery (CDR) unit, coupled to the equalizer is used for obtaining the clock signal from the serial data; a serial-to-parallel unit is coupled to the equalizer and the clock data recovery unit, and is used for converting the serial data into the serial data according to the clock signal the parallel data; and a receiver control unit, coupled to the serial-to-parallel unit, for controlling the data transmission process in the source driving circuit. The method of claim 8, wherein the transmission-end control unit and the receiver-end control unit communicate through the at least one bidirectional control signal, and the at least one bidirectional control unit The control signal determines its control direction according to different mode settings. The method of claim 1, wherein the plurality of source driving circuits can be set simultaneously or set continuously in series. The method of claim 6, wherein when both the lock signal and the equalizer feedback signal are at a low level, the plurality of source driving circuits perform clock synchronization training to synchronize with the timing control circuit. The method of claim 11, wherein when the lock signal changes from a low level to a high level and the equalizer feedback signal remains at a low level, the plurality of source driving circuits perform training of the plurality of equalizers . The method of claim 12, wherein when the equalizer feedback signal changes from a low level to a high level and the lock signal remains at a high level, the plurality of source driving circuits pass the equalizer feedback signal to the The training results of the plurality of equalizers are returned to the timing control circuit. The method of claim 13, wherein when the timing control circuit receives the training results of the plurality of equalizers, the timing control circuit determines whether the training results of the plurality of equalizers are correct. The method of claim 13, wherein if the determination result of the timing control circuit is yes, the timing control circuit changes the lock signal from a high level to a low level and maintains the equalizer feedback signal at a high level, so as to Start to transmit display data to the plurality of source driving circuits; if the judgment result of the timing control circuit is no, the timing control circuit turns both the lock signal and the equalizer feedback signal to a low level, causing the plurality of The source driver circuit re-trains the clock synchronization. A method for automatically selecting an equalizer gear position is applied to a display device, the display device includes a display panel, a plurality of source drive circuits and a timing control circuit, the plurality of source drive circuits respectively include a plurality of equalizers The method includes the following steps: coupling the timing control circuit to the plurality of source driving circuits and coupling the plurality of source driving circuits to the display panel; and connecting the timing control circuit and the plurality of source driving circuits The training results of the plurality of equalizers are communicated with each other through at least one bidirectional control signal, so as to realize the synchronization of display data transmission; wherein, the timing control circuit transmits a training pattern with a specific frequency to the plurality of sources A pole driving circuit, when the plurality of source driving circuits respectively receive the training pattern with the specific frequency, the plurality of source driving circuits are synchronized with the specific frequency and train the plurality of equalizers. A method for automatically selecting an equalizer gear position is applied to a display device, the display device includes a display panel, a plurality of source drive circuits and a timing control circuit, the plurality of source drive circuits respectively include a plurality of equalizers The method includes the following steps: coupling the timing control circuit to the plurality of source driving circuits and coupling the plurality of source driving circuits to the display panel; and connecting the timing control circuit and the plurality of source driving circuits The training results of the plurality of equalizers are communicated with each other through at least one bidirectional control signal, so as to realize the synchronization of display data transmission; wherein, the timing control circuit includes: a transmitter control unit for controlling the data in the timing control circuit transmission process; A clock generating unit coupled to the control unit for generating a clock signal with a specific frequency; a parallel rotation sequence unit coupled to the control unit and the clock generating unit for generating a clock signal according to the clock signal The parallel data is converted into a sequence data; a pre-emphasis unit, coupled to the control unit, is used to generate a pre-emphasis setting; and a transmission end driving unit, coupled to the parallel rotation sequence unit and the pre-emphasis The unit is used for processing the sequence data according to the pre-emphasis setting and outputting it through a transmission terminal pin; wherein, each source driving circuit includes: the equalizer, which receives the sequence data through a receiving terminal pin; A clock data recovery (CDR) unit, coupled to the equalizer, for obtaining the clock signal from the serial data; a serial to parallel unit, coupled to the equalizer and the clock data recovery The unit is used for converting the serial data into the parallel data according to the clock signal; and a receiver control unit, coupled to the serial-to-parallel unit, is used for controlling the data transmission process in the source driving circuit. A method for automatically selecting an equalizer gear position is applied to a display device, the display device includes a display panel, a plurality of source drive circuits and a timing control circuit, the plurality of source drive circuits respectively include a plurality of equalizers The method includes the following steps: coupling the timing control circuit to the plurality of source driving circuits and coupling the plurality of source driving circuits to the display panel; and The timing control circuit and the plurality of source driving circuits communicate with each other the training results of the plurality of equalizers through at least one bidirectional control signal, so as to realize the synchronization of display data transmission; wherein, the at least one bidirectional control signal includes a lock The signal and an equalizer feedback signal, when the lock signal and the equalizer feedback signal are both at low level, the plurality of source driving circuits perform clock synchronization training to synchronize with the timing control circuit.

Images