TWI764444B - Constant current source generating circuit, LED display driver chip, LED display device, and information processing device - Google Patents

Abstract

A constant current source generating circuit, applied to an LED display driving chip, comprises: a reference current generating unit coupled to a first reference voltage and a peripheral resistor for generating a reference current; a current mirroring unit having a current mirror and a first group of active load units, wherein the current mirror is used for performing a first current mirror process on the reference current according to a first current mirror ratio to generate a first current, the first group of active loads The unit has a first equivalent transistor formed according to the control of a plurality of selection signals, and generates an enabling voltage according to a negative feedback mechanism to drive the first equivalent transistor, so that the first equivalent transistor is The current generated by the channel of the crystal under the bias of a second reference voltage is equal to the first current; and an output current generating unit is coupled to the current mirror unit and has a second group of active load units, wherein the first Two groups of active load units have a second equivalent transistor formed according to the control of the plurality of selection signals, and drive the second equivalent transistor according to the enable voltage, so that the second equivalent transistor The channel generates an output current under the bias of the second reference voltage. In short, the present invention can select different equivalent transistors according to different output currents to improve the accuracy of the output current.

Description

Constant current source generating circuit, LED display driver chip, LED display device, and information processing device

The present invention relates to the technical field of electronic circuits, in particular to a constant current source generating circuit applied in LED display driving chips.

FIG. 1 shows a structure diagram of a conventional LED display device. As shown in FIG. 1, the conventional LED display device 1a includes: an LED display panel 11a including X×Y LED sub-pixels 111a, a column driving unit 12a, a row driving unit 13a, and a display controller 14a. Electronic engineers who are familiar with the design and manufacture of LED display driver chips know that the row driver unit 13a usually includes a plurality of row driver chips 131a, and the number of the plurality of row driver chips 131a used depends on the size of the LED display panel 11a. Resolution (resolution) and the number of drive channels of the row drive wafer 131a.

In more detail, the row driving chip 131a includes a constant current source generating circuit for generating a constant driving current to transmit to the LED display panel 11a through the corresponding driving channel, thereby driving the designated LED sub-pixel 111a to emit light. FIG. 2 shows a block diagram of a constant current source generating circuit included in the row driving chip 131a, and FIG. 3 shows a topological structure diagram of the constant current source generating circuit. As shown in FIG. 2 and FIG. 3 , the conventional constant current source generating circuit 2a includes a reference current generating unit 21a, a current mirroring unit 22a and an output current generating unit 23a.

As shown in FIG. 3 , the reference current generating unit 21a includes a first operational amplifier OP0a and a peripheral resistor R _EXT for generating a reference current I ₀ . The negative input terminal of the first operational amplifier OP0a is coupled to a reference voltage V _REF , and the positive input terminal and the output terminal of the first operational amplifier OP0a are coupled to a first common node CN1a. FIG. 3 also shows that the peripheral resistor R _EXT is also coupled to the first common contact CN1a. According to this design, the reference current I ₀ can be calculated and obtained by the following formula (a):

On the other hand, the current mirror unit 22a is used to perform a current mirror process on the reference current I ₀ , and includes: a first P-type MOSFET element PM0a and at least one second P-type MOSFET element PM1a. A current mirror, a second operational amplifier OP1a and a first N-type MOSFET element NM0a. In more detail, on the basis that the first P-type MOSFET element PM0a and the second P-type MOSFET element PM1a have the same element parameters, the current mirror ratio of the current mirror is determined by the second P-type MOSFET element PM1a and the first P-type MOSFET element PM1a. It is determined by the ratio of the number of one element between the MOSFET elements PM0a. As shown in FIG. 2 and FIG. 3 , after the current mirroring process of the reference current _I0 is completed, the current mirroring unit 22a generates a first current I1, and the first current I1 is the drain of the first N-type MOSFET element NM0a. pole current, which can be calculated by the following formula (b): I ₁ =K. I ₀ …………………………(b)

As shown in FIG. 3, the output current generating unit 23a includes: a third operational amplifier OP2a, a second N-type MOSFET element NM1a, and at least one third N-type MOSFET element NM2a. The first N-type MOSFET element NM0a, the second N-type MOSFET element NM1a and the third N-type MOSFET element NM2a have gate voltages Vg0, Vg1 and Vg2 respectively, and Vg1=Vg2. Also, the first N-type MOSFET element NM0a, the second N-type MOSFET element NM1a, and the third N-type MOSFET element NM2a have drain voltages Vd0, Vd1, and Vd2, respectively.

According to the circuit design of the output current generating unit 23a, as long as Vg1=Vg2 and Vd1=Vd2, the drain current of the second N-type MOSFET element NM1a (ie, the first current I1) is equal to that of the third N-type MOSFET element NM2a. Drain current (ie, second current I2). In other words, the second N-type MOSFET element NM1a and the first N-type MOSFET element NM0a form another current mirror across the cell, wherein the current mirror ratio is determined by the difference between the second N-type MOSFET element NM1a and the first N-type MOSFET element NM0a It is determined by the proportion of the number of a component. Finally, an output current Iout outputted through the drain terminal of the third N-type MOSFET element NM2a can be calculated and obtained by using the following equations (c) and (d):

Referring to FIG. 3 , it can be seen that the ratio of the number of elements of the first N-type MOSFET element NM0a and the second N-type MOSFET element NM1a is M:N. It should be understood that the value of the output current Iout can be regulated by adjusting the resistance value of the peripheral resistor R _EXT and/or the current mirror ratio. Therefore, electronic engineers who are familiar with the design and manufacture of the row driver chip 131a know that the conventional constant current source generating circuit 2a has the following characteristics:

(1) When designing the constant current source generating circuit 2a, the ratio of the number of elements (ie, the current mirror ratio) of the first N-type MOSFET element NM0a and the second N-type MOSFET element NM1 must be set to an optimal value, so that The branch current (ie, I1 ) of the first N-type MOSFET element NM0a can be reduced under the condition of satisfying the regulation accuracy of the output current Iout, so as to reasonably reduce the static power consumption of the system circuit.

(2) When the constant current source generating circuit 2a is applied in the row driving chip 131a, it will multiplex output constant driving current to the LED display panel 11a according to the display requirements. It should be known that the constant driving current is in the form of PWM to facilitate controlling the display gray scale of each LED sub-pixel 111a. Therefore, as shown in FIG. 3 , a control signal V _CRES is introduced into the current mirroring unit 22 a to control the first current I1 to be output to the output current generating unit 23 a of the next stage in the form of PWM. However, the continuous switching of the first N-type MOSFET element NM0a will generate a noise signal at the gate terminal thereof, which will cause the output of the first current I1 to be unstable, and also affect the connection between the first N-type MOSFET element NM0a and the first operational amplifier OP1a. The negative feedback loop caused stability problems.

(3) Corresponding to the display grayscale of the LED sub-pixel 111a, the output current Iout ranges from a few milliamps (mA) to several tens of milliamps. Such a large current variation range has a great chance of causing the component size to be fixed. The element operating regions of the first N-type MOSFET element NM0a and the second N-type MOSFET element NM1a are changed, such as changing from the saturation region to the linear region, resulting in a lack of consistency in the output current Iout of the multiple drive channels, resulting in the LED display panel 11a . Color blocks appear when the image is displayed.

It can be seen from the above description that a novel constant current source generating circuit is urgently needed in the art.

The main purpose of the present invention is to provide a constant current source generating circuit, which is applied to an LED display driver chip, and includes a reference current generating unit, a current mirroring unit and an output current generating unit, wherein the current mirroring unit includes a current A mirror and a first grouped active load unit, and the output current generating unit includes a current output unit and a second grouped active load unit. During normal operation, the reference current generating unit generates a reference current; the current mirror converts the reference current mirror into a first current according to a first current mirror ratio; and according to the control of a selection signal, The first group of active load units constitutes a first equivalent transistor, the second group of active load units constitutes a second equivalent transistor, and the channel between the second equivalent transistor and the first equivalent transistor The ratio of the aspect ratio is used to make the output current of the output current generating unit and the first current form a second current mirror ratio. In short, the present invention can select different equivalent transistors according to different output currents to improve the accuracy of the output current.

According to the above description, since the present invention uses the selection signal to precisely set and modulate the magnitude of the output current, the output current transmitted by the driving channel of the LED display driver chip can be adjusted in several times according to the display requirements while maintaining the current accuracy. Adjustable from milliamps (mA) to tens of milliamps.

In order to achieve the above object, the present invention proposes an embodiment of the constant current source generating circuit, which includes: a reference current generating unit coupled to a first reference voltage and a peripheral resistor for generating a reference current; a The current mirror unit has a current mirror and a first group of active load units, wherein the current mirror is used for performing a first current mirror process on the reference current according to a first current mirror ratio to generate a first current, the The first group of active load units has a first equivalent transistor formed according to the control of X selection signals, X is a positive integer, and generates an enabling voltage according to a negative feedback mechanism to drive the first equivalent transistor a crystal, so that the current generated by the channel of the first equivalent transistor under the bias of a second reference voltage is equal to the first current; and an output current generating unit coupled to the current mirroring unit and having an A current output unit and a second group of active load units, wherein the second group of active load units has a second equivalent transistor formed according to the control of the X selection signals, and drives the first transistor according to the enable voltage Two equivalent transistors, so that the channel of the second equivalent transistor generates an output current under the bias of the second reference voltage, and the current output unit outputs the output current.

In one embodiment, the reference current generating unit includes: a first operational amplifier having a negative input terminal, a positive input terminal and an output terminal, wherein the negative input terminal is coupled to the first reference voltage, and The positive input terminal and the peripheral resistor are coupled to a first common contact.

In one embodiment, the current mirror includes: a first P-type MOSFET element having a gate terminal, a drain terminal and a source terminal, wherein the gate terminal is coupled to the output terminal of the first operational amplifier, the The drain terminal is coupled to the first common contact, and the source terminal is coupled to a working voltage; and at least one second P-type MOSFET element has a gate terminal, a drain terminal and a source terminal, wherein the gate terminal is coupled The output terminal of the first operational amplifier is connected, and the source terminal is coupled to the working voltage.

In one embodiment, the first grouped active load unit includes: a second operational amplifier having a negative input terminal, a positive input terminal and an output terminal, wherein the negative input terminal is coupled to the second reference voltage _S , the positive input terminal is coupled to a second common contact point, and the output terminal is coupled to a third common contact point; and X first active load units, wherein each of the first active load units includes: a a first switch element, having a first end, a second end and a control end, wherein the first end is coupled to the third common contact, and the control end is coupled to one of the selection signals; and at least one The first N-type MOSFET element has a gate terminal, a drain terminal and a source terminal, wherein the gate terminal is coupled to the second terminal of the first switching element, and the drain terminal is coupled to the second common contact , and the source terminal is coupled to a ground terminal; wherein, the current mirror transmits the first current to the second common node, and the second operational amplifier outputs the enable after receiving the second reference voltage voltage to the third common contact.

In one embodiment, the current output unit includes: a third operational amplifier having a negative input terminal, a positive input terminal and an output terminal, wherein the positive input terminal is coupled to the second common contact to receive the the second reference voltage, and the negative input terminal is coupled to a fourth common point; and a current output element, which is an N-type MOSFET element and has a gate terminal, a drain terminal and a source terminal, wherein The gate terminal is coupled to the output terminal of the third operational amplifier, the source terminal is coupled to the fourth common node, and the drain terminal is used as a current output terminal.

In one embodiment, the second group of active load cells includes X second active load cells A load unit, and each of the second active load units includes: a second switch element having a first end, a second end and a control end, wherein the first end is coupled to a fifth common contact, and the control terminal is coupled to one of the selection signals; and at least one second N-type MOSFET element has a gate terminal, a drain terminal and a source terminal, wherein the gate terminal is coupled to the first switching element of the second switching element Two terminals, the drain terminal is coupled to the fourth common contact, and the source terminal is coupled to a ground terminal; wherein a buffer is coupled between the third common contact and the fifth common contact, After performing a buffering process on the enable voltage, output it to the fifth common contact; wherein, according to the enable voltage and the control of at least one of the selection signals, at least one of the first current adjustment unit and the At least one first current adjustment unit is selectively enabled to perform the second current mirroring process on the first current to generate the second current.

The present invention also provides an LED display driver chip, which is characterized in that the LED display driver chip utilizes the constant current source generating circuit of the present invention as described above to generate at least one channel of driving current.

The present invention also provides an LED display device, which includes an LED display panel, a column driving unit, a row driving unit including at least one LED display driving chip, and a display controller; characterized in that, the LED display driving chip uses a The aforementioned constant current source generating circuit of the present invention generates at least one channel of driving current.

The present invention also provides an information processing device comprising the LED display device of the present invention as described above.

In one embodiment, the information processing device is selected from the group consisting of smart phones, smart watches, smart bracelets, tablet computers, notebook computers, all-in-one computers, access control devices, desktop computers, and industrial computers. An electronic device in a group.

1a: LED display device

11a: LED display panel

111a: LED sub-pixel

12a: Column driver module

13a: Row driver module

131a: row driver chip

14a: Display Controller

2a: constant current source generation circuit

21a: Reference current generation unit

22a: Current mirror unit

23a: output current generation unit

OP0a: first operational amplifier

OP1a: second op amp

OP2a: third op amp

PM0a: The first P-type MOSFET element

PM1a: Second P-type MOSFET element

CN1a: First common contact

NM0a: first N-type MOSFET element

NM1a: Second N-type MOSFET element

NM2a: third N-type MOSFET element

REXT: peripheral resistance

2: constant current source generation circuit

21: Reference current generation unit

22: Current mirror unit

221: Current Mirror

222: The first group of active load units

23: Output current generation unit

231: Current output unit

232: Active load unit of the second group

24: Buffer

OP0: first operational amplifier

OP1: Second Op-Amp

OP2: Third Op Amp

PM0: The first P-type MOSFET element

PM1: Second P-type MOSFET element

CN1: The first common contact

CN2: The second common contact

CN3: The third common contact

CN4: Fourth common contact

CN5: Fifth common contact

NM01~NM04: The first N-type MOSFET element

NM11~NM14: The second N-type MOSFET element

NM1e: Second Equivalent Transistor

S01~S04: The first switching element

S11~S14: The second switching element

NM2: Current output element

111: LED sub-pixel

FIG. 1 is a schematic diagram of a conventional LED display device; 2 is a block diagram of a constant current source generating circuit included in a row driving chip of a conventional LED display device; FIG. 3 is a topological structure diagram of a conventional constant current source generating circuit; FIG. 4 is one of the present invention The block diagram of the constant current source generating circuit; Fig. 5 is the topology structure diagram of the constant current source generating circuit of the present invention; topology diagram.

In order to enable your examiners to further understand the structure, features, objectives, and advantages of the present invention, drawings and detailed descriptions of preferred embodiments are attached as follows.

Electronic engineers who are familiar with the design and manufacture of LED display devices must know that existing LED display devices include: an LED display panel, a column driver unit, a row driver unit, and a display controller, wherein the row driver unit often includes a plurality of rows Driving chips, and the number of the row driving chips used depends on the resolution (resolution) of the LED display panel and the number of driving channels of the row driving chips. The present invention provides a constant current source generating circuit, which is applied in a row driving chip with multiple driving channels to generate a constant driving current and transmit it to the LED display panel through the corresponding driving channel, so as to drive a specified LED sub-section. Pixels glow.

It is added that, in a feasible embodiment, the display controller (ie, the timing controller), the column driving unit and the row driving unit can be integrated into a single LED display driving chip. In addition, in another feasible embodiment, the row driving unit can be separately made into a row driving chip as an LED display driving chip that does not include the column driving function and the timing control function.

FIG. 4 shows a block diagram of a constant current source generating circuit of the present invention, and FIG. 5 shows a topological structure diagram of the constant current source generating circuit of the present invention. As shown in FIG. 4 , the constant current source generating circuit 2 of the present invention includes: a reference current generating unit 21 , a current mirroring unit 22 and an output current generating unit 23 , wherein the reference current generating unit 21 is coupled to a first reference The voltage V _REF and a peripheral resistor R _EXT are used to generate a reference current I ₀ . In addition, the current mirror unit 22 is coupled to the reference current generation unit 21 to receive the reference current I ₀ , and has a current mirror 221 and a first grouped active load unit 222 . According to the design of the present invention, the current mirror 221 is used for performing a first current mirror process on the reference current I ₀ according to a first current mirror ratio (K) to generate a first current I ₁ , and the first grouping The active load unit 222 is coupled to the current mirror 221 , a second reference voltage V _CRES and X selection signals S1 ˜ S4 , where X is a positive integer, for setting a first current I ₁ and the second reference voltage V _CRES A drain current and a drain-source voltage (ie, V _DS ) of an equivalent MOS transistor to generate a corresponding gate-source voltage (ie, V _GS ), thereby providing an enable voltage according to the gate-source voltage V _Gate . As shown in FIG. 4 and FIG. 5 , according to the design of the present invention, the first equivalent MOS transistor system is composed of X selection signals S1 to S4 for a plurality of first MOSs included in the first group of active load units 222 The transistors (NM01, NM02, NM03, NM04) are connected in parallel.

As shown in FIG. 4 , the output current generation unit 23 is coupled to the current mirror unit 22 and has a current output unit 231 and a second group of active load units 232 , wherein the second group of active load units 232 is coupled to the current The output unit 231 and the X selection signals S1 to S4. According to this design, as shown in FIG. 4 , after receiving the second reference voltage V _CRES and the enabling voltage V _Gate transmitted by the first grouped active load unit 222 , the second grouped active load unit 232 follows the second The reference voltage V _CRES and the enable voltage V _Gate set a drain-source voltage (ie, V _DS ) and a gate-source voltage (ie, V _GS ) of a second equivalent MOS transistor to generate a corresponding drain current , and provide a second current I ₂ according to the drain current. Wherein, the second equivalent MOS transistor system is combined by the X selection signals S1 - S4 of the plurality of second MOS transistors ( NM11 , NM12 , NM13 , NM14 ) included in the second group of active load units 232 formed by operation. As shown in FIG. 4 and FIG. 5 , according to the design of the present invention, the aspect ratio (W/L) of the plurality of second MOS transistors and the aspect ratio (W/L) of the plurality of first MOS transistors The ratio of L) is equal to N/M, where N and M are positive integers, so that I ₂ =(N/M)*I ₁ . Next, the current output unit 231 outputs the second current I ₂ as an output current I _out .

As shown in FIG. 4 and FIG. 5 , the reference current generating unit 21 includes a first operational amplifier OP0 having a negative input terminal, a positive input terminal and an output terminal, wherein the negative input terminal is coupled to the first operational amplifier OP0 The reference voltage V _REF , and the positive input terminal and the peripheral resistor R _EXT are coupled to a first common node CN1. In more detail, the first reference voltage V _REF is provided by a bandgap reference voltage generating unit inside the row driving chip (ie, the LED driving chip).

Further, according to FIG. 5 , the current mirror 221 is composed of a first P-type MOSFET element PM0 and at least one second P-type MOSFET element PM1 . As shown in FIG. 5 , the first P-type MOSFET element PM0 has a gate terminal, a drain terminal and a source terminal, wherein the gate terminal is coupled to the output terminal of the first operational amplifier OP0, and the drain terminal is coupled to to the first common contact CN1, and the source terminal is coupled to a working voltage. And, the second P-type MOSFET element PM1 has a gate terminal, a drain terminal and a source terminal, wherein the gate terminal is coupled to the output terminal of the first operational amplifier OP0, and the source terminal is coupled to the Operating Voltage. It should be noted that, in the case that the first P-type MOSFET element PM0 and the second P-type MOSFET element PM1 have the same element size and parameters, the first current mirror ratio of the current mirror 221 is determined by the second P-type MOSFET element. It is determined by the ratio of the number of elements between PM1 and the first P-type MOSFET element PM0. For example, FIG. 5 indicates that the ratio of the number of components is 1:K, which means that the value of the first current mirror ratio is K.

On the other hand, when the number of the first P-type MOSFET element PM0 and the number of the second P-type MOSFET element PM1 are both fixed at 1, the first current mirror ratio of the current mirror 221 is determined from the second P-type MOSFET element PM1. It is determined by a device width (W) ratio between the MOSFET element PM1 and the first P-type MOSFET element PM0. For example, the first P-type MOSFET element PM0 and the second P-type MOSFET element PM1 have the first element width W1 and the second element width W2 respectively, then W2/W1=K.

As shown in FIG. 5 , the first grouped active load unit 222 includes a second operational amplifier OP1 and X first active load units. The second operational amplifier OP1 has a negative input terminal, a positive input terminal and an output terminal, wherein the negative input terminal is coupled to the second reference voltage V _CRES , and the positive input terminal is coupled to a second common The contact CN2, and the output end is coupled to a third common contact CN3. It should be noted that each of the first active load units includes a first switch element and at least one first N-type MOSFET element. For example, FIG. 5 shows that the first group of active load units 222 includes four first active load units, so there are four of the first switching elements S01 to S04 in the first group of active load units 222 and At least one of the first N-type MOSFET elements NM01 to NM04 of the four groups.

According to the above description, each of the first switching elements (eg S01 ) has a first terminal, A second terminal and a control terminal, wherein the first terminal is coupled to the third common contact CN3, and the control terminal is coupled to a selection signal S1. On the other hand, in the circuit composition of the first active load unit, the first N-type MOSFET element (eg NM01 ) has a gate terminal, a drain terminal and a source terminal, wherein the gate terminal is coupled to the first The second terminal of a switching element, the drain terminal is coupled to the second common node CN2, and the source terminal is coupled to a ground terminal. According to the design of the present invention, the circuit composition of each group of the first active load units includes M first N-type MOSFET elements (eg, NM01 ).

It can be seen from the foregoing description that the X selection signals S1 to S4 can be used to control the on/off of the first N-type MOSFET elements NM01 to NM04, so that the first N-type MOSFET elements NM01 to NM04 are connected in parallel to form a first equivalent MOS transistor. . Meanwhile, as can be seen from the circuit diagram of FIG. 5 , after the first current I ₁ transmitted by the current mirror 221 and a second reference voltage V _CRES input from the outside are input into the first grouped active load unit 222 , the second operational amplifier OP1 follows the A negative feedback mechanism generates an enable voltage VGAate to set the gate-source voltage (ie, V _GS ) of the first equivalent transistor, and at the same time utilizes the virtual ground characteristic of the second operational amplifier OP1 to achieve so The second reference voltage V _CRES sets the drain-source voltage (ie, V _DS ) of the first equivalent transistor.

As shown in FIG. 5 , the current output unit 231 includes a third operational amplifier OP2 and a current output element NM2. The third operational amplifier OP2 has a negative input terminal, a positive input terminal and an output terminal, the positive input terminal is coupled to the second common node CN2 to receive the second reference voltage V _CRES , and the The negative input terminal is coupled to a fourth common contact CN4. And, the current output element NM2 is an N-type MOSFET element, and has a gate terminal, a drain terminal and a source terminal, wherein the gate terminal is coupled to the output terminal of the third operational amplifier OP2, and the source terminal is coupled to Connected to the fourth common contact CN4, and the drain terminal is used as a current output terminal.

5 shows that the second group of active load units 232 includes X second active load units, and each of the second active load units includes: a second switch element and at least one second N-type MOSFET element. For example, FIG. 5 shows that the second group of active load units 232 includes four second active load units, so there are four of the second switch elements S11 to S14 in the second group of active load units 232 and Four groups of at least one of the second N-type MOSFET elements NM11 ˜ NM14 .

According to the above description, each of the second switching elements (eg S12 ) has a first end, a second end and a control end, wherein the first end is coupled to a fifth common contact CN3, and the control end The terminal is coupled to one of the selection signals S1. On the other hand, in the circuit composition of the second active load unit, the second N-type MOSFET element (eg NM11 ) has a gate terminal, a drain terminal and a source terminal, wherein the gate terminal is coupled to the first For the second ends of the two switching elements, the drain terminal is coupled to the fourth common node CN4, and the source terminal is coupled to a ground terminal. According to the design of the present invention, the circuit composition of each group of the second active load units includes N second N-type MOSFET elements (eg, NM11).

It is added that a buffer 24 is coupled between the third common contact CN3 and the fifth common contact CN5 for performing a buffering process on the enable voltage VGAate and then outputting it to the first Five total contacts CN5. As shown in FIG. 5 , the on/off of the second N-type MOSFET elements NM11 to NM14 can be controlled by using the X selection signals S1 to S4 , so that the second N-type MOSFET elements NM11 to NM14 are connected in parallel to form a second equivalent MOS circuit. crystal. In more detail, after the first group of active load units 222 transmits the second reference voltage V _CRES and the start-up voltage VGate to the current output unit 231 and the second group of active load units 232 , the third group of active load units 232 can be utilized. The virtual ground characteristic of the operational amplifier OP2 sets the drain-source voltage (ie, V _DS ) of the second equivalent transistor with the second reference voltage V _CRES . At the same time, the startup voltage VGate is used to set the gate-source voltage (ie, V _GS ) of the second equivalent transistor. After completing the setting of the gate-source voltage and the sink-source voltage of the second equivalent transistor, even if the channel of the second equivalent transistor generates an output current Iout under the bias of the second reference voltage VCRES, and the The current output unit 231 outputs the output current Iout.

According to the design of the present invention, I ₂ =(N/M)*I ₁ , and the current output unit 231 outputs I ₂ as the output current I _out . Here, N refers to "N" second N-type MOSFET elements (eg, NM11 ) included in each group of the second current adjustment units, and M refers to that each group of the first current adjustment units includes The "M" first N-type MOSFET elements (such as NM01). It is worth noting that, in the case where the first N-type MOSFET element (such as NM01) and the second N-type MOSFET element (such as NM11) have the same component size and parameters, the second current mirror ratio is determined by the second N-type MOSFET. It is determined by the ratio of the number of one element between the first N-type MOSFET element NM11 and the first N-type MOSFET element NM01. For example, the ratio of the number of elements is M:N, which means that the value of the second current mirror ratio is N/M.

On the other hand, in the case where the number of the first N-type MOSFET element (such as NM01) and the number of the second N-type MOSFET element (such as NM11) are both 1, the second current mirror ratio is determined by the second N-type MOSFET. It is determined by the ratio of an element width (W) between the MOSFET element NM11 and the first N-type MOSFET element NM01. For example, the first N-type MOSFET element NM01 and the second N-type MOSFET element NM11 have the first element width W1 and the second element width W2 respectively, then W2/W1=N/M. In addition, the value of N/M is preferably 4 to 8.

FIG. 6 shows a topological structure diagram of an iso-calibration circuit of the output current generating unit. Electronic engineers who are familiar with the design and manufacture of LED display driver chips must know that in the display driving control of LED display devices, the PWM signal generator generates a PWM signal to the channel driver according to the grayscale clock signal to generate a driving current (ie, output current Iout), the channel driver includes a current output unit 231 as shown in FIG. 6 and a second equivalent transistor NM1e formed by parallel connection of second N-type MOSFET elements NM11-NM14. Therefore, the precision of the display gray scale of the LED sub-pixels 111 of the LED panel is directly related to the precision of the driving current. In more detail, the first offset value Voff1 of the second equivalent transistor NM1e (ie, the second N-type MOSFET elements NM11 ˜ NM14 ) and the second offset value Voff2 of the third operational amplifier OP2 caused by the process error will be This results in a decrease in the control accuracy of the drive current (ie, the output current Iout) by the system circuit.

As shown in FIG. 6 , the first offset value Voff1 is introduced as a first error source, which is coupled to the gate terminal of the second equivalent transistor NM1e of the equivalent circuit. On the other hand, the second offset value Voff1 is introduced as a second error source, which is coupled to the drain terminal of the second equivalent transistor NM1e of the equivalent circuit. Among them, the aforesaid sink-source current can be calculated by the following formula (1):

Various parameters used in the above formula (1) are well known to electronic engineers, so the description will not be repeated here. It should be understood that the first error source and the second error source will inevitably cause the sink-source current variation, including the first current variation and the second current variation. Therefore, the ratio of the first current variation to the sink-source current can be ΔI ₁ / I _DS , and the ratio of the second current variation to the sink-source current can be Δ I ₂ /I DS _. And, Δ I ₁ / I _DS and Δ I ₂ / I _DS can be obtained by using the following formulas (2) and (3):

After observing the above equations (2) and (3), it can be found that the greater the gate-source voltage (ie, V _GS ) of the second N-type MOSFET elements NM11~NM14, the greater the first error source and the second error source. The influence on the output current Iout will be smaller. In other words, as shown in FIG. 6 , when the second reference voltage V _CRES is fixed, as the value of the enable voltage VGate increases, the effects of the first error source and the second error source on the output current Iout can be largely eliminated. influences.

It is worth emphasizing that, as shown in FIG. 5 , after the first said first switch S01 and the first said second switch S11 are enabled by the first said selection signal S1 , the current mirror unit 22 includes The first said first N-type MOSFET element NM01 of the first active load unit is turned on, and at the same time, the first said second N-type MOSFET element NM11 of the second active load unit included in the output current generating unit 23 is also turned on , the value of the output current Iout is small at this time. When the display requirement requires to increase the brightness of the LED sub-pixels, the second one of the first switches S02 and the second one of the second switches S12 can be further activated by using the second selection signal S2, so that the current mirror unit 22 The second N-type MOSFET element NM02 of the first active load unit included in the first active load unit is turned on, and at the same time, the second N-type MOSFET element NM02 of the second active load unit included in the output current generating unit 23 is turned on. NM12 is also turned on to achieve the effect of increasing the output current value. It is conceivable that the first switches S01 to S04 and the second switches S11 to S14 can be enabled one by one as the display requirements require to further increase the brightness of the LED sub-pixels. To put it simply, the present invention utilizes the selection signals (S1-S4) to set a reasonable output current size, which can not only achieve the effect of segmentally regulating the size of the output current Iout, but also effectively reduce the output current Iout under the condition of low output current. Reduce the static power consumption of the LED display driver chip.

To describe in more detail, when the constant current source generating circuit 2 of the present invention is applied to a row of driving chips, it will multiplex output constant driving currents to the LED display panel according to the display requirements. Wherein, the constant driving current (ie, the output current Iout) is in the form of PWM to facilitate controlling the display gray scale of each LED sub-pixel. Therefore, as shown in FIG. 5 , the second reference voltage V _CRES is a PWM signal, so that the enable voltage VGate output by the second operational amplifier OP1 is also in a PWM form, thereby controlling the first N-type MOSFET elements NM01 to NM04 and the second The N-type MOSFET elements NM11 to NM14 are periodically turned on/off, so that the output current Iout is transmitted to the corresponding LED sub-pixels in the form of PWM. In particular, as shown in FIG. 4 and FIG. 5 , the present invention enables a buffer 24 to be coupled between the third common contact CN3 and the fifth common contact CN5 for performing a After buffering, it is output to the fifth common contact CN5. This setting can not only ensure that the enable voltage VGate output by the second operational amplifier OP1 is sufficient to simultaneously drive the first N-type MOSFET elements NM01 to NM04 and the second N-type MOSFET elements NM11 to NM14 to turn on, but also ensures that the first N-type MOSFET is turned on. The stability of the negative feedback loop between the elements NM01-NM04 and the second operational amplifier OP1, thereby maintaining the accuracy of the output current Iout.

In this way, the above has completely and clearly described a constant current source generating circuit of the present invention; and, through the above, it can be known that the present invention has the following advantages:

(1) The present invention discloses a constant current source generating circuit, which is applied to an LED display driver chip, and includes: a reference current generating unit coupled to a first reference voltage and a peripheral resistor for generating a reference current; a current mirror unit having a current mirror and a first group of active load units, wherein the current mirror is used to perform a first current mirror process on the reference current according to a first current mirror ratio to generate a first current, the first group of active load units has a first equivalent transistor formed according to the control of a plurality of selection signals, and generates an enable voltage to drive the first equivalent transistor according to a negative feedback mechanism, so that the current generated by the channel of the first equivalent transistor under the bias of a second reference voltage is equal to the first current; and an output current generating unit is coupled to the current mirror unit and has a second grouped active load units, wherein the second group of active load units has a second equivalent transistor formed according to the control of the plurality of selection signals, and drives the second equivalent transistor according to the enable voltage, so as to The channel of the second equivalent transistor generates an output current under the bias of the second reference voltage. In short, the present invention can select different equivalent transistors according to different output currents to improve the accuracy of the output current. .

(2) According to the above description, since the present invention uses the selection signal to set a reasonable output current size, the output current transmitted by the driving channel of the LED display driver chip can be adjusted to a few mA according to the display requirements while maintaining the current accuracy. (mA) to several tens of mA range.

(3) The present invention also provides an LED display driver chip, characterized in that the The LED display driving chip utilizes the constant current source generating circuit of the present invention as described above to generate at least one channel of driving current.

(4) The present invention also provides an LED display device, which includes an LED display panel, a column of drive units, a row of drive units including at least one LED display drive chip, and a display controller; it is characterized in that the LED display driver The chip uses the constant current source generating circuit of the present invention as described above to generate at least one channel of driving current.

(5) The present invention also provides an information processing device including the LED display device of the present invention as described above. Wherein, the information processing device is selected from the group consisting of smart phones, smart watches, smart bracelets, tablet computers, notebook computers, all-in-one computers, access control devices, desktop computers, and industrial computers of an electronic device.

It must be emphasized that the above-mentioned disclosure in this case is a preferred embodiment, and any partial changes or modifications originating from the technical ideas of this case and easily inferred by those who are familiar with the art are within the scope of the patent of this case. category of rights.

To sum up, regardless of the purpose, means and effect of this case, it shows that it is completely different from the conventional technology, and its first invention is suitable for practical use, and indeed meets the patent requirements of the invention. Society is to pray for the best.

2: constant current source generation circuit

21: The reference current generates a single

22: Current mirror unit

221: Current Mirror

222: The first group of active load units

23: Output current generation unit

231: Current output unit

232: Active load unit of the second group

24: Buffer

R _EXT : Peripheral resistance

Claims (10)

A constant current source generating circuit, comprising: a reference current generating unit coupled to a first reference voltage and a peripheral resistor for generating a reference current; a current mirroring unit having a current mirror and a first grouping active A load unit, wherein the current mirror is used for performing a first current mirror process on the reference current according to a first current mirror ratio to generate a first current, and the first group of active load units is controlled according to X selection signals A first equivalent transistor is formed, X is a positive integer, and an enabling voltage is generated to drive the first equivalent transistor according to a negative feedback mechanism, so that the channel of the first equivalent transistor is in the The current generated under the bias of a second reference voltage is equal to the first current; and an output current generating unit, coupled to the current mirror unit, has a current output unit and a second group of active load units, wherein the The second group of active load units has a second equivalent transistor formed according to the control of the X selection signals, and drives the second equivalent transistor according to the enable voltage, so that the second equivalent transistor is The channel of the crystal generates an output current under the bias of the second reference voltage, and the current output unit outputs the output current. The constant current source generating circuit of claim 1, wherein the reference current generating unit comprises: a first operational amplifier having a negative input terminal, a positive input terminal and an output terminal, wherein the negative input terminal is coupled to the first reference voltage, and the positive input terminal and the peripheral resistor are coupled to a first common contact. The constant current source generating circuit of claim 2, wherein the current mirror comprises: a first P-type MOSFET element having a gate terminal, a drain terminal and a source terminal, wherein the gate terminal is coupled to the first the output terminal of the operational amplifier, the drain terminal is coupled to the first common node, and the source terminal is coupled to a working voltage; and at least one second P-type MOSFET element has a gate terminal, a drain terminal, and A source terminal, wherein the gate terminal is coupled to the output terminal of the first operational amplifier, and the source terminal is coupled to the operating voltage. The constant current source generating circuit of claim 3, wherein the first grouped active load unit comprises: a second operational amplifier having a negative input terminal, a positive input terminal and an output terminal, wherein the negative input terminal coupled to the second reference voltage, the positive input terminal is coupled to a second common point, and the output terminal is coupled to a third common point; and X first active load units, wherein each of the The first active load element includes: a first switch element with a first end, a second end and a control end, wherein the first end is coupled to the third common contact, and the control end is coupled to a the selection signal; and at least one first N-type MOSFET element, having a gate terminal, a drain terminal and a source terminal, wherein the gate terminal is coupled to the second terminal of the first switching element, and the drain terminal is coupled to connected to the second common point, and the source terminal is coupled to a ground terminal; wherein the current mirror transmits the first current to the second common point, and the second operational amplifier receives the first current After the two reference voltages, the enabling voltage is outputted to the third common contact. The constant current source generating circuit of claim 4, wherein the current output unit comprises: a third operational amplifier having a negative input terminal, a positive input terminal and an output terminal, wherein the positive input terminal is coupled to The second common contact is for receiving the second reference voltage, and the negative input terminal is coupled to a fourth common contact; and a current output element is an N-type MOSFET element and has a gate terminal, A drain terminal and a source terminal, wherein the gate terminal is coupled to the output terminal of the third operational amplifier, the source terminal is coupled to the fourth common node, and the drain terminal is used as a current output terminal. The constant current source generating circuit according to claim 5, wherein the second group of active load units includes X second active load units, and each of the second active load units includes: a second switch element having a a first end, a second end and a control end, wherein the first end is coupled to a fifth common contact, and the control end is coupled to one of the selection signals; and At least one second N-type MOSFET element has a gate terminal, a drain terminal and a source terminal, wherein the gate terminal is coupled to the second terminal of the second switching element, and the drain terminal is coupled to the fourth common terminal a contact, and the source terminal is coupled to a ground terminal; wherein a buffer is coupled between the third common contact and the fifth common contact for performing a buffering process on the enabling voltage, outputting it to the fifth common contact; wherein, according to the control of the enable voltage and at least one of the selection signals, at least one of the first current adjustment units and at least one of the first current adjustment units are selected and enabled, so as to A second current mirroring process is performed on the first current to generate a second current. An LED display driver chip, characterized in that, the LED display driver chip uses the constant current source generating circuit according to any one of claim 1 to claim 6 to generate at least one channel of drive current. An LED display device includes an LED display panel, a column driving unit, a row driving unit including at least one LED display driving chip, and a display controller, characterized in that the LED display driving chip utilizes the requirements of item 1 to request The constant current source generating circuit described in any one of item 6 generates at least one channel driving current. An information processing device comprising the LED display device as described in claim 8. The information processing device according to claim 9, wherein the information processing device is selected from the group consisting of smart phones, smart watches, smart bracelets, tablet computers, notebook computers, all-in-one computers, access control devices, desktop An electronic device in the group consisting of computers, and industrial computers.

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