TWI764371B - Integrated circuit device, method of generating integrated circuit layout diagram, and electronic design automation system - Google Patents

Abstract

A method of generating an integrated circuit (IC) layout diagram includes, intersecting the first active region with first through fourth gate regions to define gate locations of first and second anti-fuse bits, aligning first and second conductive regions between the first and second active regions, thereby intersecting the first conductive region with the first gate region and the second conductive region with the fourth gate region, and aligning third and fourth conductive regions between the first and third active regions, thereby either intersecting the third and fourth conductive regions with the first and third gate regions, or intersecting the third and fourth conductive regions with the second and fourth gate regions. The method further includes positioning or intersecting the first active region, or aligning the first and second or third and fourth conductive regions. An IC device and an electronic design automation system are also disclosed herein.

Description

Integrated circuit components, methods of generating integrated circuit layout diagrams, and electronic design automation Dynamic system

Embodiments of the present disclosure relate to an integrated circuit, and more particularly, to an integrated circuit having an antifuse structure, a method for generating a layout thereof, and an electronic design automation system for performing the method.

Integrated circuits (ICs) sometimes include one-time-programmable ("OTP") memory elements to provide non-volatile memory ("NVM"), wherein Data will not be lost when the IC is powered off. One type of NVM includes antifuse bits integrated into an IC by using layers of dielectric material (oxide, etc.) that connect to other circuit elements. To program the antifuse bits, a programming electric field is applied across the dielectric material layer to substantially alter (eg, destroy) the dielectric material, thereby reducing the resistance of the dielectric material layer. Typically, to determine the state of an antifuse bit, a read voltage is applied across a layer of dielectric material and the resulting current is read.

According to some embodiments of the present disclosure, a method of generating an integrated circuit layout diagram is provided. The method includes the following steps: placing the first active area between the second active area and the third active area and adjacent to the second active area and the third active area in the layout of the integrated circuit, the first active area, the third active area Each of the two active regions and the third active region extends along the first direction; the first active region is made to intersect the adjacent first to fourth gate regions, thereby defining the first antifuse bit The gate of the anti-fuse structure of the first anti-fuse bit, the gate of the transistor of the first anti-fuse bit, the gate of the transistor of the second anti-fuse bit and the anti-fuse structure of the second anti-fuse bit corresponding positions in the gate of the intersecting the gate regions and intersecting the second conductive region and the fourth gate region; and aligning separate third and fourth conductive regions along the first direction and between the first active region and the third active region , whereby the third conductive region intersects the first gate region and the fourth conductive region intersects the third gate region, or the third conductive region intersects the second gate region and the fourth conductive region intersects the The four gate regions intersect. At least one of the following steps is performed by the processor of the computer: placing the first active region so that the adjacent first active region intersects the first gate region to the fourth gate region, and aligning the individual first conductive regions area and the second conductive area, or align the separate third and fourth conductive areas.

According to some embodiments of the present disclosure, there is also provided an integrated circuit device including a first anti-fuse structure, a second anti-fuse structure, a first transistor, a second transistor, a first via, and a first The second through hole and the third through hole are and the fourth through hole. The first antifuse structure includes a first dielectric layer between the first gate conductor and the first active region. The first gate conductor extends in the first direction. The first active region extends along a second direction perpendicular to the first direction. The second antifuse structure includes a second dielectric layer between the second gate conductor and the first active region. The second gate conductor extends in the first direction. The first transistor includes a third gate conductor extending in a first direction between the first gate conductor and the second gate conductor. The second transistor includes a fourth gate conductor extending in the first direction between the second gate conductor and the third gate conductor. The first through hole and the second through hole are electrically connected to the first gate conductor. The third via is electrically connected to the second gate conductor. The fourth via is electrically connected to the third gate conductor or the fourth gate conductor. The first through hole and the third through hole are aligned with each other along the second direction, and are placed between the first active region and the second active region. The second active area is adjacent to the first active area along the first direction. The second through hole and the fourth through hole are aligned with each other along the second direction, and are placed between the first active region and the third active region. The third active area is adjacent to the first active area along the first direction.

According to some embodiments of the present disclosure, there is also provided an electronic design automation system including a processor and a non-transitory computer-readable storage medium. A non-transitory computer-readable storage medium includes computer program code for one or more programs. The non-transitory computer-readable storage medium and the computer code are configured to, with the processor, cause the system to perform the steps of: placing by adjoining the first and second layout units and the third and fourth layout units The first layout unit to the fourth layout unit. The first layout unit and the second layout unit adjoin and uniformly define a first active area corresponding to the first anti-fuse bit and the second anti-fuse bit. The third layout unit and the fourth layout unit The adjacency uniformly defines a second active region corresponding to the third antifuse bit and the fourth antifuse bit. The first to fourth layout units uniformly define the third active area. The third active area corresponds to the fifth anti-fuse bit and the sixth anti-fuse bit. The fifth antifuse bit and the sixth antifuse bit are adjacent to the first antifuse bit and the second antifuse bit and the third antifuse bit and the fourth antifuse bit. The first layout unit includes a first through hole region covering the first gate region and a second through hole region covering the second gate region. The first gate region is shared by a plurality of anti-fuse structures of the first anti-fuse bit, the third anti-fuse bit and the fifth anti-fuse bit. The second gate region is shared by a plurality of transistor structures of the first anti-fuse bit, the third anti-fuse bit and the fifth anti-fuse bit. The fourth layout unit includes a third through hole region covering the third gate region and a fourth through hole region covering the fourth gate region. The third gate region is shared by the transistor structures of the second anti-fuse bit, the fourth anti-fuse bit and the sixth anti-fuse bit. The fourth gate region is shared by multiple anti-fuse structures of the second anti-fuse bit, the fourth anti-fuse bit and the sixth anti-fuse bit. The third layout unit includes a fifth through hole region and a sixth through hole region covering the first gate region. The second layout unit includes a seventh through hole region covering the fourth gate region and a plurality of eighth through hole regions. The non-transitory computer-readable storage medium and computer code are configured to, with the processor, cause the system to perform the steps of generating an integrated circuit layout. The integrated circuit layout diagram includes the arrangement of the first layout unit to the fourth layout unit.

100: Antifuse layout

100A: Antifuse layout

100B: Antifuse Layout

100C: Antifuse Layout

210: Operation

220:Operation

230:Operation

240:Operation

250: Operation

260:Operation

270:Operation

280: Operation

290:Operation

300A: Antifuse Array

300B: Antifuse Array

300C: Antifuse Array

300D: Antifuse Array

410: Operation

420: Operation

430: Operation

440: Operation

450: Operation

460: Operation

500: IC Components

500S: Substrate

600: Method

610: Operation

620: Operation

630: Operation

640: Operation

700: Electronic Design Automation (EDA) Systems

702: Hardware Processor

704: Non-transitory computer-readable storage medium

706: Computer code

707: Cell library

708: Busbar

710: I/O interface

712: Web Interface

714: Internet

742: User Interface

800: Manufacturing Systems

820: Design Studio

822: IC Design Layout

830: Reticle Room

832: Data preparation

844: Photomask Manufacturing

845: Photomask

850:ICfab

852: Wafer Fabrication Tools

853: Semiconductor Wafers

860: IC Components

X: direction

Y: direction

Z: direction

Z1: Conductive zone

Z2: Conductive zone

Z3: Conductive zone

Z4: Conductive zone

A-A': plane

AA1: Active area

AA2: Active area

AA3: Active area

AA4: Active area

AB1: Antifuse bit

AB2: Antifuse bit

AB3: Antifuse bit

AB4: Antifuse bit

AB5: Antifuse bit

AB6: Antifuse bit

AB7: Antifuse bit

AB8: Antifuse bit

AB1P: Antifuse Structure

AB1R: Transistor

AB5P: Antifuse structure

AB5R: Transistor

ABL1: bit line

ABL2: bit line

ABL3: Bit Line

ABL4: Bit Line

AR1: Active area

AR2: Active area

AR3: Active area

AVR1: Through hole area

AVR2: Through hole area

AVR3: Through hole area

AVR4: Through hole area

AVR5: Through hole area

AVR6: Through hole area

AVR7: Through hole area

AVR8: Through hole area

AZ1: Conductive area

AZ2: Conductive area

AZ3: Conductive area

AZ4: Conductive area

AZ5: Conductive area

AZ6: Conductive area

AZ7: Conductive area

AZ8: Conductive area

B-B': plane

B1: Antifuse bit

B2: Antifuse bit

B3: Antifuse bit

B4: Antifuse bit

B5: Antifuse bit

B6: Antifuse bit

B1R: Transistor

B1P: Antifuse structure

B2R: Transistor

B2P: Antifuse Structure

B3R: Transistor

B3P: Antifuse Structure

B4R: Transistor

B4P: Antifuse Structure

B5R: Transistor

B5P: Antifuse structure

B6R: Transistor

B6P: Antifuse structure

BA: Boundary

BB: Boundary

BC: frontier

BL1: bit line

CA: layout unit

CC: layout unit

C1: Contact

C2: Contact

C3: Contact

C4: Contact

CA1: Layout unit

CA2: Layout unit

CB1: Layout Cell

CB2: Layout Cell

CC1: Layout Cell

CC2: Layout Cell

CR1: Contact area

D1: Distance

D2: Distance

IBL: current

G2: Gate structure

G3: Gate structure

G4: Gate structure

G5: Gate structure

GC2: gate conductor

GC3: Gate conductor

GC4: Gate conductor

GC5: Gate conductor

GD2: Dielectric layer

GD3: Dielectric layer

GD4: Dielectric layer

GD5: Dielectric layer

GR1: gate region

GR2: gate region

GR3: gate region

GR4: gate region

GR5: gate region

GR6: gate area

M11: Conductive segment

M12: Conductive segment

M13: Conductive segment

M14: Conductive segment

M15: Conductive segment

M16: Conductive segment

M17: Conductive segment

M18: Conductive segment

M21: Conductive segment

M22: Conductive segment

M23: Conductive segment

M24: Conductive segment

MBL1: bit line

MBL2: bit line

MBL3: bit line

MBL4: Bit Line

MR1: Conductive region

MR2: Conductive region

MR3: Conductive region

MR4: Conductive region

RAB1: Resistor

RAB5: Resistor

RABL1: Resistor

RABL2: Resistor

RABL3: Resistor

RABL4: Resistor

RR0: Resistor

RR1: Resistor

RP0: Resistor

2RP0: Resistor

RP1: Resistor

RVZ:RVZ

V11: Through hole

V12: Through hole

V13: Through hole

V14: Through hole

V15: Through hole

V16: Through hole

V17: Through hole

V18: Through hole

V21: Through hole

V22: Through hole

V23: Through hole

V24: Through hole

V25: Through hole

V26: Through hole

V27: Through hole

V28: Through hole

VR1: Through hole area

VR2: Through hole area

VR3: Through hole area

VR4: Through hole area

WLP0:Signal

WLP1:Signal

WLR0: Signal

WLR1: Signal

Aspects of some embodiments of the present disclosure may be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that according to industry standards In practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

1A-1D are diagrams of antifuse layouts according to some embodiments.

1E-1G are schematic diagrams of portions of an antifuse array in accordance with some embodiments.

FIG. 2 is a flowchart of a method of generating an IC layout, according to some embodiments.

3A-3D are diagrams of an antifuse array in accordance with some embodiments.

FIG. 4 is a flowchart of a method of generating an IC layout, according to some embodiments.

5A-5C are diagrams of IC elements according to some embodiments.

6 is a flowchart of a method of operating an antifuse bit according to some embodiments.

7 is a block diagram of an electronic design automation (EDA) system according to some embodiments.

8 is a block diagram of an IC manufacturing system and an IC manufacturing flow associated therewith, in accordance with some embodiments.

The following disclosure provides numerous different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components, materials, values, steps, operations, materials, arrangements, or the like are described below to simplify some embodiments of the present disclosure. Of course, these examples are merely examples and are not intended to be limiting. Envision other components, values, operations, materials, arrangements, or classes Similar items. For example, in the description that follows, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include additional features that may be formed on Embodiments in which the first and second features may not be in direct contact between the first and second features. Additionally, the present disclosure may repeat reference numerals and/or letters throughout the examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and/or configurations discussed.

In addition, spatially relative terms, such as "below," "below," "lower," "above," "upper," and the like, are used herein to facilitate the description of one element or feature illustrated in the figures and another Relationship of element(s) or feature(s). In addition to the orientation depicted in the figures, spatially relative terms are intended to encompass different orientations of elements in use or operation. The device may be differently oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted likewise accordingly.

In various embodiments, an IC layout and an antifuse element fabricated based on the IC layout include four electrical connections between each active region corresponding to two antifuse bits and two adjacent active regions. The increased number of parallel current paths to a given antifuse bit reduces the number of electrical connections between the active region corresponding to two antifuse bits and the adjacent active region with fewer than four electrical connections. Path resistance is reduced, thereby increasing current flow and improving performance in both program and read operations.

1A-1C are diagrams of antifuse layouts 100A- 100C in accordance with some embodiments. Figures 1A-1C depict corresponding antifuse layouts 100A-100C in the X direction and the Y direction perpendicular to the X direction floor plan. The anti-fuse layout 100A includes a layout cell CA1 adjacent to the layout cell CB1 in the X direction, thereby sharing a boundary BA extending in the Y direction; the anti-fuse layout 100B includes a layout cell CB2 adjacent to the layout cell CC1 in the X direction, by This shares a boundary BB extending in the Y direction; and the antifuse layout 100C includes a layout cell CB2 adjacent to the layout cell CB1 in the X direction, thereby sharing a boundary BC extending in the Y direction.

Each of antifuse layouts 100A and 100B includes alternate embodiments indicated by the selective inversion of the Y direction. An alternate embodiment of antifuse layout 100A includes layout cell CA2 corresponding to layout cell CA1 inverted in the Y direction, and an alternate embodiment of antifuse layout 100B includes a layout corresponding to layout cell CC1 inverted in the Y direction Unit CC2. Due to vertical symmetry considerations, layout cells CB1 and CB2 are not affected by inversion in the Y direction.

IC layouts (eg, IC layouts including antifuse layouts 100A-100C) may be used in a manufacturing process, such as the IC manufacturing flow associated with IC manufacturing system 800 discussed below with respect to FIG. 8, to define IC components (eg, , part of one or more features of IC device 500) discussed below with respect to FIGS. 5A-5C.

In various embodiments, placement cells (eg, placement cells CA1, CA2, CB1, CB2, CC1, or CC2) are independent cells (eg, stored in a cell library (eg, cell library 707 as discussed below with respect to FIG. 7) standard cells), or are part of a larger IC layout (eg, standard cells or other circuits that include features other than those depicted in Figures 1A-1C). In some embodiments, multiple layout units (eg, cloth Office cells CA1(CA2)/CB1, CB2/CC1(CC2), or CB2/CB1), are stored as individual cells in the cell library. In some embodiments, layout cells (eg, layout cells CA1 , CA2 , CB1 , CB2 , CC1 , or CC2 ) are included in an antifuse array (eg, the antifuses discussed below with respect to FIGS. 1D-1G ) layout 100).

Each of antifuse layouts 100A-100C includes bit line BL1 extending in the X direction. In some embodiments, the portion of bit line BL1 that intersects a given layout cell is included in the corresponding layout cell CA1, CA2, CB1, CB2, CC1, or CC2. In some embodiments, the portion of bit line BL1 that intersects a given layout cell is not included in the corresponding layout cell CA1, CA2, CB1, CB2, CC1, or CC2, and is an antifuse layout 100A, 100B, or 100C Parts separated from a given layout unit.

Each of the antifuse layouts 100A-100C includes adjacent gate regions GR1-GR6 extending in the Y direction. In various embodiments, portions of gate regions GR1-GR6 where some or all of the gate regions GR1-GR6 intersect a given layout cell are included in the corresponding layout cell CA1, CA2, CB1, CB2, CC1, or CC2, or are not included in the corresponding layout cell Cells CA1, CA2, CB1, CB2, CC1, or CC2, and are components of the antifuse layout 100A, 100B, or 100C that are separate from a given layout cell.

Each of the layout cells CA1 , CA2 , CB1 , CB2 , CC1 , and CC2 includes a portion of each of the adjacent active regions AR1 , AR2 , and AR3 extending in the X direction. The layout cells CA1, CA2, or CB2 are adjacent to the layout cells CB1, CC1, or CC2 in the X direction to be uniformly bounded. The combined part of the active area AR1, the whole of the active area AR2, and the combined part of the active area AR3 are determined. In various embodiments, layout cells CA1, CA2, or CB2 adjacent to layout cells CB1, CC1, or CC2 are unified with layout cells other than layout cells CA1, CA2, or CB2 and layout cells CB1, CC1, or CC2 ( (not shown) adjoin and thereby collectively define the entirety of one or both of the active regions AR1 or AR3.

Active regions (eg, active regions AR1, AR2, or AR3) are regions in an IC layout (eg, IC layouts including antifuse layouts 100A-100C) that are included in the manufacturing process as part of defining the active regions , also known as oxide diffusion or definition (OD) in a semiconductor substrate in which one or more IC device features (eg, source/drain regions) are formed. In various embodiments, the active region is an N-type or P-type active region of a planar transistor or a fin field-effect transistor (FinFET). In some embodiments, the active regions are included in the manufacturing process as part of defining the active regions AA1-AA4 discussed below with respect to Figures 5A-5C.

Gate regions (eg, gate regions GR1-GR6) are regions in an IC layout (eg, IC layouts including antifuse layouts 100A-100C) that are included in the manufacturing process as defining IC elements including conductive A portion of a gate structure of at least one of a material or a dielectric material. In various embodiments, one or more gate structures corresponding to gate regions GR1-GR6 include at least one conductive material overlying at least one dielectric material. In some embodiments, gate regions are included in the manufacturing process as defined below with respect to Portions of gate structures G2-G5 discussed in Figures 5A-5C.

In the embodiment depicted in Figures 1A-1C, each gate region GR2-GR5 intersects each active region AR1, AR2, and AR3. In various embodiments, one or more of gate regions GR2-GR5 do not intersect with one or more of active regions AR1 or AR3, or one or more gate regions other than gate regions GR2-GR5 (not shown) intersects one or more of active regions AR1, AR2, or AR3.

In the embodiment depicted in Figures 1A-1C, each gate region GR1 and GR6 does not intersect with any of the active regions AR1, AR2, or AR3. In some embodiments, the gate regions GR1 and GR6 are referred to as dummy gate regions corresponding to dummy gate structures of the IC device. In various embodiments, one or more of gate regions GR1 or GR6 intersect or adjoin one or more of active regions AR1, AR2, or AR3. In various embodiments, layout cells CA1, CA2, or CB2 include one or more gate regions (not shown) in addition to gate regions GR1-GR3, and/or layout cells CA1, CA2, or CB2 do not include One or more of the gate regions GR1-GR3. In various embodiments, layout cells CB1, CC1, or CC2 include one or more gate regions (not shown) in addition to gate regions GR4-GR6, and/or layout cells CB1, CC1, or CC2 do not include One or more of gate regions GR4-GR6.

Each of the layout cells CA1, CA2, and CB2 includes a conductive region Z1 extending in the X direction between the active region AR1 and the active region AR2, and a conductive region Z2 extending in the X direction between the active region AR2 and the active region AR3 . Each of layout cells CB1, CC1, and CC2 It includes a conductive region Z3 extending in the X direction between the active region AR1 and the active region AR2, and a conductive region Z4 extending in the X direction between the active region AR2 and the active region AR3. Conductive zone Z1 is aligned with conductive zone Z3 in the X direction, and conductive zone Z2 is aligned with conductive zone Z4 in the X direction.

Conductive regions (eg, bit line BL1 or conductive regions Z1-Z4) are regions in an IC layout (eg, IC layout including antifuse layouts 100A-100C) that are included in the fabrication process to define IC elements part of one or more segments of one or more conductive layers. In various embodiments, one or more of conductive regions Z1-Z4 or bit line BL1 correspond to one or more segments of the same or different conductive layers in the IC element. In various embodiments, one or more of conductive regions Z1-Z4 or bit line BL1 corresponds to one or more of a first metal layer, a second metal layer, or higher metal layers in the IC element. In some embodiments, one or more of conductive regions Z1-Z4 or bit line BL1 corresponds to a metal layer known as a metal zero layer in an IC device. In some embodiments, conductive regions (eg, conductive regions Z1-Z4 or bit line BL1) are included in the fabrication process to define conductive segments M11-M18 or M21-discussed below with respect to FIGS. 5A-5C M24 or part of bit lines MBL1-MBL4.

In each of antifuse layouts 100A-100C, conductive region Z1 intersects gate regions GR1 and GR2, and via region VR1 is placed where conductive region Z1 intersects gate region GR2.

In antifuse layout 100A, conductive region Z2 intersects each of gate regions GR1-GR3, and via region VR2 is placed where conductive region Z2 intersects gate region GR3. In some embodiments, the antifuse cloth In the station 100A, the conductive region Z2 intersects with the gate regions GR2 and GR3 but does not intersect with the gate region GR1. In the anti-fuse layouts 100B and 100C, the conductive region Z2 intersects the gate regions GR1 and GR2, and the via region VR2 is placed where the conductive region Z2 intersects the gate region GR2.

In each of antifuse layouts 100A-100C, conductive region Z3 intersects gate regions GR5 and GR6, and via region VR3 is placed where conductive region Z3 intersects gate region GR5.

In the antifuse layouts 100A and 100C, the conductive region Z4 intersects the gate regions GR5 and GR6, and the via region VR4 is placed where the conductive region Z4 intersects the gate region GR5. In antifuse layout 100B, conductive region Z4 intersects each of gate regions GR4-GR6, and via region VR4 is placed where conductive region Z4 intersects gate region GR4. In some embodiments, in antifuse layout 100B, conductive region Z4 intersects gate regions GR4 and GR5 but does not intersect gate region GR6.

Via regions (eg, via regions VR1-VR4) are regions in an IC layout (eg, an IC layout including antifuse layouts 100A-100C) that are included in the manufacturing process as defining one of the IC components or A portion of one or more segments of a plurality of conductive layers configured to conduct between a conductive layer segment corresponding to a conductive region and a gate structure corresponding to a gate region or another conductive region corresponding to another conductive region Electrical connections are formed between the layer segments. In various embodiments, the one or more conductive layer segments formed based on the via regions comprise vias located in the gate structures or segments in a given metal layer and segments in the overlying metal layer of the IC element between. In some embodiments, the via regions correspond to slotted vias or square vias in IC components. In some embodiments, the The hole region is included in the fabrication process as part of defining the vias V11-V18 or V21-V28 discussed below with respect to Figures 5A-5C.

In each of antifuse layouts 100A-100C, bit line BL1 intersects active region AR2 and is within active region AR2 between gate region GR3 and gate region GR4 and along layout cells CA1 , A boundary BA, BB, or BC between CA2, or CB2, and layout cells CB1, CC1, or CC2 places a contact region CR1. In various embodiments, one or more of antifuse layouts 100A-100C include one or more bit lines (not shown) and one or more contacts in addition to bit line BL1 and contact region CR1 Regions (not shown) (eg, bit lines and contact regions that intersect active regions AR1 or AR3).

A contact region (eg, contact region CR1 ) is a region in an IC layout (eg, an IC layout including antifuse layouts 100A-100C) that is included in the manufacturing process to define one or more conductive layers in an IC element A portion of one or more segments configured to form electrical current between the segment corresponding to the conductive region (eg, bit line BL1 ) and the active region corresponding to the active region (eg, active region AR2 ) connect. In various embodiments, the one or more conductive layer segments formed based on the contact regions include contacts between corresponding active regions and conductive segments of the IC element. In some embodiments, contact regions are included in the fabrication process as part of defining contacts C1-C4 discussed below with respect to Figures 5A-5C.

With the above configuration, the IC device fabricated based on the anti-fuse layouts 100A-100C includes the anti-fuse bits B2 and B5 placed in the active region based on the active region AR2. The anti-fuse bit B2 includes the anti-fuse structure B2P and the electrical Crystal B2R. Antifuse structure B2P has a gate (also referred to as B2P) located at a location bounded by the intersection of active region AR2 and gate region GR2, and transistor B2R has a gate located at a location bounded by the intersection of active region AR2 and gate region GR3. gate at the location (also known as B2R). The anti-fuse bit B5 includes an anti-fuse structure B5P and a transistor B5R. Antifuse structure B5P has a gate (also referred to as B5P) located at a location bounded by the intersection of active region AR2 and gate region GR5, and transistor B5R has a gate located at a location bounded by the intersection of active region AR2 and gate region GR4. gate at location (also known as B5R).

In the embodiment in which the anti-fuse layouts 100A-100C are adjacent to layout cells adjacent to the active region AR1, IC devices fabricated based on the anti-fuse layouts 100A-I00C and the adjacent layout cells include cells located within the active region based on the active region AR1. Antifuse bits B1 and B4. The anti-fuse bit B1 includes an anti-fuse structure B1P and a transistor B1R. Antifuse structure B1P has a gate (also referred to as B1P) located at a location bounded by the intersection of active region AR1 and gate region GR2, and transistor B1R has a gate located at a location bounded by the intersection of active region AR1 and gate region GR3 gate at location (also known as B1R). The anti-fuse bit B4 includes an anti-fuse structure B4P and a transistor B4R. Antifuse structure B4P has a gate (also referred to as B4P) located at a location bounded by the intersection of active region AR1 and gate region GR5, and transistor B4R has a gate located at a location bounded by the intersection of active region AR1 and gate region GR4. Gate at location (also known as B4R).

In an embodiment where the antifuse layouts 100A-100C are contiguous with layout cells adjacent to the active region AR3, based on the antifuse layout IC devices fabricated by 100A-100C and adjacent layout cells include antifuse bits B3 and B6 located in the active area based on the active area AR3. The anti-fuse bit B3 includes an anti-fuse structure B3P and a transistor B3R. Antifuse structure B3P has a gate (also referred to as B3P) located at a location bounded by the intersection of active region AR3 and gate region GR2, and transistor B3R has a gate located at a location bounded by the intersection of active region AR3 and gate region GR3. Gate at location (also known as B3R). The anti-fuse bit B6 includes an anti-fuse structure B6P and a transistor B6R. Antifuse structure B6P has a gate (also referred to as B6P) located at a location bounded by the intersection of active region AR3 and gate region GR5, and transistor B6R has a gate located at a location bounded by the intersection of active region AR3 and gate region GR4. gate at location (also known as B6R).

For each of the antifuse structures B1P-B6P, at least a portion of the gate structure based on the corresponding gate region GR2 or GR5 and the overlying active region based on the corresponding active region AR1-AR3 may correspond to include one or more A gate of a layer of various dielectric materials. This gate is configured such that, in operation, a sufficiently large electric field across the dielectric layer substantially changes the dielectric material, thereby significantly reducing the resistance of the dielectric layer from the level prior to application of the electric field. In some embodiments, the step of substantially changing the dielectric material is also referred to as breaking down the dielectric material. In some embodiments, one or more of the antifuse structures B1P-B6P are referred to as programmed transistors.

Therefore, the transistors B1R-B6R are electrically connected to the respective inverters through the active region portion based on the active regions AR1-AR3 between the gate region GR2 and the gate region GR3 or between the gate region GR4 and the gate region GR5. Fuse structure B1P-B6P. Through the active area based on the corresponding active area AR1-AR3 In part, corresponding active regions AR1-AR3 are between gate region GR3 and gate region GR4 and in series with one or more conductive segments corresponding to contact region CR1, based on the corresponding bit line (eg, bit line BL1) The transistors B1R-B6R are electrically connected to one or more segments.

The gate structure corresponding to gate region GR2 is thus configured as a terminal of each of antifuse structures B1P-B3P, and the gate structure corresponding to gate region GR3 is thus configured as one of transistors B1R-B3R. The gate of each, the gate structure corresponding to gate region GR4 is thus configured as the gate of each of transistors B4R-B6R, and the gate structure corresponding to gate region GR5 is thus configured as Terminals for each of antifuse structures B4P-B6P.

In each of antifuse layouts 100A-100C, conductive region Z1 and via region VR1 define locations that are electrically connected to each of antifuse structures B1P-B3P through a gate structure corresponding to gate region GR2 .

In antifuse layout 100A, conductive region Z2 region and via region VR2 define locations that are electrically connected to each of transistors B1R-B3R through the gate structure corresponding to gate region GR3. In antifuse layouts 100A and 100C, conductive region Z2 and via region VR2 define locations that are electrically connected to each of antifuse structures B1P-B3P through the gate structure corresponding to gate region GR2.

In each of antifuse layouts 100A-100C, conductive region Z3 and via region VR3 define locations that are electrically connected to each of antifuse structures B4P-B6P through a gate structure corresponding to gate region GR5 .

In antifuse layouts 100A and 100C, conductive regions Z4 and Via region VR4 defines a location that is electrically connected to each of antifuse structures B4P-B6P through the gate structure corresponding to gate region GR5. In antifuse layout 100B, conductive region Z4 and via region VR4 define locations that are electrically connected to each of transistors B4R-B6R through a gate structure corresponding to gate region GR4.

In each of the antifuse layouts 100A-100C, the conductive regions Z1 and Z3 are separated by a distance D1 along the X direction. In antifuse layouts 100A and 100B, conductive regions Z2 and Z4 are separated by a distance D2 along the X direction, and in antifuse layout 100C, conductive regions Z2 and Z4 are separated by a distance D1.

Each of distance D1 and distance D2 has a value greater than or equal to a predetermined distance based on one or more design rules for the conductive layer including conductive regions Z1-Z4, and thereby corresponds to one or more design rules. In various embodiments, the predetermined distance is based on a minimum spacing rule for a metal layer (eg, a first metal layer), or between conductive zone Z1 and conductive zone Z3 or between conductive zone Z2 and conductive zone Z4 One or a combination of minimum separation rules based on circuit design voltage differences. In a non-limiting example, the minimum separation rule for voltage differences based on circuit design is the minimum distance between two conductors that is configured such that one of the two conductors can carry the supply voltage level, and both conductors The other one can transmit the reference voltage level or the ground voltage level.

In some embodiments, one or both of distance D1 or distance D2 has a value greater than or equal to the minimum spacing rule based on one or more manufacturing process constraints. In some embodiments, the minimum spacing rule is based on manufacturing The wavelength of electromagnetic waves used in one or more lithography operations of the process. In some embodiments, the minimum spacing rule is based on an extreme ultraviolet (EUV) manufacturing process. In some embodiments, the EUV fabrication process corresponds to wavelengths ranging from 12 nanometers (nm) to 15 nm. In some embodiments, the EUV manufacturing process corresponds to a wavelength approximately equal to 13.5 nm.

In the embodiment depicted in Figures 1A-1C, distance D1 is greater than distance D2. In various embodiments, distance D1 is equal to or less than distance D2.

In the embodiment depicted in Figures 1A-1C, the distance D1 is large enough that the corresponding conductive region Z1 or Z2 does not intersect the gate region GR3, and the corresponding conductive region Z3 or Z4 does not intersect the gate region GR4. In various embodiments, distance D1 corresponds to one or both of corresponding conductive regions Z1 or Z2 intersecting gate region GR3 or corresponding conductive regions Z3 or Z4 intersecting gate region GR4.

Distance D2 is sufficiently small that conductive region Z2 intersects gate region GR3 and conductive region Z4 intersects gate region GR5, or conductive region Z2 intersects gate region GR2 and conductive region Z4 intersects gate region GR4.

In IC components fabricated based on antifuse layouts 100A-100C, the total number of electrical connections to antifuse structures B1P-B6P and transistors B1R-B6R is based on two vias between each pair of adjacent active regions The gate structures are connected, where antifuse bits B1-B6 are placed in these active regions. Thereby a total of four electrical connections are located between the two active regions adjacent to the active region and corresponding to the two antifuse bits. Compared to a through-hole gate structure connection complete With an all between adjacent active regions approach, IC components fabricated based on the antifuse layouts 100A-100C can thus include an increased number of electrical connections per antifuse bit. Based on an increased number of parallel current paths to a given antifuse bit, path resistance is reduced and current is increased, thereby improving performance in both programming and read operations, as discussed further below.

Figure ID is a diagram of an antifuse layout 100 in accordance with some embodiments. Antifuse layout 100 is a non-limiting example of a layout of an antifuse array based on a combination of antifuse layouts 100A-100C. As depicted in Figure 1D, based on anti-fuse layouts 100A and 100B, anti-fuse layout 100 includes layout cell CA1 adjacent to layout cell CB1 in the X direction, and layout cells adjacent to layout cells CB2 and CC1 in the Y direction CA1 and CB1. Details of layout cells CA1, CB1, CB2, and CC1 are omitted for clarity.

Based on the configuration of layout cells CA1, CB1, CB2, and CC1, two layout cells (not labeled) adjacent to layout cells CB2 and CC1 in the negative Y direction, and gate regions and GR2-GR5, antifuse layout 100 corresponds to an anti-fuse Fuse bits AB1-AB8, each of which is an instance of antifuse bits B1-B6. Bit line ABL1 is associated with antifuse bits AB1 and AB5, bit line ABL2 is associated with antifuse bits AB2 and AB6, bit line ABL3 is associated with antifuse bits AB3 and AB7, and bit line ABL3 is associated with antifuse bits AB3 and AB7. Metaline ABL4 is associated with antifuse bits AB4 and AB8. Conductive regions AZ1-AZ8 correspond to examples of conductive regions Z1-Z4 of antifuse layouts 100A-100C.

Antifuse layout 100 includes conductive regions MR1-MR4, each along Extends in the Y direction. Conductive region MR1 intersects each of conductive regions AZ1-AZ4, and via regions AVR1, AVR3, and AVR4 are placed at locations where conductive region MR1 intersects conductive regions AZ1, AZ3, and AZ4, respectively. Conductive region MR2 intersects each of conductive regions AZ1-AZ4, and via region AVR2 is placed at a position where conductive region MR2 intersects conductive region AZ2. Conductive region MR3 intersects each of conductive regions AZ5-AZ8, and via region AVR8 is placed at a position where conductive region MR3 intersects conductive region AZ8. Conductive region MR4 intersects each of conductive regions AZ5-AZ8, and via regions AVR5-AVR7 are placed at positions where conductive region MR4 intersects conductive regions AZ5-AZ7, respectively.

In the embodiment depicted in Figure ID, antifuse layout 100 includes conductive regions MR1-MR4, gate regions GR2-GR5, and bit lines ABL1-ABL4 corresponding to a total of eight antifuse bits AB1-AB8. In various embodiments, antifuse layout 100 includes conductive regions MR1-MR4 and gate regions GR2-GR5 extending in the positive and/or negative Y direction, thereby corresponding to all but antifuse bits AB1-AB8 Antifuse bit (not shown). In various embodiments, antifuse layout 100 includes bit lines ABL1-ABL4 extending in positive and/or negative X directions, thereby corresponding to antifuse bits other than antifuse bits AB1-AB8 ( not shown).

An IC device (eg, an antifuse array) fabricated based on antifuse layout 100 is thereby configured such that conductive segments based on conductive region MR1 are electrically connected through at least three current paths corresponding to conductive regions AZ1 , AZ3 , and AZ4 Terminals of the antifuse structure to each of antifuse bits AB1-AB4, and through at least one current path corresponding to conductive area AZ2 The diameter electrically connects the conductive segment based on conductive region MR2 to the gate of the transistor of each of antifuse bits AB1-AB4. The conductive segments based on conductive region MR3 are thereby electrically connected to the gates of the transistors of each of antifuse bits AB5-AB8 through at least one current path corresponding to conductive region AZ8, and through the conductive regions corresponding to conductive regions At least three current paths of AZ5-AZ7 electrically connect the conductive segment based on conductive region MR4 to the terminals of the antifuse structure of each of antifuse bits AB5-AB8.

The gate structure corresponding to gate region GR2 is thereby configured as a terminal of each of the anti-fuse structures of anti-fuse bits AB1-AB4, and is responsive to a signal received on a segment corresponding to conductive region MR1. Signal WLP0. The gate structure corresponding to gate region GR3 is thereby configured as the gate of each of the transistors of antifuse bits AB1-AB4, and responsive to signals received on the segment corresponding to conductive region MR2 WLR0. The gate structure corresponding to gate region GR4 is thereby configured as the gate of each of the transistors of anti-fuse bits AB5-AB8 and responsive to signals received on the segment corresponding to conductive region MR3 WLR1. The gate structure corresponding to gate region GR5 is thereby configured as a terminal of each of the anti-fuse structures of anti-fuse bits AB5-AB8, and is responsive to a signal received on a segment corresponding to conductive region MR4. Signal WLP1. Signals WLP0, WLR0, WLR1 and WLP1 and antifuse bits AB1-AB8 are discussed below with respect to Figures 1E-1G.

1E is a schematic diagram of a portion of an antifuse layout 100 corresponding to antifuse bits AB1 and AB5, according to some embodiments. As depicted in Figure 1E, bit line ABL1 is electrically connected to the gate region GR3 and the gate The first source/drain terminals of each of transistor AB1R of anti-fuse bit AB1 and transistor AB5R of anti-fuse bit AB5 in the corresponding active region portion between regions GR4. The second source/drain terminal of transistor AB1R is electrically connected to the source/source of antifuse structure AB1P of antifuse bit AB1 in the corresponding active region portion between gate region GR2 and gate region GR3 The drain terminal, and the second source/drain terminal of transistor AB5R are electrically connected to the antifuse structure of antifuse bit AB5 in the corresponding active region portion between gate region GR4 and gate region GR5 Source/drain terminals of AB5P.

The portion of the gate structure corresponding to the gate region GR2, which is between the antifuse bit AB1 and one of the conductive regions AZ1 or AZ2, and the gate corresponding to the gate region GR5, are denoted as resistor RP0. The pole structure portion is denoted as resistor RP1, with gate region GR5 between antifuse bit AB5 and one of conductive regions AZ5 or AZ6.

In program and read operations on anti-fuse bit AB1, signal WLP0 is applied to anti-fuse structure AB1P through resistor RP0 in response to signal WLR0 applied through the gate structure corresponding to gate region GR3 to turn on transistor AB1R and apply a reference voltage to bit line ABL1. In program and read operations on anti-fuse bit AB5, signal WLP1 is applied to anti-fuse structure AB5P through resistor RP1 in response to signal WLR1 applied through the gate structure corresponding to gate region GR4 to turn on transistor AB5R and apply the reference voltage level to bit line ABL1.

During the process of either antifuse bit AB1 or AB5 During format and read operations, current IBL flows to bit line ABL1. The magnitude and polarity of current IBL is based on the magnitude and polarity of signals WLP0 and WLP1 with respect to the reference voltage applied to bit line ABL1, and is based on any of the series of resistors RP0, antifuse structure AB1P, and transistor AB1R. One, or the path resistance value represented by any of the resistor RP1, the antifuse structure AB5P, and the transistor AB5R series.

In the embodiment depicted in Figure 1E, the antifuse structures AB1P and AB5P and the transistors AB1R and AB5R are NMOS devices, whereby the transistors AB1R and AB5R are configured to turn on in response to the respective signal WLR0 or WLR1, wherein The signal WLR0 or WLR1 has a sufficiently large positive value with respect to the reference voltage level. In some embodiments, antifuse structures AB1P and AB5P and transistors AB1R and AB5R are PMOS devices, whereby transistors AB1R and AB5R are configured to turn on in response to a respective signal WLR0 or WLR1, wherein signal WLR0 or WLR1 Has a sufficiently large negative value with respect to the reference voltage level.

In a programming operation, the signal WLP0 or WLP1 has a programming voltage level such that the difference between the programming voltage level and the reference voltage level produces a voltage across the dielectric layer of the gate of the corresponding antifuse structure AB1P or AB5P An electric field, which is large enough to substantially alter the dielectric material, and the resulting reduced resistance are shown in Figure 1E as resistors RAB1 or RAB5, respectively.

In a read operation, the signal WLP0 or WLP1 has a read voltage level such that the difference between the read voltage level and the reference voltage level generates an electric field that is small enough to avoid substantially changing the corresponding antifuse structure AB1P or AB5P dielectric material, and large enough to generate a magnitude of The current IBL can be sensed by a sense amplifier (not shown) and used thereby to determine the programmed state of the corresponding antifuse structure AB1P or AB5P.

In various embodiments, one or both of the programming or reading voltage levels are positive relative to the reference voltage level or negative relative to the reference voltage level.

FIG. 1F is a schematic diagram of a portion of an antifuse layout 100 corresponding to antifuse bits AB1-AB8, according to some embodiments. Figure 1F includes signals WLP0, WLR0, WLR1 and WLP1, resistors RP0 and RP1, bit lines ABL1-ABL4 and antifuse bits AB1-AB8 (discussed above with respect to Figures 1D and 1E) and above Gate structures G2-G5 based on respective gate regions GR2-GR5 discussed with respect to Figures 1A-1D.

Figure IF also includes resistors RR0, RR1, and RABL1-RABL4. Resistor RR0 represents the portion of gate structure G3 between a given one of anti-fuse bits AB1-AB4 and conductive area AZ2, and resistor RR1 represents gate structure G4 given in anti-fuse bits AB5-AB8. The portion between one and conductive region AZ8, and each resistor RABL1-RABL4 represents one or more conductive segments corresponding to a respective one of bit lines ABL1-ABL4.

As discussed above with respect to Figure 1E, resistor RP0 represents the length of the portion of gate structure G2 between antifuse bit AB1 and one of conductive regions AZ1 or AZ2, and resistor RP1 represents the length of gate structure G5 in anti-fuse of the portion between fuse bit AB5 and one of conductive areas AZ5 or AZ6 length. In the embodiment depicted in FIGS. 1F and 1G, gate structure G2 has the same length in each portion between antifuse bits AB1-AB4 and the nearest conductive region AZ1, AZ3, or AZ4, such that the resistors RP0 has the same value for each antifuse bit AB1-AB4, and gate structure G5 has the same length for each portion between antifuse bits AB5-AB8 and the nearest conductive area AZ5-AZ7, so that the resistor RP1 has the same value for each antifuse bit AB1-AB4.

In at least some examples, based on the layout of antifuse layout 100, the gate structure portion is different in length between a given one of antifuse bits AB1-AB8 and the nearest conductive region AZ2 or AZ8 than the gate structure portion One or more lengths between another one or more of antifuse bits AB1-AB8 and the nearest conductive region AZ2 or AZ8. In such an example, the corresponding resistors RR0 and/or RR1 have different nominal values based on different lengths.

In some embodiments, in at least some instances, the gate structure portion has a length between a given one or more of antifuse bits AB1-AB8 and the nearest conductive region AZ2 or AZ8 that is equal to one or more of the lengths The gate structure portion is the same length between one or more of the antifuse bits AB1-AB8 and the nearest conductive region AZ2 or AZ8. In such an example, the corresponding resistors RR0 and/or RR1 have the same nominal value based on the same length.

Resistors RABL1-RABL4 have values that vary based on the size of one or more conductive segments corresponding to the respective bit lines ABL1-ABL4. The size of such conductive segments includes based on a given antifuse bit The length of the bit line that varies along the position of the given bit line. In the embodiment depicted in Figures IF and 1G, the resistivity of one or more conductive segments is sufficiently small (the variation is not significant), and each resistor RABL1-RABL4 is considered to have the same nominal value .

FIG. 1G is a schematic diagram of a portion of an antifuse layout 100 corresponding to antifuse bits AB5-AB8, according to some embodiments. In addition to a subset of the features depicted in Figure IF, Figure 1G includes resistors RVZ and 2RPO.

Each resistor RVZ represents a conductive path corresponding to one of via regions AVR5-AVR7, the corresponding example of via region VR3 or VR4 discussed above with respect to FIGS. 1A-1C, and based on via region AVR5 - the corresponding portion of the conductive segments of conductive regions AZ5-AZ7 between one of AVR7 and the instance of via region VR3 or VR4. Resistors RVZ have the same nominal value based on each of the conductive regions AZ5-AZ7 having a similar layout.

Each resistor 2RPO represents the portion of gate structure G5 between adjacent antifuse bits AB7 and AB8 that does not contain electrical connections corresponding to instances of via region VR3 or VR4. Because gate structure G5 includes two portions corresponding to resistor RP0 for the portion corresponding to resistor 2RP0, the nominal value of resistor 2RP0 is significantly greater than the nominal value of resistor RP0. In some embodiments, the nominal value of resistor 2RP0 is approximately twice the nominal value of resistor RP0.

As discussed above with respect to Figure 1E, during a read operation on antifuse bit B5, signal WLP1 causes current IBL to flow through antifuse Bit AB5 and bit line ABL1, and the value of current IBL are used to determine the programmed state of antifuse bit AB5. As depicted in Figures 1F and 1G, the read current path for antifuse bit AB5 includes antifuse bit AB5 itself and resistor RABL1.

Based on the configuration of antifuse layout 100, as depicted in FIG. 1G, the read current path also includes a parallel current path between antifuse bit AB5 and signal WLP1 on the conductive segment corresponding to conductive region MR4. Based on conductive regions AZ5 and AZ6 adjacent to antifuse bit AB5, each of the two parallel current paths has a path resistance equal to the sum of RP0 and RVZ. The third parallel current path has a path resistance equal to RVZ plus three times RP0 based on conductive area AZ7 separating antifuse bit AB6 from antifuse bit AB5.

Similarly, for each anti-fuse bit AB6-AB8, the read current path includes the corresponding anti-fuse bit, one of the resistors RABL2-RABL4 corresponding to the respective bit lines ABL2-ABL4, and in the reverse A parallel current path between fuse bits AB6-AB8 and signal WLP1 on the conductive segment corresponding to conductive region MR4. For each antifuse bit AB6-AB8, the parallel path includes at least one path having a path resistance equal to the sum of RPO and RVZ based on the corresponding conductive area AZ5-AZ7 adjacent to the antifuse bit AB6-AB8.

Compared to methods in which the parallel current paths do not include conductive regions adjacent to each antifuse bit, the antifuse array based on the antifuse layout 100 includes a reduced average current path resistance, and thus for signals such as , the increased operable current value for a given value of the signal WLP1).

In a non-limiting example based on the embodiment depicted in FIGS. 1D-1G, because the parallel read current path includes at least one path based on conductive regions AZ5-AZ7 adjacent to antifuse bits AB8-AB8, In a method in which a given antifuse bit does not include a parallel read current path adjacent to at least one path of the given antifuse bit, the equalized read current path resistance is reduced compared to the equalized read current resistance 20%.

FIG. 2 is a flow diagram of a method 200 of generating an IC layout diagram in accordance with some embodiments. In some embodiments, the step of generating an IC layout includes generating an IC layout of an antifuse layout, such as the antifuse layouts 100A-100C discussed above with respect to FIGS. 1A-1C or above The antifuse layout 100 discussed herein is with respect to FIGS. 1D-1G.

The operations of method 200 can be performed as part of a method of forming one or more IC components including one or more antifuse structures fabricated based on a generated IC layout, such as described below with respect to Section 1. IC device 500 discussed in Figures 5A-5C. Non-limiting examples of IC elements include memory circuits, logic elements, processing elements, signal processing circuits, and the like.

In some embodiments, some or all of the method 200 is performed by a processor of a computer. In some embodiments, some or all of the method 200 is performed by the processor 702 of the EDA system 700 , as discussed below with respect to FIG. 7 .

Some or all of the operations of method 200 can be performed as part of a design process performed in a design studio (eg, design studio 820 discussed below with respect to FIG. 8).

In some embodiments, the operations of method 200 are performed in the order depicted in FIG. 2 . In some embodiments, the operations of method 200 are performed in an order other than that depicted in FIG. 2 . In some embodiments, one or more operations of method 200 are performed before, during, and/or after one or more operations of method 200 are performed.

At operation 210, a first active area, the first active area, the second active area, and the third active area are placed between and adjacent to the second active area and the third active area in the IC layout. Each of the three active regions extends in a first direction. In some embodiments, the step of placing the first active region includes the step of obtaining one or more layout cells. Such layout units include some or all of the first active area, the second active area, and the third active area. In some embodiments, the step of placing the first active region includes the step of obtaining one or more layout cells from a cell library (eg, cell library 707 discussed below with respect to FIG. 7).

In some embodiments, the step of placing the first active region includes the step of defining one or more active regions by adjoining one or more layout cells with one or more additional layout cells. In some embodiments, the step of placing the first active area includes the step of placing active area AR2 between and adjacent to active area AR1 and active area AR3, as above with respect to antifuse layout 100A -100C and Figures 1A-1C discussed. In some embodiments, the step of placing each of the first active area, the second active area, and the third active area along the first direction includes the step of: between the active area AR1 and the active area AR3 extending along the X direction And the active area AR2 is placed adjacent to the active area AR1 and the active area AR3, As discussed above with respect to antifuse layouts 100A-100C and Figures 1A-1C.

In some embodiments, the step of placing the first active area includes the step of placing a plurality of active areas including the first active area, the second active area and the third active area. In some embodiments, the step of placing the plurality of active regions includes the step of placing the plurality of active regions of the antifuse array. In some embodiments, the step of placing the plurality of active regions of the antifuse array includes placing the plurality of active regions of the antifuse array comprising the antifuse layout 100, as discussed above with respect to FIGS. 1D-1G.

At operation 220, the first active region intersects the first through fourth adjacent gate regions, thereby defining the antifuse structures of the first and second antifuse elements and the gates of the transistors position, such antifuse elements are also referred to as antifuse bits in some embodiments. The intersection of the first active region and the first gate region can define the position of the gate of the antifuse structure of the first antifuse bit; the intersection of the first active region and the second gate region can define the first antifuse bit The position of the gate of the transistor of the element; the intersection of the first active region and the third gate region can define the position of the gate of the transistor of the second antifuse bit; and the first active region and the fourth gate region The intersection may define the location of the gate of the antifuse structure of the second antifuse bit.

In various embodiments, the step of intersecting the first active region with the first to fourth adjacent gate regions includes the step of intersecting the first active region with one or more of the first to fourth adjacent gate regions gate regions, and/or intersect the first to fourth adjacent gate regions and one or more active regions other than the first active region.

In some embodiments, the step of intersecting the first active region with the first to fourth adjacent gate regions includes the step of intersecting one or both of the active region AR1 or AR3 and the active region AR2 and the gate region GR2− GR5, as discussed above with respect to antifuse layouts 100A-100C and Figures 1A-1C.

In some embodiments, the step of intersecting the first active region with the first to fourth adjacent gate regions includes the step of intersecting a plurality of active regions including the first active region and the first to fourth adjacent gate regions A plurality of gate regions of the region. In some embodiments, the step of intersecting the plurality of active regions and the plurality of gate regions includes the step of intersecting the plurality of active regions and the plurality of gate regions of the antifuse array. In some embodiments, the step of intersecting the plurality of active regions and the plurality of gate regions of the antifuse array includes the step of intersecting the plurality of active regions and the plurality of gates of the antifuse array including the antifuse arrangement 100 region, as discussed above with respect to Figures 1D-1G.

At operation 230, the individual first and second conductive regions are aligned along the first direction and between the first and second active regions. The step of aligning the individual first and second conductive regions includes the steps of intersecting the first conductive region and the first gate region, and intersecting the second conductive region and the fourth gate region. Thus, the step of aligning the individual first and second conductive regions includes the steps of intersecting the first conductive region with a gate region corresponding to the gate of the antifuse structure of the first antifuse element, and The second conductive region intersects with a gate region corresponding to the gate of the transistor of the second antifuse element.

In various embodiments, the step of aligning the individual first conductive regions and the second conductive regions in the first direction includes the steps of: aligning conductive regions Z1 of layout cells CA1 ( CA2 ) and conductive regions of layout cells CB1 in the X direction Area Z3 (as discussed above with respect to antifuse layout 100A and FIG. 1A ), or aligns conductive region Z1 of layout cell CB2 with conductive region Z3 of layout cell CC1 (CC2 ) in the X direction (as discussed above with respect to antifuse layout 100B) and FIG. 1B ), or align conductive regions Z1 or Z2 of layout cell CB2 with corresponding conductive regions Z3 or Z4 of layout cell CB1 in the X direction (discussed above with respect to antifuse layout 100C and FIG. 1C ).

In some embodiments, the step of aligning the individual first conductive regions and the second conductive regions in the first direction includes the step of: aligning the first conductive regions and the plurality of the first conductive regions in the first direction The corresponding second conductive region of the two conductive regions. In various embodiments, the step of aligning the individual first and second conductive regions in the first direction includes the steps of: aligning conductive regions AZ1 and AZ5 in the X-direction, and/or aligning in the X-direction Conductive regions AZ3 and AZ7 are as discussed above with respect to antifuse layout 100 and Figures 1D-1G.

In some embodiments, the step of aligning the separate first and second conductive regions includes the step of: based on one or more design rules for conductive layers including the separate first and second conductive regions, The first conductive region is separated from the second conductive region by an interval equal to or greater than a predetermined distance. In some embodiments, the step of aligning the individual first and second conductive regions includes the step of separating the first and second conductive regions by a spacing equal to or greater than the minimum spacing rule of the metal layers. In some embodiments, the step of aligning the separate first and second conductive regions includes the step of separating the first and second conductive regions by a distance corresponding to the minimum spacing rule of the EUV manufacturing process.

In some embodiments, the step of aligning the individual first and second conductive regions includes the step of placing a plurality of conductive regions including the first and second conductive regions and a plurality of conductive regions other than the first and second conductive regions one or more conductive regions. In some embodiments, the step of placing the plurality of conductive regions includes the step of placing one or more bit lines. In various embodiments, the step of placing one or more bit lines includes the steps of placing bit line BL1 and contact region CR1 (discussed above with respect to Figures 1A-1C), or above with respect to Figure 1D To one or more of the bit lines ABL1-ABL4 discussed in Figure 1G.

At operation 240, the separate third and fourth conductive regions are aligned along the first direction and between the first and third active regions. The step of aligning the separate third and fourth conductive regions includes the steps of intersecting the third conductive region and the first gate region and intersecting the fourth conductive region and the third gate region, or intersecting the third conductive region and the The second gate region and the intersecting fourth conductive region and the fourth gate region.

In some embodiments, the step of aligning the separate third and fourth conductive regions along the first direction includes the step of separating the third and fourth conductive regions corresponding to a minimum spacing rule (eg, EUV Minimum spacing rules for the manufacturing process) distance. In some embodiments, the step of aligning the separate third and fourth conductive regions in the first direction includes the step of separating the third and fourth conductive regions by a first distance corresponding to a minimum spacing rule , and the step of aligning the individual first conductive regions and the second conductive regions along the first direction includes the steps of: separating the first conductive regions and the second conductive regions by a second distance greater than the first distance. In some embodiments, the The step of separating the third conductive region and the fourth conductive region by a first distance includes the steps of separating the conductive region Z2 and the conductive region Z4 by a distance D2, and separating the first conductive region and the second conductive region by a second distance The steps include the steps of separating conductive regions Z1 from conductive regions Z3 by a distance D1, as discussed above with respect to antifuse layouts 100A-100C and FIGS. 1A-1C.

In various embodiments, the step of aligning the individual third and fourth conductive regions in the first direction includes the steps of: aligning the conductive regions Z2 of layout cells CA1 ( CA2 ) and the conduction of layout cells CB1 in the X direction Zone Z4 (discussed above with respect to antifuse layout 100A and FIG. 1A), or aligns conductive zone Z2 of layout cell CB2 with conductive zone Z4 of layout cell CC1 (CC2) in the X direction (discussed above with respect to antifuse layout 100B and discussed in Figure 1B).

In some embodiments, the step of aligning the individual third conductive regions and the fourth conductive regions in the first direction includes the step of: aligning the third conductive regions and the plurality of the plurality of third conductive regions in the first direction The fourth conductive regions correspond to the fourth conductive regions. In various embodiments, the step of aligning the separate third and fourth conductive regions in the first direction includes the steps of: aligning conductive regions AZ2 and AZ6 in the X-direction, and/or aligning in the X-direction Conductive regions AZ4 and AZ8 are as discussed above with respect to antifuse layout 100 and Figures 1D-1G.

In some embodiments, when the step of aligning the separate third and fourth conductive regions includes intersecting the third and first gate regions and intersecting the fourth and third gate regions, the alignment The step of separating the first conductive area and the second conductive area includes the steps of: intersecting the first conductive area and the second gate area, and intersect the second conductive area and the fourth gate area, for example, align the conductive area Z2 of the layout cell CA1 (CA2) and the conductive area Z4 of the layout cell CB1 along the X direction, as above with respect to the antifuse layout 100A and the first Figure 1A discussion.

In some embodiments, when the step of aligning the separate third and fourth conductive regions includes intersecting the third and second gate regions and intersecting the fourth and fourth gate regions, the alignment The step of separating the first conductive region and the second conductive region includes the steps of intersecting the first conductive region and the first gate region, and intersecting the second conductive region and the third gate region, eg, aligning the layout cells along the X direction Conductive region Z2 of CB2 and conductive region Z4 of layout cell CC1 (CC2), as discussed above with respect to antifuse layout 100B and FIG. 1B.

In some embodiments, each of aligning the individual first and second conductive regions in the first direction and aligning the individual third and fourth conductive regions in the first direction includes the steps of: The corresponding first and second conductive regions or the third and fourth conductive regions are separated by a distance corresponding to the minimum spacing rule. In some embodiments, each of aligning the individual first and second conductive regions in the first direction and aligning the individual third and fourth conductive regions in the first direction includes the steps of: Corresponding first and second conductive regions or third and fourth conductive regions are separated by a distance D2, discussed above with respect to antifuse layouts 100A- 100C and FIGS. 1A-1C.

In various embodiments, the step of aligning the separate third and fourth conductive regions in the first direction includes the steps of: aligning conductive regions AZ1 and AZ5 in the X-direction, and/or aligning in the X-direction Conductive regions AZ3 and AZ7 are as discussed above with respect to antifuse layout 100 and Figures 1D-1G.

In some embodiments, the step of aligning the individual third and fourth conductive regions along the first direction includes the step of: aligning the fifth and sixth conductive regions along the first direction. In some embodiments, the third active region is located between the third and fourth conductive regions and the fifth and sixth conductive regions, and the step of aligning the individual fifth and sixth conductive regions includes the step of: intersecting The fifth conductive region and the first gate region intersect the sixth conductive region and the fourth gate region. For example, intersecting one of conduction regions AZ1 or AZ3 and gate region GR2, and intersecting one of conduction regions AZ5 or AZ7 and gate region GR5, as discussed above with respect to antifuse layout 100 and FIGS. 1D-1G .

In some embodiments, the first active region is located between the first and second conductive regions and the fifth and sixth conductive regions, when the step of aligning the separate third and fourth conductive regions includes intersecting the third conductive regions region and the first gate region and intersecting the fourth conductive region and the third gate region, the step of aligning the separate fifth conductive region and the sixth conductive region includes the following steps: intersecting the fifth conductive region and the second gate region, and intersecting the sixth conductive region and the fourth gate region, and the step of aligning the separate third and fourth conductive regions includes intersecting the third conductive region and the second gate region and intersecting the fourth conductive region and the fourth gate region, the step of aligning the separate fifth conductive region and the sixth conductive region includes the steps of intersecting the fifth conductive region and the first gate region, and intersecting the sixth conductive region and the third gate Area. In some embodiments, each of aligning the individual third and fourth conductive regions and aligning the individual fifth and sixth conductive regions in the first direction includes the step of: aligning the corresponding third and the fourth conductive region or the fifth and sixth conductive regions are separated by a distance corresponding to the minimum spacing rule.

At operation 250, in some embodiments, a first via is placed area to the fourth through hole area. The first via area is placed at the intersection of the first conductive area and the first gate area, the second via area is placed at the intersection of the second conductive area and the fourth gate area, and the third via area is placed at a location where the third conductive region intersects one of the first or second gate regions, and a fourth via region is placed where the fourth conductive region intersects one of the third or fourth gate regions .

In various embodiments, the step of placing the first through fourth via regions includes the steps of placing respective via regions VR1, VR3, VR2, and VR4 of one of the antifuse layouts 100A- 100C, as above The text is discussed with respect to Figures 1A to 1C.

In some embodiments, the step of placing the first through hole regions to the fourth through hole regions includes the following steps: placing a plurality of through hole regions including the first through hole regions to the fourth through hole regions. In various embodiments, the step of placing the plurality of via regions includes the steps of placing via regions AVR1-AVR8, as discussed above with respect to antifuse layout 100 and FIGS. 1D-1G.

In some embodiments, each step of placing the first through hole region to placing the fourth through hole region includes the following steps: placing a slot-shaped through hole region or a square through hole region.

At operation 260, in some embodiments, the IC layout is stored in a storage element. In various embodiments, the step of storing the IC layout in the storage element includes storing the IC layout in a non-volatile computer readable memory or cell library (eg, a database), and/or includes storing the IC on a network Layout. In some embodiments, the step of storing the IC layout in the storage device includes storing the IC layout on the network 714 of the EDA system 700 Figure 7, as discussed below with respect to Figure 7.

At operation 270, in some embodiments, the IC layout is placed in the IC layout of the antifuse array. In some embodiments, the step of placing the IC layout in the IC layout of the antifuse array includes the steps of: rotating the IC layout in one or more axes, or in one or more directions relative to one or more An additional IC layout diagram shifts the IC layout diagram.

In various embodiments, the step of placing the IC layout in the IC layout of the antifuse array includes the steps of placing one or more active areas other than the first active area and the second active area, placing the active area except the first active area and the second active area. A gate region to one or more gate regions other than the fourth gate region, place one or more conductive regions except the first conductive region and the second conductive region, and/or place the first through hole region and one or more through hole regions outside the second through hole region.

In some embodiments, the step of placing the IC layout in the IC layout of the antifuse array includes placing the IC in one of the antifuse arrays 300A-300D discussed below with respect to FIGS. 3A-3D Layout.

In some embodiments, the step of placing the IC layout on the IC layout of the antifuse array includes performing one or more of the operations of method 400 discussed below with respect to FIG. 4 .

At operation 280, in some embodiments, at least one of the one or more semiconductor masks, or at least one feature of the semiconductor IC layer, is fabricated based on an IC layout. Fabrication of at least one component of one or more semiconductor masks or semiconductor IC layers is discussed below with respect to FIG. 8 .

At operation 290, in some embodiments, based on the IC layout A graph performs one or more manufacturing operations. In some embodiments, the step of performing one or more fabrication operations includes performing one or more lithographic exposures based on the IC layout. Performing one or more fabrication operations (eg, one or more lithographic exposures) based on the IC layout is discussed below with respect to FIG. 8 .

By performing some or all of the operations of method 200, an IC layout is generated in which gate regions corresponding to read current paths have the properties and benefits discussed above with respect to antifuse layouts 100A-100C and 100 .

Figures 3A-3D are diagrams of respective antifuse arrays 300A-300D in accordance with some embodiments. Figures 3A-3D each depict the arrangement of layout cells CA1, CA2, CB1, CB2, CC1, and CC2 (simplified for clarity), and a plan view of the IC layout in the X and Y directions, each Discussed above with respect to Figures 1A-1D.

Layout cell CA1 and layout cell CA2 are collectively denoted as layout cell CA, such that the location labeled CA corresponds to either layout cell CA1 or layout cell CA2, and layout cell CC1 and layout cell CC2 are collectively denoted as layout cell CC , so that the location labeled CC corresponds to either layout cell CC1 or layout cell CC2.

In antifuse arrays 300A and 300B, column pairs are repeated in four rows extending in the Y direction, and in antifuse arrays 300C and 300D, three column combinations are repeated in rows extending in the Y direction. The total number of layout cells depicted in each of Figures 3A-3D is for illustration only. In various embodiments, one or more of the antifuse arrays 300A-300D include layout cells other than those depicted in FIGS. 3A-3D (not shown) icon).

In the antifuse array 300A depicted in Figure 3A, each pair of columns includes a first column (not labeled) in which each layout cell CA adjoins layout cell CB1 in the X-direction, which corresponds to that discussed above with respect to Figure 1A Antifuse layout 100A, and includes a second column (not labeled) in which each layout cell CB2 adjoins layout cells CC in the X-direction, which corresponds to antifuse layout 100B discussed above with respect to FIG. 1B . Within each pair of columns, each pair of layout cells CA and CB1 abuts a pair of layout cells CB2 and CC along the Y direction, which corresponds to the antifuse layout 100 discussed above with respect to Figures ID-IG.

In the antifuse array 300B depicted in Figure 3B, each pair of columns includes a first column (not labeled). In the first column, the first layout cell CA adjoins the layout cell CB1 in the X direction, which corresponds to the antifuse layout 100A, and the layout cell CB2 adjoins the second layout cell CA in the X direction. Each pair of columns also includes a second column (not labeled). The layout cell CB2 is adjacent to the first layout cell CC in the X direction in the second column, and the second layout cell CC is adjacent to the layout cell CB1 in the X direction. Within each pair of columns, each pair of layout cells CA and CB1 is adjacent to the pair of layout cells CB2 and CC in the Y direction, and each pair of layout cells CB2 and CA is adjacent to the pair of layout cells CC and CB1 in the Y direction.

In the antifuse array 300C depicted in FIG. 3C, pairs of columns configured in the manner described above with respect to antifuse array 300A are separated by additional columns (not labeled) including layout cells CB2 alternating with layout cells CB1 . In each additional column, each layout cell CB2 adjoins layout cell CB1, which corresponds to the antifuse layout IOOC discussed above with respect to Figure 1C. Each pair of layout cells CB2 and CB1 is adjacent to the pair of layout cells CA and CB1 in the Y direction, and adjacent to the pair of layout cells CB2 and CC in the Y direction.

In the antifuse array 300D depicted in Figure 3D, pairs of columns configured in the manner described above with respect to antifuse array 300B are separated by additional columns (not labeled) configured as described above with respect to antifuse array 300C open. In each additional column, the first pair of layout cells CB2 and CB1 adjoins the pair of layout cells CA and CB1 in the Y direction, and the pair of layout cells CB2 and CC in the Y direction, and the second pair of layout cells CB2 and CB1 abuts in the Y direction The pair of layout cells CB2 and CA are adjacent to the pair of layout cells CC and CB1 along the Y direction.

With the configuration discussed above, each set of four layout cells highlighted in bold in each of antifuse arrays 300A and 300B corresponds to two rows of antifuse bits, with the highlighted cells defining the A total of three electrical connections to one row of antifuse structures, one electrical connection to the first row of transistors, three electrical connections to the second row of antifuse structures, and one electrical connection to the second row of transistors. an electrical connection.

With the configurations discussed above, each set of six layout cells highlighted in bold in each of antifuse arrays 300C and 300D corresponds to two rows of antifuse bits, with the highlighted cells defining the A total of five electrical connections to one row of antifuse structures, one electrical connection to one of the transistors in the first row, five electrical connections to the second row of antifuse structures, and one electrical connection to one of the transistors in the second row electrical connection.

In some embodiments, the antifuse array (not shown) includes layout elements such as those depicted in FIG. 3A or FIG. 3D in addition to the layout cells depicted in FIGS. 3C and 3D. Figure 3B depicts additional columns of placement cells CB2 and CB1 between and/or within the pair of columns as configured, and the antifuse array thus includes groups of placement cells. This set of layout cells defines, for each electrical connection to a transistor in a given row of antifuse bits, more than five (eg, seven) electrical connections to the antifuse structure.

In some embodiments, an antifuse array (not shown) includes one or more combinations of the layout cell configurations depicted in FIGS. 3A-3D, and thereby includes groups of layout cells. This set of layout cells defines, for each electrical connection to a transistor in a given row of antifuse bits, at least three transistors leading to the antifuse structure.

By including the above-described configurations, the IC layout diagrams of antifuse arrays 300A-300D and the IC elements fabricated thereon can realize the benefits discussed above with respect to antifuse layouts 100A-100C and 100.

FIG. 4 is a flowchart of a method 400 of generating an IC layout, according to some embodiments. In some embodiments, the step of generating the IC layout includes generating the IC layout of the antifuse array. Such an antifuse array is, for example, the antifuse layout 100 discussed above with respect to FIGS. 1D-1G or the antifuse arrays 300A-300D discussed above with respect to FIGS. 3A-3D.

The operations of method 400 can be performed as part of a method of forming one or more IC components. The one or more IC elements include one or more antifuse structures fabricated based on a generated IC layout, such as IC element 500 discussed below with respect to Figures 5A-5C. Non-limiting examples of IC elements include memory circuits, logic elements, processing elements, signal processing circuits, and the like.

In some embodiments, some or all of method 400 is performed by a processor of a computer. In some embodiments, some or all of method 400 is performed by processor 702 of EDA system 700 , discussed below with respect to FIG. 7 .

Some or all of the operations of method 400 can be performed as part of a design process performed in a design studio (eg, design studio 820 discussed below with respect to FIG. 8).

In some embodiments, the operations of method 400 are performed in the order depicted in FIG. 4 . In some embodiments, the operations of method 400 are performed in an order other than that depicted in FIG. 4 . In some embodiments, one or more operations of method 400 are performed before, during, and/or after one or more operations of method 400 are performed.

At operation 410, in some embodiments, first to fourth layout units are received. The step of receiving the first layout unit to the fourth layout unit includes the steps of receiving one of layout unit CA1 or CA2, one of layout unit CC1 or CC2, layout unit CB1 and layout unit CB2, as above with respect to the antifuse Layouts 100A-100C and Figures 1A-1C are discussed.

In some embodiments, the step of receiving the first layout unit through the fourth layout unit includes the steps of performing one or more operations of the method 200 discussed above with respect to FIG. 2 .

In some embodiments, the step of receiving the first to fourth layout cells includes the step of obtaining one or more layout cells from a cell library (eg, cell library 707 discussed below with respect to FIG. 7).

At operation 420, the first to fourth layout cells are arranged by adjoining the first and second layout cells with the third and fourth layout cells. Adjacent the first layout unit and the second layout unit can uniformly define the first active area corresponding to the first and second anti-fuse bits; the third layout unit and the fourth layout unit can be adjacent to uniformly define corresponding to the third and the third layout unit. The second active area of the four antifuse bits; the first to fourth layout units are uniformly defined corresponding to the fifth and sixth antifuse bits and adjacent to the first and second antifuse bits and adjacent to the first and second antifuse bits. The third active area of the third and fourth antifuse bits; the first layout unit includes a first through hole area covering the first gate area, the first gate area is composed of the first, third and fifth antifuses The anti-fuse structure of the bit is shared, and includes a second through hole region covering the second gate region, and the second gate region is shared by the transistor structures of the first, third and fifth anti-fuse bits; The quad layout unit includes a third via area covering a third gate area shared by the transistor structures of the second, fourth and sixth antifuse bits, and includes covering the fourth gate area The fourth through hole area of the fourth gate area is shared by the anti-fuse structures of the second, fourth and sixth anti-fuse bits; the third layout unit includes fifth and sixth covering the first gate area. a via region; and the second layout unit includes seventh and eighth via regions covering the fourth gate region.

In some embodiments, the second through hole is placed between the first active region and the third active region, or the third through hole is placed between the second active region and the third active region.

In some embodiments, the step of arranging the first layout unit to the fourth layout unit includes the step of: arranging each layout unit of the plurality of identical layout unit arrangements and at least two of the plurality of identical layout unit arrangements The outer layout cells are arranged contiguously, thereby forming an antifuse array.

In some embodiments, the step of arranging the first layout unit to the fourth layout unit includes the following steps: adjoining the fifth layout unit and the sixth layout unit to the first layout unit and the second layout unit, and the fifth layout unit includes covering the first gate The ninth to tenth through hole regions of the gate region, and the sixth layout unit includes eleventh and twelfth through hole regions covering the fourth gate region. In some embodiments, the step of arranging the first to fourth layout cells further comprises the step of: arranging each of the plurality of identical layout cell arrangements and at least two additional layout cells of the plurality of identical layout cell arrangements The arrangement is contiguous, thereby forming an antifuse array.

In various embodiments, the step of arranging the first to fourth layout cells includes the step of arranging the layout cells CA, CB1, CB2, and CC according to one of the antifuse arrays 300A-300D, as described above with respect to FIG. 3A To the discussion of the 3D figure.

At operation 430, in some embodiments, an IC layout diagram is generated that includes an arrangement of the first to fourth layout cells. In some embodiments, the step of generating the IC layout includes the steps of: generating the IC layout. This IC layout diagram includes one or more of: antifuse layouts 100A-100C discussed above with respect to Figures 1A-1C, antifuse layout 100 discussed above with respect to Figures 1D-1G , or the antifuse arrays 300A-300D discussed above with respect to FIGS. 3A-3D.

At operation 440, in some embodiments, the IC layout is stored in a storage element. In various embodiments, the step of storing the IC layout in the storage device includes the steps of: storing in a non-volatile computer readable memory or The IC layouts are stored in a cell library (eg, a database), and/or the IC layouts are stored on a network. In some embodiments, the step of storing the IC layout in the storage element includes the step of storing the IC layout on the network 714 of the EDA system 700, as discussed below with respect to FIG. 7 .

At operation 450, in some embodiments, at least one of the one or more semiconductor masks, or at least one feature of the semiconductor IC layer, is fabricated based on an IC layout. Fabrication of at least one of the one or more semiconductor masks or semiconductor IC layers is discussed below with respect to FIG. 8 .

At operation 460, in some embodiments, one or more fabrication operations are performed based on the IC layout. In some embodiments, the step of performing one or more fabrication operations includes the step of performing one or more lithographic exposures based on the IC layout. Performing one or more fabrication operations (eg, one or more lithographic exposures) based on the IC layout is discussed below with respect to FIG. 8 .

By performing some or all of the operations of method 400, an IC layout is generated in which gate regions corresponding to read current paths have the properties and benefits discussed above with respect to antifuse layouts 100A-100C and 100 .

5A-5C are diagrams of an IC device 500 according to some embodiments. IC device 500 is formed by performing some or all of methods 200 and/or 400, and is configured based on antifuse layouts 100A-100C and 100, as discussed above with respect to FIGS. 1A-1G. In some embodiments, the IC component 500 is included in an IC component manufactured by an IC manufacturer/fabricator (“fab”) 850 860, as discussed below with respect to FIG. 8 .

Figure 5A depicts IC element 500 (simplified for clarity), the X and Y directions discussed above with respect to Figures 1A-1D, and antifuse bit AB1 discussed above with respect to Figures 1D-1G - Floor plan of AB8. Figure 5B depicts a cross-sectional view along plane AA', the X direction, and a Z direction perpendicular to each of the X and Y directions, and Figure 5C depicts a cross-sectional view along plane BB' and the X and Z directions .

IC device 500 includes active areas AA1-AA4, gate structures G2-G5, contacts C1-C4, conductive segments MBL1-MBL4, M11-M18, and M21-M24, and vias V11-V18 and V21-V28, as follows Argumentally configured.

Each of the active areas AA1-AA4 is an N-type or P-type active area extending along the X direction of the substrate 500S and is configured according to an active area (eg, active areas AR1-AR3 discussed above with respect to FIGS. 1A-1C ) .

Gate structures G2-G5 are gate structures extending in the Y direction and configured in accordance with the respective gate regions GR2-GR5 discussed above with respect to FIGS. 1A-1D, and thereby include overlying dielectric layers GD2- Gate conductors GC2-GC5 of GD5.

Contacts C1-C4 are conductive structures that are electrically connected to respective active areas AA1-AA4 and configured in accordance with the contact areas (eg, contact area CR1 ) discussed above with respect to FIGS. 1A-1C.

Conductive segments MBL1-MBL4, also referred to in some embodiments as bit lines MBL1-MBL4, extend in the X-direction, are electrically connected to respective contacts C1-C4, and are configured according to the Figure to Conductive segments of the bit line BL1) configuration discussed in Figure 1C. In the embodiment depicted in Figure 5A, the conductive segments MBL1-MBL4 are the conductive segments of the first metal layer. In some embodiments, one or more of the conductive segments MBL1-MBL4 are conductive segments of a layer other than the first metal layer (eg, the second or third metal layer).

Conductive segments M11-M18 are extending along the X direction and are based on conductive regions (eg, conductive regions Z1-Z4 discussed above with respect to Figures 1A-1C or conductive regions AZ1-AZ8 discussed above with respect to Figure 1D) Configured conductive segments. In the embodiment depicted in FIG. 5A, the conductive segments M11-M18 are conductive segments of the first metal layer. In some embodiments, one or more of the conductive segments M11-M18 are conductive segments of a layer other than the first metal layer (eg, the second or third metal layer).

Conductive segments M21-M24 are conductive segments extending in the Y direction and configured according to conductive regions (eg, conductive regions MR1-MR4 discussed above with respect to Figure ID), which are referred to in some embodiments as conductive lines. In the embodiment depicted in Figure 5A, the conductive segments M21-M24 are conductive segments of the second metal layer. In some embodiments, one or more of the conductive segments M21-M24 are conductive segments of a layer other than the second metal layer (eg, the third or fourth metal layer).

Each of the vias V11-V18 is a conductive structure that is electrically connected to one of the gate conductors GC2-GC5 and to the respective overlying layer of the respective segment M11-M18, and is electrically connected according to the via region (eg, , the configuration of the via regions VR1-VR4) discussed above with respect to Figures 1A to 1G.

Each of the vias V21-V28 is electrically connected to a conductive segment The respective lower layers of M11-M18 are electrically connected to the conductive structures of the overlying layers of conductive segments M21-M24, and according to via regions (eg, via region AVR1-discussed above with respect to FIGS. 1D-1G ) each of the AVRBs) configuration.

The description of the IC device 500 in FIGS. 5A to 5C is simplified for the sake of illustration. In various embodiments, IC element 500 includes one or more elements other than those described above, such as source/drain regions within each of active regions AA1-AA4.

Unless expressly indicated, the above-mentioned elements have the shape, size and space relation depicted in FIGS. 5A to 5C for illustrative purposes only. In various embodiments, IC component 500 includes components having shapes, dimensions, and/or spatial relationships other than those depicted in FIGS. 5A-5C.

As depicted in FIG. 5B, gate structure G2 covering active area AA1 is included in antifuse structure AB1P covering active area AA1; gate structure G3 covering active area AA1 is included in antifuse bit AB1 In the transistor AB1R; the gate structure G4 covering the active area AA1 is included in the transistor AB5R of the anti-fuse bit AB5; and the gate structure G5 covering the active area AA1 is included in the anti-fuse bit AB5. Antifuse structure in AB5P.

Similarly, the gate structures G2 and G3 covering the active area AA2 are included in the antifuse structure and transistor of the antifuse bit AB2, respectively; the gate structures G2 and G3 covering the active area AA3 are respectively included in the antifuse structure and transistor. In the anti-fuse structure and transistor of fuse bit AB3; the gate structures G2 and G3 covering the active area AA4 are respectively included in the opposite side of anti-fuse bit AB4. In the fuse structure and the transistor; the gate structures G4 and G5 covering the active area AA2 are respectively included in the anti-fuse structure and the transistor of the anti-fuse bit AB6; the gate structures G4 and G5 covering the active area AA3 are included in the anti-fuse structure and transistor of anti-fuse bit AB7, respectively; gate structures G4 and G5 covering active area AA4 are included in the anti-fuse structure and transistor of anti-fuse bit AB8, respectively . The antifuse structures and transistors corresponding to antifuse bits AB2-AB4 and AB6-AB8 are not labeled or depicted in detail for clarity.

As depicted in Figure 5B, contact C1 is electrically connected to conductive segment MBL1 and to active area AA1 between gate structure G3 and gate structure G4, and is thereby configured from conductive segment MBL1 to the antifuse bit A portion of the current path for each of transistor AB1R of cell AB1 and transistor AB5R of antifuse bit AB5. The portion of IC device 500 depicted in FIG. 5B thus corresponds to the schematic diagram of antifuse layout 100 depicted in FIG. 1E and described above.

As depicted in Figure 5C, via V12 is electrically connected to lower gate conductor GC3 and overlying conductive segment M12, and via V22 is electrically connected to lower conductive segment M12 and overlying conductive segment M22. The via V16 is electrically connected to the lower gate conductor GC5 and the overlying conductive segment M16, and the via V26 is electrically connected to the lower conductive segment M16 and the overlying conductive segment M24. Conductive segment M12 and conductive segment M16 aligned in the X direction thereby correspond to the respective conductive regions AZ2 and AZ4 of the anti-fuse layout 100 depicted in FIG. 1D and described above.

Similarly, the conductive segment M11 is electrically connected to the via V11 The gate conductor GC2 and the through hole V21 are electrically connected to the conductive segment M21, aligned with the conductive segment M15 in the X direction, electrically connected to the gate conductor through the through hole V15 and electrically connected to the conductive segment M24 through the through hole V25 , can be uniformly corresponding to the respective conductive areas AZ1 and AZ5 of the anti-fuse layout 100; the conductive section M13 is electrically connected to the gate conductor GC2 through the through hole V13 and is electrically connected to the conductive section M21 through the through hole V23, along the X The direction is aligned with the conductive section M17, electrically connected to the gate conductor GC5 through the via V17 and electrically connected to the conductive section M24 through the via V27, which may uniformly correspond to the respective conductive regions AZ3 and AZ7 of the antifuse layout 100 and a conductive segment M14, electrically connected to the gate conductor GC2 through the via V14 and electrically connected to the conductive segment M21 through the via V24, aligned with the conductive segment M18 in the X direction, and electrically connected to the gate through the via V18 The pole conductor GC4 is electrically connected to the conductive area M23 through the via V28 , which may collectively correspond to the respective conductive areas AZ4 and AZ8 of the antifuse layout 100 .

With the configurations described above and depicted in FIGS. 5A-5C, IC device 500 corresponds to anti-fuse layout 100 as discussed above with respect to FIGS. 1D-1G and including the anti-fuse according to the discussion above with respect to FIG. 3A. The layout cells CA, CB1, CB2 and CC of the fuse array 300A arrangement. IC element 500 thus includes a first antifuse structure including a dielectric layer between the first gate conductor and the first active region, eg, a dielectric layer included between the gate conductor GC2 and the active region AA3 The anti-fuse structure of the anti-fuse bit AB3 of GD2; the second anti-fuse structure, including the dielectric layer between the second gate conductor and the first active region, for example, including the gate conductor GC5 and the active region Antifuse bit AB7 between AA3 dielectric layer GD5 An anti-fuse structure; a first transistor including a third gate conductor, such as a transistor including an anti-fuse bit AB3 of the gate conductor GC3 between the first gate conductor and the second gate conductor; Two transistors, including a fourth gate conductor, such as a transistor including an antifuse bit AB7 of the gate conductor GC4 between the second gate conductor and the third gate conductor; the first through hole and the second through hole holes, such as vias V13 and V14 electrically connected to the first gate conductor; third vias, such as via V17 electrically connected to the second gate conductor; and fourth vias, such as electrically connected to the fourth gate The through hole V18 of the pole conductor. The first through hole and the third through hole are aligned with each other along the X direction, the second through hole and the fourth through hole are aligned with each other along the X direction, and each of the first, second, third and fourth through holes Compared to the second and third active areas, the active areas are closer to the first active area. For example, the active areas AA2 and AA4 are adjacent to the first active area in the Y direction.

In various embodiments, IC element 500 corresponds to layout cells CA, arranged in other manners (eg, according to one or more of antifuse arrays 300B-300D discussed above with respect to FIGS. 3B-3D), CB1, CB2, and CC, and thus include first through fourth through holes having the above-described configuration, wherein each of the first through fourth through holes is compared to the first through hole adjacent to the first active region in the Y direction The second and third active areas are closer to the first active area.

By configuring according to antifuse layouts 100A-100C and 100 and/or antifuse arrays 300A-300D (discussed above with respect to FIGS. 1A-1D and 3A-3D), and by performing method 200 Fabrication of some or all of the operations of and 400 (discussed above with respect to FIGS. 2 and 4), IC element 500 enables the implementation of the above with respect to the antifuse layout Advantages discussed in 100A-100C and 100.

FIG. 6 is a flowchart of a method 600 of operating an antifuse bit according to some embodiments. The operations of method 600 can be performed as part of a method of operating one or more IC components. The one or more IC elements include one or more antifuse structures, such as IC element 500 discussed above with respect to Figures 5A-5C.

In some embodiments, the operations of method 600 are performed in the order depicted in FIG. 6 . In some embodiments, the operations of method 600 are performed in an order other than that depicted in FIG. 6 . In some embodiments, one or more operations of method 600 are performed before, during, and/or after one or more operations of method 600 are performed.

At operation 610, a first voltage is applied to a program line electrically connected to a gate structure included in the antifuse structure of each of the four adjacent antifuse bits. In various embodiments, the step of applying the first voltage to the program line includes the steps of applying a read voltage as part of a read operation, or applying a program voltage as part of a program operation.

In some embodiments, the step of applying the first voltage to the program line includes the step of applying the signal WLP0 or WLP1 (discussed above with respect to antifuse layout 100 and FIGS. 1D-1G ) to the respective conductive line M21 or M24 (discussed above with respect to IC element 500 and Figures 5A-5C).

At operation 620, a second voltage is applied to a bit line electrically connected to a first antifuse bit of four adjacent antifuse bits, thereby causing bit cell current to flow through the first antifuse Bit antifuse structure, bit cell The current path for the current includes four vias between the program line and the gate structure, each of the four vias being adjacent to the antifuse bits of the four adjacent antifuse bits.

The magnitude of the bit cell current is based on the voltage level of the first voltage, the voltage level of the second voltage, and the resistance of the current path between the program line and the gate structure. In some embodiments, the current path between the program line and the gate structure includes via V11, via V13, via V14, and a fourth via (not shown) adjacent to antifuse bits AB1-AB4 , or vias V15-V17 and a fourth via (not shown) adjacent to antifuse bits AB5-AB5, as discussed above with respect to IC device 500 and FIGS. 5A-5C.

In some embodiments, the step of applying the second voltage includes the step of applying a bit line voltage to one of the bit lines MBL1-MBL4, as discussed above with respect to IC device 500 and FIGS. 5A-5C.

At operation 630, in some embodiments, the bit cell current is sensed using a sense amplifier. In some embodiments, the step of using the sense amplifier to sense the current of the bit cell includes the step of determining the programmed state of the corresponding antifuse structure.

At operation 640, in some embodiments, one or more of operations 610-630 are repeated for at least a second bit cell structure, thereby causing bit cell current to flow into the two or more bit cell structures . In various embodiments, repeating one or more of operations 610-630 includes the steps of causing bit cell current to flow into a second of the four bit cell structures, and/or causing bit cell current to flow Influx in addition to the four-bit cell structure in the outer bit cell structure.

By performing some or all of the operations of method 600, an antifuse bit operation is performed, wherein the gate structure portion of the read current path has the properties discussed above with respect to antifuse layouts 100A-100C and 100 and thus benefit obtained.

FIG. 7 is a block diagram of an electronic design automation (EDA) system 700 in accordance with some embodiments.

In some embodiments, EDA system 700 includes an APR system. The methods described herein for designing layout diagrams represent wire routing arrangements, such as may be implemented using EDA system 700 in accordance with one or more embodiments.

In some embodiments, the EDA system 700 is a general-purpose computing element including a hardware processor 702 and a non-transitory computer-readable storage medium 704 . The storage medium 704 is encoded with the computer code 706, that is, the computer code 706 is stored, and the instruction set can be executed. Execution of instructions 706 by the hardware processor 702 represents (at least in part) an EDA tool, such as the method 200 discussed above with respect to FIG. 2 and/or the method 400 discussed above with respect to FIG. 4 (hereinafter, the process mentioned above) and/or method) in whole or in part.

Processor 702 is electrically coupled to computer-readable storage medium 704 via bus 708 . Processor 702 is also electrically coupled to I/O interface 710 via bus 708 . The network interface 712 is also electrically connected to the processor 702 via the bus bar 708 . Network interface 712 is connected to network 714 so that processor 702 and computer-readable storage medium 704 can be connected to external components via network 714 . Processor 702 for executing computer code 706 encoded in computer-readable storage medium 704 such that system 700 can be used to perform the process and/or part or all of the method. In one or more embodiments, processor 702 is a central processing unit (CPU), multiprocessor, distributed processing system, application specific integrated circuit (ASIC), and/or suitable processing unit.

In one or more embodiments, computer-readable storage medium 704 is an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or device or element). For example, the computer readable storage medium 704 includes semiconductor or solid state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid Discs and/or CDs. In one or more embodiments using optical disks, computer-readable storage medium 704 includes compact disk read only memory (CD-ROM), compact disk read/write (CD-R/W), and/or Digital video disc (digital video disc, DVD).

In one or more embodiments, storage medium 704 stores computer code 706 for causing system 700 (wherein such execution represents (at least in part) an EDA tool) to be used to execute portions of the process and/or method or all. In one or more embodiments, storage medium 704 also stores information that facilitates performing some or all of the processes and/or methods. In one or more embodiments, the storage medium 704 stores a cell library 707 including such cells as disclosed herein, such as the layout cells CA1, CA2, CB1, CB2, CC1, or CC2 and/or antifuse layouts 100A-100C.

EDA system 700 includes I/O interface 710 . The I/O interface 710 is coupled to external circuitry. In one or more embodiments, the I/O interface 710 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and/or cursor direction keys for exchanging information and commands with the processor 702 .

The EDA system 700 also includes a network interface 712 coupled to the processor 702 . Network interface 712 allows system 700 to communicate with network 714 to which one or more other computer systems are connected. The network interface 712 includes a wireless network interface such as Bluetooth, WIFI, WIMAX, GPRS or WCDMA; or a wired network interface such as Ethernet, USB or IEEE-1364. In one or more embodiments, some or all of the processes and/or methods are implemented in two or more systems 700 .

System 700 is configured to receive information via I/O interface 710 . Information received via I/O interface 710 includes one or more of instructions, data, design rules, standard cell libraries, and/or other parameters for processing by processor 702 . Information is passed to processor 702 via bus 708 . EDA system 700 is configured to receive information about the UI via I/O interface 710 . The information is stored in a computer-readable medium 704 serving as a user interface (UI) 742 .

In some embodiments, some or all of the processes and/or methods are implemented as stand-alone software applications executed by a processor. In some embodiments, part or all of the process and/or method is implemented as a software application that is part of an additional software application. In some embodiments, some or all of the process and/or method is implemented as a plug-in for a software application. In some embodiments, at least one implementation of the process and/or method The application is a software application that is part of the EDA tool. In some embodiments, some or all of the processes and/or methods are implemented as software applications used by the EDA system 700 . In some embodiments, a layout drawing including standard cells is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, or another suitable layout generation tool.

In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external/removable and/or internal/embedded storage or memory units, eg, optical discs such as DVDs, magnetic disks such as hard disks, One or more of semiconductor memories such as ROM, RAM, memory cards, and the like.

FIG. 8 is a block diagram of an IC fabrication system 800 and an IC fabrication flow associated therewith, in accordance with some embodiments. In some embodiments, fabrication system 800 is used to fabricate at least one of one or more semiconductor masks (A) or at least one component (B) in layers of a semiconductor integrated circuit based on the layout.

In FIG. 8, an IC manufacturing system 800 includes entities such as a design room 820, a reticle room 830, and an IC fabricator/fab 850, each of which is involved in the design, development, and manufacturing of IC components 860. interact with each other in the manufacturing cycle and/or service. Entities in system 800 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. A communication network includes wired and/or wireless communication channels. Each entity interacts with and provides services to and/or receives services from one or more other entities. In some embodiments, two or more of design room 820, reticle room 830, and IC fab 850 are owned by a larger company. In some embodiments, two or more of design room 820, reticle room 830, and IC fab 850 coexist in a common facility and use common resources.

A design house (or design team) 820 generates an IC design layout 822 . IC design layouts 822 include various geometric patterns, such as the IC layouts depicted in Figures 1A-1D or 3A-3D and designed for IC element 860, such as those described above with respect to Figures 5A-5C IC device 500 discussed. The geometric patterns correspond to the patterns of metal, oxide, or semiconductor layers that make up the various components of IC element 860 to be fabricated. Various layers are combined to form various IC features. For example, the portion of IC design layout 822 includes various IC features, such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bond pads, which IC features will form In semiconductor substrates (such as silicon wafers) and various material layers (disposed on this semiconductor substrate). Design house 820 implements a suitable design process to form IC design layout 822 . Design procedures include one or more of logical design, physical design, and/or placement and routing. The IC design layout 822 exists in one or more data files with geometric pattern information. For example, the IC design layout diagram 822 may be represented in the GDSII file format or the DFII file format.

The reticle chamber 830 includes data preparation 832 and reticle fabrication 844 . The reticle chamber 830 manufactures one or more reticle using the IC design layout 822 At 845 , the reticle 845 is to be used to fabricate the various layers of the IC element 860 according to the IC design layout 822 . The reticle chamber 830 performs reticle data preparation 832, in which the IC design layout 822 is converted into a representative data file ("RDF"). Mask data preparation 832 provides RDF to mask fabrication 844 . The reticle fabrication 844 includes a reticle writer. The reticle writer converts the RDF to an image on a substrate, such as a reticle (master reticle) 845 or a semiconductor wafer 853 . The design layout 822 is manipulated by the reticle data preparation 832 to meet the specific characteristics of the reticle writer and/or the requirements of the IC fab 850. In Figure 8, reticle data preparation 832 and reticle fabrication 844 are shown as separate elements. In some embodiments, reticle data preparation 832 and reticle fabrication 844 may be collectively referred to as reticle data preparation.

In some embodiments, reticle data preparation 832 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for aberrations, such as those that may be caused by diffraction, interference, other process effects, etc. . The OPC adjusts the IC design layout 822. In some embodiments, reticle data preparation 832 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase change masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

In some embodiments, mask profile preparation 832 includes a mask rule checker (MRC) that utilizes a set of light Mask generation rules check the IC design layout 822 that has undergone the process in OPC, the rules include certain geometric and/or connectivity constraints to ensure sufficient margins, to account for variability in the semiconductor manufacturing process, and the like. In some embodiments, the MRC modifies the IC design floorplan 822 to compensate for constraints during reticle fabrication 844, which may undo portions of the modifications performed by OPC to meet reticle generation rules.

In some embodiments, reticle data preparation 832 includes lithography process checking (LPC) that simulates processing to be performed by IC fab 850 to fabricate IC device 860 . LPC simulates this process based on the IC design layout 822 to produce simulated fabrication components, such as IC components 860 . Process parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as spatial imaging contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc., or combinations thereof. In some embodiments, after analog fabricated components have been generated by LPC, if the shapes of the simulated components do not fit enough to meet the design rules, then the OPC and/or MRC are repeated to further refine the IC design layout 822.

It should be understood that the above description of reticle profile preparation 832 has been simplified for the sake of brevity. In some embodiments, data preparation 832 includes additional features such as logic operations (LOPs) to alter IC design layout 822 according to manufacturing rules. Additionally, the processes applied to IC design layout 822 during data preparation 832 may vary Execute sequentially.

After reticle data preparation 832 and during reticle fabrication 844, a reticle 845 or reticle set 845 is fabricated based on the modified IC design layout 822. In some embodiments, reticle fabrication 844 includes performing one or more lithographic exposures based on IC design layout 822 . In some embodiments, an electron-beam (e-beam) or multiple electron beam mechanism is used to form a pattern on the reticle (reticle or master) 845 based on the modified IC design layout 822 . The reticle 845 can be formed by various techniques. In some embodiments, the reticle 845 is formed using a binary technique. In some embodiments, the reticle pattern includes opaque regions and transparent regions. A beam of radiation, such as an ultraviolet (UV) beam, used to expose a layer of image-sensitive material (eg, photoresist) that has been coated on the wafer is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary reticle version of reticle 845 includes a transparent substrate (eg, fused silica) and an opaque material (eg, chrome) coated in the dark areas of the binary reticle. In another example, the reticle 845 is formed using phase transfer techniques. In a phase shift mask (PSM) version of reticle 845, the various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase transfer reticle may be an attenuated PSM or an alternating PSM. The masks produced by mask fabrication 844 are used in various processes. For example, such masks are used in an ion implantation process to form various doped regions and in semiconductor wafer 853, in an etch process to form various etched regions and in semiconductor wafer 853, and/or for other appropriate processes.

IC fab 850 is an IC manufacturing company, including for manufacturing various One or more manufacturing facilities for different IC products. In some embodiments, IC Fab 850 is a semiconductor fabrication facility. For example, there may be a fabrication facility for front-eud-of-line (FEOL) fabrication of multiple IC products, while a second fabrication facility may provide a back-end- of-line, BEOL) manufacturing, and the third manufacturing facility may provide other services to the manufacturing company.

IC Fab 850 includes wafer fabrication tool 852 configured to perform various wafer fabrication operations on semiconductor wafer 853 such that IC components 860 are fabricated from a reticle (eg, reticle 845). In various embodiments, the fabrication tool 852 includes one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a process chamber such as a CVD chamber or LPCVD furnace, A CMP system, plasma etch system, wafer cleaning system, or other fabrication equipment capable of performing one or more fabrication processes as discussed herein.

IC fab 850 manufactures IC elements 860 using reticle 845 fabricated by reticle chamber 830 . Thus, IC fab 850 uses IC design floorplan 822 to manufacture IC components 860, at least indirectly. In some embodiments, semiconductor wafer 853 is fabricated by IC fab 850 using reticle 845 to form IC elements 860 . In some embodiments, IC fabrication includes performing one or more lithographic exposures based at least indirectly on the IC design floorplan 822 . Semiconductor wafer 853 includes a silicon substrate or other suitable substrate having material layers formed thereon. Semiconductor wafer 853 further includes one or more of various doped regions, dielectric features, multi-level interconnects, etc. (formed in subsequent fabrication steps).

Details regarding an integrated circuit (IC) manufacturing system (eg, system 800 of FIG. 8 ) and its associated IC manufacturing flow are found in, eg, US Patent No. 9,256,709, issued February 9, 2016; U.S. Pre-Grant Publication No. 20150278429, published Oct. 1, 2015; U.S. Pre-Grant Publication No. 20140040838, published Feb. 6, 2014; and U.S. Patent No. 7,260,442, issued Aug. 21, 2007, above The contents of each are incorporated herein by reference in their entirety.

In some embodiments, a method of generating an IC layout includes the steps of placing a first active area in the IC layout between and adjacent to the second active area and the third active area region, each of the first active region, the second active region and the third active region extends along the first direction; intersecting the first active region and the adjacent first gate region to fourth gate region, thereby defining The gate of the anti-fuse structure of the first anti-fuse bit, the gate of the transistor of the first anti-fuse bit, the gate of the transistor of the second anti-fuse bit, and the second anti-fuse bit The corresponding positions of the gates of the anti-fuse structure of the element; align the separate first and second conductive regions along the first direction and between the first and second active regions, thereby intersecting the first conductive regions region and the first gate region and intersecting the second conductive region and the fourth gate region; and separate third and fourth conductive regions aligned along the first direction and between the first active region and the third active region region, whereby the third conductive region and the first gate region are intersected and the fourth conductive region and the third gate region are intersected, or the third conductive region and the second gate region are intersected and the fourth conductive region and the fourth gate region are intersected polar region. The processor of the computer performs at least one of the following steps: placing the first active area, intersecting the first active area The region and the adjacent first to fourth gate regions are aligned with the individual first conductive regions and the second conductive regions, or are aligned with the individual third conductive regions and the fourth conductive regions. In some embodiments, the step of aligning the individual third and fourth conductive regions along the first direction includes the step of: separating the third and fourth conductive regions corresponds to extreme ultraviolet (EUV) fabrication The first distance step of the minimum interval rule of the process. In some embodiments, the step of aligning the separate first and second conductive regions in the first direction includes the step of separating the first and second conductive regions by a second distance greater than the first distance. In some embodiments, the method further includes the step of aligning the individual fifth and sixth conductive regions along the first direction, wherein the third active region is located in the third and fourth conductive regions and the fifth conductive region between the region and the sixth conductive region, and the step of aligning the fifth conductive region and the sixth conductive region includes the following steps: intersecting the fifth conductive region and the first gate region and intersecting the sixth conductive region and the fourth gate Area. In some embodiments, the method further includes the step of aligning the individual fifth and sixth conductive regions along the first direction, wherein the first active region is located in the first and second conductive regions and the fifth conductive region and the sixth conductive region, when the step of aligning the separate third conductive region and the fourth conductive region includes intersecting the third conductive region and the first gate region and intersecting the fourth conductive region and the third gate region, The step of aligning the individual fifth and sixth conductive regions includes the steps of intersecting the fifth and second gate regions and intersecting the sixth and fourth gate regions, and when aligning the individual The step of the third conductive region and the fourth conductive region includes aligning the separate fifth conductive region and the sixth conductive region when intersecting the third conductive region and the second gate region and intersecting the fourth conductive region and the fourth gate region The step includes the following steps: intersecting the fifth conductive area with The first gate region intersects the sixth conductive region and the third gate region. In some embodiments, each of aligning the individual third and fourth conductive regions along the first direction and aligning the individual fifth and sixth conductive regions along the first direction includes the steps of: The corresponding third conductive region and the fourth conductive region or the fifth conductive region and the sixth conductive region are separated by a distance corresponding to the minimum interval rule. In some embodiments, the method further includes the following steps: placing the first via area at a position where the first conductive area and the first gate area intersect; placing the second via area between the second conductive area and the fourth where the gate regions intersect; placing the third via region at the location where the third conductive region intersects either the first gate region or the second gate region; and placing the fourth via region at the At a position where the four conductive regions intersect with either the third gate region or the fourth gate region. In some embodiments, each step of placing the first through hole region to placing the fourth through hole region includes the following steps: placing a slot-shaped through hole region or a square through hole region.

In some embodiments, the IC device includes: a first antifuse structure included between a first gate conductor extending in a first direction and a first active region extending in a second direction perpendicular to the first direction the first dielectric layer; the second anti-fuse structure, including the second dielectric layer between the second gate conductor extending along the first direction and the first active region; the first transistor, including the first a third gate conductor extending along the first direction between the gate conductor and the second gate conductor; the second transistor includes a third gate conductor extending along the first direction between the second gate conductor and the third gate conductor Four gate conductors; a first through hole and a second through hole electrically connected to the first gate conductor; a third through hole electrically connected to the second gate conductor; and a fourth through hole electrically connected to the third gate conductor pole conductor or fourth gate conductor. The first through hole and the third through hole are aligned with each other along the second direction and placed on the Between the first active area and the second active area adjacent to the first active area along the first direction, and the second through hole and the fourth through hole are aligned with each other along the second direction and placed in the first active area and along the first active area One direction is adjacent to between the first active area and the third active area. In some embodiments, the IC device further includes a fifth through hole and a sixth through hole aligned with each other along the second direction, wherein the second active region is located in the fifth and sixth through holes and the first through hole and the third through hole Between the holes, the fifth through hole is electrically connected to the second gate conductor, when the fourth through hole is electrically connected to the third gate conductor, the sixth through hole is electrically connected to the fourth gate conductor, and when the fourth through hole is electrically connected to the fourth gate conductor When the hole is electrically connected to the fourth gate conductor, the sixth through hole is electrically connected to the third gate conductor. In some embodiments, the IC device includes a fifth through hole and a sixth through hole aligned with each other along the second direction, wherein the third active region is located in the fifth through hole and the sixth through hole and the second through hole and the fourth through hole Between the vias, the fifth via is electrically connected to the first gate conductor, and the sixth via is electrically connected to the second gate conductor. In some embodiments, the IC device further includes: a first conductive line extending along the first direction and electrically connected to each of the first through hole, the second through hole and the fifth through hole; extending along the first direction and electrically connected to each of the first through hole, the second through hole and the fifth through hole; a second conductive line electrically connected to each of the third and sixth vias; and a third conductive line extending in the first direction and electrically connected to the fourth via. In some embodiments, the IC device further includes a fifth through hole and a sixth through hole aligned with each other along the second direction, wherein the second active region is located between the fifth through hole and the sixth through hole and the first through hole Between the third via, the fifth via is electrically connected to the first gate conductor, and the sixth via is electrically connected to the second gate conductor. In some embodiments, the IC device further includes: a seventh through hole and an eighth through hole aligned with each other along the second direction; and a fourth active region adjacent to the third active region, wherein the fourth active region is located in the seventh Between the through hole and the eighth through hole and the fifth through hole and the sixth through hole, the seventh through hole is electrically connected to the first gate conductor, and the eighth through hole is electrically connected to the second gate conductor. In some embodiments, the IC device further includes a first conductive line extending along the first direction and electrically connected to each of the first through hole, the second through hole, the fifth through hole and the seventh through hole; A second conductive line extending in one direction and electrically connected to each of the third, sixth, and eighth through holes; and a third conductive line extending in the first direction and electrically connected to the fourth through hole .

In some embodiments, an EDA system includes a processor and a non-transitory computer-readable storage medium including computer code for one or more programs. The non-transitory computer-readable storage medium and the computer code are configured (with the processor) to cause the system to perform the following steps: by adjoining the first layout unit and the second layout unit with the third layout unit and the fourth layout unit to arrange the first layout unit to the fourth layout unit, wherein the adjoining of the first layout unit and the second layout unit can uniformly define the first active area corresponding to the first anti-fuse bit and the second anti-fuse bit. The adjacent three layout units and the fourth layout unit can uniformly define the second active area corresponding to the third antifuse bit and the fourth antifuse bit, and the first layout unit to the fourth layout unit are uniformly defined corresponding to adjacent to The first antifuse bit and the second antifuse bit and the third antifuse bit and the fourth antifuse bit are the fifth antifuse bit and the sixth antifuse bit. The active area, the first layout unit includes a first through hole area covering the first gate area, and the first gate area is composed of a first anti-fuse bit, a third anti-fuse bit and a fifth anti-fuse bit The anti-fuse structure is shared and covers the second through hole area of the second gate area. The second gate area is composed of a first anti-fuse bit, a third anti-fuse bit and a fifth anti-fuse bit. The transistor structure is shared, The fourth layout unit includes a third through hole area covering the third gate area, and the third gate area is composed of transistors of the second anti-fuse bit, the fourth anti-fuse bit and the sixth anti-fuse bit The structure is shared and covers the fourth through hole region of the fourth gate region. The fourth gate region is composed of the second anti-fuse bit, the fourth anti-fuse bit and the anti-fuse of the sixth anti-fuse bit. The structure is shared, the third layout unit includes fifth and sixth through hole areas covering the first gate area, and the second layout unit includes a seventh through hole area and an eighth through hole area covering the fourth gate area; and An IC layout diagram including an arrangement of the first to fourth layout cells is generated. In some embodiments, the arrangement of the first to fourth layout cells is a first layout cell arrangement of a plurality of identical layout cell arrangements, and the non-transitory computer-readable storage medium and the computer code are configured to (with The processors together) cause the system to perform the steps of abutting each placement cell arrangement of the plurality of identical placement cell arrangements with at least two additional placement cell arrangements of the plurality of identical placement cell arrangements, thereby forming an antifuse array. In some embodiments, the non-transitory computer-readable storage medium and computer program code are configured (with the processor) to cause the system to perform the steps of: associating the fifth and sixth layout units with the first and sixth layout units Two layout units are adjacent, wherein the fifth layout unit includes a ninth through hole area and a tenth through hole area covering the first gate area, and the sixth layout unit includes an eleventh through hole area covering the fourth gate area and The twelfth through hole area. In some embodiments, the arrangement of the first to sixth layout cells is a first layout cell arrangement of a plurality of identical layout cell arrangements, and the non-transitory computer-readable storage medium and the computer code are configured to (with processor together) cause the system to perform the steps of: aligning each placement cell arrangement of the plurality of identical placement cell arrangements with the plurality of placement cell arrangements At least two additional layout cell arrangements of the same layout cell arrangement abut, thereby forming an antifuse array. In some embodiments, at least one of the following occurs: the second via is placed between the first active region and the third active region, or the third via is placed between the second active region and the third active region between.

As can be readily appreciated by one of ordinary skill in the art, one or more of the disclosed embodiments perform one or more of the advantages set forth above. After reading the foregoing specification, one of ordinary skill in the art will be able to implement various changes, substitutions of equivalents, and various other embodiments as broadly disclosed herein. Accordingly, it should be considered that the protection claimed herein is limited only by the definitions contained in the appended claims and their equivalents.

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Claims (10)

A method of generating an integrated circuit layout diagram, the method comprising the steps of: placing a first active area between a second active area and a third active area and adjacent to the first active area in an integrated circuit layout diagram Two active areas and the third active area, each of the first active area, the second active area and the third active area extends along a first direction; the first active area is connected to an adjacent one The first gate region to a fourth gate region intersect, thereby defining a gate of an anti-fuse structure of a first anti-fuse bit, a gate of a transistor of the first anti-fuse bit a gate, a gate of a transistor of a second anti-fuse bit, and a gate of an anti-fuse structure of the second anti-fuse bit; making a single first conductive region and a second conductive region are aligned along the first direction and between the first active region and the second active region, whereby the first conductive region intersects the first gate region and the first Two conductive regions intersect the fourth gate region; and a separate third conductive region and a fourth conductive region are aligned along the first direction and between the first active region and the third active region, Thereby, the third conductive region and the first gate region are intersected and the fourth conductive region is intersected with the third gate region, or the third conductive region and the second gate region are intersected and the The fourth conductive region intersects the fourth gate region, wherein at least one of the following steps is performed by a processor of a computer: placing the first active region so that the adjacent first active region and the first active region are adjacent to each other. A gate region to the fourth gate region intersects, aligning the first conductive region and the fourth gate region individually Two conductive regions, or the third conductive region and the fourth conductive region are aligned independently. The method for generating an integrated circuit layout diagram as claimed in claim 1, wherein the step of aligning the individual third conductive region and the fourth conductive region along the first direction comprises the steps of: the third conductive region The fourth conductive region is separated from the fourth conductive region by a first distance corresponding to a minimum spacing rule of an EUV manufacturing process, wherein the step of aligning the individual first conductive region and the second conductive region along the first direction Including the steps of: separating the first conductive area from the second conductive area by a second distance greater than the first distance. The method for generating an integrated circuit layout diagram as claimed in claim 1, further comprising: aligning a fifth conductive region and a sixth conductive region along the first direction, wherein: the third active region is located in the third between the conductive region and the fourth conductive region and between the fifth conductive region and the sixth conductive region, and the step of aligning the fifth conductive region and the sixth conductive region includes: aligning the fifth conductive region intersecting the first gate region and intersecting the sixth conductive region with the fourth gate region. The method for generating an integrated circuit layout diagram as described in claim 1, further comprising: A fifth conductive region and a sixth conductive region are aligned along the first direction, wherein: the first active region is located between the first conductive region and the second conductive region and the fifth conductive region and the first conductive region Between six conductive regions, when the step of aligning the individual third conductive region and the fourth conductive region includes the steps of: intersecting the third conductive region with the first gate region and making the fourth conductive region Intersecting the third gate region, the step of aligning the individual fifth conductive region and the sixth conductive region includes the steps of intersecting the fifth conductive region with the second gate region and making the sixth conductive region region intersects the fourth gate region, and when the step of aligning the third conductive region and the fourth conductive region individually comprises the steps of intersecting the third conductive region and the second gate region and causing the third conductive region to intersect the second gate region The fourth conductive region intersects the fourth gate region, and the step of aligning the individual fifth and sixth conductive regions includes the steps of intersecting the fifth conductive region with the first gate region and The sixth conductive region intersects the third gate region. The method of generating an integrated circuit layout diagram of claim 4, wherein the individual third and fourth conductive regions are aligned along the first direction and the individual fifth conductive regions are aligned along the first direction The step of the conductive region and the sixth conductive region includes the following steps: separating the corresponding third conductive region and the fourth conductive region or the fifth conductive region and the sixth conductive region by a distance corresponding to a minimum spacing rule distance. The method for generating an integrated circuit layout diagram as claimed in claim 1, further comprising the steps of: placing a first through hole region at the intersection of the first conductive region and the first gate region; placing a first through hole region at the intersection of the first conductive region and the first gate region; Two via regions are placed at the intersection of the second conductive region and the fourth gate region; a third via region is placed in the third conductive region and the first gate region or the second gate at the intersection of one of the regions; and placing a fourth via region at the intersection of the fourth conductive region and one of the third gate region or the fourth gate region. An integrated circuit device, comprising: a first anti-fuse structure, including a first dielectric layer between a first gate conductor and a first active region, the first gate conductor along a first direction extending, the first active region extends along a second direction perpendicular to the first direction; a second anti-fuse structure includes a second gate conductor and the first active region between a second a dielectric layer, the second gate conductor extends along the first direction; a first transistor includes a third gate conductor extending along the first direction between the first gate conductor and the second gate conductor gate conductor; a second transistor including a fourth gate conductor extending along the first direction between the second gate conductor and the third gate conductor; a first through hole and a second a through hole, electrically connected to the first gate conductor; a third through hole electrically connected to the second gate conductor; and a fourth through hole electrically connected to the third gate conductor or the fourth gate conductor, wherein: the first through hole and the first through hole The three through holes are aligned with each other along the second direction, and are placed between the first active area and a second active area, the second active area is adjacent to the first active area along the first direction, and the first active area The two through holes and the fourth through hole are aligned with each other along the second direction, and are placed between the first active area and a third active area, the third active area being adjacent to the first along the first direction Active zone. The integrated circuit device of claim 7, further comprising: a fifth through hole and a sixth through hole aligned with each other along the second direction, wherein: the third active region is located between the fifth through hole and the fifth through hole Between the sixth through hole and between the second through hole and the fourth through hole, the fifth through hole is electrically connected to the first gate conductor, and the sixth through hole is electrically connected to the second gate pole conductor; a first conductive line extending along the first direction and electrically connected to each of the first through hole, the second through hole and the fifth through hole; a second conductive line along the extending in a first direction and electrically connected to each of the third through hole and sixth through hole; and a third conductive line extending along the first direction and electrically connected to the fourth through hole hole. An electronic design automation system, comprising: a processor; and a non-transitory computer-readable storage medium including computer program code for one or more programs, the non-transitory computer-readable storage medium and the computer program code being configured to, in conjunction with the processor, cause the system to perform the steps of: arranging the first layout unit to the a fourth layout unit, wherein: the first layout unit and the second layout unit adjoin and uniformly define a first active area corresponding to a first anti-fuse bit and a second anti-fuse bit, the The third layout unit is adjacent to the fourth layout unit and uniformly defines a second active area corresponding to a third antifuse bit and a fourth antifuse bit, the first layout unit to the fourth The layout unit uniformly defines a third active area, the third active area corresponds to a fifth anti-fuse bit and a sixth anti-fuse bit, the fifth anti-fuse bit and the sixth anti-fuse bit The fuse bit is adjacent to the first anti-fuse bit and the second anti-fuse bit and the third anti-fuse bit and the fourth anti-fuse bit, the first layout unit includes covering a A first through hole area of the first gate area and a second through hole area covering a second gate area, the first gate area is composed of the first anti-fuse bit and the third anti-fuse bits and the fifth antifuse A plurality of anti-fuse structures of fuse bits are shared, and the second gate region is composed of a plurality of transistors of the first anti-fuse bit, the third anti-fuse bit and the fifth anti-fuse bit The structure is shared, and the fourth layout unit includes a third through hole region covering a third gate region and a fourth through hole region covering a fourth gate region, and the third gate region is formed by the second gate region. A plurality of transistor structures of the fuse bit, the fourth anti-fuse bit and the sixth anti-fuse bit are shared, and the fourth gate region is composed of the second anti-fuse bit, the fourth anti-fuse bit The fuse bit and the plurality of anti-fuse structures of the sixth anti-fuse bit are shared, and the third layout unit includes a fifth through hole region and a sixth through hole region covering the first gate region, And the second layout unit includes a seventh through hole region and a plurality of eighth through hole regions covering the fourth gate region; and generating an integrated circuit layout diagram, the integrated circuit layout diagram includes the first layout The cells are arranged to one of the fourth layout cells. The electronic design automation system of claim 9, wherein: the arrangement of the first layout unit to the fourth layout unit is a first layout unit arrangement among a plurality of identical layout unit arrangements, and the non-transitory computer can The read storage medium and the computer code are configured to, with the processor, cause the system to perform the steps of: adjoining each of the same layout cell arrangements and at least two additional ones of the same layout cell arrangements layout unit layout, Thereby, an antifuse array is formed.

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