TWI763573B - Transistor device with buried conductive layer and manufacturing method thereof - Google Patents

Abstract

A transistor device with a buried conductive layer and a method of forming a buried conductive layer for transistor devices are provided. The method includes forming adjacent transistor devices on a substrate, wherein the adjacent transistor devices are separated by a gap which is filled by a fill layer. The transistor device includes a base layer protruding from the substrate, an intermediate layer disposed on top of base layer, and a semiconductor layer on the intermediate layer. The device structure further includes a first protective layer and a second protective layer made of a material different from the first protective layer. The intermediate layer includes a first dielectric layer on the base layer, a buried conductive layer disposed on the first dielectric layer and a second dielectric layer is on the top surface of the buried conductive layer. The method further includes removing a portion of the protective layers to form the transistor devices and to form an insulating layer covering the sidewalls of the buried conductive layers.

Description

Transistor element with buried conductive layer and method of manufacturing the same

The present invention mainly relates to a buried conductive layer for transistor elements, especially for fin type (Fin FET), nanowire type (Nanowire FET) and nanosheet type (Nanosheet FET) field effect transistor elements. Buried conductive layer.

The pursuit of high-density computing components has always been a common goal of the semiconductor industry. Some transistor devices such as FinFET, Nanowire FET and Nanosheet FET can improve the device performance by changing the structure of the unit transistor device . Among them, the nano-chip field effect transistor can achieve better control of the current tunnel by the gate terminal and smaller leakage current through the nano-chip current tunnel covered by the gate electrode. With nanochip FET technology, semiconductor circuit designers can reduce overall circuit power consumption or speed up digital logic integrated circuits. The advantages of nanochip transistors are leading the digital logic integrated circuit, semiconductor industry, and even the computer industry to a faster, more complex, but also more energy-efficient field.

Nanochip FET technology with a buried conductive layer below the device can simplify the complexity of the metal wiring layer above the transistor. This method can further reduce the area of the overall component, and finally achieve a more compact integrated circuit with higher computing performance per unit area.

Generally speaking, the source terminal of the transistor is connected to the power rail, the ground wire (GND), the high potential The line (VDD) connections form an operational logic/array type integrated circuit, and these connections are made by metal lines disposed on the field effect transistors. There is also a vertical metal block between the metal line and the source terminal of the FET as a bridge, but the power line still occupies a large part of the area of the metal layer of the semiconductor structure.

US Patent No. 20200411436 (U.S. Pat. No. 20200411436), published on December 31, 2020, discloses a method to form buried power lines 512 "between" transistor elements, as shown in FIG. 1 . The method includes forming a pair of adjacent transistor elements (from bottom to top, including the element bottom pillar extending from the substrate 410, the tunnel bottom dielectric layer 530, the nanochip sacrificial layer 440 and the nanochip tunnel layer 450) on a On the substrate, the pair of adjacent transistor elements are separated by a trench 479, and the trench 479 is filled with a trench filling layer 470 (which is the predecessor of the dielectric material panel 472). The method further includes forming a panel 472 of dielectric material between the pair of adjacent transistor elements and forming a protective layer 495 on each transistor element by removing portions of the trench fill layer. The method further includes forming a sidewall protection pillar 504 (for details, please refer to the original US Patent No. 20200411436 and FIG. 6 ) on the protection layer 495 , and forming a buried power line 512 between the sidewall protection pillar 504 and the protection layer 495 between. The method further includes forming a power line cover 515 over the buried power line 512 and the sidewall protection pillars 504 , the power line cover 515 may be a metal of the same material as the buried power line 512 , and a dielectric material is used for the power line cover 515 The block 527 covers the power line cover 515 as an insulating layer for blocking leakage current. Thus, the buried power lines ( 512 and 515 ) can be surrounded by dielectric materials (including the sidewall protection pillars 504 , the protective layer 495 and the dielectric material block 527 ), and the dielectric materials thus provide sufficient power for the power lines. Protect. Another embodiment is also disclosed in the text, and the source/drain regions of the semiconductor (that is, where the nanochip sacrificial layer 440 and the nanochip tunnel layer 450 are located) and the buried power lines (512 and 515) are mentioned in the text. ), which can be connected by metal vertical contact columns (Contact/Via) (for details, please refer to the original text of US Patent No. 20200411436 and Figure 19), and then protected by surrounding dielectric materials, no additional lithography patterns are required in the process. chemical process. Therefore, buried power lines provide the simplification of the complex and tight metal line structure over the transistor elements and the opportunity to reduce the overall transistor element area.

Although this patent case (US patent case No. 20200411436) provides a method of forming buried power lines between transistor elements, since the power lines can only be located between the transistor elements, therefore 1) For the overall component (including the area occupied by the transistor component and the area occupied by the metal line above the transistor) The reduction in the area occupied by the product) is of limited help. 2) The area where the power cord can be buried is limited. 3) Since the buried power line is arranged at the bottom of the transistor element, and the metal wire is arranged at the transistor Above the device, the length of the metal vertical contact column (Contact/Via) used for connection needs to reach the overall height of the transistor element structure, which increases the difficulty and resistance value of the metal vertical contact column manufacturing, and thus may reduce the performance of the transistor device.

U.S. Patent Case No. 20170243957 (U.S. Pat. No. 20170243957), published in On August 24, 2017, a semiconductor device including a fin field effect transistor (Fin FET) having a fin structure was disclosed, as shown in FIG. 2 . The fin structure includes a base layer protruding from the substrate (including the substrate 60 , device bottom pillars 611 and 711 ), an intermediate layer 614 disposed on the base layer, and a channel layer (including the silicon germanium layer 615 disposed on the intermediate layer 614 ) with the over-silicon layer 713). The fin structure further includes a first protective layer 640A and a second protective layer 650A made of different materials from the first protective layer 640A. The intermediate layer 614 includes a first semiconductor layer (including 612 and 712 ) and an upper silicon layer (including 613 and 713 ) disposed thereon. The first protective layer 640A covers the sidewalls of the first semiconductor layer (including 612 and 712 ), and the second protective layer 650A covers the first semiconductor layer 640A. The patent (US Patent No. 20170243957) further includes a method of etching back part of the sacrificial layer by depositing a sacrificial layer on the protective layer (640A and 650A) and filling the trenches. After etching back the sacrificial layer, the exposed part of the protective layer ( 640A and 650A ) is the upper half of the protective layer to be removed. After removing the upper half of the protective layer, the upper silicon layer (including 613 and 713) under the protective layer is exposed, and the remaining sacrificial layer is removed, that is, the partial removal of the first protective layer 640A and the second protective layer 650A is completed, as shown in FIG. 2 . Since this method does not leave a sacrificial layer after completion, it is not shown in FIG. 2 (for details, please refer to the original text of US Patent No. 20170243957 and FIGS. 7-10 in the text).

This patent case (US Patent Case No. 20170243957) provides a method to control the protective layer The number of layers and part of the protective layer are removed to protect the transistor element structure under the protective layer, and at the same time, the upper silicon layer (including 613 and 713) is exposed for the subsequent process. Different from the method proposed in the patent case, the upper half of the protective layer is removed to expose the semiconductor layer, the present invention proposes to modify the process of removing the protective layer structure to remove the lower half, so as to retain the protective layer of the upper half to protect the upper half of the transistor structure Segment semiconductor layer (190/330). In addition, the present invention further fills the lower part of the protective layer structure as a protective layer for protecting the buried conductive layer 150 , thereby achieving leakage protection of the buried conductive layer 150 . Therefore, the present invention expands that the protective layer structure can only protect the continuous surface of a single material below, so that the material of the protective layer structure can be changed in sections, thereby protecting the continuous surface of multiple materials below.

For devices with advanced structures, such as fin, nanowire and nanochip FETs, an efficient mechanism for constructing buried conductive layers can simplify the complexity of metal wiring connections above the FETs, The overall area of the components has been reduced, resulting in denser logic circuits with higher computing performance per unit area.

The invention provides a transistor element with a buried conductive layer and a transistor A method of forming a buried conductive layer in a bulk element structure. The method includes forming a sandwich structure of a buried conductive layer and an upper and lower dielectric material, wherein the upper and lower dielectric materials further separate the semiconductor layer above the element from the bottom pillar of the element below. The method further includes forming a multi-layered protective layer structure between adjacent device monomers. The method further includes partially removing a protective layer and filling in another protective layer of different materials, so as to change the material of the protective layer structure in sections to protect the buried conductive wires and the current tunnel of the semiconductor device from being exposed in the process.

The dielectric layers and insulating layers (including 131, 132, 141 and 142) and the additional protective layers (including 210 and 220) in the sandwich structure successfully connect the buried conductive layer 150 with the semiconductor layer 190 above and the bottom of the device. Column 110 is separated and can be 1) The buried conductive layer 150 is protected to avoid unnecessary cross-contamination between the buried conductive layer 150 and other components in the component manufacturing process. 2) The leakage current from the gate electrode 280 to the buried conductive layer 150 can be avoided. 3) The parasitic capacitance formed by the buried conductive layer 150 and other components can be substantially reduced by selecting materials with low dielectric constants for the dielectric and insulating layer materials themselves.

In the embodiment of the present invention, the buried conductive layer 150 is located between the device bottom pillar 110 and the nanochip tunnel layer 180, which can 1) Simplify the complexity of the metal lines above the components. 2) Reduce the total area of the overall device, including the total area occupied by the device structure and the metal lines above the device. 3) By reducing the distance between the traditional buried conductive layer and the nanochip tunnel layer 180, the manufacturing difficulty and resistance value of the metal vertical contact column (Contact/Via) can be reduced.

FIG. 3 is a diagram illustrating a nanochip tunnel layer of adjacent elements, buried, according to some embodiments. Cross-sectional view of the conductive layer and gate. In some embodiments, a plurality of element cells are adjacently juxtaposed on the substrate, wherein the element cells include transistor elements. These transistor elements may be horizontal finFETs, horizontal nanowire/nanochip field effect transistors, or other types of transistor elements.

These horizontal blocks of fin structures, nanowire/nanosheet structures or other components are in phase The adjacent element cells can be separated from the trench filling layer 250 by trenches.

In some embodiments, the intermediate layer 160 is disposed on the device base pillars 110 , and the nanosheet stack layer 190 is disposed on the intermediate layer 160 . The nanosheet stack layer 190 includes a nanosheet sacrificial layer 170 and a nanosheet tunnel layer 180 which are alternately stacked.

The exposure pattern transfer used to define the structure of the element can be, but is not limited to, mainly in two different ways: one is the direct-write process, which includes extreme ultraviolet (EUV) or electron beam (E-beam) or a combination of both. The other is self-aligned single patterning (SASP), or self-aligned multiple patterning (self-aligned multiple patterning) or a combination thereof.

In this embodiment, the substrate 100 is a silicon substrate.

In some embodiments, the substrate may be composed of different materials, such as single element semiconductors including single crystal, polycrystalline, amorphous Si, Ge or elements thereof, III-V compound semiconductors including GaAs, GaP, InP, InAs , InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or other materials, IV-IV compound semiconductors, including SiC, SiGe or other materials, different kinds of substrate structures, such as silicon-on-insulator (Silicon- on-Insulator (SOI)), or a combination of the above materials. Many of the blocks on the substrate 100 may be doped with different n, p or neutral impurities to achieve better conductivity.

The base layer 120 includes the substrate 100 and the device pillars 110 . Component pillars 110 may be connected to the substrate 100 is fabricated from the same material, or is an extension of substrate 100 .

The intermediate layer 160 is a sandwich structure, including the buried conductive layer 150 in the middle, and the first dielectric material layer 130 and the second dielectric material layer 140 are respectively located below and above the buried conductive layer 150 . In some embodiments, the first dielectric material layer 130 includes a first dielectric layer 131 and a first insulating layer 132 , and the second dielectric material layer 140 includes a second dielectric layer 141 and a second insulating layer 142 . However, the interlayer 160 may add additional layers or reduce the number of layers to protect the buried conductive layer 150 from leakage current. In this embodiment, the sandwich structure of the intermediate layer 160 is arranged from bottom to top, respectively, the first dielectric layer 131 , the first insulating layer 132 , the buried conductive layer 150 , the second insulating layer 142 and the second dielectric layer Layer 141. The first dielectric layer 131 and the second dielectric layer 141 in the intermediate layer 160 of the sandwich structure further separate the buried conductive layer 150 from the underlying element pillar 110 and the upper semiconductor layer 190 .

In some embodiments, the buried conductive layer 150 may be buried between the device base pillar 110 and the device semiconductor layer 190 . The buried conductive layer 150 can be deposited by a uniform deposition process, such as atomic layer deposition (ALD), plasma assisted atomic layer deposition (PEALD), or a chemical deposition process, such as chemical vapor deposition (CVD), plasma assisted chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), or other processes.

In some embodiments, the buried conductive layer 150 may be made of, but not limited to, different conductive composition of electrical materials. For example, semiconductor materials, including doped single crystal Si, polycrystalline Si, amorphous Si, Ge, SiGe, etc., metal materials, including tungsten W, Ti, Ta, Ru, Hf, Zr, Co, Ni, Cu, Al , Pt, Sn, Ag, Au or other single element metals, metal compounds, including GeSn, TaN, TiN, WN, RuO2, etc., metal silicon compounds, including CoSi, NiSi, ZrSi, RuSi, WSi, transition metal aluminum compounds, including Ti3Al, ZrAl, conductive carbon based materials such as TaC, TiC, TiAlC, TaMgC, carbon nanotubes, graphene or any combination of these materials. The doping process may be additionally performed during or after the deposition of the buried conductive layer 150 .

The first dielectric layer 131 and the second dielectric layer 141 may be composed of similar or the same dielectric layer materials. The dielectric layer may comprise one or more layers of different dielectric materials, such as phosphosilicate glass (PSG), SiON, SiCN, SiOCN, SiC, or other dielectric materials. Dielectric materials suitable for making the conductor network of the front-end process can be similar to the conductor network layers of the back-end process. In other words, a low dielectric value (k-value) material may be used for the first dielectric layer 131 and the second dielectric layer 141 . Low-k materials, including fluorine-doped silicon oxide (SiO:F), carbon-doped silicon oxide (SiO:C), methyl silsequioxane (MSQ), hydrogen silsesquioxane Hydrogen silsequioxane (HSQ), tetraethyl orthosilicate (TEOS), or a combination of the above materials.

The first insulating layer 132 and the second insulating layer 142 may comprise one or more different insulating layers Materials, including SiON, SiCN, SiOCN, SiC, etc. or a combination of the above materials.

In some embodiments, the nanosheet stack layer 190 comprises staggered stacked nanosheet sacrificial layer 170 and nanosheet tunnel layer 180 . In many embodiments, the nanosheet sacrificial layer 170 may be a semiconductor material including, but not limited to, Si, Ge, GeSn, SiGe, SiC, Si:C, or a combination thereof, and the nanosheet tunnel layer 180 may be different from The semiconductor material of the nanochip sacrificial layer 170 and the second dielectric layer 141 can provide the nanochip tunnel layer 180 with an etching selectivity ratio different from that of the nanochip sacrificial layer 170 and the second dielectric layer 141, which is convenient for subsequent process implementation.

In some embodiments, the first protective layer 210 and the second protective layer 220 are used to encapsulate the underlying device structure to avoid oxidation due to exposure to the environment. The protective layer can be one or more layers of different dielectric materials. The dielectric material may be a silicon oxide dielectric material, such as Phosphosilicate glass (PSG), SiON, or a silicon nitride dielectric material, such as SiN, SiCN, SiOCN, SiC, or a combination thereof. The material of the protective layer may also be different as the material under the protective layer may be different. In this embodiment, the first protective layer 210 may be a silicon oxide dielectric material SiO ₂ , and the second protective layer may be a silicon nitride dielectric material SiN.

In many embodiments, trench fill layer 250 may be one or more layers of insulating material, such as Composition of silica. The process used to form silicon dioxide can be (but not limited to) atomic layer deposition (ALD), chemical deposition mechanisms, including chemical vapor deposition (CVD), flowable chemical vapor deposition (Flowable-CVD), plasma assisted Chemical Vapor Deposition (PECVD), Atmospheric Chemical Vapor Deposition (APCVD), Low Pressure Chemical Vapor Deposition (LPCVD), High Density Plasma Chemical Vapor Deposition (HDPCVD) and combinations thereof. In some embodiments, chemical vapor deposition precursors include silicate, siloxane, silicon-based polymer materials, such as methyl silsequioxane (MSQ), Hydrogen silsequioxane (HSQ), methyl silsequioxane and hydrogen silsesquioxane synthetic materials MSQ/HSQ, perhydrosilanzane (TCPS), perhydropolysilicon Azane (perhydro-polysilazane (PHPS)), tetraethyl orthosilicate (TEOS), or trisilylamine (TSA). After the CVD process, the film will be cured and annealed to remove unnecessary impurities and form a reduced and dense silicon dioxide film. In some embodiments, the number of anneals is greater than one. CVD films can be doped with boron (B) or phosphorus (P) atoms. The trench filling layer 250 can be composed of one or more layers of different insulating materials, including spin-on glass SOG, SiO, SiON, SiOCN or fluorosilicate glass FSG. After the trench filling layer 250 is formed, an annealing process can still be added to improve the quality of the inner insulating layer.

In many embodiments, gate layer 280 includes a gate dielectric layer, a work function adjustment layer, and Gate electrode (not shown in detail in layers in the drawings, please refer to US Patent No. 20170243957 for details).

FIGS. 4-12 are diagrams illustrating nanosheet tunnels forming adjacent elements, according to some embodiments. A cross-sectional view of the middle stage of the channel layer 180 , the buried conductive layer 150 and the gate layer 280 . Additionally, additional operations may be added before, during, or after the process, and some of the operations described below may be replaced or eliminated in other embodiments. The sequence of operations and processes can be interchanged.

FIG. 4 shows the base layer 310 , the intermediate layer 320 , the semiconductor layer 330 and the hard mask layer 340 . In some embodiments, the base layer 310 is a silicon substrate or a silicon layer of SOI. The intermediate layer 320 has a sandwich structure, and includes the first dielectric layer 131 , the first insulating layer 132 , the buried conductive layer 150 , the second insulating layer 142 and the second dielectric layer 141 from bottom to top. The semiconductor layer 330 (ie, the nanosheet stack layer 190 ) is disposed on the intermediate layer 320 . The semiconductor layer generally includes a nanosheet sacrificial layer 170 and a nanosheet tunnel layer 180 . The hard mask layer 340 is further disposed on the semiconductor layer 330 .

In some embodiments, the rigid mask layer 340 may be composed of multiple layers of different materials, and A hard mask layer 340 may be used to protect and define the device area. In this embodiment, the hard mask layer 340 is composed of two different material layers, which are a pad oxide layer 341 and a pad nitride layer 342 respectively. However, one or more layers of different materials may also be added to finely define the device area and trench area. Generally, the thickness of the pad oxide layer 341 ranges from about 2 nm to 15 nm, and the thickness of the pad nitride layer 342 ranges from about 10 nm to 50 nm.

In some embodiments, the thickness T1 of the buried conductive layer 150 ranges from about 5 nm to 50 nm. The thickness of the first dielectric layer 131 and the second dielectric layer 141 ranges from about 10 nm to 50 nm. The thickness of the first insulating layer 132 and the second insulating layer 142 ranges from about 1 nm to 20 nm.

As shown in FIG. 5 , the first hard mask layer 340 patterning process is completed. After patterning), a hard mask pattern 345 of the device structure including the pad oxide layer 341 and the pad nitride layer 342 is formed. The first patterning process of the hard mask layer 340 is completed for the first time to define the width of the trench under the hard mask layer 340 and the width of the nanochip tunnel layer 180 . With the etching selectivity ratio between the second insulating layer 142 and the second dielectric layer 141, the second insulating layer 142 can be the etch stop layer of the first patterning process of the hard mask layer 340, so the buried conductive layer 150 and its underlying device structures are protected during the first hard mask layer 340 patterning process.

The depth range of the trench depth D1 after the first hard mask layer 340 patterning process is completed The circumference is about 50 nm to 150 nm.

FIG. 6 shows that the first protective layer 210 is formed and covers all the underlying device structures. The first protective layer 210 may include one or more layers of dielectric materials to prevent the element structures under the protective layer from being oxidized due to subsequent processes.

In some embodiments, the first protective layer 210 may be an oxide compound. In this embodiment, the first protective layer 210 is SiO ₂ . _The SiO deposition process may include (but is not limited to) atomic layer deposition (ALD), chemical deposition mechanisms, including chemical vapor deposition CVD, flowable chemical vapor deposition Flowable-CVD, plasma assisted chemical vapor deposition PECVD, atmospheric chemical vapor deposition Deposition (APCVD), Low Pressure Chemical Vapor Deposition (LPCVD), High Density Plasma Chemical Vapor Deposition (HDPCVD) and combinations thereof.

In some embodiments, the thickness of the first protective layer 210 ranges from about 1 nm to 20 nm Meter.

In some embodiments, the first protective layer 210 is used to protect the first patterned The semiconductor layer 190 and the partially exposed second dielectric layer 141 after the first patterning prevent the underlying device pattern from being damaged by the subsequent process. However, as long as the sidewalls of the nanochip sacrificial layer 170 and the nanochip tunnel layer 180 are covered by the first protective layer 210 , the first protective layer 210 does not necessarily need to cover all the sidewalls of the second dielectric layer. In other words, in the first patterning process of the hard mask layer 340 , it is not necessary to etch away all the second dielectric layer 141 at the bottom of the trench and expose the second insulating layer 142 thereunder. The deposition of the first protective layer 210 therefore does not necessarily touch the lower second insulating layer 142 because the second dielectric layer 141 which is only partially etched is interposed therebetween.

Next, go through the second hard mask patterning cycle, including the second hard mask deposition, the second patterning, the second trench etching and the remaining hard mask After removal, the trench area expands to the base layer 120 , as shown in FIG. 7 . In other words, deeper trench regions are formed. The second trench etching may etch away the intermediate layer 160 in the trench region to form the device base pillars 110 and the partially exposed substrate 100 .

The second hard mask layer patterning process mentioned in the text can also be called the trench patterning process Trench patterning cycle, which can be performed multiple times to achieve a set goal. This cycle typically includes hardmask deposition, patterning, trench etching, and removal of the remaining hardmask, and the practices of Figures 4-5 may be repeated or additional operations performed before, during, or after the cycle, and part of the cycle. Steps can be omitted, replaced and exchanged. In order to avoid repeating the concepts shown in FIGS. 4 to 5 , the drawings of the process are omitted here, and only the completed FIG. 7 is attached.

After completing the trench patterning cycle, the trench depth D2 ranges from about 75 nm to about 300 nm.

The distance W1 of the buried conductive layer between adjacent elements ranges from about 3 nm to about 50 nm.

The buried conductive layer width W2 ranges from about 20 nm to about 80 nm.

The aspect ratio between the trenches is equal to the trench depth D2 divided by the buried conduction The distance W1 between layers and adjacent elements is one of the key dimensions that determines the shape of the trench.

The stability of the groove pattern process cycle can be improved by observing the change of the index W2/W1. understand.

After the device base 110 is formed, as shown in FIG. 8 , the second protective layer 220 covers all the component structure. The material of the second protective layer can be the same as that of the first insulating layer 142 and the second insulating layer 152, or other materials with excellent trench filling capability can also be used.

The buried conductive layer is marked with a distance W1 between adjacent elements after the second protective layer 220 is deposited. Shown as W3, so W3 is equal to W1 minus twice the thickness of the second protective layer.

W3 is one of the key dimensions that can be used to understand STI (shallow trench The isolation refers to the ability of the trench filling layer 250) to be filled with silicon oxide. For increasingly limited size, different deposition mechanisms can be used to fill in stages, for example, atomic layer deposition (ALD) is used to fill the narrow part of the bottom of the trench, and then chemical vapor deposition (CVD) is used to fill the upper part. Wider trench sections to reduce the chance of trench bottom fill failures.

As shown in FIG. 9 , after the trenches are defined, a trench filling layer 250 is filled to cover the second protective layer 220 , and the second protective layer is protected in subsequent processes, such as STI etching back and protective layer removal processes The second half of the 220.

Since the sidewall of the semiconductor layer 190 and the upper half of the first protective layer 210 are protected by the second The layer 220 covers the semiconductor layer 190 in the upper part of the device structure and the device bottom pillar 110 in the lower part of the device structure without being oxidized by oxygen atoms in the environment due to the formation of the trench filling layer 250 (ie, STI silicon oxide).

As shown in FIG. 10, part of the STI silicon oxide and the first and second protective layers 210, 220 are is removed and exposes the semiconductor layer 190 of the underlying device structure. In this embodiment, the device structure includes a nanosheet tunnel layer 180 , a nanosheet sacrificial layer 170 and a second dielectric layer 141 .

As described in the previous paragraph 42, the second dielectric layer 141 is subjected to different process conditions. After removing part of the STI silicon oxide and the first and second protective layers 210 and 220 as shown in FIG. 8 , they may be buried under the STI silicon oxide, partially exposed, or fully exposed. If the second dielectric layer 141 is buried under the STI silicon oxide, part of the first protective layer 210 can remain on the sidewall of the second dielectric layer and provide better protection for the buried conductive layer 150 below, so as to achieve a higher level of protection. Low gate-to-buried leakage current.

The vertical distance between the buried conductive layer 150 and the subsequent gate layer 280 is T2. this key The dimension T2 is particularly important because T2 must be large enough to avoid leakage current from the gate to the buried conductive layer 150 , but not so large as to affect the subsequent formation of the gate layer 280 .

After the etching back of the STI silicon oxide and the removal of the upper half of the protective layer are completed, the bottom of the trench is The angle of the corner formed with the side wall of the element is denoted as R1. R1 can be used not only as an indicator of process stability, but also as an important parameter for calculating the leakage current from the gate layer 280 to the buried conductive layer 150 . The removal of the upper protective layer directly affects the critical dimension R1. As described in the previous paragraph 42, by controlling the process conditions for removing the top half of the protective layer, the remaining protective layers (210 and 220) can cover part of the second dielectric layer 141, and increase R1 and T2 to achieve optimization control of leakage current.

As shown in FIG. 11, with different etching selectivity ratios, the nanochip sacrificial layer 170 can be The nanosheet tunnel layer 180 required by the element structure is removed and left, which becomes the current tunnel of the element structure.

In some embodiments, nanostack layer 190 includes staggered nanosheet sacrificial layers 170 with the nanosheet tunnel layer 180 . In various embodiments, the sacrificial nanosheet layer 170 may be a semiconductor material including, but not limited to, Si, Ge, GeSn, SiGe, SiC, Si:C, or a combination thereof, wherein the sacrificial nanosheet layer 170 may be The materials of the second dielectric layer 141 and the nanosheet tunnel layer 180 are different to provide a sufficiently good etching selectivity ratio. The nanosheet sacrificial layer 170 may be SiGe, and the Ge concentration is in the range of, but not limited to, about 20 to 40 atomic percent concentration.

In many embodiments, the nanosheet tunnel layer 180 may be a semiconductor material including, Without limitation, Si, Ge, GeSn, SiGe, SiC, Si:C, or combinations thereof. The nanosheet tunnel layer 180 can be made of different materials from the second dielectric layer 141 and the nanosheet sacrificial layer 170 to provide a sufficiently good etching selectivity ratio.

In this embodiment, the nanosheet tunnel layer 180 may be single crystal Si or different from nanosheets Sacrificial layer 170 Ge atomic percent concentration of SiGe.

The critical dimensions R1 and T2 may be affected by the nanochip tunneling process. Variations, such as selectivity loss, are unexpected damage to components caused by selective etching. By observing the changes of indicators such as R1 and T2 with the process, the device manufacturer can ensure the control of the leakage current of the device.

As shown in FIG. 12 , the gate layer 280 is deposited and wraps around the nanochip tunnel layer 180 . The gate layer 280 generally includes, but is not limited to, a gate dielectric layer, a work function adjustment layer, and a gate electrode (not layered in the drawings).

The gate dielectric layer typically includes one or more layers of different dielectric materials, such as silicon oxide, silicon nitride, or high-k materials or other suitable dielectric materials in combination therewith. High dielectric constant materials, including HfO ₂ , HfSiON, HfTaO, HfSiO, HfZrO, ZrO, Al ₂ O ₃ , TiO ₂ , HfO ₂ -Al ₂ O ₃ , other suitable high dielectric constant materials or combinations thereof.

The gate electrode may comprise one or more layers of different conductive materials, such as highly conductive semiconductor materials, including doped monocrystalline Si, doped polycrystalline Si or doped amorphous Si, Ge, SiGe or combinations thereof, metals, including W, Ti, Ta, Ru, Hf, Zr, Co, Ni, Cu, Al, Pt, Sn, Ag, Au or other metal elements, metal compounds, including GeSn, TaN, TiN, WN, RuO2 or other metal compounds, metal silicide materials, including CoSi, NiSi, ZrSi, RuSi, WSi and other metal silicides, transition metal aluminum alloys, including Ti3Al or ZrAl, conductive carbon-based materials, including TaC, TiC, TiAlC, TaMgC, carbon nanotubes, graphene or its combination. The doping process can also be added during or after the deposition process of the conductive material.

In some embodiments, a work function adjustment layer may be added between the gate dielectric layer and the gate electrode. The work function adjustment layer can be composed of conductive materials, such as metal compounds, including nitrides TiN, TaN, WN or other nitrides, carbides TaAlC, TiC, TaC, TiAlC and other carbides, aluminum alloys TiAl, ZrAl, TiAlC and others Aluminum alloys, silicides HfTi, TiSi, TaSi, RuSi and other silicides, or multi-layer structures. For n-type tunneling, one or more layers of TaN, TaAlC, TiC, Co, TiAl, HfTi, TiSi, TaS are used as work function adjustment layers. For p-type tunneling, one or more layers of TaN, TaAlC, TiAl, Co, TiAl, Al, TiC, TiN are used as work function adjustment layers.

The vertical distance between the buried conductive layer 150 and the top of the second dielectric layer 141 is T3. this The critical dimensions can be used to quantify the parasitic capacitance between the buried conductive layer 150 and the nanochip tunnel layer 180 . By reducing the dielectric constant of the second dielectric layer 141 and the second insulating layer 142 therebetween, the resulting parasitic capacitance can be substantially reduced.

The vertical distance between the buried conductive layer 150 and the bottom of the first dielectric layer 131 is T4. this The critical dimension can be used to quantify the parasitic capacitance between the buried conductive layer 150 and the device bottom pillar 110 . By reducing the dielectric constant of the first dielectric layer 131 and the first insulating layer 132 therebetween, the resulting parasitic capacitance can be substantially reduced.

The embodiment of the present invention provides a method for forming the buried conductive layer 150 in a transistor element. The method includes forming a sandwich structure of buried conductive layer 150 and upper and lower dielectric materials, wherein the upper and lower dielectric materials further separate the semiconductor layer 190 above the device from the bottom pillar 110 of the device below. The method further includes forming a protective layer of the multilayer structure between adjacent device monomers. The method further includes partially removing the protective layer so that the protective layer can be applied to different material surfaces to protect the buried conductive wires and the semiconductor device current tunnels from being exposed to the manufacturing process.

The dielectric layer (including 131, 132, 141 and 142) and the additional protective layer (including 210 and 220) in the sandwich structure successfully separate the buried conductive layer 150 from the semiconductor layer 190 above and the bottom pillar 110 of the device below ,Can 1) Protect the buried conductive layer 150 from cross-contamination with other components. 2) Avoid leakage current from the gate 280 to the buried conductive layer 150 . 3) The parasitic capacitance can be substantially reduced by selecting a low dielectric constant material by the dielectric material itself.

In the embodiment of the present invention, placing the buried conductive layer 150 between the device bottom pillar 110 and the nanochip tunnel layer 180 can 1) simplify the complexity of the metal lines above the device, and 2) reduce the place where the device contains metal lines 3) By reducing the distance between the traditional buried conductive layer and the nanochip tunnel layer 180, the manufacturing difficulty and resistance value of the vertical contact column (Contact/Via) can be reduced.

The present invention can be applied in different fields, including (but not limited to): complementary metal oxide semiconductors, transistor elements, logic circuits, memory circuits and integrated circuits.

The method described above can be used for integrated circuit wafer fabrication. Manufacturers can wafer form The integrated circuit chip produced by packaging and distribution in the form of a single chip, a bare chip form, and a packaged chip form. In the form of packaged wafers, it is divided into single-chip packaging and multi-chip packaging. Chips can be integrated into different forms of chips such as discrete circuit elements, signal processing elements, or can be integrated into motherboards or even client products. Client products can be any product that uses integrated circuit chips, from the lowest-end applications such as traditional refrigerators to advanced computer products.

Elemental concentrations in compounds are expressed as Six Ge _{(1-x) .} where x is less than or equal to 1. Different concentration ratios are included in the simplest chemical formula SiGe. If the compound has other elements, it can also be called an alloy.

"In one embodiment" does not necessarily all refer to the same embodiment, but rather a single feature. "In some embodiments" does not necessarily all refer to the same embodiments, but rather to just some features.

When "comprising A, B, C, or a combination thereof" appears in the description, it means that the context includes items of A, B, and C alone, or A and B, A and C, B and C, or A and B and C. This concept can also be extended, as the enumeration may only be part of the possible ways.

As used herein, when referring to the structure of a field effect transistor device FET When used, spatial adjectives such as below, above, bottom, top, vertical, horizontal, etc. may be used for convenience. These references are intended to be used in a manner consistent with the figures only, for teaching purposes, and are not intended to be absolute references to FETs. For example, the FETs may be spatially oriented in any manner other than the orientation shown in the figures. When referring to the drawings, "vertical" is used to refer to the direction perpendicular to the surface of the semiconductor layer, and "horizontal" is used to refer to the direction only horizontal to the surface of the semiconductor layer. "Above" is used to refer to the vertical direction away from the semiconductor layer. An element located "above" ("below") another element is further (closer) to the surface of the semiconductor layer than the other element.

The specific embodiments disclosed above are merely exemplary in nature, as the invention may be modified and carried out in different but equivalent manners apparent to those skilled in the art having the aid of the teachings herein. For example, the above-described process steps may be performed in a different order. Furthermore, the invention is not intended to be limited to the details of construction or design herein shown, but rather is as described in the above claims. Therefore, it is apparent that modifications or variations may be made to the specific embodiments disclosed above, and such variations fall within the scope and spirit of the invention. It is to be noted that the use of terms such as "first," "second," "third," or "fourth" to describe various processes or structures within the scope of this specification and the appended claims are used only A quick reference to such structures/steps does not necessarily imply a sequential order/formation of such steps/structures. Of course, such an order of processing may or may not be required depending on the precise scope language. Therefore, the claimed scope of the present invention is as described in the above claims.

Known Technology (shown in Figure 1) 410: Element Base Post 440: Nanochip Sacrificial Layer 450: Nanosheet Tunnel Layer 470: trench filling layer (predecessor of dielectric panel 472) 472: Panels with Dielectric Materials 495: Protective Layer 504: Sidewall guard column (for details, please refer to the original text of US Patent No. 20200411436 and its Figure 6 512: Buried power cord 515: Power cord cover 527: Dielectric Material Block 530: Dielectric layer at the bottom of the tunnel

Prior art (shown in Figure 2) 60: Substrate 611, 711: Component base column 612, 712: the first semiconductor layer 613, 713: Silicon upper layer 614: middle layer 615: SiGe layer 640A: first protective layer 650A: Second protective layer

The present invention (shown in Figures 3 to 12) 100: Substrate 110: Component base column 130: the first dielectric material layer (including the first dielectric layer 131 and the first insulating layer 132) 131: first dielectric layer 132: first insulating layer 150: Buried conductive layer 140: the second dielectric material layer (including the second dielectric layer 141 and the second insulating layer 142) 141: Second Dielectric Layer 142: Second insulating layer 210: First protective layer 220: Second protective layer 250: trench fill layer 170: Nanochip Sacrificial Layer 180: Nanosheet Tunnel Layer 280: gate layer 120, 310: grassroots 160, 320: middle layer 190, 330: Semiconductor layer/nanosheet stack 340: Hard cover layer 341: Pad oxide layer 342: Pad nitride layer 345: Rigid Mask Graphics for Component Structures W1: The distance between the buried conductive layer and the adjacent components W2: Buried conductive layer width W3: The distance between the buried conductive layer and the adjacent elements W1 is marked as W3 after the second protective layer 220 is deposited T1: Thickness of the buried conductive layer 150 T2: the vertical distance between the buried conductive layer 150 and the subsequent gate layer 280 T3: the vertical distance between the buried conductive layer 150 and the top of the second dielectric layer 141 T4: the vertical distance between the buried conductive layer 150 and the bottom of the first dielectric layer 131 D1: trench depth after the first hard mask layer 340 patterning process D2: trench depth after trench patterning cycle R1: The angle of the corner formed by the bottom of the trench and the side wall of the device

1 to 2 are cross-sectional views of transistor elements provided according to the prior art.

3 is a cross-sectional view illustrating the nanochip tunnel layer 180 , the buried conductive layer 150 , and the gate layer 280 of adjacent devices, according to some embodiments.

4-12 are cross-sectional views illustrating intermediate stages of forming the nanochip tunnel layer 180, the buried conductive layer 150, and the gate layer 280 of adjacent elements, according to some embodiments.

Diagrams used in this document (including FIGS. 1 and 2 of the prior art and FIGS. 3 to 12 of the present invention) All are cross-sectional views of transistor device channels or intermediate stages of their fabrication. The cross-sectional direction of such a cross-sectional view is perpendicular to the fin pattern of the device silicon substrate, and the cross section crosses the device channel area, so it can also be called a cross-sectional view at the device channel and perpendicular to the device silicon substrate pattern (fin structure), which is called in English. It is Cross Fin-Cut on device channel region or Fin-Cut across device channel region, which is the y direction in the figure.

100: Substrate

110: Component base column

131: first dielectric layer

132: first insulating layer

150: Buried conductive layer

141: Second Dielectric Layer

142: Second insulating layer

220: Second protective layer

250: trench fill layer

180: Nanosheet Tunnel Layer

280: gate layer

120, 310: grassroots

160, 320: middle layer

190, 330: Semiconductor layer/nanosheet stack

W1: The distance between the buried conductive layer and the adjacent components

W2: Buried conductive layer width

W3: The distance between the buried conductive layer and the adjacent elements W1 is marked as W3 after the second protective layer 220 is deposited

T1: Thickness of the buried conductive layer 150

T2: the vertical distance between the buried conductive layer 150 and the subsequent gate layer 280

T3: the vertical distance between the buried conductive layer 150 and the top of the second dielectric layer 141

T4: the vertical distance between the buried conductive layer 150 and the bottom of the first dielectric layer 131

D1: The trench depth after the first hard mask patterning process (hard mask patterning) is completed

D2: trench depth after trench patterning cycle

R1: The angle of the corner formed by the bottom of the trench and the side wall of the device

Claims (8)

A method of fabricating an embedded conductive layer on a transistor element in a transistor element, the method comprising: forming a substrate, wherein the transistor structure comprises a base layer, an intermediate layer located above the base layer, and a layer located above the intermediate layer The semiconductor layer; adjacent transistor elements are formed on the substrate, wherein the adjacent transistor elements are separated by a trench with a depth of D1; a first protective layer is formed to cover the adjacent transistor elements ; remove the lower half of the first protective layer, leave the upper half of the protective layer and expose the second dielectric layer; form elongated trenches, wherein the adjacent transistor elements are separated by a trench of depth D2 ; forming a second protective layer to cover the adjacent transistor elements; and forming a trench filling layer in the trench to cover the first protective layer and the second protective layer below. The method of claim 1, wherein the intermediate layer comprises a first dielectric layer disposed on the base layer, a buried conductive layer disposed on the first dielectric layer, and a buried conductive layer disposed on the first dielectric layer on top of the second dielectric layer. The method of claim 1, wherein removing the lower half of the first protective layer comprises: forming another hard mask layer covering the element structure and the first protective layer; removing the hard mask layer The lower portion, exposing the lower portion of the first protective layer; removing the exposed lower portion of the first protective layer; and removing the remaining hard mask layer. The method of claim 1, wherein forming the extended trench comprises: removing the second dielectric layer and the second insulating layer to expose the buried conductive layer; removing and exposing the buried conductive layer to expose the buried conductive layer The lower dielectric layer is exposed; the first insulating layer and the first dielectric layer are removed to expose the substrate; and part of the substrate is removed to form the element bottom pillar. The method according to claim 4, wherein the interval of the buried conductive layer after etching is W1. The method of claim 1, wherein the width of the middle section of the trench after the deposition of the second protective layer is W3. The method of claim 1, further comprising: etching back part of the trench filling layer; removing the first protective layer and the upper half of the second protective layer to expose the semiconductor layer; removing the nanochip sacrificial layer layer to expose the nanosheet tunnel layer; and forming a gate layer to cover the exposed nanosheet tunnel layer. The method of claim 7, wherein forming a gate layer to cover the exposed nanosheet tunnel layer comprises: forming a gate dielectric layer; forming a work function adjustment layer; and forming a gate electrode.

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