TWI763429B - semiconductor device - Google Patents

Abstract

An object of the present invention is to improve the connection reliability of the solder alloy layer interposed between the semiconductor chip and the chip connection portion. The semiconductor device 100 of the present invention includes a semiconductor wafer 10 , a conductor pattern 32A, a solder alloy layer 40 and an intermetallic compound layer 50 . The conductor pattern 32A includes metal (eg, Cu), and is connected to the lower surface 10b of the semiconductor wafer 10 via the solder alloy layer 40 . The intermetallic compound layer 50 is formed on the boundary between the lower surface 10b of the semiconductor wafer 10 and the solder alloy layer 40, and has a concavo-convex surface from the lower surface 10b side to the conductor pattern 32A side. The lower surface 10b of the semiconductor wafer 10 includes a first region including the center of the lower surface 10b and a second region including the outer periphery of the lower surface 10b. As shown in FIG. 2, the thickness of the intermetallic compound layer 50, the average thickness of the portion 50R1 overlapping with the first region of the lower surface 10b is thicker than the average thickness of the portion 50R2 overlapping with the second region.

Description

semiconductor device

The present invention relates to a semiconductor device, for example, a semiconductor device including a semiconductor chip connected to a chip connection portion via solder.

In Japanese Patent Laid-Open No. 2007-109834 (Patent Document 1), a configuration is described in which a semiconductor chip is mounted as a power IGBT (Insulated Gate Bipolar Transistor: Insulated Gate Bipolar Transistor) module via a solder bonding layer. In the semiconductor device, solders having different compositions are arranged on the center surface portion and the outer peripheral surface portion. [Prior Art Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open No. 2007-109834

[Problems to be Solved by Invention]

A semiconductor device called a power semiconductor device (power module) has requirements for controlling electric power. A power semiconductor device is a semiconductor device in which a power semiconductor chip is mounted on a chip connection portion such as a substrate via solder, and a heat dissipation member or the like is connected as necessary. Power semiconductor devices need to improve the connection reliability of solder alloy layers used for connection of semiconductor chips. In particular, in recent years, the development of power semiconductor wafers that can operate at high temperatures has been progressing. Therefore, for power semiconductor devices, connection reliability in a high temperature environment is required.

An object of the present invention is to provide a technique for improving the connection reliability of a solder alloy layer between a semiconductor chip and a chip connection portion.

[Technical means to solve problems] A semiconductor device according to an embodiment includes: a first semiconductor chip having a first surface and a second surface opposite to the first surface; and a first chip connecting portion including a metal and connected to the first surface via a first solder alloy layer. 1. The second surface of the semiconductor wafer is connected; the first solder alloy layer is disposed between the second surface of the first semiconductor wafer and the connection portion of the first wafer; and the first intermetallic compound layer is The boundary formed on the second surface of the first semiconductor wafer and the first solder alloy layer has a concavo-convex surface from the second surface side to the first chip connection portion side. The second surface includes a first region including the center of the second surface, and a second region including the outer periphery of the second surface. The thickness of the first intermetallic compound layer is such that the average thickness of the first portion overlapping the first region of the second surface is thicker than the average thickness of the second portion overlapping the second region.

A semiconductor device according to another embodiment includes: a first semiconductor wafer having a first surface and a second surface opposite to the first surface; The second surface of the first semiconductor wafer is connected; the first solder alloy layer is disposed between the second surface of the first semiconductor wafer and the connection portion of the first wafer; and the first intermetallic compound layer, It is formed in the said 2nd surface of the said 1st semiconductor chip, and the boundary of the said 1st solder alloy layer, and has the uneven surface from the said 2nd surface side toward the said 1st chip connection part side. The second surface includes a first region including the center of the second surface, and a second region including the outer periphery of the second surface. The said 1st intermetallic compound layer has the 1st part which overlaps with the 1st area|region of the said 2nd surface, and the 2nd part which overlaps with the said 2nd area|region. The height difference of the said concave-convex surface in the said 1st part is larger than the height difference of the said concave-convex surface in the said 2nd part. [Effect of invention]

According to the invention disclosed in this application, the connection reliability of the solder alloy layer between the semiconductor chip and the chip connection portion can be improved.

Problems, configurations, and effects other than those described above will be clarified by the description of the following embodiments.

In each of the drawings for describing the following embodiments, in principle, the same members are given the same reference numerals, and their repeated descriptions are omitted. In addition, there are cases in which the functionally the same requirements are displayed with the same number or the corresponding number. In addition, in order to make it easy to understand a drawing below, even if it is a top view, hatching may be attached|subjected. In addition, the accompanying drawings show implementations and installation examples based on the principles of the present disclosure, but these are for the purpose of understanding the present disclosure and are not intended to limit the interpretation of the present disclosure. The descriptions in this specification are typical examples.

In the present embodiment, the description of the implementation of the present disclosure has been described in sufficient detail, but it should be understood that other installations and forms are also possible, and changes in the configuration/structure or various requirements may be made without departing from the scope and spirit of the technical idea of the present disclosure. replacement.

In the description of the following embodiments, as an example of a semiconductor device, a semiconductor device (power semiconductor device, power module) in which a plurality of semiconductor chips are mounted via solder on a metal pattern formed on an insulating substrate to be modularized is used. illustrate. However, the technology described below can be applied to various modifications as long as it is a semiconductor device including a semiconductor chip connected to a chip connection portion via solder.

In addition, in the description of the following embodiment, as an example of the chip connection part which connects a semiconductor chip via a solder alloy layer, the metal conductor pattern formed on the insulating substrate is exemplified and described. However, there are various variations of the chip connection portion. For example, lead members electrically connected to the semiconductor chip, chip pads of the lead frame supporting the semiconductor chip, or electrodes of other electronic parts electrically connected to the semiconductor chip can be exemplified. Wait.

<Configuration example of semiconductor device> FIG. 1 is a cross-sectional view schematically showing a configuration example of the semiconductor device of the present embodiment. The semiconductor device 100 includes a plurality of semiconductor chips (semiconductor chips 10 and 20 ), and a substrate 30 on which the semiconductor chips 10 and 20 are mounted. The substrate 30 includes an insulating substrate 31 , a plurality of conductor patterns 32 formed on the upper surface 31 t of the insulating substrate 31 , and conductor patterns 33 formed on the lower surface 31 b of the insulating substrate 31 . The semiconductor chips 10 and 20 are mounted on the conductor patterns 32A included in the plurality of conductor patterns 32 . The substrate 30 on which the semiconductor chips 10 and 20 are mounted is mounted on the base plate 3 via the solder alloy layer 2 . The substrate 30 mounted on the base plate 3 is covered by the cover 4 together with the semiconductor chips 10 and 20 , and is accommodated in the space surrounded by the cover 4 and the base plate 3 . The space surrounded by the lid 4 and the base plate 3 is filled with, for example, a gel-like insulating material, that is, a sealing material 5 , and the semiconductor chips 10 and 20 and the wires 6 are sealed by the sealing material 5 .

The substrate 30 is, for example, attached to both sides of the insulating substrate 31, which is a ceramic substrate, with a metal film, and the metal film is patterned to form a circuit. The substrate 30 can be made of DBC (Direct Bond Copper: Direct Bond Copper) using a metal mainly composed of copper as the conductor patterns 32 and 33 , or DBA (Direct Bond Copper: direct bond copper) using a metal mainly composed of aluminum as the conductor patterns 32 and 33 . Aluminum: Directly bonded to aluminum). However, as a material constituting the chip mounting portion (chip connecting portion) on which the semiconductor chips 10 and 20 are mounted, various metal materials can be applied. For example, it can be connected to Cu, Al, Cu-Mo, Al-SiC (composite of aluminum and silicon carbide), Mg-SiC (composite of magnesium and silicon carbide), 42Alloy or CIC (Copper Invar Copper: Copper-Invar In the case of a metal chip connecting portion such as steel-copper), the connection reliability of the solder alloy layer between the semiconductor chip and the chip connecting portion can also be improved by applying the techniques described below.

In the cross-section shown in FIG. 1 , the plurality of conductor patterns 32 include conductor patterns 32A on which the semiconductor chips 10 and 20 are mounted, conductor patterns 32B electrically connected to the semiconductor chips 10 and 20 via the wires 6 , and electrically connected to the pins 7 . The connected conductor pattern 32C. A part of the lead 7 is led out of the cover 4 and connected to the terminal of the semiconductor device 100 . Or, use pin 7 itself as a terminal.

The semiconductor device 100 is an electronic component (power semiconductor device, power module) for power control incorporated in a power supply circuit. As a power module, the inverter etc. which use the semiconductor chips 10 and 20 as switching elements can be illustrated, for example. The semiconductor device 100 is incorporated in, for example, a power supply device mounted on a body of a rail vehicle or an automobile, an airplane, an industrial device, or the like. In the case of such an application, the semiconductor device 100 is exposed to a high temperature environment, and reliability under high temperature is required for each component constituting the semiconductor device 100 . For example, when SiC, GaN, or the like is used as the semiconductor substrate constituting the semiconductor wafer 10 or 20, it is possible to operate at a higher temperature than when Si is used. Therefore, it is necessary to ensure the reliability of the connection reliability of the portion electrically or thermally connecting the semiconductor chips 10 and 20 to the chip connection portion at a higher temperature.

As shown in FIG. 2 to be described later, the semiconductor wafer 10 has a metallization film 11 formed on the lower surface 10b and electrode pads 12 formed on the upper surface 10t. The electrode pads 12 are electrically connected to the conductor patterns 32B via the wires 6 shown in FIG. 1 . The metallization film 11 is electrically connected to the conductor pattern 32A via the solder alloy layer 40 . The metallization film 11 and the electrode pads 12 function as electrodes of the semiconductor wafer 10, respectively. For example, when the semiconductor chip 10 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), any one of the electrode pad 12 and the metallization film 11 is the source electrode, and the other is the drain electrode. For example, when the semiconductor chip 10 is a bipolar transistor, either one of the electrode pad 12 and the metallization film 11 is an emitter electrode, and the other is a collector electrode. In the case of a transistor, on the upper surface 10t, in addition to the electrode pads 12, electrode pads for gate electrodes are formed. Also, for example, when the semiconductor chip 10 is a diode, either one of the electrode pad 12 and the metallized film 11 is an anode electrode, and the other is a cathode electrode.

<Connection structure of semiconductor chip> In view of the above-mentioned matters, a configuration example of the present embodiment for improving the reliability of the connecting portion between the semiconductor chip and the chip connecting portion will be described. FIG. 2 is an enlarged cross-sectional view showing an enlarged periphery of a solder alloy layer electrically connecting one of the plurality of semiconductor chips shown in FIG. 1 and the conductor pattern. FIG. 3 is a top view of the lower surface side of the semiconductor wafer shown in FIG. 2 . FIG. 8 is an enlarged cross-sectional view schematically showing the type of cracks generated in the connection structure of the semiconductor device as the study example of FIG. 2 . In the following, the technology for improving the reliability of the connection portion between the semiconductor chip and the chip connecting portion will be described by exemplifying the connection structure of the semiconductor chip 10 and the conductor pattern 32A shown in FIG. 1 . However, for example, it can be applied to various parts connected via the solder alloy layer 40, such as the connection structure between the semiconductor chip 20 and the conductor pattern 32A, and the like.

As shown in FIG. 2 , the semiconductor device 100 includes a semiconductor wafer 10 , a conductor pattern 32A, a solder alloy layer 40 , and an intermetallic compound layer 50 . The semiconductor wafer 10 has an upper surface 10t and a lower surface 10b opposite to the upper surface 10t. The conductor pattern 32A includes metal (eg, Cu), and is connected to the lower surface 10b of the semiconductor wafer 10 via the solder alloy layer 40 . The intermetallic compound layer 50 is formed on the boundary between the lower surface 10b of the semiconductor wafer 10 and the solder alloy layer 40, and has a concavo-convex surface from the lower surface 10b side to the conductor pattern 32A side. As shown in FIG. 3 , the lower surface 10b of the semiconductor wafer 10 includes a region R1 including the center of the lower surface 10b and a region R2 including the outer periphery of the lower surface 10b. As shown in FIG. 2, the thickness of the intermetallic compound layer 50, the average thickness of the portion 50R1 overlapping the region R1 (refer to FIG. 3) of the lower surface 10b is thicker than the average thickness of the portion 50R2 overlapping the region R2 (refer to FIG. 3) .

After the failure mode of the connection portion is described using the semiconductor device 100C shown in FIG. 8 , the reason why the reliability of the connection portion is improved by the connection structure of the present embodiment shown in FIGS. 2 and 3 will be described. According to the study of the inventors of the present application, the failure modes causing the decrease in the connection reliability of the solder alloy layer 40 electrically connecting the semiconductor chip 10 and the conductor pattern 32A can be roughly classified into the following two types.

First, the failure mode is caused by thermal stress caused by the difference in the coefficient of linear expansion of each member constituting the periphery of the connecting portion. This first failure mode occurs in the outer peripheral portion (portion close to the side surface of the semiconductor wafer 10 ) of the solder alloy layer 40 and progresses toward the inner side of the solder alloy layer 40 , in other words, the central portion. When the crack CR1 occurs in the solder alloy layer 40 due to the first failure mode, it is likely to occur in the crack extending in the direction of the lower surface 10 b of the semiconductor wafer 10 . If repeated temperature cycle loads are applied, the crack CR1 extends toward the central portion.

Second, in the semiconductor chip 10, a failure mode is caused by the deterioration of the solder alloy layer 40 due to the heat generated at the time of energization. The second failure mode occurs in the central portion where the heat dissipation characteristics are relatively low. When the crack CR2 is generated in the second failure mode, the crack CR2 is likely to be generated in the thickness direction of the solder alloy layer 40 (in other words, the out-of-plane direction of the lower surface 10b). When repeated temperature cycle loads are applied, the generation site of the crack CR2 expands from the central portion toward the outer peripheral portion. In the case of the second failure mode, compared with the occurrence of the crack CR2 itself, the expansion of the generation range of the crack CR2 will lead to a decrease in the connection reliability.

In order to suppress the first failure mode, it is preferable to use a solder alloy with low elasticity. If the outer peripheral portion of the solder alloy layer 40 has low elasticity, the thermal stress can be relieved, and the occurrence of the crack CR1 at the origin or the progress of the crack CR1 after the occurrence of the crack CR1 can be suppressed. In order to suppress the second failure mode, it is preferable to use the solder alloy layer 40 with high heat resistance for the central portion. However, when different types of solder alloys are used, the mixing degree of the two types of solder alloys changes due to the conditions of the coating process or reflow soldering conditions, so it is difficult to stably form the two types of solder alloy layers at the designed positions. Connection reliability may decrease due to differences in manufacturing conditions. Therefore, the solder alloy layer 40 disposed between the semiconductor chip 10 and the conductor pattern 32A preferably includes one kind of solder alloy.

Therefore, the present inventors focused on providing a member at the connection interface of the central portion to prevent the expansion of the crack CR2 from the central portion toward the outer peripheral portion as a method for suppressing the second failure mode. As shown in FIG. 2 , in the case of the present embodiment, the portion 50R1 of the intermetallic compound layer 50 corresponds to a member that prevents the occurrence site of the crack CR2 from expanding from the central portion toward the outer peripheral portion.

The intermetallic compound layer 50 shown in FIG. 2 is a compound generated between the metal contained in the solder alloy layer 40 and the metal constituting the metallization film 11 formed on the lower surface 10 b of the semiconductor wafer 10 . For example, in the case of the present embodiment, the solder alloy of the solder alloy layer 40 contains copper (Cu) and antimony (Sb) in addition to tin (Sn), and contains 0.7% by weight or more of copper. In addition, a general lead-free solder may be used for the solder alloy constituting the solder alloy layer 40, but it is preferable to contain antimony and 0.7% by weight or more of copper. In addition, in consideration of improving the stress relaxation properties, Sn-3 to 5Cu-10Sb solder is particularly preferable. In addition, as a modification of the solder alloy, for example, Sn-3 to 7Cu solder can be used. Various metals and alloys such as Cu, Ni, Au, Ag, Pt, Pd, Ti, TiN, Fe-Ni, or Fe light alloys such as Fe-Co can be applied to the metallization film 11 of the semiconductor wafer 10 . For example, in the case of the present embodiment, the metallized film 11 contains nickel (Ni). In this case, the intermetallic compound layer is the metal of the main component of the solder alloy and the metallized film 11 , that is, the intermetallic compound layer of Ni—Sn.

The intermetallic compound layer 50 is formed by the reaction between the solder alloy and the metallized film 11 in the reflow process of mounting the semiconductor wafer 10 on the conductor pattern 32A. Therefore, the intermetallic compound layer 50 grows downward (towards the conductor pattern 32A) from the lower surface 10b of the semiconductor wafer 10, that is, the metallization film 11. At this time, the intermetallic compound layer 50 is formed non-uniformly, but as shown in FIG. 2 , is formed so as to form a concavo-convex surface from the lower surface 10b side to the conductor pattern 32A side. In the case where the height difference of the uneven surface is large, the expansion of the crack caused by the above-mentioned second failure mode to the outer peripheral side can be suppressed. That is, in the case of the present embodiment, by increasing the height difference of the uneven surface of the intermetallic compound layer 50, the expansion of the crack caused by the second failure mode to the outer peripheral side is suppressed.

On the other hand, the intermetallic compound layer 50 is vulnerable to external force in a direction orthogonal to its growth direction, and is easily damaged. Therefore, when the intermetallic compound layer 50 having the uneven surface with a large height difference is formed to the outer peripheral side of the lower surface 10b of the semiconductor wafer 10, the intermetallic compound layer 50 is caused by thermal stress as the first failure mode described above. damaged. Therefore, from the viewpoint of suppressing the first failure mode, it is preferable that the height difference of the uneven surface of the intermetallic compound layer 50 formed in the outer peripheral portion is small.

Therefore, in the case of the present embodiment, the intermetallic compound layer 50 is formed in the outer peripheral region so that the level difference of the uneven surface is reduced. Specifically, as shown in FIG. 3 , the lower surface 10b of the semiconductor wafer 10 includes a region R1 including the center of the lower surface 10b and a region R2 including the outer periphery of the lower surface 10b. As shown in FIG. 2 , the intermetallic compound layer 50 has a portion 50R1 overlapping with the region R1 (see FIG. 3 ) of the lower surface 10b and a portion 50R2 overlapping with the region R2 (see FIG. 3 ). The height difference of the uneven surface of the intermetallic compound layer 50 is greater than the height difference of the portion 50R1 of the lower surface 10b.

The height difference of the uneven surface of the intermetallic compound layer 50 can be formed as follows, for example. The height difference of the uneven surface of the intermetallic compound layer 50 increases in proportion to the time of the reflow process in a state where the solder alloy is in contact with the metallized film 11 . Therefore, in the reflow process, if the reflow process is managed as follows, the connection structure shown in FIG. 2 can be manufactured in a state where only the region R1 (refer to FIG. 3 ) of the lower surface 10b of the semiconductor chip 10 is in contact with the solder alloy Reflow soldering is started, and the solder alloy is brought into contact with the region R2 in the middle of the reflow soldering process. In the case of this method, first, a paste-like or flake-like solder alloy is applied (disposed) on the conductor pattern 32A. Next, the semiconductor wafer 10 is placed on the solder alloy in the form of paste or sheet. At this time, only the region R1 is in contact with the solder alloy, and the region R2 is not in contact with the solder alloy. Next, as a heating step, the solder alloy is heated. At this time, an intermetallic compound layer is generated at the connection interface between the solder alloy and the lower surface 10b of the semiconductor chip 10 and grows toward the conductor pattern 32A. Next, the distance between the semiconductor wafer 10 and the conductor pattern 32 is brought closer. Thereby, the molten solder spreads around, and the area|region R2 (refer FIG. 3) comes into contact with the solder alloy. If it is heated again in this state, as shown in FIG. 2, the intermetallic compound layer 50 whose height difference is controlled for each part can be obtained.

In this case, the height difference of the concave-convex surface can be expressed as the average thickness of the portion 50R1 (the average value of the distances from the lower surface 10b to the apexes of a plurality of convex portions of the concave-convex surface) and the average thickness of the portion 50R2. That is, as described above, the thickness of the intermetallic compound layer 50, the average thickness of the portion 50R1 overlapping the region R1 (refer to FIG. 3 ) of the lower surface 10b is thicker than the average thickness of the portion 50R2 overlapping the region R2 (refer to FIG. 3 ) . In this case, in the portion 50R1 having a relatively thick average thickness, the height difference of the uneven surface is increased, and in the portion 50R2 having a relatively thin average thickness, the height difference of the uneven surface is decreased.

In addition, as a modification of the formation method of the intermetallic compound layer 50, the following method also exists. That is, in the region R1 (refer to FIG. 3 ) of the lower surface 10b, a metal film having a concavo-convex shape formed so that the height difference of the intermetallic compound layer 50 increases is formed in advance. This metal film can be formed by, for example, a plating method. If a metal film having irregularities is selectively formed in the region R1 by the plating method in a state where the region R2 (see FIG. 3 ) is used as a mask, even in the reflow process, the solder alloy is brought into contact with the When the reflow is started in the state of the entire lower surface 10b, as shown in FIG. 2, the height difference of the intermetallic compound layer 50 can also be controlled.

In the case of the semiconductor device 100 of the present embodiment, as described above, since the height difference (in other words, the average thickness) of the uneven surface is formed so that the portion 50R1 and the portion 50R2 are different, the first failure mode and the second failure mode described above can be suppressed. Various failure modes. Moreover, since the solder alloy layer 40 contains one kind of solder alloy, the connection structure shown in FIG. 2 can be stably realized. As a result, the connection reliability at the connection interface between the lower surface 10b of the semiconductor chip 10 and the solder alloy layer 40 can be improved.

In addition, since the solder alloy layer 40 connects the semiconductor chip 10 and the conductor pattern 32A, it is preferable to form an intermetallic compound layer similar to the intermetallic compound layer 50 on the conductor pattern 32A side in addition to the lower surface 10b side of the semiconductor chip 10 60. In the case of the present embodiment, as shown in FIG. 2 , the conductor pattern 32A is provided on the upper surface 32t facing the entire lower surface 10b when the semiconductor wafer 10 is viewed in plan view from the upper surface 10t. On the boundary between the upper surface 32t of the conductor pattern 32A and the solder alloy layer 40, an intermetallic compound layer 60 having a concavo-convex surface from the upper surface 32t side to the semiconductor wafer 10 side is formed. As for the thickness of the intermetallic compound layer 60, the average thickness of the portion 60R1 overlapping with the region R1 (see FIG. 3 ) of the lower surface 10b is thicker than the average thickness of the portion 60R2 overlapping with the region R2 (see FIG. 3 ).

The intermetallic compound layer 60 shown in FIG. 2 may behave as follows. The intermetallic compound layer 60 has a portion 60R1 overlapping with the region R1 (see FIG. 3 ) of the lower surface 10b and a portion 60R2 overlapping with the region R2 (see FIG. 3 ). The height difference of the uneven surface of the intermetallic compound layer 60 is that the height difference of the part 60R1 of the lower surface 10b is larger than the height difference of the part 60R2. Thereby, the connection interface on the lower surface side of the solder alloy layer 40, in other words, the connection interface between the solder alloy layer 40 and the conductor pattern 32, can improve the connection reliability.

In addition, in the outer peripheral portion of the solder alloy layer 40, in order to improve the stress relief function of the solder alloy layer 40, it is preferable to increase the thickness of the solder alloy layer 40 in the outer peripheral portion. As shown in FIG. 4, the thickness of the solder alloy layer 40, the average thickness T2 of the portion 40R2 overlapping the region R2 (refer to FIG. 3) of the lower surface 10b is thicker than the average thickness T2 of the portion 40R1 overlapping the region R1 (refer to FIG. 3) T1. In the case of this embodiment, by forming the average thickness of the intermetallic compound layers 50 and 60 as described above, the average thickness of the solder alloy layer 40 can be controlled. 4 is an enlarged cross-sectional view of the same cross-section as in FIG. 2, but is described as a separate drawing in order to make the symbols easier to see.

However, within the range of the region R1 and the region R2 shown in FIG. 3 , there are various embodiments. Hereinafter, a preferred aspect from the viewpoint of improving connection reliability will be described. First, the region R1 and the region R2 are adjacent to each other. The region R1 can be defined as the region R1 at the portion of the lower surface 10b that is in contact with the raw material of the solder alloy layer 40 , that is, the solder alloy in the form of paste or sheet, at the start of the reflow process. The region R2 is the portion around the region R1, and can be defined as a region that is in contact by spreading of the paste or flake-like solder alloy after the reflow process is started. When the thickness (height difference) of the intermetallic compound layers 50 and 60 is controlled by the contact time in the reflow process, strictly speaking, since the solder alloy gradually diffuses from the central part to the outer peripheral part, in the vicinity of the region R1, There is a region where the thickness of the intermetallic compound layers 50 and 60 is thicker than the outermost periphery of the region R2. In this case, the area is considered to belong to the area R2. In addition, as a modification example, when a metal film having an uneven surface is selectively formed in the region R1, the region where the metal film is formed can be defined as the region R1, and the surrounding region can be defined as the region R2.

In the above definition, in order to suppress the damage of the intermetallic compound layers 50 and 60 (refer to FIG. 2 ), it is preferable that the range of the region R1 is not too large. Specifically, it is preferable that the region R2 is provided so as to surround the region R1, and the area of the region R2 is larger than the area of the region R1. By making the area of the region R2 larger than the area of the region R1 , the portion 50R1 of the intermetallic compound layer 50 and the portion 60R1 of the intermetallic compound layer 60 having a large height difference can be prevented from being damaged by thermal stress.

Ideally, the contour of the region R1 is preferably a circle or an ellipse. When the shape of the lower surface 10b is a square, it is preferably a circle. Moreover, when the shape of the lower surface 10b is a rectangle, it is preferable that it is an ellipse which has a long diameter in the direction along a long side. In addition, when a vertical line (imaginary line) is drawn from the center of the lower surface 10b toward each side of the lower surface 10b, the region R1 is preferably arranged between a circle or an ellipse passing through 80% of the center side of the entire length of the vertical line. inside.

In the above definition, the diameter length D1 when the region R1 shown in FIG. 3 is converted to a circle is preferably 1/3 or more of the length L1 of one side when the lower surface 10b is converted to a square. By increasing the area of the region R1, the expansion of the crack CR2 shown in FIG. 8 can be suppressed even when the portion where the crack CR2 is generated is deviated from the center. In addition, as will be described later, the shape of the region R1 is not limited to a circle, and the shape of the lower surface 10b is not limited to a square. Evaluate.

In addition, from the viewpoint of suppressing the above-mentioned first failure mode and second failure mode, the thickness of the intermetallic compound layer 50 is particularly preferred, and the average thickness of the portion 50R1 is three times or more the average thickness of the portion 50R2. Likewise, the thickness of the intermetallic compound layer 60 is preferably, and the average thickness of the portion 60R1 is 3 times or more the average thickness of the portion 60R2.

<Variation 1> Next, a modification of the connection structure of the semiconductor device 100 shown in FIG. 2 will be described. FIG. 5 is a plan view of the lower surface side of a semiconductor wafer included in a semiconductor device, which is a modification of FIG. 3 . This variation is a technique effective in the case where a plurality of semiconductor chips are arranged close to each other. In addition, the semiconductor device 200 described below is the same as the semiconductor device 100 described above except that the positional relationship of the regions in the lower surfaces of the semiconductor wafers 10 and 20 is different from that in FIG. 3 . In the following description, it demonstrates with reference to FIGS. 1-4 as needed.

As shown in FIG. 5 , like the semiconductor device 100 shown in FIG. 1 , the semiconductor device 200 has a semiconductor wafer 20 mounted in the vicinity of the semiconductor wafer 10 in a plan view. The lower surface 10b of the semiconductor wafer 10 is in the shape of a quadrangle, and the quadrangle has a side 10s1 opposite to the semiconductor wafer 20, a side 10s2 on the opposite side of the side 10s1, a side 10s3 intersecting with the side 10s1 and the side 10s2, and a side 10s4 on the opposite side of the side 10s3 . The region R1 is disposed at a position closer to the side 10s1 than the side 10s2. In other words, the region R1 is arranged close to the semiconductor wafer 20 .

In the case where a plurality of semiconductor chips are arranged adjacently as in the semiconductor chips 10 and 20, compared with the case where a single semiconductor chip 10 is arranged alone, the place where the temperature tends to become high in the surface of the lower surface 10b is changed. . The fact that the outer peripheral region of the semiconductor wafer 10 is easier to dissipate heat than the central region remains unchanged. However, in the central region, a region close to the side 10s1 (in other words, a region close to the semiconductor wafer 20 ) tends to have a higher temperature than a region close to the side 10s2 (in other words, a region farther from the semiconductor wafer 20 ). It is considered that this is because the heat dissipation characteristic is lowered due to the presence of another heat source, that is, the semiconductor wafer 20 on the side 10s1. As in the present embodiment, when the region R1 is provided at a position closer to the side 10s1 than the side 10s2, it is equivalent to providing the region R1 at a site where the crack CR2 described with reference to FIG. 8 is likely to occur. In this way, in the case of a semiconductor device including a plurality of semiconductor chips, it is preferable to define the layout of the region R1 in consideration of the heat distribution accompanying the positional relationship of the plurality of semiconductor chips. As a result, the expansion of the site where the crack CR2 occurs can be effectively suppressed.

However, from the viewpoint of suppressing the progress of the crack CR1 (refer to FIG. 8 ) caused by the above-mentioned first failure mode, it is preferable that the range of the region R1 is not extremely close to the side 10s1 side. Ideally, when a vertical line (imaginary line) is drawn from the center of the lower surface 10b to each side (sides 10s1, 10s2, 10s3, and 10s4) of the lower surface 10b, the region R1 is preferably arranged to pass through the entire length of the vertical line The inside of a circle or ellipse that is 80% of the center side of the center.

In addition, in FIG. 5, the example in which the number of semiconductor wafers is 2 has been illustrated, but the number of semiconductor wafers is not limited to two. For example, in the case of the semiconductor device 200 shown in FIG. 6, six semiconductor wafers (semiconductor wafers 10, 20, 10A, 20A, 10B, and 20B) are provided. FIG. 6 is a top view of a conductor pattern on which the semiconductor chip shown in FIG. 1 is mounted. FIG. 6 is a plan view from the upper surface side of the semiconductor wafer, but shows the extent of the regions R1 and R2 of the lower surface. Alternatively, although illustration is omitted, there are cases where four semiconductor wafers are mounted adjacent to each other in one semiconductor device. In this way, when a plurality of semiconductor chips are mounted adjacent to each other, the position of the region R1 is preferably arranged close to the adjacent semiconductor chips. In addition, there is also the following situation: when the semiconductor chips 10 and 10B are arranged on two adjacent sides like the semiconductor chip 10A shown in FIG. area. Compared with the semiconductor chips 10 and 10B, the semiconductor chip 10A is mounted in a position where heat dissipation is more difficult, but by enlarging the area of the central region (region R1 ), the occurrence of the second failure mode described above can be suppressed.

<Variation 2> FIG. 7 is an enlarged cross-sectional view of the periphery of a semiconductor wafer provided in a semiconductor device, which is a modification of FIG. 2 . In this modification, the embodiment in which the solder alloy layers are connected to the upper surface and the lower surface of one semiconductor wafer will be described.

The semiconductor device 300 is different from the semiconductor device 100 shown in FIG. 2 in that, in the structure of the semiconductor device 100 described using FIG. 2 , the electrode pad 12 on the upper surface 10t side is connected to the conductor pattern 80 via the solder alloy layer 70 . . Since other points are the same as those of the semiconductor device 100 shown in FIG. 2 , repeated descriptions are omitted.

The semiconductor device 300 includes a conductor pattern (second wafer connection portion) 80 including metal and connected to the upper surface 10 t of the semiconductor wafer 10 via a solder alloy layer 70 , and a solder alloy layer 70 disposed on the upper surface of the semiconductor wafer 10 . between 10t and the conductor pattern 80 .

Further, the semiconductor device 300 includes the intermetallic compound layer 55 formed on the upper surface 10t of the semiconductor wafer 10 and the boundary between the solder alloy layer 70 and the concavo-convex surface from the upper surface 10t side to the conductor pattern 80 side. As for the thickness of the intermetallic compound layer 55, the average thickness of the portion 55R1 overlapping the region R1 (see FIG. 3 ) of the lower surface 10b is thicker than the average thickness of the portion 55R2 overlapping the region R2 (see FIG. 3 ).

The structure of the intermetallic compound layer 55 can also be expressed as follows. That is, the intermetallic compound layer 55 has a portion 55R1 overlapping with the region R1 (see FIG. 3 ) of the lower surface 10b and a portion 55R2 overlapping with the region R2 (see FIG. 3 ). The height difference of the uneven surface of the intermetallic compound layer 55 is that the height difference of the part 55R1 of the lower surface 10b is larger than the height difference of the part 55R2. When the solder alloy layer 70 is connected to the upper surface 10t side of the semiconductor chip 10 , the connection reliability of the connection interface between the solder alloy layer 70 and the electrode pad 12 of the semiconductor chip 10 can be improved by the configuration of this modification.

Similarly, the semiconductor device 300 has the intermetallic compound layer 65 formed on the lower surface 80b of the conductor pattern 80 and the boundary between the solder alloy layer 70 and having a layer extending from the lower surface 80b side to the upper surface 10t side of the semiconductor wafer 10 Concave and convex surface. Further, the intermetallic compound layer 65 has a portion 65R1 overlapping with the region R1 (see FIG. 3 ) of the lower surface 10b and a portion 65R2 overlapping with the region R2 (see FIG. 3 ). The height difference of the uneven surface of the intermetallic compound layer 65 is that the height difference of the part 65R1 of the lower surface 10b is larger than the height difference of the part 65R2. The connection reliability of the connection interface between the solder alloy layer 70 and the conductor pattern 80 can be improved by the configuration of the modified example.

In addition, although the conductor pattern 80 is mentioned as an example connected to the chip connection part of the semiconductor chip 10 via the solder alloy layer 70, it is effective also when mounting components, such as a heat sink, for example. In the case of the heat dissipation plate, the heat path is broken due to the generation and progression of the crack CR1 or the crack CR2 described in FIG. 8 , so that the heat dissipation characteristic is lowered. By applying the above-described structure, it is possible to suppress a decrease in heat dissipation. In addition, although illustration is abbreviate|omitted, for example, there exists a case where a conductor pattern is connected to the upper surface and the lower surface of each of a plurality of semiconductor chips shown in FIG. 6. FIG.

In addition, although various modification examples have been described above, it is also possible to apply each modification example in an appropriate combination.

The representative modifications of the present embodiment have been described above, but the present invention is not limited to the above-described embodiments or representative modifications, and various modifications can be applied without departing from the gist of the invention. [Industrial Availability]

The present invention can be used in optical devices.

2: Solder alloy layer 3: base plate 4: Cover 5: Sealing material 6: Wire 7: Pin 10: Semiconductor wafers (semiconductor components) 10A: Semiconductor wafer (semiconductor element) 10B: Semiconductor wafer (semiconductor element) 10b: Lower surface (back surface) 10s1: Side 10s2: Side 10s3: Side 10s4: Side 10t: upper surface (front) 11: Metallized film 12: Electrode pads 20: Semiconductor wafers (semiconductor components) 20A: Semiconductor wafer (semiconductor element) 20B: Semiconductor wafers (semiconductor components) 30: Substrate 31: Insulating substrate 31b: lower surface 31t: upper surface 32: Conductor pattern 32A: Conductor pattern 32B: Conductor pattern 32C: Conductor Pattern 32t: upper surface 33: Conductor pattern 40: Solder alloy layer 40R1: Parts 40R2: Parts 50: Intermetallic compounds 50R1: Parts 50R2: Parts 55: Intermetallic compounds 55R1: Parts 55R2: Parts 60: Intermetallic compounds 60R1: Parts 60R2: Parts 65: Intermetallic compounds 65R1: Parts 65R2: Parts 70: Solder alloy layer 80: Conductor pattern (second chip connection part) 80b: lower surface 100: Semiconductor Devices 100C: Semiconductor device 200: Semiconductor Devices 300: Semiconductor Devices CR1: Cracking CR2: Cracking D1: Diameter length L1: length R1: Area (Central Area) R2: (peripheral area) T1: Average thickness T2: Average thickness

FIG. 1 is an explanatory diagram schematically showing a configuration example of a semiconductor device according to an embodiment. FIG. 2 is an enlarged cross-sectional view showing an enlarged periphery of a solder alloy layer electrically connecting one of the plurality of semiconductor chips shown in FIG. 1 and the conductor pattern. FIG. 3 is a top view of the lower surface side of the semiconductor wafer shown in FIG. 2 . FIG. 4 is an enlarged cross-sectional view for comparing the thickness range of the solder alloy layer in the same enlarged cross-section as in FIG. 2 . FIG. 5 is a plan view of the lower surface side of a semiconductor wafer included in a semiconductor device, which is a modification of FIG. 3 . FIG. 6 is a plan view of the conductor pattern on which the semiconductor chip shown in FIG. 1 is mounted. FIG. 7 is an enlarged cross-sectional view of the periphery of a semiconductor wafer provided in a semiconductor device, which is a modification of FIG. 2 . FIG. 8 is an enlarged cross-sectional view schematically showing the type of cracks generated in the connection structure of the semiconductor device as the study example of FIG. 2 .

10: Semiconductor wafers (semiconductor components)

10b: Lower surface (back surface)

10t: upper surface (front)

11: Metallized film

12: Electrode pads

30: Substrate

31: Insulating substrate

32: Conductor pattern

32A: Conductor pattern

32t: upper surface

33: Conductor pattern

40: Solder alloy layer

50: Intermetallic compounds

50R1: Parts

50R2: Parts

60: Intermetallic compounds

60R1: Parts

60R2: Parts

100: Semiconductor Devices

Claims (10)

A semiconductor device comprising: a first semiconductor wafer having a first surface and a second surface opposite to the first surface; and a first chip connecting portion including a metal and connected to the first surface via a first solder alloy layer The second surface of the semiconductor wafer is connected; the first solder alloy layer is disposed between the second surface of the first semiconductor wafer and the connection portion of the first wafer; and the first intermetallic compound layer is formed The boundary between the second surface of the first semiconductor chip and the first solder alloy layer is provided with a concavo-convex surface from the second surface side to the first chip connecting portion side; and the second surface includes the The thickness of the first region in the center of the second surface and the second region including the outer periphery of the second surface, the thickness of the first intermetallic compound layer, and the average thickness of the first portion overlapping the first region of the second surface Thicker than the average thickness of the second portion overlapping the above-mentioned second region. The semiconductor device according to claim 1, wherein the first chip connecting portion includes a third surface that faces the entirety of the second surface when viewed from the first surface side in a plan view of the first semiconductor chip. ; On the boundary between the third surface of the first chip connection portion and the first solder alloy layer, a second intermetallic compound layer having a concave and convex surface from the third surface side to the first semiconductor chip side is formed , the thickness of the above-mentioned second intermetallic compound layer, the thickness of the third layer overlapping the first region of the above-mentioned second surface The average thickness of the part is thicker than the average thickness of the fourth part overlapping the above-mentioned second region. The semiconductor device of claim 2, wherein the thickness of the first solder alloy layer, the average thickness of the fifth portion overlapping the second region of the second surface is thicker than the average thickness of the sixth portion overlapping the first region . The semiconductor device of claim 3, wherein the area of the second region is larger than the area of the first region. The semiconductor device of claim 4, wherein the first region and the second region are adjacent to each other, and the length of the diameter when the first region is converted to a circle with respect to the length of one side when the second surface is converted to a square The length is 1/3 or more. The semiconductor device of claim 1, wherein the average thickness of the first portion overlapping the first region of the second surface is three times or more the average thickness of the second portion overlapping the second region. The semiconductor device of claim 1, wherein the first solder alloy layer contains copper (Cu) and antimony (Sb) in addition to tin (Sn), and contains 0.7% by weight or more of copper. The semiconductor device of claim 1, further having: A second semiconductor wafer mounted near the first semiconductor wafer in a plan view, and the second surface of the first semiconductor wafer has a quadrangular shape, and the quadrangular shape includes a first side facing the second semiconductor wafer and the first side The second side on the opposite side, the third side intersecting the first side and the second side, and the fourth side on the opposite side of the third side, the first area is provided closer to the first side than the second side. 1 side position. The semiconductor device according to claim 1, further comprising: a second chip connecting portion comprising metal and connected to the first surface of the first semiconductor chip via a second solder alloy layer; and the second solder alloy layer arranged between the first surface of the first semiconductor wafer and the connecting portion of the second wafer; and a third intermetallic compound layer formed on the first surface of the first semiconductor wafer and the second solder alloy The boundary of the layer has a concave-convex surface from the first surface side to the second chip connecting portion side; the thickness of the third intermetallic compound layer is the average of the third portion overlapping the first region of the second surface. Thickness is thicker than the average thickness of the 4th part which overlaps with the said 2nd area. A semiconductor device comprising: a first semiconductor wafer having a first surface and a second surface opposite to the first surface; and a first chip connecting portion including a metal and connected to the first surface via a first solder alloy layer The second surface of the semiconductor chip is connected; the first solder alloy layer is disposed between the second surface of the first semiconductor chip and the connection portion of the first chip; and The first intermetallic compound layer is formed on the boundary between the second surface of the first semiconductor wafer and the first solder alloy layer, and has a concavo-convex surface from the second surface side to the first wafer connection portion side. and the second surface includes a first region including the center of the second surface, and a second region including the outer periphery of the second surface, and the first intermetallic compound layer has an overlap with the first region of the second surface. The first part and the second part overlapping the second area, the height difference of the uneven surface in the first part is larger than the height difference of the uneven surface in the second part.

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