TWI760760B - Computer program product and method and apparatus for controlling access to flash storage - Google Patents

Abstract

A method for controlling access to a flash storage, performed by a processing unit of a bridge Integrated Circuit (IC), is introduced to include: receive a host write command from a host side; determine whether a flash storage needs to enter a hibernate state according to information indicating how much data has been programmed into a flash storage and/or how many host write commands have been executed after the host write command is executed; and direct the flash storage to enter the hibernate state when the information satisfies a triggering condition. The aforementioned control mechanism prevents the flash storage from being crashed due to over-heat when numerous data write operations are performed.

Description

Computer program product and method and apparatus for controlling access to flash memory devices

The present invention relates to a storage device, in particular to a computer program product, method and device for controlling access to a flash memory device.

A Universal Serial Bus (USB) memory disk is a data storage device that includes a flash memory integrated with a USB interface, and is usually unloadable, rewritable, and small. Storage capacity can vary from 16 gigabytes (Gigabytes, GB) to 1 terabytes (Terabytes, TB). USB memory disks are usually used for computer file storage, data backup, etc. However, as the data access speed of the flash memory increases, the temperature of the USB memory disk may be higher than the allowable operating range, resulting in unexpected errors in the execution of read or write commands. Therefore, the present invention provides a computer program product, method and apparatus for controlling access to a flash memory device, which are used to solve the above-mentioned problems.

In view of this, how to alleviate or eliminate the above-mentioned deficiencies in related fields is a problem to be solved.

This specification relates to a computer program product for controlling access to a flash memory device, including program codes loaded and executed by a processing unit of a bridge integrated circuit, for: receiving a host write command from a host; After the command, determine whether the flash memory device needs to enter the dormant state according to the information of how many lengths of data have been written to the flash memory device and/or how many host write commands have been executed; and when the above length and/or number meet the trigger conditions, Instructs the flash device to enter hibernation.

The present specification also relates to a method for controlling access to a flash memory device, executed by a processing unit of a bridge integrated circuit, comprising: receiving a host write command from a host; The flash memory device and/or the information of how many host write commands have been executed to determine whether the flash memory device needs to enter the sleep state; and when the above length and/or number satisfy the trigger condition, the flash memory device is instructed to enter the sleep state.

The present specification further relates to a device for controlling access to a flash memory device, comprising: a host interface coupled to a host; a device interface coupled to the flash memory device; and a processing unit coupled to the host interface and the device interface. The processing unit receives the host write command from the host side through the host interface; after executing the host write command, it judges the flash memory device according to how much data has been written to the flash memory device and/or how many host write commands have been executed. Whether it is necessary to enter the sleep state; and when the above-mentioned length and/or quantity satisfy the trigger condition, instruct the flash memory device to enter the sleep state through the device interface.

One of the advantages of the above-mentioned embodiments is to avoid device failure caused by overheating of the flash memory device due to a large number of data writing operations through the control mechanism shown above.

Other advantages of the present invention will be explained in more detail in conjunction with the following description and drawings.

110: computer host

115:USB port

130:USB memory disk

210, 310: USB connectors

230,330: Motherboard

250: Bridge IC

260: card slot

270: flash card

280: Flash Controller

370: Flash memory

410: Flash Module

430: CPU

510: Bus Architecture

530: Processing Unit

550:RAM

570: Host Interface

580: Device Interface

S610~S690: Method steps

FIG. 1 is a schematic diagram of the use of a universal serial bus memory disk according to an embodiment of the present invention.

2A and 2B are schematic diagrams of the appearance of a general-purpose serial bus memory disk according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of the appearance of a general-purpose serial bus memory disk according to an embodiment of the present invention.

4 is a block diagram of a host side and a general purpose serial bus memory disk according to an embodiment of the present invention.

5 is a block diagram of a bridge IC and external components according to an embodiment of the present invention.

FIG. 6 is a flowchart of a method for controlling access to a flash memory device according to an embodiment of the present invention.

The following descriptions are preferred implementations for accomplishing the invention, and their purpose is to describe the basis of the invention. the spirit of the present invention, but is not intended to limit the present invention. Reference must be made to the scope of the following claims for the actual inventive content.

It must be understood that the words "comprising" and "including" used in this specification are used to indicate the existence of specific technical features, values, method steps, operation processes, elements and/or components, but do not exclude the possibility of adding More technical features, values, method steps, job processes, elements, components, or any combination of the above.

The use of words such as "first", "second", "third", etc. in the claims is used to modify the elements in the claims, and is not used to indicate that there is a priority order, a preceding relationship between them, or an element Prior to another element, or chronological order in which method steps are performed, is only used to distinguish elements with the same name.

It must be understood that when an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, and intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements can also be read in a similar fashion, such as "between" versus "directly interposed," or "adjacent" versus "directly adjoining," and the like.

Refer to Figure 1. After the user inserts the Universal Serial Bus (USB) memory drive (USB Memory Drive) 130 into the USB port 115 of the computer host 110, the user can back up data from the storage device in the computer host 110 to the USB memory drive 130, and copy the data to the USB memory drive 130. The data in the USB memory disk 130 is transferred to the storage device in the computer host 110, or other data access operations are performed. The USB memory disk 130 contains a high-capacity NAND flash memory card, which can vary from 16 Gigabytes (GB) to 1 Terabytes (TB). With the increase of access speed, NAND flash memory cards tend to heat up during data access. However, for the convenience of portability, the USB memory disk 130 is made as small as possible, which makes it difficult to dissipate heat. As a result, the NAND flash memory card may cause unexpected errors in data access due to high temperature, and even make the NAND flash memory card invalid. The failure of the NAND flash memory card may cause the computer host 110 to fail to receive a response from the USB memory disk 130 during data access. It should be mistakenly assumed that the USB memory disk 130 is damaged. Although the embodiments of the present invention describe a USB interface connected to the computer host 110 as an example, those skilled in the art can also apply to a memory disk connected to the computer host 110 using other interfaces, such as IEEE1394, etc., the present invention is not limited thereto. In other embodiments, those skilled in the art can alternatively implement the computer host 110 as an electronic product such as a laptop computer (Laptop PC), a tablet computer, a mobile phone, a digital camera, a digital video camera, etc., and the present invention is not limited thereto.

In order to solve the above problems, in some embodiments, a temperature monitoring integrated circuit (IC) may be added to the USB memory disk 130 to detect the temperature of the USB memory disk 130 during data access. And, when the temperature exceeds a threshold, an operation to avoid failure of the flash memory device is performed.

However, adding a temperature monitoring IC increases the cost of the USB memory stick. Therefore, an embodiment of the present invention proposes a technical solution, which is applied to a USB memory disk without a temperature monitoring integrated circuit. Since the data writing operation requires a large amount of power, the temperature of the USB memory disk 130 is likely to rise. Therefore, the embodiment of the present invention supervises the data writing operation that has been performed in the past, and when the data writing operation reaches a preset condition, executes the Avoid operations where NAND flash cards fail.

Refer to Figure 2A. In some embodiments, the USB memory disk 130 includes a USB connector 210 and a rectangular motherboard 230 , and one end of the motherboard 230 is connected to the USB connector 210 . A bridge integrated circuit (Bridge IC) 250 is disposed on one side of the motherboard 230 , and the bridge IC 250 is coupled to the USB connector 210 through the circuit in the motherboard 230 . Referring to FIG. 2B , a card slot 260 is provided on the other side of the motherboard 230 , and a flash memory card 270 can be placed in the card slot 260 and coupled to the bridge IC 250 through a circuit in the motherboard 230 . The flash memory card 270 includes a flash memory controller 280 and a flash memory module. Generally, when the size of the motherboard 230 is smaller than 3 cm by 2 cm, it is difficult to dissipate heat.

Refer to Figure 3. The USB memory disk 130 includes a USB connector 310 and a motherboard 330 with two rectangular corners on the same side cut off. The narrow end of the motherboard 330 is connected to the USB connector 310 . One side of the motherboard 330 is provided with a bridge integrated circuit 250 and a flash memory (Flash Memory) 370 , and the bridge IC 250 is coupled to the USB connector 310 and the flash memory 370 through the circuit in the motherboard 330 . flash The memory 370 is packaged in a Ball Grid Array (BGA), and includes the flash memory controller 280 and the flash memory module.

The flash memory card 270 and the flash memory 370 may be collectively referred to as a flash memory device (Flash Storage), and other types of NAND flash memory may be configured in the USB memory disk 130 as a flash memory device, and the present invention is not limited thereto.

Refer to Figure 4. The computer host (hereinafter referred to as the host side) 110 includes the central processing unit 430 , and the USB memory disk (hereinafter referred to as the memory disk) 130 includes the bridge IC 250 . The flash card 270 or flash memory 370 includes a flash controller 280 and a flash module 410 . In one aspect, the bridge IC 250 plays the role of the device end of the CPU 330, and can communicate with the CPU 430 through the USB communication protocol. On the other hand, the bridge IC 250 plays the role of the host side of the flash memory card 270 or the flash memory 370 , which can be used for peripheral component interconnect express (PCI-E), Universal Flash Storage (Universal Flash Storage) Interfaces such as UFS) and Embedded Multi-Media Card (eMMC) communicate with the flash memory controller 280 . The flash memory controller 280 and the flash memory module 410 can communicate with each other through a Double Data Rate DDR protocol, such as Open NAND Flash Interface ONFI, DDR Toggle or others communication protocol. The central processing unit 430 can be implemented using a variety of ways, such as using general-purpose hardware (eg, a single processor, multiple processors with parallel processing capabilities, graphics processors, or other processors with computing capabilities), and execute software and/or or firmware commands, provide the functions described later.

Refer to Figure 5. The bridge IC 250 includes a processing unit 530 , a random access memory (RAM) 550 , a host interface 570 , and a device interface 580 , and these elements 530 , 550 , 570 and 580 are connected to each other by a bus architecture 510 coupled. The bus structure 510 is used to allow data, addresses, control signals, etc. to be communicated between the components 530 , 550 , 570 and 580 . The processing unit 530 may be implemented using a variety of ways, such as using general purpose hardware (eg, a single processor, multiprocessing with parallel processing capabilities) computer, graphics processor, or other processor with computing capabilities), and when executing software and/or firmware instructions, provide the functions described later. The processing unit 530 receives host commands, such as Read Command, Write Command, Erase Command, etc., from the host terminal 110 through the host interface 570, and schedules and executes these commands. The RAM 550 can be implemented as a dynamic random access memory (DRAM), a static random access memory (SRAM), or a combination of the two, and is used to configure the space as a data buffer. Store user data (also called host data) read from the host 110 and to be written to the flash card 270 or flash memory 370, and read from the flash card 270 or flash memory 370 and output to the host 110 user data. The RAM 550 can also store data required in the execution process, such as variables, data tables, and the like.

The flash memory module 410 provides a large amount of storage space, usually hundreds of GB, or even several TB, for storing a large amount of user data, such as high-resolution pictures, videos, and the like. The flash memory module 410 includes a control circuit and a memory array, and the memory cells in the memory array may include single-level cells (Single Level Cells, SLCs), multi-level cells (Multiple Level Cells, MLCs), triple-level cells (Triple Level Cells, MLCs) Level Cells, TLCs), Quad-Level Cells (Quad-Level Cells, QLCs), or any combination of the above. The processing unit 530 communicates with the flash memory controller 280 through the device interface 580, and is used for writing user data of a designated logical location and reading user data of a designated logical location. The logical location may be a logical block address (Logical Block Address, LBA) said.

In order to solve the above-mentioned problems, an embodiment of the present invention provides a method for controlling access to a flash memory device, which is implemented when the processing unit 530 loads and executes relevant firmware or software instructions, so as to reduce the time for the flash memory device to execute a host write command. possibility of overheating. After executing the host write command, it is determined whether the flash memory device needs to be entered according to the information of how much data has been written to the flash memory device and/or how many host write commands have been executed. Hibernate State. When the above information satisfies the triggering condition, the flash memory device is instructed to enter the sleep state, so that the flash memory device can be cooled down and avoid failure. After that, when the next command comes in, the flash device is woken up again. Applying the algorithm of the present invention to the USB memory disk 130 will not make the user feel much difference in performance, but can greatly reduce the risk of being stuck due to excessive temperature. Referring to FIG. 6 , the detailed steps are described as follows: Step S610 : Set trigger conditions regarding the length of the written data and the executed host write command. In general, the trigger conditions can be set to the current host write command requesting the writing of n-k bytes or more of data, and the cumulative processing of m requests for the writing of n-k bytes or more of data. Host write commands, where m and n are integers greater than 0. The variables "n" and "m" may be changed to reflect the capacity of the flash memory device or the size of the USB memory disk 130. In some embodiments, the variable "n" is set to 96 and the variable "m" is set to any integer from 4 to 7. In other embodiments, the variable "n" is set to 32 and the variable "m" is set to any integer from 15 to 25. The processing unit 530 may store the variables "n" and "m" in the RAM 550 as preset values. In addition, the processing unit 530 may maintain a count value "cmd_count" in the RAM 550 for recording how many host write commands requesting to write n-k bytes or more have been accumulated and processed, and is initially zero.

Step S620 : Receive a write command (also referred to as a host write command) from the host terminal 110 through the host interface 570 .

Step S630: Determine whether the flash memory device enters a sleep state. If yes, the process of step S650 is performed. Otherwise, the process of step S660 is performed. The processing unit 530 may maintain a Status Flag in the RAM 550 for recording information about whether the flash memory device enters the sleep state. For example, whenever the processing unit 530 instructs the flash controller 280 through the device interface 580 to put the flash memory device into a hibernation state, the status flag is set to "1". Whenever the processing unit 530 instructs the flash controller 280 through the device interface 580 to wake up the flash device, the status flag is set to "0". The processing unit 530 can detect the value of the status flag to complete the determination in step S630. It should be noted here that when the host side 110 enters the S3/S4 state, the bridging IC 250 is also used to instruct the flash memory device to enter the sleep state.

Step S650: Wake up the flash memory device. The processing unit 530 may issue a series of instructions to the flash memory controller 280 through the device interface 580 to request the flash memory device to leave the hibernate state (Un-hibernate). For example, the technical details of leaving the sleep state can be found in Section 9.5.2 of the UniPro Standard Version 1.8 "Specification for UniPro Version 1.8" published on September 13, 2017. When the flash memory device successfully leaves the hibernation state, the processing unit 530 changes the status flag in the RAM 550 to "0".

Step S660: Instruct the flash memory device to execute the write command. The processing unit 530 can send an instruction to the flash memory controller 280 through the device interface 580 to request data to be written at a specific logical block address. If the length of the written data is equal to or greater than n-k bytes, the processing unit 530 increments the count value "cmd_count" in the RAM 550 by one.

Step S670: Determine whether the trigger condition is satisfied. If yes, the process of step S690 is performed. Otherwise, the process of step S680 is performed. The processing unit 530 can detect whether the count value "cmd_count" is equal to or greater than the variable "m". When the count value "cmd_count" is equal to or greater than the variable "m", it means that the trigger condition is satisfied.

Step S680: Let the flash memory device stay in an idle state (Idle State). When the flash memory device finishes executing the write command and there is no background operation to be performed, it will automatically enter an idle state, waiting for the entry of the next command or the start of the background operation. That is, in step S680, the processing unit 530 does not issue an instruction to the flash memory controller 280 through the device interface 580, so that the flash memory device can stay in an idle state.

Step S690: Instruct the flash memory device to enter a sleep state. The processing unit 530 can issue a series of commands to the flash memory controller 280 through the device interface 580 to request to put the flash memory device into a sleep state. For example, for the technical details of entering the sleep state, please refer to Section 9.5.1 of the UniPro Standard Version 1.8 "Specification for UniPro Version 1.8" published on September 13, 2017. When the flash memory device successfully enters the sleep state, the processing unit 530 changes the status flag in the RAM 550 to "1". When the flash device enters the hibernation state, there is little message exchange between the bridge IC 250 and the flash controller 280 and between the flash controller 280 and the flash module 410, and the components in the flash controller 280 and the flash module 410 also almost Not working, so that the temperature of the USB memory disk 130 can drop. After the flash memory device enters the sleep state, the processing unit 530 may further reset the count value "cmd_count" to 0, so as to re-accumulate the number of host write commands.

All or part of the steps in the method described in the present invention can be implemented by computer instructions, such as a specific hardware driver. In addition, it can also be implemented in other types of programs. Those skilled in the art can compose the methods of the embodiments of the present invention into computer instructions, which will not be described for brevity. Computer instructions for implementing methods according to embodiments of the present invention may be stored in a suitable computer-readable medium, such as DVD, CD-ROM, USB disk, hard disk, or may be other suitable vehicles) to access the web server.

Although the above-described elements are included in FIGS. 4 and 5 , it is not excluded that more other additional elements can be used to achieve better technical effects without violating the spirit of the invention. In addition, although the flowchart of FIG. 6 is executed in the specified sequence, those skilled in the art can modify the sequence of these steps under the premise of achieving the same effect without violating the spirit of the invention. Therefore, the present invention does not It is not limited to use only the sequence as described above. In addition, those skilled in the art can also integrate several steps into one step, or in addition to these steps, perform more steps sequentially or in parallel, and the present invention is not limited thereby.

Although the present invention is described using the above embodiments, it should be noted that these descriptions are not intended to limit the present invention. On the contrary, this invention covers modifications and similar arrangements obvious to those skilled in the art. Therefore, the scope of the appended claims is to be construed in the broadest manner so as to encompass all obvious modifications and similar arrangements.

S610~S690: Method steps

Claims (12)

A computer program product for controlling access to a flash memory device, comprising program codes loaded and executed by a processing unit of a bridge integrated circuit, for: receiving a host write command from a host; After the write command, determine whether the flash memory device needs to enter a dormant state according to a length of data written to a flash memory device and/or a number of one or more host write commands that have been executed; When the length of the data written to the flash memory device and/or the number of the host write commands that have been executed satisfy a trigger condition, the flash memory device is instructed to enter the sleep state. A method for controlling access to a flash memory device, executed by a processing unit of a bridge integrated circuit, comprises: receiving a host write command from a host end; after executing the host write command, according to a flash memory device already written A length of the data and/or a number of one or more host write commands that have been executed to determine whether the flash memory device needs to enter a dormant state; Or when the above-mentioned number of the above-mentioned host write commands that have been executed satisfies a trigger condition, the above-mentioned flash memory device is instructed to enter the above-mentioned sleep state. The method for controlling access to a flash memory device according to claim 2, wherein the trigger condition is that the host write command requests to write n-kilobyte or more data, and m data for A host write command requesting to write n-kilobytes or more of data, where m and n are integers greater than zero. The method of controlling access to a flash memory device of claim 3, wherein n is set to 96, and m is set to any integer from 4 to 7. The method of controlling access to a flash memory device of claim 3, wherein n is set to 32, and m is set to any integer from 15 to 25. A device for controlling access to a flash memory device, comprising: a host interface, coupled to a host; a device interface, coupled to a flash memory device; and a processing unit, coupled to the host interface and the device interface, for passing the The host interface receives a host write command from the above-mentioned host terminal; after executing the above-mentioned host write command, according to a length of the data that has been written into the above-mentioned flash memory device and/or one or more host write commands that have been executed. A number to determine whether the flash memory device needs to enter a dormant state; and when the length of the data that has been written into the flash memory device and/or the number of the host write commands that have been executed satisfies a trigger condition, through the above The device interface instructs the flash memory device to enter the sleep state. The apparatus for controlling access to a flash memory device as claimed in claim 6, wherein the trigger condition is that the host write command requests to write n-kilobyte or more data, and m data for A host write command requesting to write n-kilobytes or more of data, where m and n are integers greater than zero. The apparatus for controlling access to a flash memory device of claim 7, wherein n is set to 96 and m is set to any integer from 4 to 7. The apparatus for controlling access to a flash memory device of claim 7, wherein n is set to 32, and And m is set to any integer from 15 to 25. The device for controlling access to a flash memory device according to any one of claims 6 to 9, wherein the device for controlling access to the flash memory device and the flash memory device are arranged on a motherboard and combined into a memory disk. The device for controlling access to a flash memory device according to claim 10, wherein the flash memory device is a flash memory card, and the size of the motherboard is less than 3 cm by 2 cm. The device for controlling access to a flash memory device as claimed in claim 10, wherein the flash memory device is a flash memory packaged with a ball grid array.

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