TWI759938B - Memory device transmitting and receiving data at high speed and low power - Google Patents

Abstract

A memory device includes a control logic circuit, a write data strobe signal divider, a data transceiver, and a memory cell array. The control logic circuit generates a reset signal before a write data strobe signal provided from a memory controller starts to toggle. The write data strobe signal divider generates internal write data strobe signals that toggle depending on toggling of the write data strobe signal, the internal write data strobe signals toggling with different phases, respectively. The control logic circuit initializes the internal write data strobe signals to given values in response to the reset signal. The data transceiver receives write data provided from the memory controller based on the internal write data strobe signals. The memory cell array stores the received write data.

Description

Memory device for high speed and low power transmission and reception of data [Cross-reference to related applications]

This application claims Korean Patent Application No. 10-2020-0008110 filed with the Korea Intellectual Property Office on January 21, 2020 and Korean Patent Application filed with the Korea Intellectual Property Office on May 22, 2020 Priority to No. 10-2020-0061441, the disclosures of each of these Korean Patent Applications are incorporated herein by reference in their entirety.

Embodiments relate to a semiconductor device, and more particularly, to a memory device that transmits and receives data at high speed and low power.

Electronic devices such as smart phones, graphics accelerators, and artificial intelligence (AI) accelerators process data by using memory devices such as dynamic random access memory (DRAM). As the amount of data to be processed by electronic devices increases, high capacity and high bandwidth memory devices are required. In particular, memory devices that provide wide input/output in a multi-channel interface, such as high-bandwidth memory for high-speed processing of data, are increasingly being used.

When the memory device supports high bandwidth, data can be transferred at high speed between the memory controller and the memory device. To ensure data integrity during high-speed data transmission, a data strobe signal may be exchanged between the memory controller and the memory device. When data signals are transmitted between the memory controller and the memory device, the data strobe signal can be toggled between a high level and a low level periodically. In this way, the data strobe signal can provide timing information for the level of the latched data signal. That is, in a situation in which data is transmitted at high speed, a data strobe signal having a high frequency may be required. However, data exchange based on data strobe signals with high frequency may result in increased power consumption of the memory device.

One aspect is to provide a memory device that transmits and receives data at high speed and low power.

According to aspects of the exemplary embodiments, there is provided a memory device comprising: a buffer die configured to communicate with a host device via a plurality of channels, each of the plurality of channels constituting a separate interface; and a plurality of core dies stacked on the buffer die by silicon through electrodes, each of the plurality of core dies including corresponding to at least one of the plurality of channels array of memory cells. The buffer die includes a command/address receiver configured to receive from the host device to the channel based on a clock signal provided from the host device to a first channel of the plurality of channels a command for a first channel; control logic configured to generate an internal command in accordance with the command received from the command/address receiver, and upon write provided to the first channel from the host device The reset signal is generated before the input data strobe signal starts toggling; the write data strobe signal frequency divider is configured to: generate a multi-state switching signal according to the toggling of the write data strobe signal. a plurality of internal write data strobe signals, the plurality of internal write data strobe signals are toggled in different phases respectively; and the plurality of internal write data strobe signals are switched in response to the reset signal initialized to a given value; and a data transceiver configured to receive write data provided to the first channel from the host device based on the plurality of internal write data strobes, wherein the plurality of A core die supporting the first channel of the core dies is configured to store the write data transmitted from the buffer die in response to the internal command transmitted from the buffer die.

According to another aspect of an exemplary embodiment, there is provided a memory device comprising: a buffer die configured to communicate with a host device via a plurality of channels, each of the plurality of channels constituting a separate interface ; and a first core die stacked on the buffer die by through-silicon electrodes and including a first array of memory cells corresponding to a first channel of the plurality of channels; and a second core die The die is stacked on the first core die by the through-silicon electrode, and includes a second memory cell array corresponding to the first channel. The buffer die includes a command/address receiver configured to receive a command provided to the first channel from the host device based on a clock signal provided to the first channel from the host device and a stack identifier; control logic configured to generate an internal command in accordance with the command received from the command/address receiver, and in write data provided to the first channel from the host device A reset signal is generated before the strobe signal begins toggling; write A data strobe signal frequency divider, configured to: generate a plurality of internal write data strobe signals that are toggled according to toggling of the write data strobe signal, the plurality of internal write data strobes The strobe signals are toggled with different phases respectively; and the plurality of internal write data strobe signals are initialized to a given value in response to the reset signal; and a data transceiver is configured to be based on the a plurality of internal write data strobe signals to receive write data provided from the host device to the first channel, wherein the first core die and the second core die are identified with the stack The core die corresponding to the symbol is configured to store the write data transmitted from the buffer die in response to the internal command transmitted from the buffer die.

According to yet another aspect of an exemplary embodiment, there is provided a memory device comprising: a buffer die configured to communicate with a host device via a plurality of channels, each of the plurality of channels constituting a separate interface ; and a plurality of core dies stacked on the buffer die by through-silicon electrodes, wherein each of the plurality of core dies includes a memory corresponding to at least one of the plurality of channels A voxel array, wherein the buffer die is configured to: receive a command provided from the host device to the first channel based on a clock signal provided to the first channel from the host device; Before the write data strobe signal provided by the host device to the first channel starts to toggle, a plurality of internal write data strobe signals are initialized to a given value; The plurality of internal write data strobe signals that are toggled by toggling, the plurality of internal write data strobe signals are toggled in different phases respectively; and based on the plurality of internal write data data strobe signal to receive write data from the host device to the first channel material, wherein a core die of the plurality of core dies supporting the first channel is configured to store the received write data.

According to yet another aspect of the exemplary embodiments, there is provided a semiconductor package comprising: a package substrate; an interposer substrate stacked on the package substrate; a system chip stacked on the interposer substrate and including at least one process device and memory controller; and a memory device including a buffer die stacked on the interposer substrate and in communication with the system chip through the interposer substrate and stacked on the buffer by through-silicon electrodes Multiple core dies on a die. The buffer die is configured to: receive a write command provided from the memory controller based on a clock signal provided from the memory controller; write data provided from the memory controller Before the strobe signal is toggled, a plurality of internal write data strobe signals are initialized to a given value; Write data strobe signals, the plurality of internal write data strobe signals are toggled in different phases; and received from the memory controller based on the plurality of internal write data strobe signals Write data. One of the plurality of core dies stores the received write data. The sum of the number of pre-amble cycles of the write data strobe signal and the number of post-amble cycles of the write data strobe signal is an even number.

10: Memory System

100, 1220, 3220: memory controller

110: Memory interface (I/F)

111: Phase-locked loop

112: Phase Controller

113: First Transmitter

114: Second Transmitter

115: Internal clock divider

116: Third Transmitter

117: Fourth Transmitter

200: memory device

210: Host Interface (I/F)

211, 411: Command/Address (CA) receiver

212, 412: control logic circuit

213, 230, 240, 413: Write data strobe signal (WDQS) frequency divider

214, 414: read data strobe signal (RDQS) transmitter

215, 415: Data transceiver

220, 423, 433: memory cell array

231, 241: the first latch

232, 242: the second latch

301: Memory Group

302, 401: TSV area

310, 410, 1110, 3110: Buffer Die

311, 1111, 1210, 3111, 3210: Physical Layer (PHY)

320, 420: core die/first core die

330, 340, 350, 1120, 1130, 1140, 1150, 3120, 3130, 3140, 3150: Core Die

400, 1100, 2100, 3100: Stacked Memory Devices

402, 403, 1101, 3001: TSV

416: Timeline Tree

421, 431: Command Decoder

422, 432: Data input/output (I/O) circuits

430: Core Die/Second Core Die

1000, 2000, 3000: Semiconductor packages

1102, 1103, 3002, 3003: bumps

1104, 2001, 3004: Solder Balls

1112: Direct Access Area (DAB)

1200, 2200: system chip

1300, 2300: intermediary layer

1400, 2400, 3300: Package substrate

3200: host die

4000: Computing Systems

4100: host

4110: Host processor

4120: Host Memory Controller

4130: host memory

4140: interface

4200: Accelerator Subsystem

4210: Dedicated processor

4220: Local memory controller

4230: Local memory

4240: Host Interface/Interface

4300: Interconnects

ACT: Active command

ADD: address

AWORD: command address input/output block

C: Clock terminal

C/A: command/address signal

CH0: channel/first channel

CH1, CH2, CH3, CH4, CH5, CH6, CH7, CHa: Channel

CK: clock signal

cmd:command

D: The first input terminal

D’: The second input terminal

D0, D1, D2, D3, D4, D5, D6, D7, DATA: data

Da0, Da1, Da2, Da3, Da4, Da5, Da6, Da7: first data

Db0, Db1, Db2, Db3, Db4, Db5, Db6, Db7: second data

dICS1: The first frequency-divided internal clock signal/frequency-divided internal clock signal

dICS2: Second frequency-divided internal clock signal/frequency-divided internal clock signal

DQ: data signal

DR: Divider reset command

DRCT: Divider Reset Conditions Table

dWDQS: Internal write data strobe signal

dWDQS[0]: Internal write data strobe number/first internal write data strobe number

dWDQS[1]: Internal write data strobe number/second internal write data strobe number

dWDQS[2]: Internal write data strobe number/third internal write data strobe number

dWDQS[3]: Internal write data strobe number/4th internal write data strobe number

DWORD0, DWORD1, DWORD2, DWORD3: Data input/output block

iCMD: Internal Command

ICS1: The first internal clock signal

ICS2: Second internal clock signal

iCTRL: control signal

P1: first pad

P2: Second pad

P3: The third pad

P4: Fourth pad

P5: Fifth pad

PWS: Power Status Information

Q: The first output terminal

Q': The second output terminal

RD: read command

RDQS: read data strobe signal

RESET: reset signal

RL: read latency

RST: reset terminal

S201, S202, S203, S204, S211, S212, S213, S214, S221, S222, S223: Operation

SID: stack identifier

SID0: First stack identifier

SID1: Second stack identifier

t1: the first time

t2: second time

t3: the third time

t4: Fourth time

t5: Fifth time

t6: sixth time

t7: Seventh time

t8: Eighth time

t9: ninth time

t10: tenth time

t11: Eleventh time

WDQS: write data strobe signal

WDQSB: Complementary write data strobe signal

WL: write latency

WR: write command

WRa: first write command

WRb: Second write command

These and other aspects will become apparent from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which: FIG. 1 is a block diagram illustrating a memory system according to an embodiment.

FIG. 2 is an exemplary block diagram illustrating a memory device of the memory system shown in FIG. 1 .

FIG. 3 is a table indicating exemplary conditions for generating a reset signal by the control logic circuit of the memory device shown in FIG. 2 .

4 is a flowchart illustrating an exemplary write operation of a memory device according to an embodiment.

5A and 5B are timing charts showing an example of the write operation shown in FIG. 4 .

6 is a flowchart illustrating an exemplary write operation of a memory device according to an embodiment.

7A and 7B are timing charts showing an example of the write operation shown in FIG. 6 .

8 is a flowchart illustrating an exemplary read operation of a memory device according to an embodiment.

FIG. 9 is a timing chart showing an example of the read operation shown in FIG. 8 .

10A and 10B are block diagrams illustrating a write data strobe signal (WDQS) divider according to various embodiments.

11 is an exemplary block diagram illustrating a memory interface of the memory system shown in FIG. 1 according to an embodiment.

12 is a block diagram illustrating a stacked memory device according to various embodiments.

13 is a more detailed exemplary block diagram illustrating the stacked memory device shown in FIG. 12, according to an embodiment.

FIG. 14 is a diagram illustrating a more detailed view of the stacked memory device shown in FIG. 12, according to an embodiment. Detailed exemplary block diagram.

FIG. 15 is a block diagram illustrating an embodiment of a buffer die of the stacked memory device shown in FIG. 13 .

FIG. 16 is a diagram illustrating a semiconductor package according to an embodiment.

FIG. 17 is a diagram illustrating an implementation example of a semiconductor package according to an embodiment.

FIG. 18 is a diagram illustrating a semiconductor package according to another embodiment.

19 is a block diagram illustrating a computing system according to an embodiment.

Hereinafter, the embodiments of the present invention will be described in detail and clearly to the extent that those skilled in the art can easily implement the embodiments of the present invention.

FIG. 1 is a block diagram illustrating a memory system according to an embodiment. Referring to FIG. 1 , the memory system 10 may include a memory controller 100 and a memory device 200 . The memory controller 100 can control the overall operation of the memory device 200 . For example, the memory controller 100 can control the memory device 200 so that data is output from the memory device 200 or data is stored in the memory device 200 . For example, the memory controller 100 may be implemented as, but not limited to, part of a system on chip (SoC).

The memory controller 100 may include a memory interface (I/F) 110 . Through the memory interface 110 , the memory controller 100 can transmit various signals to the memory device 200 and can receive various signals from the memory device 200 . For example, as shown in FIG. 1 , through the memory interface 110 , the memory controller 100 can transmit the clock signal CK, the command/address signal C/A, the write data strobe signal WDQS and the data to the memory device 200 Signal DQ and can receive read data strobe from memory device 200 Signal RDQS and data signal DQ.

The memory device 200 may operate under the control of the memory controller 100 . For example, under the control of the memory controller 100 , the memory device 200 can output the stored data, or can store the data provided from the memory controller 100 .

The memory device 200 may include a host interface (I/F) 210 and a memory cell array 220 . Through the host interface 210 , the memory device 200 can transmit various signals to the memory controller 100 and can receive various signals from the memory controller 100 . For example, through the host interface 210, the memory device 200 can transmit the read data strobe signal RDQS and the data signal DQ to the memory controller 100, and can receive the clock signal CK, command/bit from the memory controller 100 address signal C/A, write data strobe signal WDQS and data signal DQ. The host interface 210 can generate the control signal iCTRL based on the signal provided from the memory controller 100 . In response to the control signal iCTRL, the memory cell array 220 may store the data "DATA", or may output the stored data "DATA".

The memory cell array 220 may include a plurality of memory cells. For example, the memory cells may be dynamic random access memory (DRAM) cells. In this case, the memory interface 110 and the host interface 210 may be based on, for example, double data rate (DDR), low power double data rate (LPDDR), graphics double data rate (graphics double data rate, GDDR), wide input/output (input/output, I/O), high bandwidth memory (high bandwidth memory, HBM) and/or hybrid memory cube (hybrid memory cube, HMC) and other standards to communicate with each other.

The memory interface 110 can generate the clock signal CK, and can transmit the clock signal CK to the memory device 200 . In some embodiments, the clock signal CK may be a differential signal. The clock signal CK may be a signal that periodically toggles between a high level and a low level. The memory interface 110 may transmit the command/address signal C/A to the memory device 200 based on the toggle timing of the clock signal CK.

The memory interface 110 can generate the write data strobe signal WDQS, and can transmit the write data strobe signal WDQS to the memory device 200 . In some embodiments, the write data strobe signal WDQS may be a differential signal. For the write operation and the read operation of the memory device 200, the memory interface 110 can generate the write data strobe signal WDQS that periodically toggles between a high level and a low level. The memory interface 110 can transmit the data signal DQ to the memory device 200 based on the toggling timing of the write data strobe signal WDQS.

The memory interface 110 can receive the read data strobe signal RDQS from the memory device 200 . In some embodiments, the read data strobe signal RDQS may be a differential signal. The memory interface 110 can receive the data signal DQ from the memory device 200, and can latch the received data signal DQ based on the toggling timing of the read data strobe signal RDQS. In this way, the memory interface 110 can receive the data "DATA" contained in the data signal DQ.

The host interface 210 can receive the clock signal CK from the memory controller 100 . The host interface 210 can receive the command/address signal C/A from the memory controller 100 and can latch the command/address based on the toggling timing (eg, rising edge and/or falling edge) of the clock signal CK Signal C/A. As such, the host interface 210 can Receive the command or address contained in the command/address signal C/A.

An example in which commands and addresses are transmitted from the memory controller 100 to the memory device 200 by using the same input/output channels is shown in FIG. 1, but the embodiment is not limited thereto. For example, in some embodiments, commands and addresses may be transmitted from memory controller 100 to memory device 200 by using different input/output channels.

The host interface 210 can receive the write data strobe signal WDQS from the memory controller 100 . The host interface 210 can receive the data signal DQ and can latch the data signal DQ based on the toggling timing (eg, rising edge and/or falling edge) of the write data strobe signal WDQS. In this way, the host interface 210 can receive the data "DATA" contained in the data signal DQ.

The host interface 210 can generate the read data strobe signal RDQS, and can transmit the read data strobe signal RDQS to the memory controller 100 . The host interface 210 can generate a read data strobe signal RDQS that periodically toggles between a high level and a low level during a read operation of the memory device 200 . In an exemplary embodiment, the host interface 210 may generate the read data strobe signal RDQS based on the write data strobe signal WDQS received from the memory controller 100 . The host interface 210 can transmit the data signal DQ to the memory controller 100 based on the toggling timing of the read data strobe signal RDQS.

In an exemplary embodiment, the frequency of each of the write data strobe signal WDQS and the read data strobe signal RDQS may be twice the frequency of the clock signal CK. When the data signal DQ is transmitted based on the data strobe signals WDQS and RDQS, The memory controller 100 and the memory device 200 can transmit and receive data at high speed.

FIG. 2 is an exemplary block diagram illustrating a memory device of the memory system shown in FIG. 1 . 2, the memory device 200 may include a command/address (CA) receiver 211, a control logic circuit 212, a write data strobe signal (WDQS) frequency divider 213, a read data strobe signal (RDQS) transmission 214, data transceiver 215 and memory cell array 220. In some embodiments, the C/A receiver 211 , the control logic circuit 212 , the WDQS divider 213 , the RDQS transmitter 214 , and the data transceiver 215 may be included in the host interface 210 shown in FIG. 1 .

The C/A receiver 211 may receive the command CMD by latching the command/address signal C/A based on the clock signal CK. The received command CMD may be provided to the control logic circuit 212 . Although not shown in FIG. 2 , the C/A receiver 211 may receive an address by latching the command/address signal C/A based on the clock signal CK. The received address may be provided to an address register placed within or outside the control logic circuit 212 to be decoded.

The control logic circuit 212 can decode the received command CMD, and can generate control signals for controlling any other components of the memory device 200 according to the decoding result of the command CMD. For example, the control logic circuit 212 may generate the control signal iCTRL for storing the data “DATA” in the memory cell array 220 or outputting the data “DATA” from the memory cell array 220 based on the decoding result of the command CMD. For example, the control logic circuit 212 may generate the reset signal RESET for resetting the WDQS frequency divider 213 based on the decoding result of the command CMD.

The control logic circuit 212 may receive power state information of the memory device 200 News PWS. For example, in some embodiments, control logic circuit 212 may receive power state information PWS from outside of memory device 200 or from outside of memory system 10 (eg, from a host device). In other embodiments, the power state information PWS may be generated by the memory device 200 . For example, the power state information PWS may include voltage information provided to or generated by the memory device 200 . The control logic circuit 212 can determine the power state of the memory device 200 based on the power state information PWS. For example, based on the power state information PWS, the control logic circuit 212 can determine whether the memory device 200 is in a power-up state or whether the memory device 200 is in a power down exit state.

The control logic circuit 212 can generate a reset signal RESET for resetting the WDQS frequency divider 213 . The control logic circuit 212 can generate the reset signal RESET before the write data strobe signal WDQS provided from the memory controller 100 is toggled. In some exemplary embodiments, the control logic circuit 212 may generate the reset signal RESET based on the command CMD or the power state information PWS. The conditions for generating the reset signal RESET by the control logic circuit 212 will be described more fully with reference to FIG. 3 .

The WDQS frequency divider 213 can generate a plurality of internal write data strobe signals dWDQS based on the write data strobe signal WDQS. In detail, the WDQS frequency divider 213 can generate the internal write data strobe signal dWDQS which is toggled according to the toggle of the write data strobe signal WDQS. The WDQS frequency divider 213 can divide the frequency of the write data strobe signal WDQS to generate the internal write data strobe signal dWDQS with different phases. For example, WDQS divider 213 may divide The frequency of the write data strobe signal WDQS is halved to generate four internal write data strobe signals dWDQS with different phases. In this case, the phase of the internal write data strobe signal dWDQS may be 0 degrees, 90 degrees, 180 degrees and 270 degrees.

Before the write data strobe signal WDQS is toggled, the WDQS frequency divider 213 can initialize the internal write data strobe signal dWDQS to a given value in response to the reset signal RESET. Each of the internal write data strobe signals dWDQS may be initialized to a given value of a high level or a low level (hereinafter referred to as a "reset value"). In an exemplary embodiment, the WDQS divider 213 may initialize half of the internal write data strobe signal dWDQS to a low level and may initialize the other half to a high level. The internal write data strobe signal dWDQS can maintain the reset value until the write data strobe signal WDQS performs two-state switching.

In the case where the internal write data strobe signal dWDQS is maintained at the reset value according to the reset operation, the WDQS frequency divider 213 can generate the internal write data strobe signal dWDQS with the desired phase. As such, the memory device 200 may not perform automatic synchronization for synchronizing the phase of the internal write data strobe signal dWDQS with the clock signal CK alone.

The RDQS transmitter 214 can generate the read data strobe signal RDQS based on the internal write data strobe signal dWDQS, and can transmit the read data strobe signal RDQS to the memory controller 100 . For example, the RDQS transmitter 214 may transmit the read data strobe signal RDQS based on the rising edge and/or the falling edge of the internal write data strobe signal dWDQS. The frequency of the read data strobe signal RDQS transmitted to the memory controller 100 may be equal to the frequency of the write data strobe signal WDQS.

The data transceiver 215 can transmit and receive the data signal DQ including the data "DATA" based on the internal write data strobe signal dWDQS. In a write operation, the data transceiver 215 may receive the data "DATA" by latching the data signal DQ based on the internal write data strobe signal dWDQS. For example, the data transceiver 215 may latch the data signal DQ received from the memory controller 100 based on the rising edge and/or the falling edge of the internal write data strobe signal dWDQS. The received data "DATA" may be provided to and stored in the memory cell array 220. In an exemplary embodiment, when the data "DATA" is transferred to the memory cell array 220, the data "DATA" may be transferred based on the toggling timing of the clock signal CK. That is, in the case where the data "DATA" is transferred to the memory cell array 220, the field can be changed from the field of the write data strobe signal WDQS to the field of the clock signal CK.

In the read operation, the data transceiver 215 may transmit the data signal DQ including the data "DATA" to the memory controller 100 based on the internal write data strobe signal dWDQS. The data “DATA” can be read from the memory cell array 220 . For example, the data transceiver 215 may transmit data "DATA" based on the rising edge and/or the falling edge of the internal write data strobe signal dWDQS. In this way, the data “DATA” can be aligned with the toggling timing of the read data strobe signal RDQS, and can be transmitted to the memory controller 100 . In an exemplary embodiment, when the data "DATA" is read from the memory cell array 220, the data "DATA" may be read based on the toggling timing of the clock signal CK. The data transceiver 215 can align the read data “DATA” with the toggling timing of the read data strobe signal RDQS for transmission to the memory controller 100 . That is, in which the data "DATA" is transferred to the memory control In the case of the device 100, the field can be changed from the field of the clock signal CK to the field of the read data strobe signal RDQS (ie, the field of the write data strobe signal WDQS).

As described above, before the write data strobe signal WDQS is toggled, the memory device 200 may initialize the internal write data strobe signal dWDQS to a given value. In this case, the internal write data strobe signal dWDQS generated when the write data strobe signal WDQS is toggled can have a desired phase. In the case where the internal write data strobe signal dWDQS has a desired phase, the memory device 200 may transmit and receive data "DATA" based on the internal write data strobe signal dWDQS. As such, the memory device 200 may not perform the automatic synchronization for adjusting the phase of the internal write data strobe signal dWDQS alone. In situations where automatic synchronization is not performed separately, memory device 200 may not receive a separate command for automatic synchronization, and may not include separate circuitry for automatic synchronization. In other words, a separate command for automatic synchronization can be omitted, and a separate circuit for automatic synchronization can be omitted. As such, the power consumption of the memory device 200 can be reduced.

As described above, the memory device 200 can generate the read data strobe signal RDQS and the data signal DQ based on the internal write data strobe signal dWDQS. Since the internal write data strobe signal dWDQS is generated based on the write data strobe signal WDQS, the read data strobe signal RDQS and the data signal DQ can be generated based on the write data strobe signal WDQS. In this case, compared with the case where the read data strobe signal RDQS and the data signal DQ are generated based on the clock signal CK, the power consumption of the memory device 200 can be reduced.

FIG. 3 is a diagram indicating a control logic circuit for the memory device shown in FIG. 2 A table of exemplary conditions for generating a reset signal. Referring to FIG. 2 and FIG. 3 , the control logic circuit 212 can generate the reset signal RESET according to at least one condition of the frequency divider reset condition table DRCT. In the case where the command CMD matches the divider reset condition or where the power state of the memory device 200 determined according to the power state information PWS matches the divider reset condition, the control logic circuit 212 may generate the reset signal RESET. In this case, the control logic circuit 212 can generate the reset signal RESET before the write data strobe signal WDQS is toggled.

In an exemplary embodiment, in a situation where the memory device 200 is in a power-on state (ie, after a power-on sequence of the memory device 200 ), the control logic circuit 212 may generate the reset signal RESET. For example, the control logic circuit 212 may determine whether the memory device 200 is in the power-on state based on the power state of the memory device 200 determined according to the power state information PWS.

In an exemplary embodiment, the control logic circuit 212 may generate the reset signal RESET in situations where the memory device 200 is in a power-off exit state (ie, after a power-off exit sequence for the memory device 200). For example, the control logic circuit 212 may determine whether the memory device 200 is in the power-off exit state based on the power state of the memory device 200 determined according to the power state information PWS. In addition, the control logic circuit 212 can generate the reset signal RESET in response to the command CMD instructing the power off to exit.

In an exemplary embodiment, in situations where memory device 200 is in a self refresh exit state (ie, after a self-refresh exit sequence of memory device 200 ), control logic 212 may generate reset signal RESET. For example, the control logic circuit 212 may generate the reset signal RESET in response to the command CMD indicating the self-reset exit.

In an exemplary embodiment, the control logic circuit 212 may generate the reset signal RESET in response to the active command ACT. For example, the active command ACT may be a command for enabling a selected word line of the memory cell array 220 . Alternatively, the control logic circuit 212 may generate the reset signal RESET in response to the write command WR and/or the read command RD.

In an exemplary embodiment, the control logic circuit 212 may generate the reset signal RESET in response to the frequency divider reset command DR. Here, the divider reset command DR may be a command CMD transmitted from the memory controller 100 and indicating a reset of the WDQS divider 213 .

4 is a flowchart illustrating an exemplary write operation of a memory device according to an embodiment. 2 and 4 , in operation S201, before the write data strobe signal WDQS is toggled, the memory device 200 may initialize the internal write data strobe signal dWDQS to a given value. For example, the memory device 200 may perform the reset operation according to the reset condition shown in FIG. 3 . In this way, the internal write data strobe signal dWDQS can be maintained at the reset value, and then starts toggling.

In operation S202, the memory device 200 may generate an internal write data strobe signal dWDQS that toggles with different phases according to the toggling of the write data strobe signal WDQS. When the internal write data strobe signal dWDQS is maintained at the reset value and then starts toggling, the memory device 200 can generate the internal write data strobe signal dWDQS with the desired phase.

In an exemplary embodiment, when the write data strobe signal WDQS is toggled, the number of preamble cycles written to the data strobe signal WDQS and the number of postamble cycles written to the data strobe signal WDQS The sum can be even. In this case, even if the toggling of the internal write data strobe signal dWDQS is stopped due to the toggling of the write data strobe signal WDQS being stopped, the internal write data strobe signal dWDQS may not be activated. The reset value is maintained in the case of additional reset operations. In this way, in the case where the write data strobe signal WDQS is toggled again, the internal write data strobe signal dWDQS with the desired phase can also be generated without additional reset operation.

In operation S203, the memory device 200 may receive the data "DATA" by latching the data signal DQ based on the internal write data strobe signal dWDQS. In operation S204 , the memory device 200 may store the received data “DATA” in the memory cell array 220 .

5A and 5B are timing charts showing an example of the write operation shown in FIG. 4 . 5A and 5B , the memory device 200 may receive a clock signal CK, a command/address signal C/A including a write command WR, a write data strobe signal WDQS, and a data signal DQ including data D0 to D7 . Hereinafter, as shown in FIGS. 5A and 5B , the memory device 200 will explain that when the write data strobe signal WDQS is toggled, the memory device 200 generates four internal write data strobe signals dWDQS that are toggled with different phases. [0] to dWDQS[3], but the number of internal write data strobe signals dWDQS generated by memory device 200 may be determined in various ways.

2 and 5A, at the first time t1, the memory device 200 may Initialize the internal write data strobe signals dWDQS[0] to dWDQS[3] to reset values. For example, the memory device 200 can initialize the first internal write data strobe signal dWDQS[0] and the second internal write data strobe signal dWDQS[1] to a low level, and can select the third internal write data strobe The communication signal dWDQS[2] and the fourth internal write data strobe signal dWDQS[3] are initialized to high level.

For example, as described with reference to FIG. 3, the memory device 200 may reset the internal write data strobe signals dWDQS[0] to dWDQS[3] based on the command CMD or the power state of the memory device 200. That is, before the write data strobe signal WDQS starts toggling, the memory device 200 may reset the internal write data strobe signals dWDQS[0] to dWDQS[3] based on various reset conditions.

The memory device 200 may receive the command/address signal C/A including the write command WR at the second time t2. The memory device 200 can receive the command CMD by latching the command/address signal C/A based on the rising and falling edges of the clock signal CK. An example in which the write command WR is received during two cycles of the command/address signal C/A is shown in FIG. 5A, but the embodiment is not limited thereto.

The memory device 200 may receive the write data strobe signal WDQS toggled from the third time t3 to the sixth time t6. Before the write data strobe signal WDQS is toggled (ie, before the third time t3 ), the write data strobe signal WDQS may remain static. For example, the write data strobe signal WDQS can be kept low, as shown in FIG. 5A . The frequency of the write data strobe signal WDQS may be twice the frequency of the clock signal CK. The write data strobe signal WDQS may include a preamble loop when the write data strobe signal WDQS is toggled and a postamble loop. That is, the sum of the number of preamble cycles in which the data strobe signal WDQS is written and the number of postamble cycles in which the data strobe signal WDQS is written may be an even number. FIG. 5A shows an example in which the postamble of the written data strobe signal WDQS corresponds to the toggle period from the fifth time t5 to the sixth time t6, but the embodiment is not limited thereto.

In the case in which the write data strobe signal WDQS starts toggling from the third time t3, the memory device 200 may generate based on the reset values of the internal write data strobe signals dWDQS[0] to dWDQS[3] Internal write data strobe signals dWDQS[0] to dWDQS[3] with the desired phase. For example, at the third time t3, the memory device 200 may generate the first internal write data strobe signal dWDQS[0] with the same edge timing as that of the write data strobe signal WDQS. The memory device 200 can generate a second internal write data strobe signal dWDQS[1] delayed by a phase difference of 90 degrees with respect to the first internal write data strobe signal dWDQS[0], relative to the first internal write data strobe signal dWDQS[1], The third internal write data strobe signal dWDQS[2] delayed by a phase difference of 180 degrees and the fourth internal write data strobe signal dWDQS[0] delayed by a phase difference of 270 degrees with respect to the first internal write data strobe signal dWDQS[0] Write the data strobe signal dWDQS[3]. In this case, the frequency of each of the internal write data strobe signals dWDQS[0] to dWDQS[3] may be half the frequency of the write data strobe signal WDQS.

After the fourth time t4 of the write latency WL has elapsed since the second time t2 when the write command WR is received, the memory device 200 may start to receive the data signal DQ including the data D0 to D7. The memory device 200 can be selected based on the internally written data The communication signals dWDQS[0] to dWDQS[3] latch the data signal DQ to receive the data D0 to D7. For example, memory device 200 may latch data signal DQ at the falling edge of each of the internal write data strobe signals dWDQS[0] through dWDQS[3]. In this case, the data D0 and D4 can be received based on the first internal write data strobe signal dWDQS[0], the data D1 and D5 can be received based on the second internal write data strobe signal dWDQS[1], Data D2 and D6 may be received based on the third internal write data strobe signal dWDQS[2], and data D3 and D7 may be received based on the fourth internal write data strobe signal dWDQS[3]. In this way, from the fourth time t4 to the fifth time t5, the data D0 to D7 can be received from the data signal DQ.

Since the toggling of the write data strobe signal WDQS is stopped at the sixth time t6, the toggling of the internal write data strobe signals dWDQS[0] to dWDQS[3] can be stopped. Even if the toggling of the internal write data strobe signals dWDQS[0] to dWDQS[3] is stopped, the internal write data strobe signals dWDQS[0] to dWDQS[3] can have the same value as at the first time t1 value. As such, after the sixth time t6, each of the internal write data strobe signals dWDQS[0] to dWDQS[3] may maintain the reset value.

2 and 5B, in some embodiments, the write data strobe signal WDQS may include two preamble cycles and two postamble cycles. In this case, in order to generate the desired phase (ie, the same as the internal write data strobe signals dWDQS[0] to dWDQS[3] shown in FIG. 5A in order to generate a The internal write data strobe signals dWDQS[0] to dWDQS[3] of the same phase), the memory device 200 can strobe the internal write data The signals dWDQS[0] to dWDQS[3] are initialized to a value different from the reset value shown in FIG. 5A. That is, the reset values of the internal write data strobe signals dWDQS[0] to dWDQS[3] can be defined according to the number of preamble cycles of the write data strobe signal WDQS (ie, the reset value). An example in which the postamble of the data strobe signal WDQS is written corresponds to the toggle period from the fifth time t5 to the sixth time t6 is shown in FIG. 5B , but the embodiment is not limited thereto.

At the first time t1, the memory device 200 can initialize the first internal write data strobe signal dWDQS[0] and the second internal write data strobe signal dWDQS[1] to a high level, and can initialize the third internal write data strobe signal dWDQS[1] to a high level The write data strobe signal dWDQS[2] and the fourth internal write data strobe signal dWDQS[3] are initialized to the low level. In this case, the internal write data strobe signals dWDQS[0] to dWDQS[3] generated when the write data strobe signal WDQS starts toggling from the third time t3 may have desired phases. Thus, as described with reference to FIG. 5A, the memory device 200 can receive data D0-D7 by latching the data signal DQ based on the falling edges of the internal write data strobe signals dWDQS[0]-dWDQS[3].

As described above, before the write data strobe signal WDQS is toggled, the memory device 200 can initialize the internal write data strobe signal dWDQS to a reset value, and can generate an internal write data strobe with a desired phase. Communication number dWDQS. As such, the memory device 200 may not perform the automatic synchronization for adjusting the phase of the internal write data strobe signal dWDQS alone. That is, automatic synchronization can be omitted. In situations where automatic synchronization is not performed, additional toggling of the write data strobe signal WDQS may not be required for automatic synchronization. that is, Since the period in which the write data strobe signal WDQS remains static increases before the data D0 to D7 are transmitted, the toggle period can be shortened.

6 is a flowchart illustrating an exemplary write operation of a memory device according to an embodiment. 2 and 6, in operation S211, before the write data strobe signal WDQS is toggled, the memory device 200 may initialize the internal write data strobe signal dWDQS to a given value.

In operation S212, the memory device 200 may generate an internal write data strobe signal dWDQS according to toggling of the write data strobe signal WDQS corresponding to the first write command and the second write command. In an exemplary embodiment, the memory device 200 may generate the write data strobe signal WDQS corresponding to the first write command and the second write command without performing an additional reset operation. For example, even if the toggling of the write data strobe signal WDQS is performed between the first toggling cycle of the write data strobe signal WDQS according to the first write command and the write according to the second write command The data strobe signal WDQS is stopped between the second toggling cycles, and the memory device 200 can also generate the internal write data strobe signal dWDQS without performing an additional reset operation.

In operation S213, the memory device 200 may receive the first data and the second data based on the thus generated internal write data strobe signal dWDQS. Here, the first data may correspond to the first write command, and the second data may correspond to the second write command. In operation S214 , the memory device 200 may store the first data and the second data in the memory cell array 220 .

7A and 7B are timings showing an example of the write operation shown in FIG. 6 picture. 7A and 7B, the memory device 200 can receive a clock signal CK, a command/address signal C/A including a first write command WRa and a second write command WRb, a write data strobe signal WDQS, and The data signal DQ includes the first data Da0 to Da7 and the second data Db0 to Db7. In detail, FIG. 7A shows when the interval between the first write command WRa and the second write command WRb is equal to or less than the reference time (ie, when the first data Da0 to Da7 and the second data Db0 to Db7 is seamless) timing diagram of the write operation. 7B is a diagram illustrating when the interval between the first write command WRa and the second write command WRb exceeds the reference time (ie, when the first data Da0 to Da7 and the second data Db0 to Db7 are not seamless) Timing diagram of the write operation. Here, the reference time may be the data transmission time corresponding to one write command. For example, as shown in FIGS. 7A and 7B , when the data transmission time corresponding to one write command corresponds to two cycles of the clock signal CK, the reference time may correspond to two cycles of the clock signal CK.

2 and 7A, before the write data strobe signal WDQS is toggled, that is, at the first time t1, the memory device 200 may write the first internal write data strobe signal dWDQS[0] and The second internal write data strobe signal dWDQS[1] is initialized to a low level, and the third internal write data strobe signal dWDQS[2] and the fourth internal write data strobe signal dWDQS[3] can be initialized as high level.

Based on the clock signal CK, the memory device 200 may receive the first write command WRa at the second time t2, and may receive the second write command WRb at the third time t3. For example, in some embodiments, the first write command WRa and the second write command Let the interval between WRb be equal to or less than two cycles of the clock signal CK.

The memory device 200 may receive the write data strobe signal WDQS toggled from the fourth time t4 to the eighth time t8. In this case, the write data strobe signal WDQS may have one toggle period corresponding to the first write command WRa and the second write command WRb (ie, from the fourth time t4 to the eighth time t8 ) . As such, regarding the first write command WRa and the second write command WRb, the write data strobe signal WDQS may have a preamble and a postamble, as shown in FIG. 7A .

The memory device 200 may generate a first edge timing that is the same as the edge timing of the write data strobe signal WDQS at the fourth time t4 based on the reset values of the internal write data strobe signals dWDQS[1] to dWDQS[3]. Internal write data strobe signal dWDQS[0], and can generate the second internal write data with a phase difference of 90 degrees, 180 degrees and 270 degrees respectively delayed from the first internal write data strobe signal dWDQS[0] The strobe signal dWDQS[1] to the fourth internal write data strobe signal dWDQS[3]. After the reset operation is performed at the first time t1, the memory device 200 may generate the internal write data strobe signals dWDQS[0] to dWDQS[3] without performing an additional reset operation.

After the fifth time t5 of the write latency WL has elapsed since the second time t2 when the first write command WRa is received, the memory device 200 may start to receive the data signal DQ including the first data Da0 to Da7. After the sixth time t6 of the write latency WL has elapsed since the third time t3 when the second write command WRb is received, the memory device 200 may start to receive the data signal DQ including the second data Db0 to Db7 .

The memory device 200 can receive the first data Da0 to Da7 and the second data Db0 to Db7 by latching the data signal DQ based on the internal write data strobe signals dWDQS[0] to dWDQS[3]. For example, memory device 200 may latch data signal DQ at the falling edge of each of the internal write data strobe signals dWDQS[0] through dWDQS[3]. In this way, from the fifth time t5 to the seventh time t7, the first data Da0 to Da7 and the second data Db0 to Db7 can be received from the data signal DQ.

2 and 7B, before the write data strobe signal WDQS is toggled, that is, at the first time t1, the memory device 200 may write the first internal write data strobe signal dWDQS[0] and The second internal write data strobe signal dWDQS[1] is initialized to a low level, and the third internal write data strobe signal dWDQS[2] and the fourth internal write data strobe signal dWDQS[3] can be initialized as high level.

Based on the clock signal CK, the memory device 200 may receive the first write command WRa at the second time t2, and may receive the second write command WRb at the third time t3. For example, the interval between the first write command WRa and the second write command WRb may exceed two cycles of the clock signal CK.

The memory device 200 may receive a write data strobe signal WDQS including toggle periods corresponding to the first write command WRa and the second write command WRb, respectively. The write data strobe signal WDQS may have a first (1 ^st ) toggle period corresponding to the first write command WRa (ie, from the fourth time t4 to the seventh time t7 ) and the second write command WRb The corresponding second (2 ^nd ) toggle period (ie, from the eighth time t8 to the eleventh time t11). That is, the toggling of the write data strobe signal WDQS may be stopped between the first toggling period and the second toggling period (ie, from the seventh time t7 to the eighth time t8 ). As such, for each of the first toggle and the second toggle, the write data strobe signal WDQS may have one preamble and one postamble, as shown in Figure 7B.

The memory device 200 can generate the internal write data strobe signals dWDQS[0] to dWDQS[3] for the first toggle from the fourth time t4 to the seventh time t7, and can generate the second The internal write data strobe signals dWDQS[0] to dWDQS[3] for toggling are toggled from the eighth time t8 to the eleventh time t11. After the reset operation is performed at the first time t1, the memory device 200 may generate the internal write data strobe signals dWDQS[0] to dWDQS[3] without performing an additional reset operation.

The toggling of the internal write data strobe signals dWDQS[0] to dWDQS[3] can be stopped from the seventh time t7 to the eighth time t8. When the toggling is stopped, the internal write data strobe signals dWDQS[1] to dWDQS[3] can maintain the same value as at the first time t1. As such, the internal write data strobe signals dWDQS[1] to dWDQS[3] toggled with respect to the second toggling may have the desired phase (ie, the internal write data toggled with respect to the first toggle input data strobe signals dWDQS[1] to dWDQS[3] phase).

After the fifth time t5 of the write latency WL has elapsed since the second time t2 when the first write command WRa is received, the memory device 200 may start to receive the data signal DQ including the first data Da0 to Da7. At the ninth time t9 that elapses the write latency WL from the third time t3 when the second write command WRb is received, the memory device 200 The reception of the data signal DQ including the second data Db0 to Db7 can be started.

The memory device 200 can receive the first data Da0 to Da7 and the second data Db0 to Db7 by latching the data signal DQ based on the internal write data strobe signals dWDQS[0] to dWDQS[3]. For example, memory device 200 may latch data signal DQ at the falling edge of each of the internal write data strobe signals dWDQS[0] through dWDQS[3]. In this way, from the fifth time t5 to the eleventh time t11, the first data Da0 to Da7 and the second data Db0 to Db7 can be received from the data signal DQ.

As described with reference to FIGS. 7A and 7B , in the case where the internal write data strobe signal dWDQS is initialized to a reset value before the write data strobe signal WDQS starts toggling, the memory device 200 may not perform An internal write data strobe signal dWDQS with a desired phase is generated in the case of an additional reset operation, and write data corresponding to a plurality of write commands can be received. As such, the power consumption of the memory device 200 can be reduced.

A write operation according to a plurality of write commands is explained with reference to FIGS. 6 , 7A and 7B, but the embodiment is not limited thereto. For example, in a read operation according to multiple read commands, the memory device 200 may generate the internal write data strobe signal dWDQS without performing an additional reset operation. Alternatively, in the write operation according to the write command and the read operation according to the read command, the memory device 200 may generate an internal write data strobe signal without performing an additional reset operation dWDQS.

8 is a flowchart illustrating an exemplary read operation of a memory device according to an embodiment. Referring to FIG. 2 and FIG. 8, in operation S221, select communication in writing data Before the toggling of signal WDQS, the memory device 200 may initialize the internal write data strobe signal dWDQS to a given value. In this way, the internal write data strobe signal dWDQS can be maintained at the reset value before toggling.

In operation S222, the memory device 200 may generate an internal write data strobe signal dWDQS that toggles with different phases according to the toggling of the write data strobe signal WDQS. Since the internal write data strobe signal dWDQS is maintained at the reset value before toggling, the memory device 200 can generate the internal write data strobe signal dWDQS with the desired phase.

In operation S223, the memory device 200 may transmit the read data strobe signal RDQS and the data “DATA” read from the memory cell array 220 to the memory controller 100 based on the internal write data strobe signal dWDQS.

FIG. 9 is a timing chart showing an example of the read operation shown in FIG. 8 . Referring to FIG. 2 and FIG. 9 , the memory device 200 can receive a clock signal CK, a command/address signal C/A including a read command RD, and a write data strobe signal WDQS. The memory device 200 can transmit the read data strobe signal RDQS and the data signal DQ including the data D0 to D7 to the memory controller 100 in response to the memory controller 100 (refer to FIG. 1 ).

At the first time t1, the memory device 200 may initialize the internal write data strobe signals dWDQS[0] to dWDQS[3] to reset values. The memory device 200 can initialize the first internal write data strobe signal dWDQS[0] and the second internal write data strobe signal dWDQS[1] to a low level, and can initialize the third internal write data strobe signal dWDQS[2] and the fourth internal write data strobe signal dWDQS[3] are initialized to high level.

The memory device 200 may receive the command/address signal C/A including the read command RD at the second time t2. The memory device 200 can receive the read command RD by latching the command/address signal C/A based on the rising and falling edges of the clock signal CK. An example in which the read command RD is received during two cycles of the command/address signal C/A is shown in FIG. 9, but the embodiment is not limited thereto.

The memory device 200 may receive the write data strobe signal WDQS toggled from the third time t3 to the sixth time t6. When the write data strobe signal WDQS performs two-state switching, the write data strobe signal WDQS may include a preamble cycle and a postamble cycle.

At the third time t3, the memory device 200 may generate the first internal write data strobe signal dWDQS[0] with the same edge timing as the edge timing of the write data strobe signal WDQS. The memory device 200 can generate the second internal write data strobe signal dWDQS[1] to the first internal write data strobe signal dWDQS[1] which is delayed by a phase difference of 90 degrees, 180 degrees and 270 degrees, respectively, with respect to the first internal write data strobe signal dWDQS[0]. Four internal write data strobe signal dWDQS[3].

The memory device 200 may generate a read data strobe signal RDQS that toggles from the third time t3 to the sixth time t6 based on the internal write data strobe signals dWDQS[0] to dWDQS[3]. When the read data strobe signal RDQS is toggled, the read data strobe signal RDQS may include a preamble cycle and a postamble cycle. It is shown in FIG. 9 that the time to start receiving the toggled write data strobe signal WDQS is the same as the time to start transmitting the toggled read data strobe signal RDQS (ie, both correspond to a third time) t3) , but there may be a delay between the time at which the toggled write data strobe signal WDQS begins to be received and the time at which the toggled read data strobe signal RDQS begins to be transmitted. In the following, for the convenience of description, it is assumed that the time of starting to receive the write data strobe signal WDQS of the toggle is the same as the time of starting to transmit the read data strobe signal RDQS of the toggle.

The memory device 200 may generate the data signal DQ including the data D0 to D7 from the fourth time t4 to the fifth time t5 based on the internal write data strobe signals dWDQS[0] to dWDQS[3]. After the fourth time t4 of the read latency RL has elapsed since the second time t2 when the read command RD was received, the memory device 200 may start to transmit the data signal DQ including the data D0 to D7. In this way, the data D0 to D7 can be aligned with the toggling timing of the read data strobe signal RDQS, and can be transmitted to the memory controller 100 .

Since the toggling of the write data strobe signal WDQS is stopped at the sixth time t6, the toggling of the internal write data strobe signals dWDQS[0] to dWDQS[3] can be stopped. In this case, each of the internal write data strobe signals dWDQS[0] to dWDQS[3] may have the same value as at the first time t1. That is, after the sixth time t6, each of the internal write data strobe signals dWDQS[0] to dWDQS[3] may maintain the reset value. Thus, as described with reference to FIGS. 7A and 7B , the memory device 200 can generate the internal write data strobe signals dWDQS[0] to dWDQS[3] with desired phases without additional reset operations, And the following write and read operations can be performed. An example of a read operation has been explained with reference to FIGS. 8 and 9 . However, those of ordinary skill in the art will understand that the above The technical concept of the write operation explained with reference to the timing diagrams shown in FIGS. 5B , 7A and 7B can also be applied to the read operation. Therefore, for the sake of brevity, it will not be repeated here.

10A and 10B are block diagrams illustrating a WDQS frequency divider according to various embodiments. For example, the WDQS frequency divider 213 of the memory device 200 shown in FIG. 2 may be implemented using the WDQS frequency divider 230 shown in FIG. 10A or the WDQS frequency divider 240 shown in FIG. 10B . Each of the WDQS dividers 230 and 240 may generate four internal write data strobe signals dWDQS[0] through dWDQS[3] based on the write data strobe signal WDQS, as described with reference to FIG. 5A.

Referring to FIG. 10A , the WDQS frequency divider 230 may include a first latch 231 and a second latch 232 . Each of the first latch 231 and the second latch 232 may include a first input terminal "D", a second input terminal D', a first output terminal "Q", a second output terminal Q', Reset terminal RST and clock terminal "C". Each of the first latch 231 and the second latch 232 may receive complementary inputs through the first input terminal "D" and the second input terminal D', and may receive complementary inputs through the first output terminal "Q" " and the second output terminal Q' output complementary values.

The first input terminal "D" of the first latch 231 can be connected to the second output terminal Q' of the second latch 232, and the second input terminal D' of the first latch 231 can be connected to the second latch 232. The first output terminal "Q" of the register 232 is connected. The first output terminal "Q" of the first latch 231 may be connected with the first input terminal "D" of the second latch 232, and the second output terminal Q' of the first latch 231 may be connected with the second input terminal "D" of the second latch 232. The second input terminal D' of the latch 232 is connected.

The reset signal RESET can be input to the first latch 231 and the second latch A reset terminal RST of each of the registers 232. The first latch 231 and the second latch 232 can be reset by the reset signal RESET. For example, as described with reference to FIGS. 5A and 5B , each of the first latch 231 and the second latch 232 may be initialized to low bits according to the number of preamble cycles of the write data strobe signal WDQS standard or high level. When each of the first latch 231 and the second latch 232 is reset, each of the first latch 231 and the second latch 232 can pass through the first output terminal " Q" outputs the reset value, and can output the complementary value through the second output terminal Q'.

The write data strobe signal WDQS may be input to the clock terminal “C” of the first latch 231 , and the complementary write data strobe signal WDQSB may be input to the clock terminal “C” of the second latch 232 . The write data strobe signal WDQS and the complementary write data strobe signal WDQSB can be input to the clock terminal "C" of the first latch 231 and the second latch 232, respectively. In this case, the write data strobe signal WDQS and the complementary write data strobe signal WDQSB can be provided from the memory controller 100 as differential signals. The first latch 231 may output the values input to the input terminals "D" and D' to the output terminals "Q" and Q' based on the rising edge of the write data strobe signal WDQS. The second latch 232 may output the values input to the input terminals "D" and D' to the output terminals "Q" and Q' based on the rising edge of the complementary write data strobe signal WDQSB.

The first internal write data strobe signal dWDQS[0] can be output from the first output terminal "Q" of the first latch 231, and the third output terminal Q' can be output from the first latch 231 Internal write data strobe signal dWDQS[2]. The second internal write data strobe signal can be output from the first output terminal "Q" of the second latch 232 dWDQS[1], and the fourth internal write data strobe signal dWDQS[3] can be output from the second output terminal Q' of the second latch 232.

5A and FIG. 10A , when the reset signal RESET is input before the write data strobe signal WDQS is toggled, the WDQS frequency divider 230 can be output through the first output terminal “Q” according to the reset signal RESET The first internal write data strobe signal dWDQS[0] and the second internal write data strobe signal dWDQS[1] have a low level, and the third internal write data strobe signal with a high level can be output through the second output terminal Q' Write data strobe signal dWDQS[2] and the fourth internal write data strobe signal dWDQS[3]. When the write data strobe signal WDQS is toggled, the WDQS frequency divider 230 can output the internal toggling based on the rising edge of the write data strobe signal WDQS and the rising edge of the complementary write data strobe signal WDQSB. Write the data strobe signals dWDQS[0] to dWDQS[3].

Referring to FIG. 10B , the WDQS frequency divider 240 may include a first latch 241 and a second latch 242 . Each of the first latch 241 and the second latch 242 may include an input terminal "D", a first output terminal "Q", a second output terminal Q', a reset terminal RST, and a clock terminal "C" ". Each of the first latch 241 and the second latch 242 can output complementary values through the first output terminal "Q" and the second output terminal Q'. The input terminal "D" of the first latch 241 may be connected to the second output terminal Q' of the second latch 242. The first output terminal "Q" of the first latch 241 may be connected to the input terminal "D" of the second latch 242 .

The first internal write data strobe signal dWDQS[0] can be output from the first output terminal “Q” of the first latch 241 , and can be output from the second output terminal of the first latch 241 . The output terminal Q' outputs the third internal write data strobe signal dWDQS[2]. The second internal write data strobe signal dWDQS[1] can be output from the first output terminal "Q" of the second latch 242, and the fourth output terminal Q' can be output from the second latch 242. Internal write data strobe signal dWDQS[3]. As such, the operation of the WDQS frequency divider 240 may be substantially the same as that of the WDQS frequency divider 230 shown in FIG. 10A, and thus, additional description will be omitted to avoid redundancy.

FIG. 11 is an exemplary block diagram illustrating a memory interface of the memory system 10 shown in FIG. 1 . 11 , the memory interface (I/F) 110 may include a phase-locked loop 111 , a phase controller 112 , a first transmitter 113 , a second transmitter 114 , an internal clock divider 115 , and a third transmitter 116 and the fourth transmitter 117 . The phase-locked loop 111 can generate the first internal clock signal ICS1. Based on the first internal clock signal ICS1, the phase controller 112 can generate a second internal clock signal ICS2 with a phase different from that of the first internal clock signal ICS1. For example, the first internal clock signal ICS1 and the second internal clock signal ICS2 may be out of phase by 90 degrees.

The first transmitter 113 can transmit the data "DATA" based on the second internal clock signal ICS2. In this way, the first transmitter 113 can transmit the data signal DQ including the data “DATA” to the memory device 200 . The second transmitter 114 can transmit the first internal clock signal ICS1 to the memory device 200 as the write data strobe signal WDQS.

The internal clock frequency divider 115 can divide the frequency of the first internal clock signal ICS1 to generate the first frequency-divided internal clock signal dICS1 and the second frequency-divided internal clock signal dICS2 having different phases. The first divided internal clock signal dICS1 The edge timing of dICS1 may be the same as the edge timing of the first internal clock signal ICS1, and the first frequency-divided internal clock signal dICS1 and the second frequency-divided internal clock signal dICS2 may be out of phase by 270 degrees. For example, the frequency of the divided internal clock signals dICS1 and dICS2 may be half the frequency of the second internal clock signal ICS2.

The third transmitter 116 can transmit the first divided internal clock signal dICS1 to the memory device 200 as the clock signal CK. Since the edge timing of the first frequency-divided internal clock signal dICS1 is the same as that of the second internal clock signal ICS2, the clock signal CK and the write data strobe signal WDQS can be output at the same edge timing. The fourth transmitter 117 may transmit the command CMD and/or the address ADD based on the second divided internal clock signal dICS2. In this way, the fourth transmitter 117 can transmit the command/address signal C/A including the command CMD and/or the address ADD to the memory device 200 .

As mentioned above, the clock signal CK and the write data strobe signal WDQS can be generated by a phase-locked loop 111 . As such, the operating current of the memory controller 100 can be reduced.

12 is a block diagram illustrating a stacked memory device according to various embodiments. Referring to FIG. 12 , the stacked memory device 300 may include a buffer die 310 and a plurality of core dies 320 to 350 . For example, buffer die 310 may also be referred to as an "interface die," "base die," "logic die," or "main die," and each of core dies 320-350 may also be referred to as Known as "memory die" or "slave die". An example in which the stacked memory device 300 includes four core dies 320-350 is shown in FIG. 12, but the number of core dies may be varied in various ways. For example, stack Format memory device 300 may include 8, 12, or 16 core dies.

The buffer die 310 and the core dies 320-350 may be stacked and electrically connected by using through silicon vias (TSVs). As such, the stacked memory device 300 may have a three-dimensional memory structure in which a plurality of dies 310 to 350 are stacked. For example, the stacked memory device 300 may be implemented in compliance with the HBM or HMC standards.

The stacked memory device 300 may support multiple channels (or vaults) that are functionally independent from each other. For example, as shown in FIG. 12, the stacked memory device 300 can support 8 channels CH0 to CH7. In the case where each of channels CH0-CH7 supports 128 DQ I/Os, stacked memory device 300 may support 1204 DQ I/Os. However, the embodiments are not so limited. For example, stacked memory device 300 may support 1024 or more DQ I/Os, and may support 8 or more channels (eg, 16 channels). In the case where stacked memory device 300 supports 16 channels, each of the channels may support 64 DQ I/Os.

Each of core dies 320-350 may support at least one channel. For example, as shown in FIG. 12, core dies 320-350 may support channel pairs CH0 and CH2, CH1 and CH3, CH4 and CH6, and CH5 and CH7, respectively. In this case, core dies 320-350 may support different channels. However, the embodiments are not so limited. For example, at least two of core dies 320-350 may support the same channel. For example, each of core dies 320-350 may support the first channel CH0.

Each of the channels can form independent command and data interfaces. E.g, Channels can be independently clocked based on independent timing requirements, and can also be asynchronous. For example, each channel can change power state or perform a refresh operation based on an independent command.

Each of the channels may include multiple memory banks 301 . Each of the memory groups 301 may include memory cells, column decoders, row decoders, sense amplifiers, etc. connected to word lines and bit lines. For example, as shown in FIG. 12 , each of channels CH0 to CH7 may support 8 memory groups 301 . However, the embodiments are not so limited. For example, each of channels CH0-CH7 may support 8 or more memory banks 301 . An example in which memory groups belonging to one channel are included in one core die is shown in FIG. 12 , but memory groups belonging to one channel may be distributed to a plurality of core dies. For example, in the case where each of the core dies 320-350 supports the first channel CH0, the memory groups included in the first channel CH0 may be distributed among the core dies 320-350.

In an exemplary embodiment, one channel may be divided into two pseudo channels that operate independently of each other. For example, pseudo-channels can share the command and pulse input of the corresponding channel (eg, the clock signal CK and the pulse enable signal CKE), but can decode and execute the commands independently. For example, in the case where one channel supports 128 DQ I/Os, each of the pseudo channels may support 64 DQ I/Os. For example, in the case where one channel supports 64 DQ I/Os, each of the pseudo channels may support 32 DQ I/Os.

Buffer die 310 and core dies 320 - 350 may each include TSV region 302 . TSV region 302 may be provided with dies 310 to 350 configured to penetrate TSV. The buffer die 310 can exchange signals and/or data with the core dies 320 to 350 through the TSV. Each of core dies 320-350 can exchange signals and/or data with buffer die 310 via TSVs, and core dies 320-350 can exchange signals and/or data with each other via TSVs. In such a case, signals and/or data can be exchanged independently by the corresponding TSV of each channel. For example, in a situation where the external host device transmits commands and addresses to the first channel CH0 in order to access the memory cells of the first core die 320, the buffer die 310 may The TSV transmits control signals to the first core die 320 and can access the memory cells of the first channel CH0.

The buffer die 310 may include a physical layer (PHY) 311 . The physical layer 311 may include interface circuitry for communicating with external host devices. For example, the physical layer 311 may include interface circuits corresponding to the host interface 210 described with reference to FIGS. 1 to 11 . Signals and/or data received through physical layer 311 may be transmitted to core dies 320-350 through TSV.

In an exemplary embodiment, the buffer die 310 may include channel controllers corresponding to the channels, respectively. The channel controller can manage the memory reference operation of the corresponding channel and can determine the timing requirements of the corresponding channel.

In an exemplary embodiment, the buffer die 310 may include a plurality of pins for receiving signals from an external host device. Through the plurality of pins, the buffer die 310 can receive the clock signal CK, the command/address signal C/A, the write data strobe signal WDQS and the data signal DQ, and can transmit the read data strobe signal RDQS and data signal DQ. For example, for each channel, buffer die 310 may include a buffer die 310 for receiving 2 pins of pulse signal CK, 14 pins used to receive command/address signal C/A, 8 pins used to receive write data strobe signal WDQS, used to transmit read data strobe 8 pins of RDQS and 128 pins of DQ for transmitting and receiving data signals.

13 is a more detailed exemplary block diagram illustrating the stacked memory device shown in FIG. 12, according to an embodiment. Referring to FIG. 13 , the stacked memory device 400 may include a buffer die 410 and a core die 420 . The core die 420 may support the channel CHa of the plurality of channels. Buffer die 410 and core die 420 can communicate with each other through TSVs 402 and 403 placed in TSV region 401 . The TSV area 401 may correspond to the channel CHa. For example, the buffer die 410 can transmit the internal command iCMD to the core die 420 through the TSV 402 , and can exchange data “DATA” with the core die 420 through the TSV 403 .

The buffer die 410 may include a C/A receiver 411 , a control logic circuit 412 , a WDQS frequency divider 413 , an RDQS transmitter 414 and a data transceiver 415 . The C/A receiver 411 , the control logic circuit 412 , the WDQS divider 413 , the RDQS transmitter 414 and the data transceiver 415 may be included in the physical layer 311 of the stacked memory device 300 shown in FIG. 12 as the channel CHa interface circuit. That is, for each channel, the physical layer 311 shown in FIG. 12 may include the interface circuit shown in FIG. 13 . The C/A receiver 411 , the control logic circuit 412 , the WDQS frequency divider 413 , the RDQS transmitter 414 and the data transceiver 415 may correspond to the C/A receiver 211 , the control logic circuit 212 , and the WDQS frequency divider shown in FIG. 2 , respectively. 213, RDQS transmitter 214, and data transceiver 215, and therefore, additional descriptions will be omitted to avoid redundancy.

The buffer die 410 can receive the clock signal CK, the command/address signal C/A, the write data strobe signal WDQS and the data signal DQ provided by the channel CHa. The buffer die 410 can transmit the read data strobe signal RDQS and the data signal DQ generated at the channel CHa to the external host device.

The C/A receiver 411 may receive the command CMD by latching the command/address signal C/A based on the clock signal CK. The received command CMD may be provided to control logic circuit 412 .

According to the command CMD or the power state information PWS, the control logic circuit 412 can generate the reset signal RESET before the write data strobe signal WDQS starts toggling. The control logic circuit 412 can decode the command CMD, and can generate the internal command iCMD according to the command CMD. For example, the internal command iCMD may be generated in a format different from that of the command CMD, or may be generated in the same format as the command CMD, in accordance with the internal communication protocol between the buffer die 410 and the core die 420 . The internal command iCMD can be transmitted through the TSV 402 to the core die 420 supporting the channel CHa.

The WDQS frequency divider 413 can be reset in response to the reset signal RESET. In this way, the WDQS frequency divider 413 can initialize the internal write data strobe signal dWDQS to a reset value. The WDQS frequency divider 413 can generate the internal write data strobe signal dWDQS which is toggled in different phases according to the toggling of the write data strobe signal WDQS.

In an exemplary embodiment, the stacked memory device 400 may transmit or receive the write data strobe signal WDQS without a separate termination resistor. In other words, a separate terminating resistor can be omitted. here In this case, the write data strobe signal WDQS may be in a static low state or a static high state instead of the high impedance state High-Z. In this way, the reset operation of the WDQS frequency divider 413 can be easily performed.

The RDQS transmitter 414 can generate the read data strobe signal RDQS based on the internal write data strobe signal dWDQS, and can transmit the read data strobe signal RDQS to the external host device. The read data strobe signal RDQS may be generated to have the same frequency as the write data strobe signal WDQS.

The data transceiver 415 can transmit and receive the data signal DQ including the data "DATA" based on the internal write data strobe signal dWDQS. In a write operation, the data transceiver 415 may receive the data "DATA" by latching the data signal DQ based on the internal write data strobe signal dWDQS. The received data "DATA" can be transmitted to the core die 420 supporting the channel CHa through the TSV 403 . In a read operation, data transceiver 415 may receive data "DATA" transmitted from core die 420 via TSV 403 . The data transceiver 415 can transmit the data signal DQ including the data "DATA" to the external host device based on the internal write data strobe signal dWDQS. The data "DATA" can be aligned with the toggling timing of the read data strobe signal RDQS and can be transmitted.

The core die 420 may include a command decoder 421 , data input/output (I/O) circuits 422 and a memory cell array 423 . The command decoder 421, the data input/output circuit 422, and the memory cell array 423 may be circuits supporting the channel CHa.

The command decoder 421 can decode the transmission from the buffer die 410 through the TSV 402 Input the internal command iCMD. For example, the internal commands iCMD may include active commands, write commands, read commands, refresh commands, etc. associated with the memory cell array 220 . In a write operation, the command decoder 421 may receive an internal command iCMD including a write command. In a read operation, the command decoder 421 may receive an internal command iCMD including a read command. The command decoder 421 can control the data input/output circuit 422 and the memory cell array 423 according to the internal command iCMD.

The data input/output circuit 422 can exchange data with the buffer die 410 through the TSV 403 . In a write operation, the data input/output circuit 422 may receive the data "DATA" transmitted from the buffer die 410 by the TSV 403 and may transmit the data "DATA" to the memory cell array 423. The memory cell array 423 can store data "DATA". In the read operation, the data input/output circuit 422 can read the data “DATA” from the memory cell array 423 , and can transmit the received data “DATA” to the buffer die 410 through the TSV 403 .

In an exemplary embodiment, the buffer die 410 may further include an error correction code (ECC) circuit (not shown) for detecting and correcting errors of the data "DATA". For example, in a write operation, the ECC circuit may generate error detection bits (eg, parity bits) for the data "DATA" received by the data transceiver 415 . During a read operation, the ECC circuit can detect and correct errors in the data "DATA" transmitted from the core die 420 by using the error detection bits, and can transmit the error-corrected data "DATA" to the data Transceiver 415.

As described above, before the write data strobe signal WDQS starts toggling, the stacked memory device 400 can internally write the data strobe signal dWDQS Initialized to reset value. In this case, the internal write data strobe signal dWDQS generated when the write data strobe signal WDQS is toggled can have a desired phase. As such, the stacked memory device 400 can adjust the phase of the internal write data strobe signal dWDQS without performing a separate automatic synchronization. The stacked memory device 400 can transmit and receive data "DATA" based on the internal write data strobe signal dWDQS having a desired phase.

14 is a more detailed exemplary block diagram illustrating the stacked memory device shown in FIG. 12, according to an embodiment. 14 , the stacked memory device 400 may include a buffer die 410 , a core die 420 (with respect to the embodiment shown in FIG. 14 , hereinafter referred to as “first core die 420 ”) and a second core die 430 . The first core die 420 and the second core die 430 may support the same channel CHa in multiple channels. In this case, the first core die 420 and the second core die 430 can be distinguished by using the stack identifier SID. For example, the first core die 420 may correspond to the first stack identifier SID0, and the second core die 430 may correspond to the second stack identifier SID1. An example is shown in FIG. 14 in which no other core die exists between the first core die 420 and the second core die 430 , but there may be between the first core die 420 and the second core die 430 sandwiched with any other core die.

The buffer die 410 and the first core die 420 and the second core die 430 can communicate with each other through the TSVs 402 and 403 placed in the TSV region 401 . For example, the buffer die 410 can transmit the internal command iCMD to the first core die 420 and/or the second core die 430 through the TSV 402, and can communicate with the first core die 420 and/or the second core die 430 through the TSV 403 The two core dies 430 exchange data "DATA". Figure 14 An example is shown in which the buffer die 410 communicates with the first core die 420 and the second core die 430 by using the same TSVs 402 and 403, but the buffer die 410 may communicate with the first core die respectively by using the same TSVs 402 and 403 The individual TSVs corresponding to the die 420 and the second core die 430 communicate with each other.

The second core die 430 may include a command decoder 431 , a data input/output (I/O) circuit 432 and a memory cell array 433 . The operations of the command decoder 431 , the data input/output circuit 432 and the memory cell array 433 may be substantially the same as the operations of the command decoder 421 , the data input/output circuit 422 and the memory cell array 423 of the core die 420 , as described with reference to FIG. 13 , and therefore, for the sake of brevity, will not be repeated here.

The C/A receiver 411 may receive the command CMD and the stack identifier SID by latching the command/address signal C/A based on the clock signal CK. The stack identifier SID may be an address indicating at least one core die for distinguishing core dies supporting the same channel. The received command CMD and stack identifier SID may be provided to control logic circuit 412 .

The control logic circuit 412 may transmit the internal command iCMD to at least one of the first core die 420 and the second core die 430 based on the stack identifier SID. For example, in the case where the stack identifier SID indicates the first stack identifier SID0 , the control logic circuit 412 may transmit the internal command iCMD to the first core die 420 .

In an exemplary embodiment, as shown in FIG. 14, in which the internal command iCMD and the data "DATA" are transmitted to the first via the common TSVs 402 and 403 In the case of a core die 420 and a second core die 430 , the buffer die 410 can transmit the stack identifier SID to the first core die 420 and the second core die 430 . The first core die 420 and the second core die 430 can decode the transmitted stack identifier SID to selectively receive the internal command iCMD and the data "DATA". For example, in the case where the stack identifier SID indicates the first stack identifier SID0 , the first core die 420 may receive the internal command iCMD and the data “DATA” transmitted through the TSVs 420 and 430 . In this case, the second core die 430 may not receive the internal command iCMD and the data "DATA" transmitted through the TSVs 420 and 430 .

In another embodiment, in the case where the internal command iCMD and the data "DATA" are transmitted to the first core die 420 and the second core die 430 by separate TSVs, the buffer die 410 may be transmitted by A separate TSV transmits the internal command iCMD and data "DATA" to the core die corresponding to the stack identifier SID.

As described above, in the case where the first core die 420 and the second core die 430 support the same channel CHa, the stacked memory device 400 can identify the first core die 420 and the second core according to the stack identifier SID At least one of the dies 430 performs a write operation and a read operation.

15 is a block diagram illustrating an embodiment of a buffer die of the stacked memory device shown in FIG. 13, according to an embodiment. 15, the buffer die 410 may include a command address input/output block AWORD and data input/output blocks DWORD0 to DWORD3. An example in which the buffer die 410 includes four data input/output blocks DWORD0 to DWORD3 is shown in FIG. 15 , but the number of data input/output blocks included in the buffer die 410 may be changed in various ways. For example, buffer die 410 may include two data input/output blocks.

The command address input/output block AWORD may include a C/A receiver 411 , a control logic circuit 412 and a clock tree 416 . The C/A receiver 411 may receive the command CMD by latching the command/address signal C/A received from the first pad P1 based on the clock signal CK received from the second pad P2. The control logic circuit 412 can generate the reset signal RESET based on the command CMD or the power state information PWS, and can transmit the reset signal RESET to the corresponding data input/output blocks DWORD0 to DWORD3. The control logic circuit 412 can generate the internal command iCMD according to the command CMD, and can transmit the internal command iCMD to the core die 420 . Clock tree 416 may be implemented with an inverter chain including multiple inverters. The internal clock signal iCK generated by the clock tree 416 based on the clock signal CK can be transmitted to the corresponding data input/output blocks DWORD0 to DWORD3.

Each of the data input/output blocks DWORD0 to DWORD3 can receive the internal clock signal iCK and the reset signal RESET from the command address input/output block AWORD. Each of the data input/output blocks DWORD0 through DWORD3 may include a WDQS divider 413 , an RDQS transmitter 414 and a data transceiver 415 . The WDQS frequency divider 413 can generate the internal write data strobe signal dWDQS based on the write data strobe signal WDQS received from the third pad P3. The WDQS frequency divider 413 can initialize the internal write data strobe signal dWDQS to a reset value in response to the reset signal RESET. The RDQS transmitter 414 can generate the read data strobe signal RDQS based on the internal write data strobe signal dWDQS. The read data strobe signal RDQS can be transmitted to the external host device through the fourth pad P4. data sending and receiving The device 415 may generate a data signal DQ including the data "DATA" transmitted from the core die 420 based on the internal write data strobe signal dWDQS. The data signal DQ can be transmitted to the external host device through the fifth pad P5.

As described above, the second pad P2 for receiving the clock signal CK can be placed at the command address input/output block AWORD, and thereby respectively receive the write data strobe signal WDQS and the read data strobe signal RDQS The third pad P3 and the fourth pad P4 can be placed at the data input/output block DWORD. The clock signal CK received by the command address input/output block AWORD can be transmitted to the data input/output block DWORD through the clock tree 416 . Thus, in the case where the read data strobe signal RDQS is generated based on the clock signal CK, since the inverter chain is placed on the path through which the clock signal CK is transmitted, power noise and process-voltage-temperature ( The effect of process-voltage-temperature, PVT) changes can increase. In the case where the read data strobe signal RDQS is generated based on the write data strobe signal WDQS received by the data input/output block DWORD, since there is no setting on the path through which the write data strobe signal WDQS is transmitted inverter chain, so the effects of power noise and PVT variations can be reduced. In this way, the reliability of reading the data strobe signal RDQS can be improved.

FIG. 16 is a diagram illustrating a semiconductor package according to an embodiment. 16 , a semiconductor package 1000 may include a stacked memory device 1100 , a system chip 1200 , an interposer 1300 and a package substrate 1400 . The stacked memory device 1100 may include a buffer die 1110 and core dies 1120-1150. The buffer die 1110 may correspond to the buffer die 310 shown in FIG. 12 , and the core dies 1120 to 1150 may correspond to should correspond to the core dies 320 to 350 shown in FIG. 12 .

Each of core dies 1120-1150 may include an array of memory cells. The buffer die 1110 may include a physical layer 1111 and a direct access area (DAB) 1112 . The physical layer 1111 may be electrically connected to the physical layer 1210 of the system die 1200 . Through the physical layer 1111 , the stacked memory device 1100 can receive signals from the SoC 1200 , or can transmit signals to the SoC 1200 . The physical layer 1111 may include the interface circuits of the buffer die 410 described with reference to FIG. 13 .

The direct access area 1112 may provide an access path capable of testing the stacked memory device 1100 without passing through the SoC 1200 . The direct access area 1112 may include conductive members (eg, ports or pins) that can communicate directly with external test devices. Test signals and data received through the direct access area 1112 may be transmitted to the core dies 1120-1150 through TSV. In order to test core dies 1120-1150, data read from core dies 1120-1150 may be transferred to a test device via TSV and direct access area 1112. As such, direct access testing can be performed on core dies 1120-1150.

The buffer die 1110 and the core die 1120 to 1150 can be electrically connected through the TSV 1101 and the bump 1102 . Buffer die 1110 may receive signals from system chip 1200 that are provided to each channel through bumps 1102 assigned to each channel. For example, bumps 1102 may be micro-bumps.

The system chip 1200 may execute the applications supported by the semiconductor package 1000 by using the stacked memory device 1100 . For example, the SoC 1200 may include a central processing unit (CPU), an application processor (application processor, AP), graphics processing unit (graphic processing unit, GPU), neural processing unit (neural processing unit, NPU), tensor processing unit (tensor processing unit, TPU), vision processing unit (vision processing unit, VPU) ), at least one of an image signal processor (image signal processor, ISP) or a digital signal processor (digital signal processor, DSP), and can perform specialized calculations.

The SoC 1200 may include a physical layer 1210 and a memory controller 1220 . The physical layer 1210 may include input/output circuits for exchanging signals with the physical layer 1111 of the stacked memory device 1100 . The system chip 1200 can provide various signals to the physical layer 1111 through the physical layer 1210 . The signals provided to the physical layer 1111 may be transmitted to the core dies 1120 to 1150 through the interface circuits of the physical layer 1111 and the TSV 1101 .

The memory controller 1220 may control the overall operation of the stacked memory device 1100 . The memory controller 1220 can provide signals for controlling the stacked memory device 1100 to the stacked memory device 1100 through the physical layer 1210 . The memory controller 1220 may correspond to the memory controller 100 shown in FIG. 1 .

The interposer 1300 may connect the stacked memory device 1100 and the SoC 1200 . The interposer 1300 can connect the physical layer 1111 of the stacked memory device 1100 and the physical layer 1210 of the system chip 1200, and can provide a physical path formed by using a conductive material. In this way, the stacked memory device 1100 and the system chip 1200 can be stacked on the interposer 1300 and can exchange signals with each other.

The bumps 1103 may be attached to the upper surface of the package substrate 1400, and the solder balls 1104 may be attached to the lower surface of the package substrate 1400 . For example, the bumps 1103 may be flip-chip bumps. The interposer 1300 may be stacked on the package substrate 1400 through the bumps 1103 . The semiconductor package 1000 can exchange signals with any other external package or semiconductor device via the solder balls 1104 . For example, the package substrate 1400 may be a printed circuit board (PCB).

FIG. 17 is a diagram illustrating an implementation example of a semiconductor package according to an embodiment. Referring to FIG. 17 , a semiconductor package 2000 may include a plurality of stacked memory devices 2100 and a system chip 2200 . The stacked memory device 2100 and the system chip 2200 may be stacked on the interposer 2300 , and the interposer 2300 may be stacked on the package substrate 2400 . The semiconductor package 2000 can exchange signals with any other external package or semiconductor device through the solder balls 2001 attached on the lower surface of the package substrate 2400 .

Each of the stacked memory devices 2100 may be implemented in compliance with the HBM standard. However, the embodiments are not so limited. For example, each of the stacked memory devices 2100 may be implemented based on GDDR, HMC, or wide I/O standards. Each of the stacked memory devices 2100 may correspond to the stacked memory devices 300 , 400 or 1100 shown in FIGS. 12-16 .

The system chip 2200 may include at least one processor (eg, CPU, AP, GPU, or NPU) and a plurality of memory controllers for controlling the plurality of stacked memory devices 2100 . The SoC 2200 can exchange signals with the corresponding stacked memory devices through the memory controller. The system wafer 2200 may correspond to the system wafer 1200 shown in FIG. 16 .

FIG. 18 is a diagram illustrating a semiconductor package according to another embodiment. ginseng As shown in FIG. 18 , a semiconductor package 3000 may include a stacked memory device 3100 , a host die 3200 and a package substrate 3300 . The stacked memory device 3100 may include a buffer die 3110 and core dies 3120-3150. Buffer die 3110 may include a physical layer 3111 for communicating with host die 3200, and each of core dies 3120-3150 may include an array of memory cells. The stacked memory device 3100 may correspond to the stacked memory devices 300 and 400 shown in FIGS. 12-13 .

The host die 3200 may include a physical layer 3210 for communicating with the stacked memory device 3100 and a memory controller 3220 for controlling the overall operation of the stacked memory device 3100 . Additionally, the host die 3200 may include a processor that controls the overall operation of the semiconductor package 3000 and executes applications supported by the semiconductor package 3000 . For example, host die 3200 may include at least one processor such as a CPU, AP, GPU, or NPU.

The stacked memory device 3100 may be disposed on the host die 3200 based on the TSV 3001 so as to be vertically stacked on the host die 3200 . In this way, the buffer die 3110 , the core dies 3120 to 3150 and the host die 3200 can be electrically connected through the TSV 3001 and the bump 3002 without an interposer. For example, bumps 3002 may be micro-bumps.

The bumps 3003 may be attached to the upper surface of the package substrate 3300 , and the solder balls 3004 may be attached to the lower surface of the package substrate 1400 . For example, the bumps 3003 may be flip chip bumps. The host die 3200 can be stacked on the package substrate 3300 through the bumps 3003 . The semiconductor package 3000 can exchange signals with any other external package or semiconductor device via the solder balls 3004 .

In another embodiment, the stacked memory device 3100 may be implemented with only the core dies 3120-3150 without the buffer die 3110. In this case, each of the core dies 3120-3150 may include interface circuitry for communicating with the host die 3200, as described with reference to FIGS. 1-15. Each of the core dies 3120 to 3150 can exchange signals with the host die 3200 through the TSV 3001 .

19 is a block diagram illustrating a computing system according to an embodiment. Computing system 4000 may be implemented with one electronic device, or may be distributed among and implemented with two or more electronic devices. For example, computing system 4000 may be implemented with at least one of various electronic devices, such as desktop computers, laptop computers, tablet computers, smartphones, autonomous vehicles, digital cameras, wearable devices, healthcare Devices, server systems, data centers, drones, handheld game consoles, Internet of Things (IoT) devices, graphics accelerators, AI accelerators.

Referring to FIG. 19 , a computing system 4000 may include a host 4100 , an accelerator subsystem 4200 , and an interconnect 4300 . The host 4100 may control the overall operation of the accelerator subsystem 4200 , and the accelerator subsystem 4200 may operate under the control of the host 4100 . Host 4100 and accelerator subsystem 4200 may be connected by interconnect 4300 . Various signals and data may be exchanged between the host 4100 and the accelerator subsystem 4200 through the interconnect 4300 .

The host 4100 may include a host processor 4110 , a host memory controller 4120 , a host memory 4130 and an interface 4140 . The host processor 4110 can control the The overall operation of the computing system 4000. The host processor 4110 can control the host memory 4130 through the host memory controller 4120 . For example, host processor 4110 may read data from host memory 4130 or may store data in host memory 4130 . Host processor 4110 can control accelerator subsystem 4200 connected by interconnect 4300. For example, host processor 4110 may transmit commands to accelerator subsystem 4200 and may assign tasks to accelerator subsystem 4200 .

Host processor 4110 may be a general-purpose or primary processor that performs general computations associated with various operations of computing system 4000 . For example, the host processor 4110 may be a CPU or an AP.

Host memory 4130 may be the main memory of computing system 4000 . Host memory 4130 may store data processed by host processor 4110 or may store data received from accelerator subsystem 4200. For example, host memory 4130 may be implemented using DRAM.

Interface 4140 may be configured to allow host 4100 to communicate with accelerator subsystem 4200. Through the interface 4140 , the host processor 4110 can transmit control signals and data to the accelerator subsystem 4200 and can receive signals and data from the accelerator subsystem 4200 . In an exemplary embodiment, host processor 4110, host memory controller 4120, and interface 4140 may be implemented using one chip.

The accelerator subsystem 4200 may perform certain functions under the control of the host 4100 . For example, accelerator subsystem 4200 may perform computations dedicated to a particular application under control of host 4100 . Accelerator subsystem 4200 may be implemented in various types such as module type, card type, package type, wafer type, and device type in order to Physically or electrically connected to the host 4100 , or connected to the host 4100 in a wired or wireless manner. For example, accelerator subsystem 4200 may be implemented using one of the semiconductor packages described with reference to FIGS. 16-18 . For example, accelerator subsystem 4200 may be implemented in the form of a graphics card or accelerator card. For example, accelerator subsystem 4200 may be implemented in the form of a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or the like.

In an exemplary embodiment, accelerator subsystem 4200 may be implemented by one of various packaging techniques. For example, accelerator subsystem 4200 may be implemented by packaging technologies such as ball grid array (BGA) technology, multi-chip package (MCP) technology, system on package, SOP) technology, system in package (SIP) technology, package on package (POP) technology, chip scale package (CSP) technology, wafer level package (WLP) ) technology or panel level package (PLP) technology. For example, all or some components of accelerator subsystem 4200 may be connected by copper-to-copper bonding. For example, all or some of the components of accelerator subsystem 4200 may be connected by interposers such as silicon interposers, organic interposers, glass interposers, or active interposers. For example, all or some components of accelerator subsystem 4200 may be stacked based on TSVs. For example, all or some of the components of accelerator subsystem 4200 may be connected by high-speed connection paths (eg, silicon bridges).

Accelerator subsystem 4200 may include dedicated processor 4210, local memory The system controller 4220, the local memory 4230 and the host interface 4240 are included. Special purpose processor 4210 may operate under the control of host processor 4110. For example, the dedicated processor 4210 can read data from the local memory 4230 through the local memory controller 4220 in response to commands from the host processor 4110 . The dedicated processor 4210 can process the read data by performing computations on the read data. The dedicated processor 4210 may transmit the processed data to the host processor 4110, or may store the processed data in the local memory 4230.

The special-purpose processor 4210 may perform computations specific to a particular application based on the values stored in the local memory 4230. For example, special purpose processor 4210 may perform computations specific to applications such as artificial intelligence, stream analysis, video transcoding, data indexing, data encoding/decoding, and data encryption. In this way, the dedicated processor 4210 can process various types of data such as image data, voice data, motion data, biological data, and key values. For example, the special purpose processor 4210 may include at least one of a GPU, NPU, TPU, VPU, ISP, and DSP.

Special-purpose processor 4210 may include one processor core, or may include multiple processor cores, such as dual-core, quad-core, or six-core. In an exemplary embodiment, special-purpose processor 4210 may include a greater number of cores than host processor 4110 for performing computations dedicated to parallelism. For example, special purpose processor 4210 may include 1000 or more cores.

In an exemplary embodiment, the dedicated processor 4210 may be a processor dedicated to image data computation. In this case, the dedicated processor 4210 can read the image data stored in the local memory 4230 through the local memory controller 4220 data, and can perform calculations on the read data. The dedicated processor 4210 may transmit the calculation result to the host processor 4110, or may store the calculation result in the local memory 4230. The host processor 4110 may store the transmitted calculation results in the host memory 4130 or in a frame buffer allocated to a separate memory. The data stored in the frame buffer can be sent to a separate display device.

In an exemplary embodiment, the special-purpose processor 4210 may be a processor dedicated to neural network-based training and inference. The dedicated processor 4210 can read neural network parameters (eg, neural network model parameters, weights, and biases) from the local memory 4230, and can perform training or inference on the read neural network parameters. The neural network parameters may be provided by the host processor 4110, may be values obtained through processing by the dedicated processor 4210, or may be pre-stored values. For example, host processor 4110 may provide weight parameters for inference to special purpose processor 4210. In this case, the weight parameter may be a parameter updated by the training of the host processor 4110 . The dedicated processor 4210 may perform training or inference by matrix multiplication and accumulation based on the neural network parameters of the local memory 4230 . The dedicated processor 4210 may transmit the calculation result to the host processor 4110, or may store the calculation result in the local memory 4230.

The local memory controller 4220 can control the overall operation of the local memory 4230 . In an exemplary embodiment, the local memory controller 4220 can process data to be written into the local memory 4230 and can write the processed data into the local memory 4230 . Alternatively, the local memory controller 4220 may process data read from the local memory 4230 . For example, the local memory controller 4220 can perform error correction code (ECC) encoding and ECC decoding, and can perform cyclic redundancy checking (cyclic redundancy check). redundancy check, CRC) method to verify data, or perform data encryption or data decryption. The local memory controller 4220 may correspond to the memory controller described with reference to FIGS. 1 to 18 . For example, for the write operation and the read operation of the local memory 4230 , the local memory controller 4220 may transmit a toggled write data strobe signal WDQS to the local memory 4230 . In this case, the sum of the number of preamble cycles written to the data strobe signal WDQS and the number of postamble cycles written to the data strobe signal WDQS may be an even number.

The local memory 4230 may be used by the dedicated processor 4210 only. In an exemplary embodiment, the local memory 4230 may be mounted on a substrate together with the dedicated processor 4210, or may be implemented in the form of a die, chip, package, module, card or device so as to be based on a separate connector Connect with the dedicated processor 4210. The local memory 4230 may correspond to the memory device or the stacked memory device described with reference to FIGS. 1 to 18 . For example, the local memory 4230 can divide the frequency of the write data strobe signal WDQS transmitted from the local memory controller 4220, and can generate the internal write data strobe signal dWDQS with different phases at low power. The local memory 4230 can communicate with the local memory controller 4220 based on the internal write data strobe signal dWDQS.

In an exemplary embodiment, the local memory 4230 may include 32 or more data pins. For example, to provide wide bandwidth, the local memory 4230 may include 1024 or more data pins. In this way, the busbar width of each chip of the local memory 4230 can be larger than the busbar width of each chip of the host memory 4130 .

In an exemplary embodiment, the local memory 4230 may be based on DDR, LPDDR, GDDR, HBM, HMC or wide I/O standard interface. However, the embodiments are not so limited. For example, the local memory 4230 may operate based on various standard interfaces.

In an exemplary embodiment, local memory 4230 may include logic circuitry capable of performing some computations. The logic circuit can perform linear operations, comparison operations, compression operations, data conversion operations, and arithmetic operations on the data read from the local memory 4230 or the data to be written into the local memory 4230 . In this way, the size of the data processed by the logic circuit can be reduced. In situations where the size of the data is reduced, the bandwidth efficiency between the local memory 4230 and the local memory controller 4220 can be improved.

Host interface 4240 may be configured to allow accelerator subsystem 4200 to communicate with host 4100. The accelerator subsystem 4200 can transmit signals and data to the host 4100 through the host interface 4240 , and can receive control signals and data from the host 4100 . In an exemplary embodiment, the dedicated processor 4210, the local memory controller 4220, and the host interface 4240 may be implemented using one chip.

Interconnect 4300 may provide a transmission path between host 4100 and accelerator subsystem 4200, and may perform the role of a data bus or data link. The data transmission path can be established in a wired or wireless manner. Interface 4140 and host interface 4240 can communicate via interconnect 4300 based on a given protocol. For example, the interfaces 4140 and 4240 can communicate with each other based on one of various standards such as: Advanced Technology Attachment (ATA), Serial ATA (SATA), external SATA (external SATA, e-SATA) ), Small Computer Small Interface (Small Computer Small Interface, SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnection (PCI), PCI Express (PCIe), NVM High-speed (NVM express, NVMe), Advanced eXtensible Interface (AXI), ARM Microcontroller Bus Architecture (AMBA), IEEE 1394, Universal Serial Bus (Universal Serial Bus, USB), Secure Digital (SD) card, multi-media card (MMC), embedded multi-media card (eMMC), Universal Flash Storage (UFS), Compact flash (compact flash, CF) and Gen-Z. Alternatively, interfaces 4140 and 4240 may communicate with each other based on inter-device communication links such as: Coherent Accelerator Processor Interface (openCAPI), Cache Coherent Interconnect for Accelerators , CCIX), Compute Express Link (CXL) and NVLINK. Alternatively, the interfaces 4140 and 4240 may communicate with each other based on wireless communication technologies such as: Long Term Evolution (LTE), ^5th generation (5G), LTE Machine-to-Machine (LTE-Machine) to Machine, LTE-M), Narrow Band-Internet of Things (NB-IoT), Low Power Wide Area Network (LPWAN), Bluetooth, Near Field Communication (Near Field Communication) Field Communication (NFC), Zigbee (Zigbee), Z-Wave (Z-Wave) or Wireless Local Area Network (WLAN).

In an exemplary embodiment, the accelerator subsystem 4200 may further include a sensor capable of sensing image data, voice data, motion data, biological data and surrounding environment information. In an exemplary embodiment, where the sensor is included in the accelerator subsystem 4200, the sensor may be interfaced with any other component (eg, dedicated processor 4210 or local memory 4230) based on the packaging techniques described above . The accelerator subsystem 4200 can process data sensed by sensors based on certain operations.

An example in which a dedicated processor 4210 uses a local memory 4230 via a local memory controller 4220 is shown in FIG. 19, but the embodiment is not limited thereto. For example, a dedicated processor 4210 may use multiple local memories through one local memory controller 4220. As another example, the dedicated processor 4210 may use the local memory by a plurality of local memory controllers respectively corresponding to the local memory.

To exchange data at high speed, memory devices according to various embodiments described herein may generate internal write data strobe signals based on write data strobe signals provided from the memory controller. In this case, the memory device can initialize the internal write data strobe signal to a given value, and thus can generate the internal write data strobe signal with the desired phase during write operations and read operations. In this way, the memory device may not perform automatic synchronization for adjusting the phase of the internal write data strobe signal alone. That is, the automatic synchronization and the circuit for implementing the automatic synchronization can be omitted. Therefore, the power consumption of the memory device can be reduced.

The memory device according to the various embodiments described above can generate the read data strobe signal to be provided to the memory controller based on the write data strobe signal, so Improved reliability of reading data strobe signals.

The memory controller according to the various embodiments described above can generate the clock signal and the write data strobe signal based on a phase-locked loop. As such, the power consumption of the memory controller can be reduced.

While various exemplary embodiments have been described, it will be apparent to those of ordinary skill in the art that the described embodiments can be made without departing from the spirit and scope of the invention as described in the following claims Various changes and retouches.

400: Stacked memory device

401:TSV area

402, 403: TSV

410: Buffer Die

411: Command/Address (CA) Receiver

412: Control Logic Circuit

413: Write data strobe signal (WDQS) frequency divider

414: read data strobe signal (RDQS) transmitter

415: Data Transceiver

420: core die/first core die

421, 431: Command Decoder

422, 432: Data input/output (I/O) circuits

423: Memory Cell Array

430: Core Die/Second Core Die

433: Memory Cell Array

C/A: command/address signal

CHa: channel

CK: clock signal

cmd:command

DATA: data

DQ: data signal

dWDQS: Internal write data strobe signal

iCMD: Internal Command

PWS: Power Status Information

RDQS: read data strobe signal

RESET: reset signal

SID: stack identifier

SID0: First stack identifier

SID1: Second stack identifier

WDQS: write data strobe signal

Claims (20)

A memory device includes: a buffer die configured to communicate with a host device through a plurality of channels; and a plurality of core dies stacked on the buffer die and connected to the buffer by through-silicon electrodes a die, each of the plurality of core dies including an array of memory cells corresponding to at least one of the plurality of channels, wherein the buffer die includes: a command/address receiver, is configured to receive a command provided from the host device to the first channel based on a clock signal provided from the host device to the first channel of the plurality of channels; the control logic circuit is configured to be based on The command received from the command/address receiver generates an internal command, and after a self-reboot, power-on, or power-off exit and upon receipt of a transfer from the host device to the first channel A reset signal is generated before the write data strobe signal that toggles between the two states; the write data strobe signal divider is configured to: generate a toggle based on the write data strobe signal and perform toggling a plurality of internal write data strobe signals, the plurality of internal write data strobe signals are respectively switched in two states with different phases; and the plurality of internal write data strobe signals are selected based on the reset signal and a data transceiver configured to receive write data provided to the first channel from the host device based on the plurality of internal write data strobe signals, wherein the plurality of The core die supporting the first channel among the core dies is configured configured to store the write data transmitted from the buffer die based on the internal command transmitted from the buffer die. The memory device of claim 1, wherein the control logic circuit is configured to generate the reset signal based on a command received from the command/address receiver or based on a power state of the memory device . The memory device of claim 2, wherein the control logic circuit is configured to generate the reset signal based on the power state of the memory device, and when the memory device is in a power-on state , the control logic circuit is configured to generate the reset signal. The memory device of claim 2, wherein the control logic circuit is configured to generate the reset signal based on the power state of the memory device, and when the first power state of the memory device The control logic circuit is configured to generate the reset signal when a channel is in a power-off exit state or a self-restart exit state. The memory device of claim 2, wherein the control logic circuit is configured to generate the reset signal based on the command received from the command/address receiver, and wherein the control logic circuit is configured to generate the reset signal based on at least one of an active command, a write command, a read command, and a divider reset command. The memory device of claim 1, wherein the sum of the number of preamble cycles of the write data strobe signal and the number of postamble cycles of the write data strobe signal is an even number. The memory device of claim 1, wherein the write data strobe signal maintains a static low value or a static high value before the write data strobe signal begins toggling. The memory device of claim 1, wherein the given value is defined based on a number of preamble cycles of the write data strobe signal. The memory device of claim 1, wherein based on the reset signal, the write data strobe signal divider is configured to initialize half of the plurality of internal write data strobe signals to low bits level and initialize the other half of the plurality of internal write data strobe signals to a high level. The memory device of claim 1, wherein the plurality of internal write data strobe signals include first internal write data strobe signals corresponding to phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees, respectively , the second internal write data strobe signal, the third internal write data strobe signal and the fourth internal write data strobe signal, and wherein the first internal write data strobe signal to the fourth internal The frequency of each of the write data strobe signals is half the frequency of the write data strobe signal. The memory device of claim 10, wherein the write data strobe signal divider comprises: a first latch, comprising: a first input terminal; a first output terminal, outputting the first internal write data strobe signal; and The second output terminal outputs the third internal write data strobe signal; the second latch includes: a second input terminal, connected to the first output terminal; and a third output terminal, outputting the second internal write data a strobe signal; and a fourth output terminal connected to the first input terminal and outputting a fourth internal write data strobe signal, wherein the first latch is configured to: based on the reset signal A reset value and a complementary reset value are output to the first output terminal and the second output terminal; and based on the rising edge of the write data strobe signal, all input through the first input terminal is the value and the complementary value of the fourth internal write data strobe signal are output to the first output terminal and the second output terminal, respectively; and wherein the second latch is configured to: based on the reset signal to output the reset value and the complementary reset value to the third output terminal and the fourth output terminal; and based on the rising edge of the complementary write data strobe signal The value and the complementary value of the first internal write data strobe signal input by the two input terminals are output to the third output terminal and the fourth output terminal, respectively. The memory device of claim 1, wherein the buffer die further comprises: a read data strobe signal transmitter, configured to generate a data strobe signal to be read by the plurality of internal write data strobe signals the first channel is provided to the host device read data strobe signals, wherein the data transceiver is configured to associate read data transmitted from the core die supporting the first channel with all of the read data strobe signals based on the plurality of internal write data strobe signals The toggling timing of the read data strobe signal is aligned to transmit the read data to the host device. The memory device of claim 1, wherein the frequency of the write data strobe signal is twice the frequency of the clock signal. The memory device of claim 1, wherein the buffer die includes 128 data pins configured to receive the write data and 8 select pins configured to receive the write data strobe signal Through pins, the 128 data pins and the 8 gate pins correspond to the first channel. A memory device includes: a buffer die configured to communicate with a host device through a plurality of channels; and a first core die stacked on the buffer die and connected to the buffer by through-silicon electrodes a die including a first array of memory cells corresponding to a first channel of the plurality of channels; and a second core die stacked on the first core die by the through silicon An electrode is connected to the first core die and includes a second array of memory cells corresponding to the first channel, wherein the buffer die includes a command/address receiver configured to The clock signal provided by the host device to the first channel is received from the host device and provided to the first channel a command and stack identifier for a first channel; control logic configured to generate an internal command based on the command received from the command/address receiver, and to provide an internal command from the host device to the first A reset signal is generated before the write data strobe signal of the channel starts toggling; the write data strobe signal divider is configured to: generate a toggling based on the write data strobe signal for toggling A plurality of switched internal write data strobe signals, the plurality of internal write data strobe signals are respectively switched in two states with different phases; and the plurality of internal write data strobes are selected based on the reset signal a communication signal initialized to a given value; and a data transceiver configured to receive write data provided to the first channel from the host device based on the plurality of internal write data strobe signals, wherein One of the first core die and the second core die corresponding to the stack identifier is configured to store all data transferred from the buffer die based on the internal command transferred from the buffer die. write data. The memory device of claim 15, wherein the control logic circuit generates the reset signal when the memory device is in a power-on state or a power-off state. The memory device of claim 15, wherein the sum of the number of preamble cycles of the write data strobe signal and the number of postamble cycles of the write data strobe signal is an even number. The memory device of claim 15, wherein based on the reset signal, the write data strobe signal divider initializes half of the plurality of internal write data strobe signals to a low level and initializes the other half of the plurality of internal write data strobe signals for high level. A memory device includes: a buffer die configured to communicate with a host device through a plurality of channels; and a plurality of core dies stacked on the buffer die and connected to the buffer by through-silicon electrodes A die, wherein each of the plurality of core dies includes an array of memory cells corresponding to at least one of the plurality of channels, wherein the buffer die is configured to: The clock signal provided by the host device to the first channel receives a command provided from the host device to the first channel; after the write data strobe signal provided by the host device to the first channel starts double Before the state switching, initialize a plurality of internal write data strobe signals to a given value; generate the plurality of internal write data strobes that perform two-state switching based on the two-state switching of the write data strobe signals signal, the plurality of internal write data strobe signals are toggled in different phases respectively; and based on the plurality of internal write data strobe signals, a signal provided from the host device to the first channel is received Write data, and wherein a core die of the plurality of core dies supporting the first channel is configured to store the received write data. The memory device of claim 19, wherein the sum of the number of preamble cycles of the write data strobe signal and the number of postamble cycles of the write data strobe signal is an even number.

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