TWI758167B - Package structure and manufacturing method thereof - Google Patents

Abstract

A package structure includes a redistribution layer, a chip assembly, a plurality of solder balls and a molding compound. The redistribution layer includes a plurality of redistribution circuits, a plurality of photoimageable dielectric layers, a plurality of conductive through holes and a plurality of chip pads. The photoimageable dielectric layers located on the two outermost sides respectively have an upper surface and a plurality of openings. The chip pads are located on the upper surface and electrically connected to the redistribution layers through the conductive through holes. The openings expose parts of the redistribution circuits to define a plurality of solder ball pads. A line width and a line pitch of the redistribution circuits become smaller from the solder ball pads to the chip pads. The chip assembly is disposed on the chip pads and includes at least two chips with different sizes. The solder balls are respectively disposed on the solder ball pads and the molding compound at least covers the chip assembly.

Description

Package structure and method of making the same

The present invention relates to a semiconductor structure and a manufacturing method thereof, and more particularly, to a packaging structure and a manufacturing method thereof.

In the prior art, when a chip-last (or RDL first) fan-out panel level package (FOPLP) is fabricated, thin lines for reconfiguring the circuit substrate are first fabricated on a temporary substrate. road. Next, after the general circuit of the reconfigured circuit substrate is fabricated, the reconfigured circuit substrate needs to be transferred from the original temporary substrate to another temporary substrate, and before the wafer and the reconfigured circuit substrate are bonded, debond the original the temporary substrate to expose the chip pads for electrical connection with the chip. However, in the process of turning the board, the reconfigured circuit substrate is prone to uneven expansion and contraction, which in turn affects the structural reliability of subsequent products.

The present invention provides a package structure, which can have better structural reliability.

The present invention also provides a method for fabricating a package structure, which is used to fabricate the aforementioned package structure.

The packaging structure of the present invention includes a reconfigured circuit layer, a chip component, a plurality of solder balls and a packaging colloid. The reconfiguration line layer includes a plurality of reconfiguration lines, a plurality of photosensitive dielectric layers, a plurality of conductive vias, and a plurality of die pads. The reconfiguration lines are alternately arranged with the photosensitive dielectric layers, and the conductive vias penetrate through the photosensitive dielectric layers and are electrically connected to the reconfiguration lines. One of the two opposite outermost photosensitive dielectric layers has an upper surface, and the chip pad is located on the upper surface and is electrically connected with the reconfiguration circuit through the conductive through hole. The other one of the two opposite outermost photosensitive dielectric layers has a plurality of openings, and the openings expose a part of the reconfiguration lines to define a plurality of solder ball pads. The line width and line spacing of the reconfiguration lines decrease from the solder ball pads to the die pads. The chip assembly is disposed on the chip pad and electrically connected to the chip pad, wherein the chip assembly includes at least two chips with different sizes. The solder balls are respectively arranged on the solder ball pads and are electrically connected to the solder ball pads. The encapsulant covers at least the chip assembly.

In an embodiment of the present invention, the above-mentioned reconfiguration line layer includes a first reconfiguration line layer, a second reconfiguration line layer, and a third reconfiguration line layer. The reconfiguration line includes a first reconfiguration line, a second reconfiguration line and a third reconfiguration line. The photosensitive dielectric layer includes a first photosensitive dielectric layer, a second photosensitive dielectric layer, a third photosensitive dielectric layer, and a fourth photosensitive dielectric layer. The conductive vias include a plurality of first conductive vias, a plurality of second conductive vias, and a plurality of third conductive vias. The first reconfiguration line layer includes a die pad, a first reconfiguration line, a first photosensitive dielectric layer, and a first conductive via penetrating the first photosensitive dielectric layer. The first photosensitive dielectric layer has an upper surface, and the chip pad is electrically connected to the first reconfiguration circuit through the first conductive through hole. The second reconfiguration line layer includes a second reconfiguration line, a second photosensitive dielectric layer, and a second conductive via penetrating the second photosensitive dielectric layer. The second conductive via electrically connects the first reconfiguration line and the second reconfiguration line. The third reconfiguration line layer includes a third reconfiguration line, a third photosensitive dielectric layer, a fourth photosensitive dielectric layer, and a third conductive via penetrating the third photosensitive dielectric layer. The third conductive via electrically connects the second reconfiguration line and the third reconfiguration line. The fourth photosensitive dielectric layer covers the third photosensitive dielectric layer and the third reconfiguration line and has an opening. The opening exposes a portion of the third reconfiguration line to define a solder ball pad. The line width and line spacing of the third reconfiguration line are larger than the line width and line spacing of the second reconfiguration line. The line width and line spacing of the second reconfiguration line are larger than those of the first reconfiguration line.

In an embodiment of the present invention, the line width and line spacing of the above-mentioned first reconfiguration lines are respectively 2 μm. The line width and line spacing of the second reconfiguration lines are respectively 5 microns. The line width and line spacing of the third reconfiguration lines are respectively 10 microns.

In an embodiment of the present invention, the thickness of the first reconfiguration line is equal to the thickness of the second reconfiguration line, and the thickness of the second reconfiguration line is smaller than the thickness of the third reconfiguration line.

In an embodiment of the present invention, the depth of the second conductive via is equal to the depth of the third conductive via, and the depth of the first conductive via is smaller than the depth of the second conductive via.

In an embodiment of the present invention, the periphery of the encapsulant is aligned with the periphery of the first reconfiguration circuit layer, the periphery of the second reconfiguration circuit layer, and the periphery of the third reconfiguration circuit layer.

In an embodiment of the present invention, the above-mentioned package structure further includes a plurality of copper pillars and a plurality of solders. The copper pillars are disposed on the chip assembly and between the chip assembly and the chip pads. The solder is disposed on the copper pillars and between the copper pillars and the chip pads.

In an embodiment of the present invention, the above-mentioned package structure further includes a primer disposed between the package compound and the reconfigured circuit layer. The primer covers the copper pillars, the solder and the chip pads, and the periphery of the primer is cut flush with the periphery of the encapsulant.

In an embodiment of the present invention, the above-mentioned chip assembly includes a processor and two memories, and the size of the processor is larger than that of each memory.

In an embodiment of the present invention, the above-mentioned package structure further includes a circuit board disposed below the reconfiguration circuit layer, and the chip components are electrically connected to the circuit board through solder balls.

The manufacturing method of the package structure of the present invention includes the following steps. A reconfiguration circuit layer is formed on a temporary carrier. The reconfiguration line layer includes a plurality of reconfiguration lines, a plurality of photosensitive dielectric layers, a plurality of conductive vias, and a plurality of die pads. The reconfiguration lines are alternately arranged with the photosensitive dielectric layers. The conductive through hole penetrates through the photosensitive dielectric layer and is electrically connected to the reconfiguration circuit. One of the two opposite outermost photosensitive dielectric layers has an upper surface, and the chip pad is located on the upper surface and is electrically connected to the reconfiguration circuit through the conductive through hole. The other of the two opposite outermost photosensitive dielectric layers is directly attached to the temporary carrier. A chip assembly is arranged on the chip pad and electrically connected to the chip pad, wherein the chip assembly includes at least two chips with different sizes. An encapsulant is formed to cover at least the chip assembly. The temporary carrier is removed after disposing the chip assembly on the chip pads to expose the other of the two opposite outermost photosensitive dielectric layers. A plurality of openings are formed in the other one of the two opposite outermost photosensitive dielectric layers to expose part of the reconfigured circuit and define a plurality of solder ball pads. The line width and line spacing of the reconfiguration lines decrease from the solder ball pads to the die pads. A plurality of solder balls are respectively formed on the solder ball pads to electrically connect the solder ball pads.

In an embodiment of the present invention, the above-mentioned reconfiguration line layer includes a first reconfiguration line layer, a second reconfiguration line layer, and a third reconfiguration line layer. The reconfiguration line includes a first reconfiguration line, a second reconfiguration line and a third reconfiguration line. The photosensitive dielectric layer includes a first photosensitive dielectric layer, a second photosensitive dielectric layer, a third photosensitive dielectric layer, and a fourth photosensitive dielectric layer. The conductive vias include a plurality of first conductive vias, a plurality of second conductive vias, and a plurality of third conductive vias. The step of forming the reconfigured circuit layer on the temporary carrier includes providing a temporary carrier, and the temporary carrier includes a base material and a release film on the base material. A third reconfiguration circuit layer is formed on the temporary carrier, and the third reconfiguration circuit layer includes a third reconfiguration circuit, a third photosensitive dielectric layer, a fourth photosensitive dielectric layer, and a third photosensitive dielectric layer extending through the third photosensitive dielectric layer. conductive vias. The fourth photosensitive dielectric layer covers the third photosensitive dielectric layer and the third reconfiguration circuit. A second reconfiguration line layer is formed on the third reconfiguration line layer. The second reconfiguration line layer includes a second reconfiguration line, a second photosensitive dielectric layer, and a second conductive via penetrating the second photosensitive dielectric layer. The second reconfiguration line is formed simultaneously with the third conductive via. The third conductive via electrically connects the second reconfiguration line and the third reconfiguration line. A first reconfiguration line layer is formed on the second reconfiguration line layer. The first reconfiguration line layer includes a die pad, a first reconfiguration line, a first photosensitive dielectric layer, and a first conductive via penetrating the first photosensitive dielectric layer. The first photosensitive dielectric layer has an upper surface, and the chip pad is electrically connected to the first reconfiguration circuit through the first conductive through hole. The first reconfiguration line is formed simultaneously with the second conductive via. The second conductive via electrically connects the first reconfiguration line and the second reconfiguration line. The die pads are formed simultaneously with the first conductive vias. The line width and line spacing of the third reconfiguration line are larger than the line width and line spacing of the second reconfiguration line. The line width and line spacing of the second reconfiguration line are larger than those of the first reconfiguration line.

In an embodiment of the present invention, the line width and line spacing of the above-mentioned first reconfiguration lines are respectively 2 μm. The line width and line spacing of the second reconfiguration lines are respectively 5 microns. The line width and line spacing of the third reconfiguration lines are respectively 10 microns.

In an embodiment of the present invention, the thickness of the first reconfiguration line is equal to the thickness of the second reconfiguration line, and the thickness of the second reconfiguration line is smaller than the thickness of the third reconfiguration line.

In an embodiment of the present invention, the depth of the second conductive via is equal to the depth of the third conductive via, and the depth of the first conductive via is smaller than the depth of the second conductive via.

In an embodiment of the present invention, the step of forming the opening includes: performing a drilling process on the fourth photosensitive dielectric layer to form an opening exposing a portion of the third reconfiguration circuit.

In an embodiment of the present invention, before disposing the chip components on the chip pads, it further includes forming a plurality of copper pillars on at least two chips of a wafer, and forming a plurality of solders on the copper pillars. The copper pillars are located between the at least two die and the solder.

In an embodiment of the present invention, before forming the encapsulant to at least cover the chip components, it further includes forming a primer on the reconfiguration circuit layer to cover the copper pillars, the solder and the chip pads.

In an embodiment of the present invention, the above-mentioned chip assembly includes a processor and two memories, and the size of the processor is larger than that of each memory.

In an embodiment of the present invention, the above-mentioned manufacturing method of the package structure further includes providing a circuit board below the reconfiguration circuit layer, wherein the chip component is electrically connected to the circuit board through solder balls.

Based on the above, in the package structure and the manufacturing method thereof of the present invention, the reconfiguration circuit layer is formed on the temporary carrier, and the temporary carrier is removed after the chip components are arranged on the chip pads. In other words, in the present invention, the relocation lines for forming solder ball pads are fabricated first, and then the relocation lines for forming chip pads are fabricated. Therefore, the present invention does not need a turning plate, which can make the package structure have better structural reliability.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

FIG. 1 is a schematic top view of a package structure according to an embodiment of the present invention. 2A to 2Z are schematic cross-sectional views of a method for fabricating a package structure according to an embodiment of the present invention. It should be noted that FIGS. 2A to 2Z are schematic cross-sectional views along the line I-I in FIG. 1 . Regarding the manufacturing method of the package structure of the present embodiment, first, referring to FIG. 2S , a reconfiguration line layer RDL is formed on a temporary carrier 10 , wherein the reconfiguration line layer RDL includes a first reconfiguration line layer 110 , a first The dual reconfiguration wiring layer 120 and a third reconfiguration wiring layer 130 .

In detail, please refer to FIG. 2A , a temporary carrier 10 is provided, wherein the temporary carrier 10 includes a substrate 12 and a release film 14 on the substrate 12 . The substrate 12 is, for example, a glass substrate, but not limited thereto. Next, a fourth photosensitive dielectric layer 138 and a first seed layer S1 thereon are formed on the release film 14 of the temporary carrier 10 .

Next, referring to FIG. 2B , a first patterned photoresist layer P1 is formed on the first seed layer S1 , wherein the first patterned photoresist layer P1 exposes part of the first seed layer S1 .

Next, referring to FIG. 2C , using the first patterned photoresist layer P1 as a plating mask, a first metal layer M1 is plated on the first seed layer S1 where the first patterned photoresist layer P1 is not disposed.

Next, referring to FIG. 2C and FIG. 2D at the same time, the first patterned photoresist layer P1 and the first seed layer S1 thereunder are removed, and a part of the fourth photosensitive dielectric layer 138 is exposed, and a third reconfiguration is formed Line 132.

Next, referring to FIG. 2E , a third photosensitive dielectric layer 134 is formed on the third reconfiguration circuit 132 and the exposed fourth photosensitive dielectric layer 138 . Here, the third photosensitive dielectric layer 134 has a plurality of openings 135 , wherein the openings 135 expose part of the third reconfiguration lines 132 .

Next, referring to FIG. 2F , a second seed layer S2 is formed on the third photosensitive dielectric layer 134 , wherein the second seed layer S2 covers the third photosensitive dielectric layer 134 and the inner wall of the opening 135 .

Next, referring to FIG. 2G , a second patterned photoresist layer P2 is formed on the second seed layer S2 , wherein the second patterned photoresist layer P2 exposes a part of the second seed layer S2 .

Next, referring to FIG. 2H , using the second patterned photoresist layer P2 as a plating mask, a second metal layer M2 is plated on the second seed layer S2 where the second patterned photoresist layer P2 is not disposed.

Next, please refer to FIG. 2H and FIG. 2I at the same time, remove the second patterned photoresist layer P2 and the second seed layer S2 under it, and expose a part of the third photosensitive dielectric layer 134 , and form the opening 135 . A plurality of third conductive vias 136 and a second reconfiguration line 122 on the third photosensitive dielectric layer 134 . Here, the third conductive via 136 and the second reconfiguration line 122 are formed at the same time, and the third conductive via 136 is electrically connected to the third reconfiguration line 132 and the second reconfiguration line 122 . So far, the third reconfiguration circuit layer 130 has been formed on the temporary carrier 10 , wherein the third reconfiguration circuit layer 130 includes the third reconfiguration circuit 132 , the third photosensitive dielectric layer 134 , and the third photosensitive dielectric layer 134 penetrating through the third photosensitive dielectric layer 134 . the third conductive via 136 and the fourth photosensitive dielectric layer 138 covering the third photosensitive dielectric layer 134 and the third reconfiguration line 132 .

In particular, in this embodiment, the line width and line spacing of the third reconfiguration lines 132 are larger than those of the second reconfiguration lines 122 . Preferably, the line width and line spacing of the second reconfiguration lines 122 are, for example, 5 μm, respectively, and the line width and line spacing of the third reconfiguration lines 132 are, for example, 10 μm, respectively. Furthermore, the thickness T2 of the second reconfiguration line 122 is smaller than the thickness T3 of the third reconfiguration line 132 , wherein the thickness T2 of the second reconfiguration line 122 is, for example, 2.5 μm, and the thickness T3 of the third reconfiguration line 132 is, for example, 2.5 μm. 8 microns. In addition, the depth D3 of the third conductive via 136 is, for example, 6.5 μm.

Next, referring to FIG. 2J , a second photosensitive dielectric layer 124 is formed on the second reconfiguration circuit 122 and the exposed third photosensitive dielectric layer 134 . Here, the second photosensitive dielectric layer 124 has a plurality of openings 125 , wherein the openings 125 expose part of the second reconfiguration lines 122 .

Next, referring to FIG. 2K , a third seed layer S3 is formed on the second photosensitive dielectric layer 124 , wherein the third seed layer S3 covers the second photosensitive dielectric layer 124 and the inner wall of the opening 125 .

Next, referring to FIG. 2L, a third patterned photoresist layer P3 is formed on the third seed layer S3, wherein the third patterned photoresist layer P3 exposes part of the third seed layer S3.

Next, referring to FIG. 2M , using the third patterned photoresist layer P3 as an electroplating mask, a third metal layer M3 is electroplated on the third seed layer S3 where the third patterned photoresist layer P3 is not disposed.

Next, please refer to FIG. 2M and FIG. 2N at the same time, remove the third patterned photoresist layer P3 and the third seed layer S3 thereunder, and expose part of the second photosensitive dielectric layer 124 , and form in the opening 125 A plurality of second conductive vias 126 and a first reconfiguration line 112 on the second photosensitive dielectric layer 124 . Here, the second conductive via 126 is formed simultaneously with the first reconfiguration line 112 , and the second conductive via 126 is electrically connected to the second reconfiguration line 122 and the first reconfiguration line 112 . So far, the second reconfiguration line layer 120 has been formed on the third reconfiguration line layer 130 , wherein the second reconfiguration line layer 120 includes the second reconfiguration line 122 , the second photosensitive dielectric layer 124 and the second photosensitive dielectric layer through the second photosensitive dielectric layer 120 . The second conductive via 126 of the electrical layer 124 .

In particular, the line width and line spacing of the second reconfiguration lines 122 are larger than those of the first reconfiguration lines 112 . Preferably, the line width and line spacing of the first reconfiguration lines 112 are, for example, 2 microns, respectively. Furthermore, the thickness T1 of the first reconfiguration line 112 is equal to the thickness T2 of the second reconfiguration line 122 , that is, the thickness T2 of the first reconfiguration line 112 is 2.5 μm. In addition, the depth D2 of the second conductive via 126 is equal to the depth D3 of the third conductive via 136 , that is, the depth D2 of the second conductive via 126 is, for example, 6.5 μm.

Next, referring to FIG. 20 , a first photosensitive dielectric layer 114 is formed on the first reconfiguration circuit 112 and the exposed second photosensitive dielectric layer 124 . Here, the first photosensitive dielectric layer 114 has a plurality of openings 115 , wherein the openings 115 expose part of the first reconfiguration lines 112 .

Next, referring to FIG. 2P , a fourth seed layer S4 is formed on the first photosensitive dielectric layer 114 , wherein the fourth seed layer S4 covers the first photosensitive dielectric layer 114 and the inner wall of the opening 115 .

Next, referring to FIG. 2Q, a fourth patterned photoresist layer P4 is formed on the fourth seed layer S4, wherein the fourth patterned photoresist layer P4 exposes part of the fourth seed layer S4.

Next, referring to FIG. 2R , using the fourth patterned photoresist layer P4 as a plating mask, a fourth metal layer M4 is plated on the fourth seed layer S4 without the fourth patterned photoresist layer P4 .

Next, referring to FIG. 2R and FIG. 2S at the same time, the fourth patterned photoresist layer P4 and the fourth seed layer S4 thereunder are removed to expose part of the first photosensitive dielectric layer 114 , and form the opening 115 . A plurality of first conductive vias 116 and a plurality of die pads 118 on the first photosensitive dielectric layer 114 . Here, the first conductive vias 116 and the die pads 118 are formed at the same time, and the first conductive vias 116 are electrically connected to the first reconfiguration lines 112 and the die pads 118 . In particular, the depth D1 of the first conductive via 116 is smaller than the depth D2 of the second conductive via 126 , wherein the depth D1 of the first conductive via 116 is, for example, 5 μm. The size of the die pad 118 is, for example, 35 microns, and the thickness T4 of the die pad 118 is, for example, 8 microns. So far, the first reconfiguration line layer 110 has been formed on the second reconfiguration line layer 120 , wherein the first reconfiguration line layer 110 includes the first reconfiguration line 112 , the first photosensitive dielectric layer 114 , and the first photosensitive dielectric The first conductive vias 116 of the electrical layer 114 and the die pads 118 .

Next, referring to FIG. 2T, a surface treatment layer E1 is formed on the chip pads 118 to protect the chip pads 118 from being oxidized. Here, the material of the surface treatment layer E1 is, for example, nickel palladium immersion gold (ENEPIG), organic solderability preservatives (OSP) or electroless nickel immersion gold (ENIG), but not the same limited.

Next, please refer to FIG. 1 and FIG. 2U at the same time, a chip assembly is disposed on the chip pads 118 , wherein the chip assembly includes a processor 140 and two memories 150 , and the size of the processor 140 is larger than that of the memory 150 . Here, the size of the processor 140 is, for example, 10 mm×10 mm, and the size of the memory 150 is, for example, 5 mm×7 mm, and the processor 140 and the memory 150 are application chipsets for mobile applications. More specifically, before disposing the chip components on the chip pads 118 , a plurality of copper pillars C are formed on the processor 140 and the memory 150 of a wafer. Next, a plurality of solders S are formed on the copper pillars C, wherein the copper pillars C are located between the solder S and the processor 140 and the memory 150 . After that, the processor 140 and the memory 150 are bonded to the surface treatment layer E1 on the chip pad 118 through the solder S on the copper pillar C, so that the processor 140 and the memory 150 are electrically connected to the chip pad 118 .

It should be noted that, in an embodiment, the wafer is cut into chips after the copper pillars C and the solder S are formed, so the copper pillars C and the solder S formed on the wafer before singulation can be called a wafer Wafer bumping. When the wafers are singulated to form independent chips (eg, the processor 140 and the memory 150 ), the solder S can be directly assembled on the chip pads 118 . In another embodiment, the dicing of the wafer into chips can also be performed before the copper pillars C and the solder S are formed, which still falls within the scope of the present invention.

Next, referring to FIG. 2V , a primer 160 is formed on the reconfiguration circuit layer RDL to cover the copper pillars C, the solder S, the surface treatment layer E1 and the chip pads 118 . Next, an encapsulant 170 is formed to cover at least the processor 140 and the memory 150 , wherein the encapsulant 170 covers the processor 140 , the memory 150 and the primer 160 .

2V and 2W, the temporary carrier 10 is removed to expose the fourth photosensitive dielectric layer 138, wherein the temporary carrier 10 is removed by, for example, laser debond, and The fourth photosensitive dielectric layer 138 is exposed. Here, before the temporary carrier 10 is removed, the temporary carrier 20 can be selectively disposed on the encapsulant 170 to increase the overall structural strength, wherein the temporary carrier 20 includes a base material 22 and is located on the base material 22 of a release film 24.

Next, referring to FIG. 2X , a drilling process is performed on the fourth photosensitive dielectric layer 138 to form an opening 139 exposing a portion of the third reconfiguration circuit 132 . Next, by etching, the first seed layer S1 in the third reconfigured circuit layer 132 exposed by the opening 139 is removed (please refer to FIG. 2A ), and part of the first metal layer M1 is exposed (please refer to FIG. 2A ). 2C) to define multiple solder ball pads SP. Here, the fourth photosensitive dielectric layer 138 can be regarded as a solder resist layer, and the drilling process is, for example, carbon dioxide laser drilling, but not limited thereto. Preferably, the thickness T5 of the fourth photosensitive dielectric layer 138 is, for example, 5 μm, and the diameter of the opening 139 is, for example, 245 μm to 250 μm.

Next, referring to FIG. 2Y , a surface treatment layer E2 is formed on the solder ball pads SP to protect the solder ball pads SP from being oxidized. Here, the material of the surface treatment layer E2 is, for example, nickel palladium immersion gold (ENEPIG), organic solder resist (OSP) or electroless nickel immersion gold (ENIG), but not limited thereto.

After that, please refer to FIG. 2Y and FIG. 2Z at the same time, a plurality of solder balls 180 are respectively formed on the surface treatment layer E2 of the solder ball pads SP to be electrically connected to the solder ball pads SP. Finally, if the temporary carrier 20 is provided, the temporary carrier 20 can be removed to expose the encapsulant 170 . The method of removing the temporary carrier 20 is, for example, peeling off the release film 24 to expose the encapsulant 170 . So far, the fabrication of the package structure 100a has been completed.

Structurally, please refer to FIG. 2Z again, the package structure 100 a of the present embodiment includes a reconfigured circuit layer RDL, a chip component, solder balls 180 and an encapsulant 170 . The reconfiguration line layer RDL includes a plurality of reconfiguration lines, a plurality of photosensitive dielectric layers, a plurality of conductive vias, and a plurality of die pads 118 , wherein the reconfiguration lines and the photosensitive dielectric layers are alternately arranged, and the conductive vias pass through the photosensitive dielectric layers. The dielectric layer is electrically connected to the reconfiguration circuit. Further, the reconfiguration line layer RDL includes a first reconfiguration line layer 110 , a second reconfiguration line layer 120 and a third reconfiguration line layer 130 . The reconfiguration lines include a first reconfiguration line 112 , a second reconfiguration line 122 and a third reconfiguration line 132 . The photosensitive dielectric layer includes a first photosensitive dielectric layer 114 , a second photosensitive dielectric layer 124 , a third photosensitive dielectric layer 134 and a fourth photosensitive dielectric layer 138 . The conductive vias include a first conductive via 116 , a second conductive via 126 and a third conductive via 136 . The first reconfiguration line layer 110 includes die pads 118 , a first reconfiguration line 112 , a first photosensitive dielectric layer 114 , and a first conductive via 116 penetrating the first photosensitive dielectric layer 114 . The first photosensitive dielectric layer 114 has an upper surface 117 , and the die pads 118 are electrically connected to the first reconfiguration lines 112 through the first conductive vias 116 . The second reconfiguration line layer 120 includes a second reconfiguration line 122 , a second photosensitive dielectric layer 124 , and a second conductive via 126 penetrating the second photosensitive dielectric layer 124 . The second conductive via 126 electrically connects the first reconfiguration line 112 and the second reconfiguration line 122 . The third reconfiguration line layer 130 includes a third reconfiguration line 132 , a third photosensitive dielectric layer 134 , a fourth photosensitive dielectric layer 138 , and a third conductive via 136 penetrating the third photosensitive dielectric layer 134 . The third conductive via 136 is electrically connected to the second reconfiguration line 122 and the third reconfiguration line 132 . The fourth photosensitive dielectric layer 138 covers the third photosensitive dielectric layer 134 and the third reconfiguration line 132 and has an opening 139 . The opening 139 exposes a portion of the third reconfiguration line 132 to define the solder ball pad SP. Here, the two outermost photosensitive dielectric layers of the reconfiguration line layer RDL are the first photosensitive dielectric layer 114 and the fourth photosensitive dielectric layer 138 respectively, wherein the first photosensitive dielectric layer 114 has an upper surface 117 , and The fourth photosensitive dielectric layer 138 has openings 139 .

In particular, in this embodiment, the line width and line spacing of the reconfiguration lines become smaller in the direction from the solder ball pads SP to the die pads 118 . That is, the line width and line spacing of the third reconfiguration line 132 are larger than those of the second reconfiguration line 122 , and the line width and line spacing of the second reconfiguration line 122 are larger than those of the first reconfiguration line 112 . Line width and line spacing. Preferably, the line width and line spacing of the first reconfiguration lines 112 are, for example, 2 μm, respectively, the line width and line spacing of the second reconfiguration lines 122 are, for example, 5 μm, respectively, and the line width of the third reconfiguration line is, for example, 5 μm, respectively. The line spacing is, for example, 10 μm, respectively. Furthermore, the thickness T1 of the first reconfiguration line 112 is equal to the thickness T2 of the second reconfiguration line 122 , and the thickness T2 of the second reconfiguration line 122 is smaller than the thickness T3 of the third reconfiguration line 132 . In addition, the depth D2 of the second conductive via 126 is equal to the depth D3 of the third conductive via 136 , and the depth D1 of the first conductive via 116 is smaller than the depth D2 of the second conductive via 126 .

Referring to FIG. 2Z again, the chip assembly is disposed on the chip pad 118 and is electrically connected to the chip pad 118 , wherein the chip assembly includes a processor 140 and a memory 150 , and the size of the processor 140 is larger than that of each memory 150 . In order to avoid oxidation of the die pads 118 , the package structure 100 a of this embodiment further includes a surface treatment layer E1 disposed on the die pads 118 . Furthermore, the package structure 100a of the present embodiment further includes a copper pillar C and a solder S, wherein the copper pillar C is disposed on the chip component and between the chip component and the chip pad 118 , and the solder S is disposed on the copper pillar C and between the copper pillar C and the die pad 118 . The processor 140 and the memory 150 are electrically connected to the chip pads 118 through the copper pillars C, the solder S and the surface treatment layer E1. In order to protect the copper pillars C, the solder S, the surface treatment layer E1 and the chip pads 118, the package structure 100a of this embodiment may further include an underfill 160 to cover the copper pillars C, the solder S, the surface treatment layer E1 and the chip bonding pads 118. The encapsulant 170 covers the processor 140 , the memory 150 and the primer 160 , wherein the primer 160 is disposed between the encapsulant 170 and the reconfiguration circuit layer RDL, and the periphery of the primer 160 is aligned with the periphery of the encapsulant 170 . Here, the periphery of the encapsulant 170 is aligned with the periphery of the first reconfiguration wiring layer 110 , the periphery of the second reconfiguration wiring layer 120 , and the periphery of the third reconfiguration wiring layer 130 . In addition, the solder balls 180 are respectively disposed on the solder ball pads SP, and are electrically connected to the solder ball pads SP.

In short, in this embodiment, the reconfiguration line layer RDL is formed on the temporary carrier 10 first, and the temporary carrier 10 is removed after the chip components are disposed on the chip pads 118 . That is to say, the third redistribution circuit 132 for forming the solder ball pads SP is formed first, and then the chip pads 118 are formed. Therefore, the present embodiment does not need a turning board, so that the package structure 100a can have better structural reliability. Furthermore, since the reconfiguration wiring layer RDL is formed on the temporary carrier 10, the reconfiguration wiring layer RDL can be very rigid and flat, so that the solder S between the chip components and the reconfiguration wiring layer RDL can be reflowed, and the reconfiguration wiring layer RDL can be reflowed. higher throughput. In addition, compared with the existing package-on-package (POP), the package structure 100a formed by the chip assembly and the reconfigured circuit layer RDL of the present embodiment does not require stacking (ie, the processor 140 and the memory). The body 150 can be placed on the same substrate), so it can have a lower manufacturing cost, a small package size, and a shorter overall signal transmission path, resulting in better performance.

It must be noted here that the following embodiments use the element numbers and part of the contents of the previous embodiments, wherein the same numbers are used to represent the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted part, reference may be made to the foregoing embodiments, and repeated descriptions in the following embodiments will not be repeated.

3 is a schematic cross-sectional view of a package structure according to another embodiment of the present invention. Please refer to FIG. 2Z and FIG. 3 at the same time. The package structure 100a of the present embodiment is similar to the package structure 100b described above. The difference between the two is that in the present embodiment, a circuit board 190 is further included in the reconfiguration circuit layer RDL. Below, the processor 140 and the memory 150 can be electrically connected to the circuit board 190 through the solder balls 180 .

To sum up, in the present invention, the reconfiguration circuit layer is first formed on the temporary carrier, and the temporary carrier is removed after the chip components are disposed on the chip pads. That is to say, the third redistribution circuit for forming the solder ball pads is fabricated first, and then the chip pads are fabricated. Therefore, the present invention does not need a turning plate, which can make the package structure have better structural reliability. In addition, because the reconfiguration wiring layer is formed on the temporary carrier, the reconfiguration wiring layer can be very rigid and flat, thereby enabling solder reflow between the chip components and the reconfiguration wiring layer, which can have a higher yield (high throughput).

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the scope of the appended patent application.

10: Temporary carrier 12: Substrate 14: Release film 20: Temporary carrier 22: Substrate 24: release film 100a, 100b: Package structure 110: The first reconfiguration line layer 112: The first reconfiguration line 114: the first photosensitive dielectric layer 115: Opening 116: first conductive via 117: Upper surface 118: Chip pads 120: Second reconfiguration line layer 122: Second reconfiguration line 124: the second photosensitive dielectric layer 125: Opening 126: Second conductive via 130: The third reconfiguration line layer 132: Third reconfiguration line 134: the third photosensitive dielectric layer 135: Opening 136: Third conductive via 138: Fourth photosensitive dielectric layer 139: Opening 140: Processor 150: memory 160: Primer 170: Encapsulating colloid 180: Solder Ball 190: circuit board C: copper pillar D1, D2, D3: Depth E1, E2: Surface treatment layer M1: first metal layer M2: Second metal layer M3: third metal layer M4: Fourth metal layer P1: first patterned photoresist layer P2: Second patterned photoresist layer P3: Third patterned photoresist layer P4: Fourth patterned photoresist layer S: Solder S1: The first sublayer S2: Second seed layer S3: The third seed layer S4: Fourth seed layer SP: Solder Ball Pad T1, T2, T3, T4, T5: Thickness RDL: Reconfiguration Line Layer

FIG. 1 is a schematic top view of a package structure according to an embodiment of the present invention. 2A to 2Z are schematic cross-sectional views of a method for fabricating a package structure according to an embodiment of the present invention. 3 is a schematic cross-sectional view of a package structure according to another embodiment of the present invention.

100a: Package structure

110: The first reconfiguration line layer

112: The first reconfiguration line

114: the first photosensitive dielectric layer

116: first conductive via

117: Upper surface

118: Chip pads

120: Second reconfiguration line layer

122: Second reconfiguration line

124: the second photosensitive dielectric layer

126: Second conductive via

130: The third reconfiguration line layer

132: Third reconfiguration line

134: the third photosensitive dielectric layer

136: Third conductive via

138: Fourth photosensitive dielectric layer

139: Opening

140: Processor

150: memory

160: Primer

170: Encapsulating colloid

180: Solder Ball

C: copper pillar

E1, E2: Surface treatment layer

S: Solder

SP: Solder Ball Pad

RDL: Reconfiguration Line Layer

Claims (20)

A package structure, comprising: a reconfiguration circuit layer, including a plurality of reconfiguration circuits, a plurality of photosensitive dielectric layers, a plurality of conductive vias and a plurality of chip pads, the reconfiguration circuits are alternated with the photosensitive dielectric layers configuration, the conductive vias pass through the photosensitive dielectric layers and are electrically connected to the reconfiguration lines, wherein one of the photosensitive dielectric layers located at the opposite two outermost sides has an upper surface, and the chip pads The upper surface is electrically connected to the reconfiguration lines through the conductive vias, and the other one of the photosensitive dielectric layers located on the opposite outermost sides has a plurality of openings, and the openings expose part of the The reconfiguration lines define a plurality of solder ball pads, and the line widths and line spacings of the reconfiguration lines become smaller in the direction from the solder ball pads to the chip pads; a chip component is disposed on the The chip pads are on and electrically connected to the chip pads, wherein the chip assembly includes at least two chips with different sizes; a plurality of solder balls are respectively disposed on the solder ball pads and electrically connected to the chip pads. solder ball pads; an encapsulant covering at least the chip assembly; and a primer disposed between the encapsulant and the reconfigured circuit layer, wherein the periphery of the primer is aligned with the periphery of the encapsulant. The packaging structure of claim 1, wherein the reconfiguration line layer includes a first reconfiguration line layer, a second reconfiguration line layer, and a third reconfiguration line layer, and the reconfiguration lines include a first reconfiguration line layer reconfiguration lines, a second reconfiguration line and a third reconfiguration line, the photosensitive dielectric layers include a first photosensitive dielectric electrical layer, a second photosensitive dielectric layer, a third photosensitive dielectric layer and a fourth photosensitive dielectric layer, the conductive vias include a plurality of first conductive vias, a plurality of second conductive vias and a plurality of a third conductive via; the first reconfiguration line layer includes the chip pads, the first reconfiguration line, the first photosensitive dielectric layer, and the first conductive layers penetrating the first photosensitive dielectric layer through holes, the first photosensitive dielectric layer has the upper surface, the chip pads are electrically connected to the first reconfiguration circuit through the first conductive through holes; the second reconfiguration circuit layer includes the second reconfiguration circuit reconfiguration lines, the second photosensitive dielectric layer, and the second conductive vias penetrating the second photosensitive dielectric layer, the second conductive vias electrically connecting the first reconfiguration line and the second reconfiguration line a configuration circuit; the third reconfiguration circuit layer includes the third reconfiguration circuit, the third photosensitive dielectric layer, the fourth photosensitive dielectric layer, and the third conductive vias penetrating the third photosensitive dielectric layer , the third conductive vias are electrically connected to the second reconfiguration line and the third reconfiguration line, the fourth photosensitive dielectric layer covers the third photosensitive dielectric layer and the third reconfiguration line and has the openings that expose a portion of the third reconfiguration line to define the solder ball pads, wherein the line width and line spacing of the third reconfiguration line are greater than the line width and line spacing of the second reconfiguration line line spacing, and the line width and line spacing of the second reconfiguration line are greater than the line width and line spacing of the first reconfiguration line. The package structure of claim 2, wherein the line width and line spacing of the first reconfiguration lines are respectively 2 micrometers, the line width and line spacing of the second reconfiguration lines are respectively 5 micrometers, and the third The line width and line spacing of the reconfiguration lines are respectively 10 microns. The package structure of claim 2, wherein the thickness of the first reconfiguration line is equal to the thickness of the second reconfiguration line, and the thickness of the second reconfiguration line is smaller than the thickness of the third reconfiguration line. The package structure of claim 2, wherein the depth of each of the second conductive vias is equal to the depth of the third conductive via, and the depth of the first conductive via is smaller than the depth of the second conductive via. The packaging structure of claim 2, wherein the periphery of the encapsulant is aligned with the periphery of the first reconfiguration wiring layer, the periphery of the second reconfiguration wiring layer, and the periphery of the third reconfiguration wiring layer. The package structure of claim 1, further comprising: a plurality of copper pillars disposed on the chip assembly and between the chip assembly and the chip pads; and a plurality of solders disposed on the copper pillars on and between the copper pillars and the chip pads. The package structure of claim 7, wherein the primer covers the copper pillars, the solders and the chip pads. The package structure of claim 1, wherein the chip assembly includes a processor and two memories, and the size of the processor is larger than the size of each of the memories. The package structure of claim 1, further comprising: a circuit board disposed below the reconfiguration circuit layer, and the chip component is electrically connected to the circuit board through the solder balls. A manufacturing method of a package structure, comprising: forming a reconfiguration circuit layer on a temporary carrier, the reconfiguration circuit layer including a plurality of reconfiguration circuits, a plurality of photosensitive dielectric layers, a plurality of conductive vias and a plurality of chip pads, the reconfiguration circuits and the The photosensitive dielectric layers are alternately arranged, the conductive vias penetrate through the photosensitive dielectric layers and are electrically connected to the reconfiguration lines, wherein one of the photosensitive dielectric layers located at the opposite two outermost sides has an upper surface , and the chip pads are located on the upper surface and are electrically connected to the reconfiguration lines through the conductive vias, and the other one of the photosensitive dielectric layers located on the opposite outermost sides is directly attached to the on the temporary carrier; disposing a chip assembly on the chip pads and electrically connecting the chip pads, wherein the chip assembly includes at least two chips with different sizes; forming an encapsulant to cover at least the chip assembly; removing the temporary carrier after disposing the chip assembly on the chip pads to expose the other one of the photosensitive dielectric layers located at the opposite two outermost sides; forming a plurality of openings at the opposite two outermost sides The other of the photosensitive dielectric layers defines a plurality of solder ball pads by exposing part of the reconfiguration lines, wherein the line width and line spacing of the reconfiguration lines are connected from the solder balls The pads become smaller toward the chip pads; and a plurality of solder balls are respectively formed on the solder ball pads to electrically connect the solder ball pads. The manufacturing method of a package structure according to claim 11, wherein the reconfiguration circuit layer includes a first reconfiguration circuit layer, a second reconfiguration circuit layer and a third reconfiguration circuit layer, and the reconfiguration circuits include a first reconfiguration line, A second reconfiguration line and a third reconfiguration line, the photosensitive dielectric layers include a first photosensitive dielectric layer, a second photosensitive dielectric layer, a third photosensitive dielectric layer, and a fourth photosensitive dielectric layer The electrical layer, the conductive vias include a plurality of first conductive vias, a plurality of second conductive vias and a plurality of third conductive vias, the step of forming the reconfigured circuit layer on the temporary carrier includes: providing the temporary carrier, the temporary carrier including a base material and a release film on the base material; forming the third reconfiguration circuit layer on the temporary carrier, the third reconfiguration circuit layer including the The third reconfiguration line, the third photosensitive dielectric layer, the fourth photosensitive dielectric layer, and the third conductive vias penetrating the third photosensitive dielectric layer, and the fourth photosensitive dielectric layer covers the first Three photosensitive dielectric layers and the third reconfiguration line; the second reconfiguration line layer is formed on the third reconfiguration line layer, and the second reconfiguration line layer includes the second reconfiguration line, the second photosensitive A dielectric layer and the second conductive vias penetrating the second photosensitive dielectric layer, the second reconfiguration circuit and the third conductive vias are formed at the same time, and the third conductive vias are electrically connected to the the second reconfiguration line and the third reconfiguration line; and the first reconfiguration line layer is formed on the second reconfiguration line layer, the first reconfiguration line layer includes the chip pads, the first reconfiguration line Configuration lines, the first photosensitive dielectric layer, and the first conductive vias penetrating the first photosensitive dielectric layer, the first photosensitive dielectric layer having the upper surface, and the chip pads passing through the first The conductive via is electrically connected to the first reconfiguration line, the first reconfiguration line is formed simultaneously with the second conductive vias, and the second conductive vias are electrically connected to the first reconfiguration Lines and the second reconfiguration lines, and the chip pads and the first conductive vias are simultaneously formed; wherein the line width and line spacing of the third reconfiguration lines are larger than the line widths of the second reconfiguration lines and line spacing, and the line width and line spacing of the second reconfiguration line are greater than the line width and line spacing of the first reconfiguration line. The method for fabricating a package structure as claimed in claim 12, wherein the line width and line spacing of the first reconfiguration lines are respectively 2 μm, and the line width and line spacing of the second reconfiguration lines are respectively 5 μm, and The line width and line spacing of the third reconfiguration lines are respectively 10 microns. The manufacturing method of the package structure of claim 12, wherein the thickness of the first reconfiguration line is equal to the thickness of the second reconfiguration line, and the thickness of the second reconfiguration line is smaller than the thickness of the third reconfiguration line . The manufacturing method of a package structure according to claim 12, wherein the depth of the second conductive via is equal to the depth of the third conductive via, and the depth of the first conductive via is smaller than the depth of the second conductive via . The method for fabricating a package structure as claimed in claim 12, wherein the step of forming the openings comprises: performing a drilling process on the fourth photosensitive dielectric layer to form the openings exposing a portion of the third reconfiguration circuit Open your mouth. The manufacturing method of the package structure of claim 11, wherein before disposing the chip assembly on the chip pads, further comprising: forming a plurality of copper pillars on the at least two chips of a wafer; and A plurality of solders are on the copper pillars, wherein the copper pillars are located between the at least two chips and the solders. The manufacturing method of the package structure according to claim 17, wherein before forming the encapsulant to at least cover the chip component, further comprising: forming a primer on the reconfiguration circuit layer to cover the copper pillars, the solder and the die pads. The manufacturing method of the package structure according to claim 11, wherein the chip assembly includes a processor and two memories, and the size of the processor is larger than the size of each of the memories. The manufacturing method of the package structure of claim 11, further comprising: providing a circuit board below the reconfiguration circuit layer, wherein the chip component is electrically connected to the circuit board through the solder balls.

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