TWI756907B - Package structure and method of fabricating the same - Google Patents

Abstract

A package structure includes a circuits substrate, a semiconductor package, a lid structure and a plurality of first spacer structures. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package, wherein the lid structure is attached to the circuit substrate through an adhesive material. The plurality of first spacer structures is surrounding the semiconductor package, wherein the first spacer structures are sandwiched between the lid structure and the circuit substrate, and includes a top portion in contact with the lid structure and a bottom portion in contact with the circuit substrate.

Description

Package structure and method of making the same

Embodiments of the present disclosure relate to a package structure and a method for fabricating the package structure.

Semiconductor devices and integrated circuits used in various electronic applications, such as cell phones and other mobile electronic devices, are typically fabricated on a single semiconductor wafer. The dies of a wafer can be processed and packaged with other semiconductor devices or dies at the wafer level, and various techniques have been developed for wafer level packaging.

Embodiments of the present disclosure provide a package structure including a circuit substrate, a semiconductor package, a cover structure, and a plurality of first spacer structures. The semiconductor package is disposed on the circuit substrate and is electrically connected to the circuit substrate. The cover structure is disposed on the circuit substrate and covers the semiconductor package, wherein the cover structure is attached to the circuit substrate through an adhesive material. The plurality of first spacer structures surround the semiconductor package, wherein the first spacer structures are sandwiched between the cover structure and the wiring substrate, and include a top portion in contact with the cover structure and with the line The bottom portion of the road substrate contact.

Embodiments of the present disclosure provide a package structure including a circuit substrate, an interposer structure, a plurality of semiconductor dies, a lid structure, a thermal interface material, and a plurality of first spacer structures. The interposer structure is disposed on the circuit substrate and is electrically connected to the circuit substrate. The plurality of semiconductor dies are disposed on the interposer structure and are electrically connected to the interposer structure. The cover structure is disposed on the circuit substrate, wherein the cover structure includes a cover body part and a side wall part, the cover body part is located on the plurality of semiconductor die, the side wall part and the cover body A portion is bonded and surrounds the plurality of semiconductor dies and the interposer structure, and the sidewall portion is attached to the circuit substrate through an adhesive material. The thermal interface material is disposed between the plurality of semiconductor dies and the cover portion of the cover structure. The plurality of first spacer structures are disposed between the circuit substrate and the sidewall portion of the cover structure adjacent to the adhesive material.

The embodiments of the present disclosure describe a method for fabricating a package structure. The method includes the following steps. Provide a circuit base. A plurality of first spacer structures are placed on the wiring substrate, wherein the plurality of first spacer structures include a top portion and a bottom portion, and the bottom portion is in contact with the wiring substrate. A semiconductor package is disposed on the wiring substrate in an area surrounded by the first spacer structure. attaching a cover structure to the circuit substrate through an adhesive material, wherein the cover structure surrounds the semiconductor package, and the plurality of first spacer structures are sandwiched between the cover structure and the circuit substrate, and the cover structure and the plurality of first spacer structures the top portion of the contact.

40: First spacer structure/spacer structure

40-BS, 42-BS: Bottom part

40C: Conductive core

40CL: Column structure or column structure

40PC: polymer core

40PS: polymer shell

40S: Conductive shell

40-TS, 42-TS: Top section

42: Second spacer structure/spacer structure

100: Interposer Structure / Interposer

100’: Interposer Structure

102: Core Parts

102a: First surface

102b: Second surface

104: Perforation

106, 210, 220, 602B, 610: Conductive pads

110: Electrical connector

112. UX: Bottom Fill Structure

114: Insulation seal

114a, 116s: Top surface

114b, D1-X, D2-X: backside surface

116: Rewiring structure

116a, 604, 608B: Dielectric layers

116b: Metallization Pattern

118: Conductive terminal

200: circuit substrate

200A: first side

200B: Second side

230, 608A: metallization layer

250, 612: Conductive ball

310: Solder Paste

320: Adhesive

510: Thermal Interface Materials

520: Cover Structure

520A: Cover part

520B: Sidewall Section

602: Semiconductor Die

602A: Semiconductor Substrate

602C: Passivation layer

602D: Post passivation layer

602E: Conductive Post or Via

602F: Protective layer

606: Insulation seal

608: Redistribution layer

ADM, ADM1, ADM2: Adhesive Materials

CM: connecting material

CR, CX: carrier

D1: Semiconductor Die

D2: Semiconductor die/die

D1A, D2A: body

D1B, D2B: Connection pads

D1-S, D2-S: Active Surfaces

DL: cutting line

Dx: distance

FR: frame

MX: Mixture

OP1: The first opening

OP2: Second Opening

OP3: The third opening

OX: Contact opening

OY: opening

PDX: Passive Components

PKR: encapsulation area

PK0, PK1, PK1', PK2, PK3, PK4, PK5: Package structure

SM: Semiconductor Package/Semiconductor Package Structure

SM2: Semiconductor Package

TP: strip

Tx, Ty: Thickness

W1: width

Various aspects of the present disclosure are best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the critical dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

1A-1H are schematic cross-sectional views of various stages in a method of fabricating a semiconductor package in accordance with some example embodiments of the present disclosure.

2A-2F are schematic cross-sectional and top views of various stages in a method of fabricating a package structure according to some exemplary embodiments of the present disclosure.

3A-3C are various designs of spacer structures according to some example embodiments of the present disclosure.

4A and 4B are schematic cross-sectional views of various methods of placing a spacer structure on a wiring substrate in accordance with some exemplary embodiments of the present disclosure.

5A and 5B are various designs of spacer structures according to some other exemplary embodiments of the present disclosure.

6A and 6B are schematic cross-sectional views of various methods of placing a spacer structure on a wiring substrate in accordance with some exemplary embodiments of the present disclosure.

7A-7D are schematic cross-sectional and top views of various stages in a method of fabricating a package structure according to some exemplary embodiments of the present disclosure.

8A-8C are various packages according to some example embodiments of the present disclosure Enlarged cross-sectional view of the structure.

9 is a package structure according to some other exemplary embodiments of the present disclosure.

10A and 10B are schematic cross-sectional views of various stages in a method of fabricating a package structure according to some other exemplary embodiments of the present disclosure.

11 is a package structure according to some other exemplary embodiments of the present disclosure.

12 is a package structure according to some comparative embodiments of the present disclosure.

13 is a package structure according to some other exemplary embodiments of the present disclosure.

The following disclosure provides many different embodiments or examples for implementing various features of the presented subject matter. Specific examples of elements and arrangements are set forth below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a second feature on or on a first feature may include embodiments in which the second feature is formed in direct contact with the first feature, and may also include embodiments in which the second feature is formed Embodiments in which additional features may be formed with the first feature such that the second feature may not be in direct contact with the first feature. Additionally, the present disclosure may reuse reference symbols and/or letters in various instances. This re-use is for the sake of brevity and clarity and is not itself indicative of the relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of description, for example, "beneath", "below", "lower", "on" may be used herein. )", "over", "overlying", Spatially relative terms such as "above", "upper" and the like are used to describe the relationship of one element or feature to another (other) element or feature shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Other features and processes may also be included. For example, test structures may be included to illustrate verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3DIC) devices. The test structure may include, for example, test pads formed in the redistribution layer or on the substrate to enable testing of the 3D package or 3DIC, use of probes and/or probe cards, and the like. Verification tests can be performed on intermediate structures as well as final structures. Additionally, the structures and methods disclosed herein can be used in conjunction with test methods that include intermediate verification of known good dies to increase yield and reduce cost.

1A-1H are schematic cross-sectional views of various stages in a method of fabricating a semiconductor package according to some example embodiments of the present disclosure. 1A, an interposer structure 100 is provided. In some embodiments, the interposer structure 100 includes a core portion 102 , and a plurality of vias 104 and conductive pads 106 formed in the core portion 102 . In some embodiments, the core portion 102 may be a substrate, such as a bulk semiconductor substrate, a silicon on insulator (SOI) substrate, or a multilayer semiconductor substrate body material base. The semiconductor material of the substrate (core portion 102) can be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof. In some embodiments, the core portion 102 may be doped or undoped.

In some embodiments, the conductive pads 106 are formed on the first surface 102a of the core portion 102 . In some embodiments, vias 104 are formed in core portion 102 and are connected to conductive pads 106 . In some embodiments, the perforations 104 extend into the core portion 102 to a certain depth. In some embodiments, the perforations 104 are substrate perforations. In some embodiments, when the core portion 102 is a silicon substrate, the vias 104 are vias of silicon. In some embodiments, the perforations 104 may be formed by forming holes or grooves in the core portion 102 and then filling the grooves with a conductive material. In some embodiments, the grooves may be formed by, for example, etching, milling, laser drilling, and the like. In some embodiments, electrochemical plating process, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) can be used to A conductive material is formed, and the conductive material may include copper, tungsten, aluminum, silver, gold, or a combination thereof. In some embodiments, conductive pads 106 connected to vias 104 may be formed as conductive portions of a redistribution layer formed on interposer structure 100 . In some embodiments, the conductive pads 106 include under bump metallurgy (UBM). In certain embodiments, the interposer structure 100 may further include active or passive elements formed in the core portion 102, such as transistors, capacitors, resistors, or diodes moving element.

As shown in FIG. 1A , the core portion 102 has a plurality of packaging regions PKR and a scribe line DL separating each of the plurality of packaging regions PKR. Through holes 104 and conductive pads 106 are formed in the core portion 102 within the package region PKR. In some embodiments, the semiconductor die D1 and the semiconductor die D2 are disposed on the interposer structure 100 or on the core portion 102 within the package region PKR. The semiconductor die D1 and the semiconductor die D2 are single die singulated from the wafer. In some embodiments, semiconductor die D1 includes the same circuitry, such as devices and metallization patterns, or semiconductor die D1 is the same type of die. In some embodiments, semiconductor die D2 contains the same circuitry, or semiconductor die D2 is the same type of die. In some embodiments, semiconductor die D1 and semiconductor die D2 have different circuitry or are different types of dies. In alternative embodiments, semiconductor die D1 and semiconductor die D2 may have the same circuitry.

In some embodiments, semiconductor die D1 may be a primary die, and semiconductor die D2 may be an auxiliary die. In some embodiments, the main dies are arranged on the core portion 102 in the center position of each package region PKR, and the auxiliary dies are arranged side by side and spaced apart from the main dies. In some embodiments, the auxiliary die is arranged next to the main die and surrounds or surrounds the main die. In one embodiment, four or six auxiliary dies are arranged around one main die of each package region PKR. The present disclosure is not limited thereto.

In certain embodiments, the surface area of semiconductor die D1 is greater than the surface area of semiconductor die D2. Additionally, in some embodiments, the semiconductor die D1 and the semiconductor The bulk grains D2 may have different sizes, including different surface areas and/or different thicknesses. In some embodiments, the semiconductor die D1 may be a logic die, including a central processing unit (CPU) die, a graphics processing unit (GPU) die, and a system-on-chip (system-on-chip) die. a-chip, SoC) die, microcontroller, etc. In some embodiments, the semiconductor die D1 is a power management die, such as a power management integrated circuit (PMIC) die. In some embodiments, the semiconductor die D2 may be a memory die, including a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die die, or high bandwidth memory (HBM) die. The present disclosure is not limited thereto, and the number, size, and type of semiconductor die provided on the core portion 102 may be appropriately adjusted based on product requirements.

In the illustrated embodiment, semiconductor die D1 includes body D1A and connection pads D1B formed on active surface D1-S of body D1A. In some embodiments, the connection pads D1B may further include pillar structures for bonding the semiconductor die D1 to other structures. In some embodiments, semiconductor die D2 includes body D2A and connection pads D2B formed on active surface D2-S of body D2A. In other embodiments, connection pads D2B may further include pillar structures for bonding die D2 to other structures.

In some embodiments, the semiconductor die D1 and the semiconductor die D2 are bonded together, for example, through the electrical connector 110 through flip-chip bonding. to the first surface 102a of the core portion 102 . Through a reflow process, the electrical connector 110 is formed between the connection pads D1B, D2B and the conductive pad 106 , and the semiconductor dies D2 and D1 are electrically and physically connected to the core portion 102 of the interposer structure 100 . In some embodiments, the electrical connector 110 is located between the semiconductor dies D1 , D2 and the interposer structure 100 . In some embodiments, the semiconductor dies D1 and D2 are electrically connected to the through hole 104 and the conductive pad 106 through the electrical connector 110 . In one embodiment, the electrical connector 110 is a microbump, such as a microbump with copper metal pillars. In another embodiment, the electrical connectors 110 are solder bumps, lead-free solder bumps, or micro-bumps, such as controlled collapse chip connection (C4) bumps or micro-bumps including copper pillars Piece. In some embodiments, the bond between the semiconductor die D1 , D2 and the core portion 102 may be a solder bond. In some embodiments, the bonding between the semiconductor dies D1 , D2 and the core portion 102 may be direct metal-to-metal bonding, such as copper-to-copper bonding.

Referring to FIG. 1B , in the next step, an underfill structure 112 may be formed to cover the plurality of electrical connectors 110 and fill the space between the semiconductor dies D1 , D2 and the interposer structure 100 . In some embodiments, the underfill structure 112 further covers the sidewalls of the semiconductor dies D1 and D2 and is located in the package region PKR. Thereafter, an insulating encapsulant 114 may be formed over the interposer structure 100 (or over the core portion 102) to cover the underfill structure 112 and surround the semiconductor dies D1 and D2.

In some embodiments, the insulating seal 114 is formed on the first surface 102a of the core portion 102 in the package region PKR and on the dicing line DL. In some embodiments, the insulating sealing body 114 is formed by, for example, a compression molding process or a transfer molding process. In one embodiment, a curing process is performed to cure the insulating encapsulant 114 . In some embodiments, the insulating sealing body 114 encapsulates the semiconductor dies D1 , D2 and the electrical connector 110 . In some embodiments, a planarization process (including grinding or polishing) may be performed to partially remove the insulating seal 114 to expose the backside surfaces D1-X, D2-X of the semiconductor dies D1, D2. Therefore, the backside surfaces D1 -X, D2 -X of the semiconductor dies D1 , D2 are flush with the top surface 114 a of the insulating sealing body 114 . The top surface 114a is opposite the backside surface 114b of the insulating seal 114 , where the backside surface 114b is in contact with the core portion 102 .

In some embodiments, the material of the insulating sealing body 114 includes a polymer (eg, epoxy resin, phenolic resin, silicon-containing resin, or other suitable resins), has a low dielectric constant (Dk), and Dielectric materials with low loss tangent (Df) properties, or other suitable materials. In alternative embodiments, the insulating seal 114 may comprise an acceptable insulating seal material. In some embodiments, insulating encapsulant 114 may further include inorganic fillers or inorganic compounds (eg, carbon dioxide) that may be added to insulating encapsulant 114 to optimize the coefficient of thermal expansion (CTE) of insulating encapsulant 114 . silicon, clay, etc.). The present disclosure is not limited thereto.

Referring to FIG. 1C , the structure of FIG. 1B is reversed or flipped and placed on the carrier CR so that the carrier CR directly contacts the backside surfaces D1 -X, D2 -X of the semiconductor dies D1 , D2 and the top surface 114 a of the insulating encapsulant 114 . As shown in FIG. 1C, at this processing stage, the interposer structure 100 has not yet been thinned and has a thickness Tx. In other words, the through holes 104 are not exposed, and the through holes 104 are embedded in the core portion 102 of the interposer structure 100 .

1D , a thinning process is performed on the interposer 100 to partially remove or thin the core portion 102 of the interposer structure 100 until the through holes 104 are exposed and the second surface 102b of the core portion 102 is formed. In some embodiments, the thinning process may include a backside grinding process, a polishing process, or an etching process. In some embodiments, after the thinning process, the interposer structure 100 is thinned to a thickness Ty. In some embodiments, the ratio of thickness Ty to thickness Tx ranges from about 0.1 to about 0.5.

Referring to FIG. 1E, a redistribution structure 116 is formed on the second surface 102b of the core portion 102 in the package region PKR and over the scribe lines DL. The second surface 102b of the core portion 102 is opposite the first surface 102a of the core portion 102 . In some embodiments, the redistribution structure 116, the core portion 102, the vias 104, and the conductive pads 106 constitute the interposer structure 100'. In some embodiments, the redistribution structure 116 electrically connects the vias 104 and/or electrically connects the vias 104 with external devices. In some embodiments, the redistribution structure 116 includes at least one dielectric layer 116a and a metallization pattern 116b in the dielectric layer 116a. In some embodiments, the metallization pattern 116b may include pads, vias, and/or traces to interconnect the vias 104 and further connect the vias 104 is connected to one or more external devices. Although one dielectric layer 116a and one metallization pattern 116b are shown in FIG. 1E, it should be noted that the number of layers of the dielectric layer 116a and the metallization pattern 116b is not limited thereto, and this can be adjusted based on requirements .

In some embodiments, the material of the dielectric layer 116a includes silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or a low-k dielectric material (eg, phosphosilicate glass material, fluorosilicate glass material, etc.) , borophosphosilicate glass material, SiOC, spin-on glass material, spin-on polymer or silicon carbon material). In some embodiments, spin coating or deposition (including chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), high density plasma CVD (high density plasma CVD) -CVD, HDP-CVD), etc.) to form the dielectric layer 116a. In some embodiments, the metallization pattern 116b includes under-bump metallurgy (UBM). In some embodiments, forming the metallization pattern 116b may include patterning the dielectric layer using lithography techniques and one or more etching processes and filling metal material into the openings of the patterned dielectric layer. Any excess conductive material on the dielectric layer can be removed, for example, by using a chemical mechanical polishing process. In some embodiments, the material of the metallization pattern 116b includes copper, aluminum, tungsten, silver, and combinations thereof.

As shown in FIG. 1E , a plurality of conductive terminals 118 are disposed on the metallization pattern 116b and are electrically coupled to the vias 104 . In some embodiments, the conductive terminal 118 is placed on the top surface 116s of the redistribution structure 116 and is electrically connected to the via 104 through the metallization pattern 116b in the package region PKR. in a In some embodiments, the conductive terminals 118 are located on the metallization pattern 116b and are physically attached to the metallization pattern 116b. In some embodiments, the conductive terminals 118 include lead-free solder balls, solder balls, ball grid array (BGA) balls, bumps, C4 bumps, or micro bumps. In some embodiments, the conductive terminals 118 may comprise conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or combinations thereof. In some embodiments, the conductive terminals 118 are formed by forming a solder paste on the redistribution structures 116 by, for example, evaporation, electroplating, printing, or solder transfer, and then the conductive terminals 118 are reflowed into the desired bump shape. In some embodiments, the conductive terminals 118 are placed on the redistribution structure 116 by ball bumping or the like. In other embodiments, the conductive terminals 118 are formed by forming solderless metal posts (eg, copper posts) by sputtering, printing, electroless plating or electroplating or CVD, and then forming lead-free by plating the metal posts A lead-free cap layer. The conductive terminals 118 may be used for bonding to external devices or additional electrical components. In some embodiments, the conductive terminals 118 are used for bonding to a wiring substrate, a semiconductor substrate, or a packaging substrate.

Referring to Figure 1F, in a subsequent step, the carrier CR is peeled off. For example, the lift-off process includes irradiating light such as laser or UV light on a lift-off layer (eg, a light-to-heat conversion release layer) attached to the carrier CR (not shown), so that the carrier CR can be easily removed Remove with release layer. In some embodiments, the backside surfaces D1-X, D2-X of the semiconductor die D1, D2 are exposed after the lift-off process.

Referring to FIG. 1G , after peeling off the carrier CR, the structure shown in FIG. 1F is attached to the strip TP (eg, dicing tape) supported by the frame FR. Subsequently, The structure shown in FIG. 1F is cut or singulated along scribe lines DL to form a plurality of semiconductor packages SM. For example, a dicing process is performed to cut through the redistribution structure 116 , the core portion 102 , and the insulating seal 114 to remove portions of the redistribution structure 116 , portions of the core portion 102 , and the insulating seal 114 along the scribe line DL some parts. In some embodiments, the dicing process or singulation process typically involves dicing with a rotating blade or a laser beam. In other words, the dicing process or the singulation process is, for example, a laser slicing process, a mechanical sawing process, or other suitable processes. After peeling off the carrier CR, the singulated semiconductor package SM shown in FIG. 1H can be obtained.

2A-2F are schematic cross-sectional and top views of various stages in a method of fabricating a package structure according to some exemplary embodiments of the present disclosure. Referring to FIG. 2A, a wiring substrate 200 is provided. In some embodiments, the wiring substrate 200 consists of a dielectric layer. In some embodiments, the wiring substrate 200 is an organic flexible substrate or a printed circuit board. In some embodiments, the wiring substrate 200 includes a conductive pad 210 , a conductive pad 220 , a metallization layer 230 , and a via (not shown) embedded in the wiring substrate 200 . In some embodiments, conductive pads 210 and 220 are distributed on two opposite sides of the wiring substrate 200, respectively, and are exposed for electrical connection with later-formed elements/features. For example, in some embodiments, the wiring substrate 200 is patterned to form first openings OP1 , second openings OP2 , and contact openings OX that expose the conductive pads 210 on the first side 200A of the wiring substrate 200 . Additionally, in some embodiments, the wiring substrate 200 is patterned to form exposed The opening OY of the conductive pad 220 on the second side 200B of the circuit substrate 200 .

In some embodiments, the metallization layer 230 and the vias are embedded in the wiring substrate 200 and together provide a routing function for the wiring substrate 200, wherein the metallization layer 230 and the vias are electrically connected to the conductive pads 210 and the conductive pads 220. In other words, at least some of the conductive pads 210 are electrically connected to some of the conductive pads 220 through the metallization layer 230 and the vias. In some embodiments, conductive pads 210 and 220 may comprise metal pads or metal alloy pads. In some embodiments, the material of the metallization layer 230 and the material of the via may be substantially the same or similar to the material of the conductive pad 210 and the material of the conductive pad 220 .

Referring to FIG. 2B , after the circuit substrate 200 is patterned, the solder paste 310 is disposed in the first opening OP1 , the second opening OP2 and the contact opening OX of the circuit substrate 200 . For example, the solder paste 310 is disposed in the first opening OP1 , the second opening OP2 and the contact opening OX by printing. In the next step, a plurality of first spacer structures 40 are placed in the second opening OP2 of the circuit substrate 200 and on the solder paste 310 . In an exemplary embodiment, the material of the first spacer structure 40 is not particularly limited, and may be a conductive material, a polymer material, or the like. This will be explained in detail in the examples later.

Referring to FIG. 2C , in a subsequent step, the semiconductor package SM obtained in FIG. 1H is mounted on the wiring substrate 200 through the conductive terminals 118 . For example, the semiconductor package SM is mounted on the circuit substrate 200 by disposing the conductive terminals 118 on the solder paste 310 in the first opening OP1 of the circuit substrate 200 . Refer to the figure 2D, FIG. 2D is a top view of the structure shown in FIG. 2C , the semiconductor package SM is disposed on the wiring substrate 200 in the area surrounded by the first spacer structure 40 . In some embodiments, the first spacer structure 40 surrounds four sides of the semiconductor package SM. Additionally, about 10 to 15 first spacer structures 40 may be located on each side. However, the present disclosure is not limited thereto, and the number of the first spacer structures 40 surrounding the semiconductor package SM may be adjusted based on product requirements.

As shown in FIGS. 2C and 2D , in some embodiments, a passive component PDX (integrated passive component or surface mount device) may be mounted on the wiring substrate 200 alongside the semiconductor package SM. For example, the passive element PDX is mounted on the circuit substrate 200 in the contact opening OX of the circuit substrate 200 and above the solder paste 310 . After placing/mounting the first spacer structure 40 , the conductive terminals 118 and the passive components PDX in their respective openings, a reflow process is performed to bond the first spacer structure 40 with the conductive pads 210 of the circuit substrate 200 . Similarly, a reflow process is performed to bond the conductive terminals 118 and the passive element PDX to the conductive pads 210 of the circuit substrate 200 . In other words, the first spacer structure 40 , the conductive terminals 118 and the passive element PDX are mounted on the conductive pads 210 of the circuit substrate 200 through a reflow process. In some embodiments, after the reflow process is performed, the semiconductor package SM and the passive element PDX may be electrically connected to the conductive pads 210 of the circuit substrate 200 . In addition, the semiconductor package SM and the passive element PDX may be further electrically connected to the conductive pads 220 , the metallization layer 230 and the through holes. In certain embodiments, the first spacer structure 40 may or may not be electrically connected to the conductive pad 220, depending on the use the material of the first spacer structure 40 . In some embodiments, the first spacer structure 40 has a bottom portion 40 -BS that is in physical contact with the conductive pad 210 of the wiring substrate 200 .

As shown in FIG. 2E , in some embodiments, the underfill structure UX is formed to fill the space between the wiring substrate 200 and the semiconductor package SM. In some embodiments, the underfill structure UX fills the space between adjacent conductive terminals 118 and covers the conductive terminals 118 . For example, an underfill structure UX surrounds the plurality of conductive terminals 118 . In some embodiments, the underfill structure UX exposes the passive element PDX, and the passive element PDX is kept at a distance from the underfill structure UX. In other words, the underfill structure UX does not cover the passive element PDX. In some embodiments, the underfill structure UX may further cover the sidewalls of the semiconductor package SM.

2F, after the formation of the underfill structure UX, a thermal interface material 510 is disposed on the backside of the semiconductor package SM. After that, the cover structure 520 is attached to the circuit substrate 200 through the adhesive material ADM. In some embodiments, the lid structure 520 is pressed onto the thermal interface material 510 such that the thermal interface material 510 is sandwiched between the semiconductor package structure SM and the lid structure 520 . In some embodiments, the lid structure 520 surrounds the semiconductor package SM and the passive device PDX. For example, the cap structure 520 includes a cap portion 520A overlying the semiconductor dies D1 and D2, and includes a sidewall portion 520B that engages with the cap portion 520A. The sidewall portion 520B may surround the semiconductor dies D1, D2 and the interposer structure 100' and pass through the adhesive material ADM Attached to the circuit substrate 200 .

As further shown in FIG. 2F , the first spacer structure 40 is sandwiched between the cover structure 520 and the wiring substrate 200 . For example, the first spacer structure 40 includes a top portion 40 -TS in contact with the cap structure 520 and a bottom portion 40 -BS in contact with the wiring substrate 200 . In some embodiments, the first spacer structure 40 is disposed between the circuit substrate 200 and the sidewall portion 520B of the cap structure 520 and adjacent to the adhesive material ADM. In some embodiments, the adhesive material ADM is also located between the cover structure 520 and the circuit substrate 200 and surrounds and contacts the first spacer structure 40 . Furthermore, in some embodiments, the ratio (W1:Dx) of the width W1 of the sidewall portion 520B to the distance Dx between the wiring substrate 200 and the sidewall portion 520B is in the range of 10:1 to 30:1. For example, in one exemplary embodiment, when the width W1 is controlled in the range of 2 mm to 3 mm, the distance Dx may be controlled in the range of 100 μm to 200 μm. The distance Dx and the width W1 can be properly controlled, thereby preventing the delamination and uneven arrangement of the thermal interface material 510 and the adhesive material ADM, as well as the problems of extrusion and exudation of these materials.

In an exemplary embodiment, by arranging the first spacer structure 40 between the cap structure 520 and the wiring substrate 200, the distance Dx between the wiring substrate 200 and the sidewall portion 520B may be properly maintained. In other words, the force applied during the bonding of the cover structure 520 to the circuit substrate 200 is controlled by maintaining the distance Dx between the cover structure 520 and the circuit substrate 200 . For example, the first spacer structure 40 is used to prevent the distance Dx from being too small (excessive applied force) and preventing the distance Dx from being too large (low applied force). Furthermore, the width W1 of the sidewall portion 520B is directly related to the amount of the adhesive material ADM used. Therefore, the width W1 is also controlled within a certain range, so that the sidewall portion 520B of the cover structure 520 is wide enough to cover the first spacer structure 40 while preventing excessive application of the adhesive material ADM.

In certain embodiments, when the ratio of the width W1 to the distance Dx (W1:Dx) is maintained within the above-mentioned range, problems caused by low applied forces (causing high thermal resistances) during bonding of the cover structure 520 may be prevented thick thermal interface material 510) or problems caused by excessively applied forces (extrusion and bleed of the adhesive material ADM), and other related problems such as delamination and uneven alignment of the thermal interface material 510 and the adhesive. On the other hand, when the ratio of the width W1 to the distance Dx (W1:Dx) is outside the above range, there is a risk that the thermal interface material 510 and the adhesive material ADM are unevenly arranged to cause bleeding and extrusion.

In some embodiments, after the cover structure 520 is attached to the circuit substrate 200, a plurality of conductive balls 250 are placed in the openings OY of the circuit substrate 200, and the plurality of conductive balls 250 are electrically connected to Conductive pads 220 . In some embodiments, the conductive balls 250 are solder balls or BGA balls, for example. So far, the package structure PK1 according to some exemplary embodiments of the present disclosure is completed.

3A-3C are various designs of spacer structures according to some example embodiments of the present disclosure. In the above-described embodiments, the first spacer structure 40 is shown as having a spherical or spherical structure. However, the present disclosure is not limited thereto, and the design of the first spacer structure 40 may be appropriately adjusted. As shown in Figure 3A, the first gap The material structure 40 is shown to include a ball structure with a conductive core 40C. In some embodiments, the conductive core 40C may be made of any conductive or metallic material (eg, copper, tungsten, aluminum, silver, gold, etc.), and the present disclosure is not limited thereto. As shown in FIG. 3B , in addition to having the conductive core 40C, the first spacer structure 40 may further include a conductive shell 40S coated around the conductive core 40C. In other words, the first spacer structure 40 may include a core-shell structure. In some embodiments, the material of the conductive shell 40S can be any conductive material, metal material or metal alloy. In one exemplary embodiment, the conductive shell 40S may be a solder shell. As further shown in FIG. 3C , in some embodiments, the first spacer structure 40 includes a pillar structure or pillar-like structure 40CL. For example, the column structure or column structure 40CL may be made of any conductive material or metal material (eg, copper, tungsten, aluminum, silver, gold, etc.), and the present disclosure is not limited thereto.

4A and 4B are schematic cross-sectional views of various methods of placing a spacer structure on a wiring substrate in accordance with some exemplary embodiments of the present disclosure. 4A , in some embodiments, when the first spacer structure 40 includes a conductive material such as a conductive core 40C, the first spacer structure 40 can be placed on the conductive pad 210 of the circuit substrate 200 through the connecting material CM on or attached to the conductive pads 210 . For example, the connection material CM may be the solder paste 310 used in the previous embodiments. In some embodiments, bottom portion 40 -BS of conductive core 40C is in contact with conductive pad 210 , while connecting material CM surrounds conductive core 40C and contacts conductive pad 210 .

In an exemplary embodiment, when a conductive material such as the conductive core 40C or the conductive shell 40S is located on the outer surface of the first spacer structure 40, the first spacer The structure 40 can be bonded to the circuit substrate 200 through a reflow process. For example, in this embodiment, the first opening OP1 and the second opening OP2 are formed on the circuit substrate 200 , and the solder paste 310 is disposed in the first opening OP1 and the second opening OP2 of the circuit substrate 200 . The first spacer structure 40 may be placed in the second opening OP2 of the wiring substrate 200 , and the conductive terminals 118 of the semiconductor package SM may be arranged in the first opening OP1 of the wiring substrate 200 . Thereafter, a reflow process may be performed to bond both the first spacer structure 40 and the conductive terminals 118 to the conductive pads 210 of the circuit substrate 200 .

Referring to FIG. 4B , in some other embodiments, when the first spacer structure 40 includes a conductive material such as a conductive core 40C, the first spacer structure 40 can be placed on the middle of the circuit substrate 200 through another connecting material CM. The dielectric layer on the electrical layer or attached to the circuit substrate 200 . For example, the connecting material CM can be any adhesive 320, glue, or the like. In some embodiments, the bottom portion 40 -BS of the conductive core 40C is in contact with the dielectric layer of the wiring substrate 200 , and the connecting material CM surrounds the conductive core 40C and contacts the wiring substrate 200 .

5A and 5B are various designs of spacer structures according to some other exemplary embodiments of the present disclosure. In the previous embodiments, the first spacer structure 40 is attached to the circuit substrate 200 through the conductive material, but the present disclosure is not limited thereto, and other materials may be applied. Referring to FIG. 5A , in some embodiments, the first spacer structure 40 is shown to include a ball structure with a conductive core 40C coated with a polymer shell 40PS. In other words, there will be a A non-conductive shell core-shell structure is applied to the first spacer structure 40 . Referring to Figure 5B, in some other embodiments, the first spacer structure 40 is shown as comprising a sphere structure having a polymer core 40PC coated with a polymer shell 40PS. In other words, a core-shell structure having a non-conductive shell on the outer surface of the polymer core 40PC is applied to the first spacer structure 40 . In some alternative embodiments, the first spacer structure 40 may include a polymer core 40PC that is not coated with any shell structure thereon.

6A and 6B are schematic cross-sectional views of various methods of placing a spacer structure on a wiring substrate in accordance with some exemplary embodiments of the present disclosure. 6A , in some embodiments, when the first spacer structure 40 includes a non-conductive material (eg, a polymer shell 40PS covering the conductive core 40C), the first spacer structure 40 may be placed through the connecting material CM on the The conductive pads 210 of the circuit substrate 200 are attached to or attached to the conductive pads 210 . For example, the connecting material CM can be any adhesive 320, glue, or the like. In a similar manner, the bottom portion 40 -BS of the polymer shell 40PS is in contact with the conductive pads 210 , while the connecting material CM surrounds the polymer shell 40PS and contacts the conductive pads 210 .

In an exemplary embodiment, when a polymer material such as the polymer core 40PC or the polymer shell 40PS is located on the outer surface of the first spacer structure 40 , the first spacer structure 40 can be penetrated through the adhesive 320 to connect with the first spacer structure 40 . The wiring substrate 200 is bonded. For example, in this embodiment, the first opening OP1 and the second opening OP2 are formed on the circuit substrate 200 , the first spacer structure 40 is placed in the second opening OP2 , and the first opening OP2 is formed through the adhesive 320 . A spacer structure 40 and circuit substrate The conductive pads 210 of 200 are bonded. In some embodiments, the solder paste 310 is disposed in the first opening OP1 , and the conductive terminals 118 of the semiconductor package SM are disposed in the first opening OP1 of the wiring substrate 200 . Thereafter, a reflow process may be performed to bond the conductive terminals 118 to the conductive pads 210 of the circuit substrate 200 .

6B , in some other embodiments, when the first spacer structure 40 includes a non-conductive material (eg, a polymer shell 40PS covering the polymer core 40PC), the first spacer structure 40 can pass through the connecting material CM It is placed on the dielectric layer of the circuit substrate 200 or attached to the dielectric layer of the circuit substrate 200 . For example, the connecting material CM can be any adhesive 320, glue, or the like. In some embodiments, the bottom portion 40 -BS of the polymeric core 40PC is in contact with the dielectric layer of the wiring substrate 200 , while the connecting material CM surrounds the polymeric core 40PC and contacts the wiring substrate 200 .

7A-7D are schematic cross-sectional and top views of various stages in a method of fabricating a package structure according to some exemplary embodiments of the present disclosure. The methods shown in FIGS. 7A to 7D are similar to those shown in FIGS. 2A to 2F , and thus the same reference numerals will be used to denote the same or similar elements, and a detailed description thereof will be omitted herein. The difference between the described embodiments is that a second spacer structure 42 is further provided.

7A, the same method as set forth in FIGS. 2A-2C may be performed to dispose the conductive terminals 118 of the semiconductor package SM in the first openings OP1, the first spacer structures 40 in the second openings OP2, and The passive element PDX is arranged in the contact opening OX. As shown in Figure 7A, in some embodiments, the line A plurality of third openings OP3 are further formed in the substrate 200, and a plurality of second spacer structures 42 are disposed in the third openings OP3. In some embodiments, the first spacer structure 40 and the second spacer structure 42 are attached to the conductive pads 210 of the circuit substrate 200 by using the connection material CM as described above. In an exemplary embodiment, the material and design of the second spacer structure 42 may be the same as the first spacer structure 40 . In some alternative embodiments, the material and design of the second spacer structure 42 may be different from the first spacer structure 40 . For example, various designs of the spacer structures shown in FIGS. 3A-3C , 5A, and 5B may be applied to the second spacer structure 42 .

As shown in FIG. 7B , which is a top view of the structure shown in FIG. 7A , in some embodiments, the second spacer structure 42 may be disposed on the wiring substrate 200 to surround the first spacer structure 40 . For example, the second spacer structure 42 may be arranged beside the first spacer structure 40 in a parallel manner around the four sides of the semiconductor package SM. However, the present disclosure is not limited thereto, and the arrangement of the second spacer structures 42 may be adjusted based on design requirements. For example, in some alternative embodiments as shown in FIG. 7C , the first spacer structure 40 and the second spacer structure 42 are arranged in a zig-zag manner around the semiconductor package SM on the circuit substrate 200 or staggered. For example, the first spacer structure 40 and the second spacer structure 42 may surround the interposer structure 100'.

Referring to FIG. 7D , after the first spacer structure 40 and the second spacer structure 42 are disposed on the circuit substrate 200 , the cover structure 520 is attached to the circuit substrate 200 through the adhesive material ADM. In the exemplary embodiment, the second spacer structure 42 It is sandwiched between the cover structure 520 and the circuit substrate 200 , and includes a top portion 42 -TS in contact with the cover structure 520 and a bottom portion 42 -BS in contact with the circuit substrate 200 . For example, the second spacer structure 42 is disposed between the circuit substrate 200 and the sidewall portion 520B of the cap structure 520 adjacent to the adhesive material ADM.

As further shown in FIG. 7D , the adhesive material ADM is sandwiched between the cover structure 520 and the circuit substrate 200 and covers and contacts the first spacer structure 40 and the second spacer structure 42 . Furthermore, in some embodiments, the ratio (W1:Dx) of the width W1 of the sidewall portion 520B to the distance Dx between the wiring substrate 200 and the sidewall portion 520B still remains in the range of 10:1 to 30:1. In this way, the delamination and uneven arrangement of the thermal interface material 510 and the adhesive material ADM, as well as the extrusion and exudation problems of these materials can be prevented.

For example, in an exemplary embodiment, when the ratio of the width W1 to the distance Dx (W1:Dx) is maintained within the above-described range, problems caused by low applied force during the fitting of the cover structure 520 can be prevented (thick thermal interface material 510 causing high thermal resistance) or problems caused by excessive applied force (extrusion and bleeding of adhesive material ADM), and others such as delamination and uneven alignment of thermal interface material 510 and adhesive Related questions. On the other hand, when the ratio of the width W1 to the distance Dx (W1:Dx) is outside the above range, there is a risk that the thermal interface material 510 and the adhesive material ADM are unevenly arranged to cause bleeding and extrusion.

After the cover structure 520 is attached to the circuit substrate 200, a plurality of conductive balls 250 are placed in the openings OY of the circuit substrate 200, and the plurality of conductive balls 250 are placed in the opening OY of the circuit substrate 200. The balls 250 are electrically connected to the conductive pads 220 . So far, the package structure PK2 according to some exemplary embodiments of the present disclosure is completed.

8A-8C are enlarged cross-sectional views of various package structures according to some example embodiments of the present disclosure. For the embodiment including the first spacer structure 40 and the second spacer structure 42, their arrangement with respect to the adhesive material ADM is further explained. Referring to FIG. 8A , in some embodiments, the sidewall portion 520B of the cover structure 520 is attached to the circuit substrate 200 through the adhesive material ADM, whereby the adhesive material ADM covers and contacts the first spacer structure 40 and the second spacer structure 42 both. However, the present disclosure is not limited thereto.

8B , in some embodiments, the sidewall portion 520B of the cover structure 520 is adhered to the circuit substrate 200 through the adhesive material ADM, but the adhesive material ADM is spaced apart from the first spacer structure 40 and the second spacer structure 42 . In other words, the adhesive material ADM does not contact the first spacer structure 40 and the second spacer structure 42 . In such an embodiment, the first spacer structure 40 and the second spacer structure 42 are disposed further away from each other (relative to the arrangement shown in Figure 8A). In some embodiments, the adhesive material ADM is located in the space between the first spacer structure 40 and the second spacer structure 42 and is sandwiched between the circuit substrate 200 and the sidewall portion 520B of the cover structure 520 .

Referring to FIG. 8C , in some embodiments, the sidewall portion 520B of the cover structure 520 is adhered to the circuit substrate 200 through the adhesive material ADM, whereby the adhesive material ADM covers and contacts the first spacer structure 40 and is connected with the second spacer structure 42 spaced apart. However, the present disclosure is not limited thereto. In some alternative embodiments, the adhesive material ADM covers and contacts the second spacer structure 42 and is spaced apart from the first spacer structure 40 . In other words, the adhesive material ADM can cover at least one of the plurality of first spacer structures 40 and the plurality of second spacer structures 42 , and simultaneously with the plurality of first spacer structures 40 and all of the plurality of first spacer structures 42 . Another one of the plurality of second spacer structures 42 is spaced apart. Such an embodiment can be achieved by selectively disposing the adhesive material ADM over the first spacer structure 40 or the second spacer structure 42 during the bonding of the cover structure 520 to the circuit substrate 200 .

9 is a package structure according to some other exemplary embodiments of the present disclosure. The package structure PK3 shown in FIG. 9 is similar to the package structure PK2 shown in FIG. 7D , so the same reference numerals will be used to denote the same or similar elements, and detailed descriptions thereof will be omitted herein. The difference between the embodiments is the design of the second spacer structure 42 . In the previous embodiment, both the first spacer structure 40 and the second spacer structure 42 have a ball structure design in the package structure. However, the present disclosure is not limited thereto. Referring to FIG. 9, in some embodiments, the first spacer structure 40 has a ball structure and the second spacer structure 42 has a column structure or a columnar structure. In cases where the first spacer structure 40 and the second spacer structure 42 have different designs, they may still have substantially the same height. Based on the above embodiments, it can be noted that the design and arrangement of the spacer structures ( 40 / 42 ) can be appropriately adjusted, as long as the spacer structures ( 40 / 42 ) help to control the relationship between the circuit substrate 200 and the cover structure 520 height or distance between them.

10A and 10B are schematic cross-sectional views of various stages in a method of fabricating a package structure according to some other exemplary embodiments of the present disclosure. The methods shown in FIGS. 10A and 10B are similar to those shown in FIGS. 2A to 2F , and thus the same reference numerals will be used to denote the same or similar elements, and detailed descriptions thereof will be omitted herein. The difference between the embodiments is the method of attaching the first spacer structure 40 to the circuit substrate 200 .

In the previous embodiment, the first spacer structure 40 can be attached to the circuit substrate 200 (or on the dielectric layer) through the connecting material CM (eg, the solder paste 310 or the adhesive 320 , and with or without a reflow process). or on the conductive pad 210). However, the present disclosure is not limited thereto, and the connection material CM may be omitted. For example, referring to FIG. 10A, in some embodiments, the mixture MX is first formed by mixing the first spacer structure 40 with the adhesive material ADM. In certain embodiments, the mixture MX is dispensed onto the wiring substrate 200 . For example, the mixture MX may be dispensed on the wiring substrate 200 such that the first spacer structure 40 is located in the second opening OP2 of the wiring substrate 200 while the adhesive material ADM covers the first spacer structure 40 . In some alternative embodiments, the mixture MX may be dispensed on the wiring substrate 200 such that the first spacer structure 40 is disposed on the dielectric layer of the wiring substrate 200 .

Referring to FIG. 10B , after the mixture MX is dispensed on the circuit substrate 200 , the cover structure 520 may be attached to the circuit substrate 200 through the adhesive material ADM, thereby sandwiching the first spacer structure 40 between the cover structure 520 and the circuit substrate between 200. So far, the package structure PK1' according to some other exemplary embodiments of the present disclosure can be completed. It should be noted that in other embodiments in which the second spacer structure 42 is present, the second spacer structure 42 may also be disposed on the wiring substrate 200 by forming a mixture, and the mixture may be dispensed on the wiring substrate 200 The upper part is used to fit the cover structure 520 .

11 is a package structure according to some other exemplary embodiments of the present disclosure. The package structure PK4 shown in FIG. 11 is similar to the package structure PK1 shown in FIG. 2F , so the same reference numerals will be used to denote the same or similar elements, and a detailed description thereof will be omitted herein. The difference between the embodiments is the design and arrangement of the first spacer structure 40 and the adhesive material ADM.

As shown in FIG. 11 , in some embodiments, an adhesive material may be formed as part of the first spacer structure 40 . For example, in an exemplary embodiment, the first spacer structure 40 may include a carrier CX, an adhesive material ADM1 on one surface of the carrier CX, and another adhesive material ADM2 on the other surface of the carrier CX. For example, the first spacer structure 40 may be a double-sided tape spacer. In some embodiments, the adhesive material ADM1 is attached to the cover structure 520 , and the adhesive material ADM2 is attached to the circuit substrate 200 . Similar to the above-mentioned embodiment, the cover structure 520 can be attached to the circuit substrate 200 through the adhesive material (ADM1 and ADM2), and the first spacer structure 40 (including ADM1, CX and ADM2) is sandwiched between the cover structure 520 and the circuit substrate 200 between. Similarly, in the exemplary embodiment, the ratio of the width W1 of the sidewall portion 520B to the distance Dx between the wiring substrate 200 and the sidewall portion 520B (W1:Dx) still remains in the range of 10:1 to 30:1. In this way, the delamination and uneven arrangement of the thermal interface material 510 and the adhesive material (ADM1/ADM2), as well as the extrusion and exudation problems of these materials can be prevented.

For example, in an exemplary embodiment, when the ratio of the width W1 to the distance Dx (W1:Dx) is maintained within the above-described range, problems caused by low applied force during the fitting of the cover structure 520 can be prevented (thick thermal interface material 510 causing high thermal resistance) or problems caused by excessively applied force (extrusion and bleed of thermal interface material 510), and for example delamination and uneven alignment of thermal interface material 510 and adhesive, etc. other related issues. On the other hand, when the ratio of the width W1 to the distance Dx (W1:Dx) is outside the above range, there is a risk that the thermal interface material 510 and the adhesive material are unevenly arranged to cause bleeding and extrusion.

So far, the package structure PK4 according to some exemplary embodiments of the present disclosure is completed.

12 is a package structure according to some comparative embodiments of the present disclosure. The comparative package structure PK0 shown in FIG. 12 is similar to the package structure PK1 shown in FIG. 2F , so the same reference numerals will be used to denote the same or similar elements, and a detailed description thereof will be omitted herein. The difference between the embodiments is that the first spacer structure 40 is omitted from the package structure PK0.

Referring to FIG. 12 , in some comparative embodiments, since there is no spacer structure between the cover structure 520 and the circuit substrate 200 , it is difficult to control the force applied during attaching the cover structure 520 to the circuit substrate 200 . In this way, the package junction Structure PK0 may suffer from many problems, such as delamination and non-uniform alignment of thermal interface material 510 and adhesive material ADM. For example, in some embodiments, when excessive force is applied during bonding of the lid structure 520, the thermal interface material 510 may be extruded and cover the sidewalls of the semiconductor package SM, causing reliability issues. Similarly, the adhesive material ADM may tend to bleed toward the adjacent passive element PDX and potentially damage the passive element PDX.

13 is a package structure according to some other exemplary embodiments of the present disclosure. The package structure PK5 shown in FIG. 13 is similar to the package structure PK1 shown in FIG. 2F , and thus the same reference numerals will be used to denote the same or similar elements, and a detailed description thereof will be omitted herein. The difference between the embodiments is the design of the semiconductor package. As shown in FIG. 2F, the semiconductor package SM involves a chip-on-wafer (CoW) package. However, the present disclosure is not limited thereto. For example, referring to FIG. 13, a semiconductor package SM2 is provided in place of the semiconductor package SM shown in FIG. 2F.

In an exemplary embodiment, semiconductor package SM2 includes semiconductor die 602 , dielectric layer 604 , insulating encapsulant 606 , redistribution layer 608 , conductive pads 610 , and conductive balls 612 . The semiconductor die 602 is located on the dielectric layer 604 . An insulating encapsulant 606 is located on the dielectric layer 604 and surrounds the semiconductor die 602 . In some embodiments, the semiconductor die 602 includes a semiconductor substrate 602A, a plurality of conductive pads 602B, a passivation layer 602C, a back passivation layer 602D, a plurality of conductive pillars or vias 602E, and a protective layer 602F. As shown in FIG. 13, the plurality of conductive pads 602B are disposed on the semiconductor substrate on the bottom 602A. The passivation layer 602C is formed over the semiconductor substrate 602A and has openings that partially expose the conductive pads 602B on the semiconductor substrate 602A. The semiconductor substrate 602A may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate, and also includes active elements (eg, transistors, etc.) and optional passive elements (eg, resistors, capacitors, inductors) formed therein Wait). The conductive pads 602B may be aluminum pads, copper pads, or other suitable metal pads. The passivation layer 602C may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of any suitable dielectric material.

Additionally, in some embodiments, a rear passivation layer 602D is optionally formed over the passivation layer 602C. The rear passivation layer 602D covers the passivation layer 602C and has a plurality of contact openings. The contact openings of the back passivation layer 602D partially expose the conductive pads 602B. The rear passivation layer 602D may be a benzocyclobutene (BCB) layer, a polyimide layer, a polybenzoxazole (PBO) layer, or a dielectric layer formed of other suitable polymers. In some embodiments, conductive posts or vias 602E are formed on conductive pads 602B by plating. In some embodiments, a protective layer 602F is formed on the back passivation layer 602D covering the conductive pillars or vias 602E to protect the conductive pillars or vias 602E. Although only one semiconductor die 602 is shown herein, it should be noted that the present disclosure is not so limited, and the number of semiconductor die 602 in semiconductor package SM2 may be more than one.

Furthermore, as shown in FIG. 13 , a redistribution layer 608 is formed on the insulating encapsulant 606 and is electrically connected to the semiconductor die 602 . In some embodiments, forming the redistribution layer 608 includes sequentially forming one or more dielectric layers 608B and a one or more metallization layers 608A. In certain embodiments, metallization layers 608A are sandwiched between dielectric layers 608B. Although only three metallization layers 608A and four dielectric layers 608B are shown herein, the scope of the present disclosure is not limited by the embodiments of the present disclosure. In other embodiments, the number of metallization layers 608A and dielectric layers 608B may be adjusted based on product requirements. In some embodiments, the metallization layer 608A is electrically connected to the conductive pillars 602E of the semiconductor die 602 .

In some embodiments, a plurality of conductive pads 610 for electrical connection with conductive balls are provided on the exposed top surface of the topmost layer of metallization layer 608A. In some embodiments, the conductive pads 610 are, for example, a metal under ball (UBM) pattern for ball mounting. As shown in FIG. 13 , conductive pads 610 are formed on the redistribution layer 608 and are electrically connected to the redistribution layer 608 . In some embodiments, the material of the conductive pad 610 may include copper, nickel, titanium, tungsten, or alloys thereof, etc., and the conductive pad 610 may be formed by, for example, an electroplating process. The number of conductive pads 610 is not limited in the present disclosure and may be selected based on the design layout. In some alternative embodiments, conductive pad 610 may be omitted. In other words, the conductive balls 612 formed in subsequent steps can be directly disposed on the redistribution layer 608 .

As shown in FIG. 13 , a plurality of conductive balls 612 are disposed on the conductive pads 610 and above the redistribution layer 608 . In some embodiments, the conductive balls 612 may be disposed on the conductive pads 610 through a ball-mounting process or a reflow process. In some embodiments, the conductive balls 612 are solder balls or ball grid array (BGA) balls, for example. In some embodiments, conductive balls 612 are connected to redistribution layer 608 through conductive pads 610 . In certain embodiments, Some of the conductive balls 612 may be electrically connected to the semiconductor die 602 through the redistribution layer 608 . The number of conductive balls 612 is not limited to the present disclosure, and may be specified and selected based on the number of conductive pads 610 .

In an exemplary embodiment, the semiconductor package SM2 is disposed on the wiring substrate 200 through flip-chip bonding. In some embodiments, the semiconductor package SM2 is electrically connected to the conductive pads 210 of the circuit substrate 200 through the conductive balls 612 . In some embodiments, the conductive balls 612 are further protected by an underfill structure UX. Similar to the above-mentioned embodiment, since the first spacer structure 40 is located between the cover structure 520 and the circuit substrate 200 , the problems of delamination and uneven arrangement of the adhesive material ADM, and extrusion and exudation of the adhesive material ADM can be prevented.

In the above embodiments, the package structure includes a plurality of first spacer structures sandwiched between the cover structure and the circuit substrate. In this way, the force applied when attaching the cover structure to the circuit substrate can be appropriately controlled. For example, problems caused by low applied force (thick thermal interface material causing high thermal resistance) or excessive applied force (extrusion and bleeding of material) during lamination of the lid structure can be prevented, And other related issues such as delamination and uneven arrangement of thermal interface materials and adhesives. Overall, a package structure with better reliability can be obtained.

According to some embodiments of the present disclosure, a package structure includes a wiring substrate, a semiconductor package, a lid structure, and a plurality of first spacer structures. The semiconductor package is disposed on the circuit substrate and is electrically connected to the circuit substrate. The cover structure is disposed on the circuit substrate and covers the semiconductor package, wherein the cover The structure is attached to the circuit substrate through an adhesive material. The plurality of first spacer structures surround the semiconductor package, wherein the first spacer structures are sandwiched between the cover structure and the wiring substrate, and include a top portion in contact with the cover structure and the bottom portion in contact with the circuit substrate.

In some embodiments, the adhesive material covers and contacts the plurality of first spacer structures and the plurality of second spacer structures. In some embodiments, the adhesive material covers one of the plurality of first spacer structures or the plurality of second spacer structures, and is associated with the plurality of first spacer structures or the plurality of spacer structures The other of the second spacer structures is spaced apart. In some embodiments, each of the plurality of first spacer structures is a sphere structure, a core-shell structure, or a pillar structure.

According to some other embodiments of the present disclosure, a package structure includes a wiring substrate, an interposer structure, a plurality of semiconductor dies, a lid structure, a thermal interface material, and a plurality of first spacer structures. The interposer structure is disposed on the circuit substrate and is electrically connected to the circuit substrate. The plurality of semiconductor dies are disposed on the interposer structure and are electrically connected to the interposer structure. The cover structure is disposed on the circuit substrate, wherein the cover structure includes a cover body part and a side wall part, the cover body part is located on the plurality of semiconductor die, the side wall part and the cover body A portion is bonded and surrounds the plurality of semiconductor dies and the interposer structure, and the sidewall portion is attached to the circuit substrate through an adhesive material. The thermal interface material is disposed between the plurality of semiconductor dies and the cover portion of the cover structure. The plurality of first spacer structures are disposed adjacent to the adhesive material on the between the circuit substrate and the sidewall portion of the cover structure.

In some embodiments, the wiring substrate includes a plurality of openings exposing conductive pads of the wiring substrate, and the plurality of first spacer structures are disposed within the plurality of openings and connected to the conductive pads. In some embodiments, the plurality of first spacer structures are attached to the dielectric layer of the circuit substrate. In some embodiments, the adhesive material is located between the plurality of first spacer structures and the plurality of second spacer structures, and is connected to the plurality of first spacer structures and the plurality of second spacer structures The two spacer structures are spaced apart. In some embodiments, the adhesive material covers at least one of the plurality of first spacer structures and the plurality of second spacer structures.

According to yet another embodiment of the present disclosure, a method of fabricating a package structure is described. The method includes the following steps. Provide a circuit base. A plurality of first spacer structures are placed on the wiring substrate, wherein the plurality of first spacer structures include a top portion and a bottom portion, and the bottom portion is in contact with the wiring substrate. A semiconductor package is disposed on the wiring substrate in an area surrounded by the first spacer structure. attaching a cover structure to the circuit substrate through an adhesive material, wherein the cover structure surrounds the semiconductor package, and the plurality of first spacer structures are sandwiched between the cover structure and the circuit substrate, And the cover structure is in contact with the top portions of the plurality of first spacer structures.

In some embodiments, the method further includes: forming a plurality of first openings and a plurality of second openings on the circuit substrate; connecting the plurality of first spacers disposing the plurality of first spacer structures in the plurality of second openings of the circuit substrate, and bonding the plurality of first spacer structures with the circuit substrate using an adhesive; disposing solder paste on the plurality of first spacer structures in the opening; and disposing the semiconductor package on the circuit substrate by disposing a plurality of conductive terminals of the semiconductor package in the first openings of the circuit substrate, and performing a reflow process to The plurality of conductive terminals are bonded to the circuit substrate. In some embodiments, placing the plurality of first spacer structures on the wiring substrate includes forming a mixture by mixing the plurality of first spacer structures with the adhesive material and forming the mixture and the The mixture is dispensed on the circuit substrate; the lid structure is attached to the circuit substrate by pressing the lid structure onto the mixture to attach the lid structure to the circuit substrate through the adhesive material on a circuit substrate, and wherein the plurality of first spacer structures are sandwiched between the cover structure and the circuit substrate. In some embodiments, the method further includes: placing a plurality of second spacer structures on the circuit substrate to surround the plurality of first spacer structures; and passing the cover structure through the all The adhesive material is attached to the circuit substrate, so that the plurality of second spacer structures are sandwiched between the cover structure and the circuit substrate.

The features of several embodiments have been summarized above so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or implementing the embodiments described herein example of the same advantages. Those skilled in the art should also recognize It is realized that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

40: First spacer structure/spacer structure

40-BS: Bottom Section

40-TS: Top Section

100’: Interposer Structure

102: Core Parts

104: Perforation

106, 210, 220: Conductive pads

110: Electrical connector

114: Insulation seal

116b: Metallization Pattern

200: circuit substrate

230: metallization layer

310: Solder Paste

510: Thermal Interface Materials

520: Cover Structure

520A: Cover part

520B: Sidewall Section

ADM: Adhesive Material

D1: Semiconductor Die

D2: Semiconductor die/die

Dx: distance

PDX: Passive Components

PK1: Package structure

SM: Semiconductor Package/Semiconductor Package Structure

UX: Underfill structure

W1: width

Claims (10)

A package structure, comprising: a circuit substrate; a semiconductor package, disposed on the circuit substrate and electrically connected to the circuit substrate; a cover structure, disposed on the circuit substrate and covering the semiconductor package, wherein the cover The structure is attached to the circuit substrate through an adhesive material; and a plurality of first spacer structures surround the semiconductor package, wherein the plurality of first spacer structures are sandwiched between the cover structure and the circuit substrate and includes a top portion in contact with the cover structure and a bottom portion in contact with the circuit substrate. The package structure of claim 1, wherein the circuit substrate includes a plurality of openings, the plurality of openings expose conductive pads of the circuit substrate, and the plurality of first spacer structures are disposed on the circuit substrate A plurality of openings are within and connected to the conductive pads. The package structure of claim 1, further comprising a plurality of second spacer structures surrounding the plurality of first spacer structures, wherein the plurality of second spacer structures are sandwiched between the cover structure and the between the circuit substrates, and includes a top portion in contact with the cover structure and a bottom portion in contact with the circuit substrate. The package structure of claim 3, wherein the adhesive material is located between the plurality of first spacer structures and the plurality of second spacer structures, and is connected to the plurality of first spacer structures and the plurality of second spacer structures. The plurality of second spacer structures are spaced apart. A package structure including: a circuit substrate; an interposer structure disposed on the circuit substrate and electrically connected to the circuit substrate; a plurality of semiconductor dies disposed on the interposer structure and electrically connected to the interposer structure; a cover The structure is arranged on the circuit substrate, wherein the cover structure includes a cover body part and a side wall part, the cover body part is located on the plurality of semiconductor die, and the side wall part is connected with the cover body part. bonding and surrounding the plurality of semiconductor dies and the interposer structure, and the sidewall portion is attached to the circuit substrate through an adhesive material; a thermal interface material is disposed on the plurality of semiconductor dies and the cover between the cover parts of the cover structure; and a plurality of first spacer structures disposed adjacent to the adhesive material and located between the circuit substrate and the sidewall parts of the cover structure, wherein the The plurality of first spacer structures are in direct contact with the circuit substrate and the sidewall portion of the cover structure. The package structure of claim 5, wherein a ratio W1:Dx of the width W1 of the sidewall portion to the distance Dx between the circuit substrate and the sidewall portion is in the range of 10:1 to 30:1 . The package structure of claim 5, further comprising a plurality of second spacer structures surrounding the plurality of first spacer structures, wherein the plurality of second spacer structures A structure is disposed adjacent to the adhesive material and between the circuit substrate and the sidewall portion of the cover structure. The package structure of claim 7, wherein the plurality of first spacer structures and the plurality of second spacer structures are arranged on the circuit substrate in a zigzag manner and surround the interposer structure. A method of fabricating a package structure, comprising: providing a circuit substrate; placing a plurality of first spacer structures on the circuit substrate, wherein the plurality of first spacer structures include a top portion and a bottom portion, and the bottom portion partially in contact with the circuit substrate; disposing a semiconductor package on the circuit substrate in an area surrounded by the plurality of first spacer structures; and attaching a cover structure to the circuit substrate through an adhesive material, The cover structure surrounds the semiconductor package, the plurality of first spacer structures are sandwiched between the cover structure and the circuit substrate, and the cover structure and the plurality of first spacer structures the top portion of the contact. The method of claim 9, further comprising: forming a plurality of first openings and a plurality of second openings on the circuit substrate; disposing solder paste on the plurality of first openings and the plurality of second openings in the opening; placing the plurality of first spacer structures in the plurality of second openings of the circuit substrate; disposing the semiconductor package on the circuit substrate by disposing a plurality of conductive terminals of the semiconductor package in the first openings of the circuit substrate; and performing a reflow process to connect the circuit substrate A plurality of first spacer structures are bonded to the circuit substrate, and the plurality of conductive terminals are bonded to the circuit substrate.

Images