TWI755164B - Method for diagnosing electrical connector and connector diagnosing device - Google Patents

Abstract

A method for diagnosing a C-type universal serial bus connector of an electronic device is disclosed. The method is to switch the electrical grounding of the first channel configuration setting pin and the second channel configuration setting pin, to generate the effect of inserting the electrical connector upper side up or lower side up into the C-type USB connector, and then test communication protocol functions and measuring voltage in sequence. After the test is completed, switch the grounding status of the first channel configuration setting pin and the second channel configuration setting pin again, and then test communication protocol functions and measuring voltage in sequence to complete the diagnosis. The method eliminates the need for plugging and unplugging the electrical connector and signal transformations, improving test efficiency.

Description

Method for testing connector and connector testing jig

The present invention relates to testing of connectors, in particular to a method for testing connectors of C-type universal serial busbar connectors and a connector testing jig.

The advantage of Type-C universal serial bus connector (USB Type-C) is that it can be plugged in both front and back. It supports USB2.0 and USB3.1 in function, and the power supply supports several power supply capabilities (USB PD, USB Power Delivery). ).

However, the advantages of supporting multi-function and any front and rear mating can complicate the test process when testing the function of the C-type universal serial bus connector. To support multi-function, it is necessary to set up separate test cards for different functions (USB2.0 and USB3.1), so that the signal transmission of the multi-layer connection process requires multiple signal conversion tests, which prolongs the test time. At the same time, the test equipment also needs to be connected to the aforementioned test card through a DIO device (Dual I/O) and an external power supply device, which makes it difficult to set up the test equipment.

At the same time, the forward insertion and reverse insertion of the C-type universal serial bus connector need to be tested separately. Manual insertion and removal are inefficient and prone to errors, such as repeated testing of positive insertion without testing reverse insertion, etc., which also reduces the testing efficiency.

Based on the above technical issues, the present invention provides a method for testing a connector and a connector testing jig, which can simplify the testing equipment, improve the testing efficiency and avoid the occurrence of testing errors.

The present invention is a method for testing a connector, which is used for testing a C-type universal serial bus connector of an electronic device, wherein the C-type universal serial bus connector has an upper row of pins to be tested and a lower row of pins to be tested a bit group, and the upper row of the pin-to-be-measured group and the lower row of the to-be-measured pin group respectively have a first channel configuration detection pin and a second channel configuration detection pin; the method includes:

A test end connector is provided; wherein, the test end connector has an upper row of test pin groups and a lower row of test pin groups; the upper row of test pin groups and the lower row of test pin groups respectively have a A first signal pin, a second signal pin conforming to a second communication protocol, at least one power pin, and at least one ground pin; the upper row of the test pin set has a first channel configuration setting pin, and the lower row The test pin group has a second channel configuration setting pin;

A cable is used to connect the C-type universal serial bus connector and the test terminal connector; wherein, the upper row of pins to be tested and the lower row of pins to be tested are respectively connected to the upper row of test pins and the lower row of test pins one of the groups;

Switch the first channel configuration setting pin to be electrically grounded through a pull-down resistor;

The power pins of the above row of test pin groups receive a driving power and enable the communication function of the first communication protocol;

The first signal pin of the above row of test pin groups receives a first communication protocol test signal and responds to the first communication protocol test signal;

Disable the communication function of the first communication protocol, and enable the communication function of a second communication protocol;

receiving a second communication protocol test signal and responding to the second communication protocol test signal with the second signal pin corresponding to the first channel configuration setting pin;

Disable the communication function of the second communication protocol;

Switch the configuration setting pin of the second channel to be electrically grounded through another pull-down resistor;

The power pins of the following test pin group receive driving power and enable the communication function of the first communication protocol;

The first signal pin of the following row of test pin groups receives the first communication protocol test signal and responds to the first communication protocol test signal;

Disable the communication function of the first communication protocol and enable the communication function of the second communication protocol;

receiving the second communication protocol test signal and responding to the second communication protocol test signal through the second signal pin corresponding to the second channel configuration setting pin; and

Disable the communication function of the second protocol.

The present invention also provides a connector testing fixture for testing a C-type universal serial bus connector of an electronic device, wherein the C-type universal serial bus connector has an upper row of pins to be tested and a lower row of pins to be tested. The test pin group has a first channel configuration detection pin and a second channel configuration detection pin in the upper row to be tested and the lower row to be tested. The connector test fixture includes a A test terminal connector, a cable, a first configuration channel switch, a second configuration channel switch, a programmable control chip, a busbar master chip and a power storage device.

The test terminal connector has an upper row of test pin groups and a lower row of test pin groups; wherein, the upper row of test pin groups and the lower row of test pin groups respectively have first signal pins conforming to a first communication protocol, A second signal pin, at least one power pin, and at least one ground pin of a second communication protocol; the upper test pin group has a first channel configuration setting pin, and the lower test pin group has a first Two-channel configuration setting pins.

The cable is used to connect the C-type universal serial bus bar connector and the test terminal connector; wherein, the upper row of the test pin group and the lower row of the test pin group are respectively connected to the upper row of test pin groups and the lower row of test pins. one of the group.

The first configuration channel switch and the second configuration channel switch are used to selectively switch the configuration setting pin of the first channel or the configuration setting pin of the second channel to be electrically grounded.

The programmable control chip is used to provide a control function to control the first configuration channel switch and the second configuration channel switch, and the programmable control chip is connected to the first row of test pin groups in the upper row and the first in the lower row of test pin groups The signal pin is used for receiving a first communication protocol test signal and responding to the first communication protocol test signal; wherein, when the first channel configuration setting pin is electrically grounded, it can be programmed to control the first test pin group of the upper row of the chip. A signal pin receives the first communication protocol test signal and responds to the first communication protocol test signal; when the second channel configuration setting pin is electrically grounded, the first signal pin of the lower row of test pin groups of the chip can be programmed to receive The first communication protocol test signal and responding to the first communication protocol test signal.

The bus-bar main control chip is connected to the upper test pin group and the second signal pin group of the lower test pin group, and is used for receiving a second communication protocol test signal and responding to the second communication protocol test signal; wherein, when The first channel configuration setting pin is electrically grounded, and the bus-bar main control chip receives the second communication protocol test signal and responds to the second communication protocol test signal through the second signal pin corresponding to the first channel configuration setting pin; The channel configuration setting pin is electrically grounded, and the busbar main control chip receives the second communication protocol test signal and responds to the second communication protocol test signal through the second signal pin corresponding to the second channel configuration setting pin.

The power storage device is used for receiving a driving power through the power pins for charging, and discharging to provide a working power. The programmable control chip and the bus-bar main control chip are respectively electrically connected to the power storage device to obtain working power; Wherein, when the first channel configuration setting pin is electrically grounded, the power pins of the upper row of test pins of the power storage device receive driving power; when the second channel configuration setting pin is electrically grounded, the power storage device lower row of test pins The power pins of the bit group receive driving power.

According to the method for testing a connector and the connector testing jig of the present invention, it is not necessary to repeatedly plug and unplug the cable during the test process, which reduces the time required for plugging and unplugging, and avoids plugging and unplugging errors. At the same time, the test process is sequentially executed by the programmable control chip and the busbar master chip of the connector test fixture, which reduces the hysteresis of signal conversion, shortens the time of each test, and improves the overall efficiency.

Please refer to FIG. 1 , FIG. 2 and FIG. 3 , it is a connector test fixture 1 for testing a Type-C USB connector 2 (Type-C USB connector) proposed by an embodiment of the present invention, including A test end connector 100 , a cable 200 , a first configuration channel switch 310 , a second configuration channel switch 320 , a programmable control chip 400 , a busbar master chip 500 and a power storage device 600 . Specifically, the connector test fixture 1 is used to test whether the C-type universal serial bus connector 2 of an electronic device 3 can work normally. The electronic device 3 can be, but is not limited to, a computer motherboard. The aforementioned computer motherboard is pre-installed with necessary memory, hard disk, operating system and test program, and is powered on to complete the boot. FIG. 1 is a circuit block diagram of a connector test fixture 1, FIG. 2 is a schematic diagram of the layout configuration of the connector test fixture 1 on a circuit board, and FIG. 3 is a connector test fixture 1 connected to an electronic device 3 and a storage device 4 schematic diagrams. The layout shown in FIG. 2 is only an example, and is not intended to limit the layout of the connector test fixture 1 on the circuit board.

As shown in FIG. 1 and FIG. 4 , the test end connector 100 has an upper row of test pin sets 110 and a lower row of test pin sets 120 ; the pin arrangement shown in FIG. Observe it.

As shown in FIG. 4 , the relative positions of the upper test pin groups 110 are marked with A1 to A12 in sequence. The composition of the upper test pin group 110 is described as follows. The two ground pins GND are located at A1 and A12. The first signal pins D+ and D- that conform to the first communication protocol (especially the USB 2.0 communication protocol) are located at A6 and A7. The second signal pins TX1+, TX1-, RX2-, RX2+ that conform to the second communication protocol (especially the USB 3.1 communication protocol) are located at A2, A3, A10, A11. The first channel configuration setting pin CC1 is located at A5. One or more power pins VBus are located at A4, A9. The pin located at A8 can be left open or other pin SBU1 used for other functions.

As shown in FIG. 4 , the relative positions of the lower test pin groups 120 are marked with B1 to B12 in sequence, and the arrangement direction of B1 to B12 is opposite to the arrangement direction of A1 to A12, so that the upper test pin group 110 and the lower row are arranged in the opposite direction. After the test pin group 120 is turned upside down, the same pin arrangement relationship can still be formed on the insertion surface of the test end connector 100 .

As shown in FIG. 4 , the composition of the lower test pin group 120 is described as follows. Two ground pins, GND, are located at B1 and B12. The first signal pins D+ and D- that conform to the first communication protocol (especially the USB 2.0 communication protocol) are located at B6 and B7. The second signal pins TX2+, TX2-, RX1-, RX1+ that conform to the second communication protocol (especially the USB 3.1 communication protocol) are located at B2, B3, B10, B11. The second channel configuration setting pin CC2 is located at B5. One or more power pins VBus are located at B4, B9. The pin located at B8 can be left open or other pin SBU2 used for other functions. The first channel configuration setting pin CC1 and the second channel configuration setting pin CC2 correspond to each other, so that after the upper test pin group 110 and the lower test pin group 120 are turned up and down, the second channel configuration setting pin CC2 can be located at The first channel configuration sets the original position of pin CC1.

As shown in FIG. 1 and FIG. 4 , the cable 200 is used to connect the C-type universal serial bus connector 2 and the test end connector 100 . The circuit configuration of the cable 200 (not shown) roughly matches the upper test pin group 110 and the lower test pin group 120 .

As shown in FIG. 1 and FIG. 5 , the C-type universal serial bus connector 2 has an upper row of pins to be tested 21 and a lower row of pins to be tested 22 ; the pin arrangement shown in FIG. 5 is a C-type universal The mating surface of the serial bus connector 2 is viewed.

As shown in FIG. 5 , the upper row of the pin groups 21 to be tested are marked with relative positions A1 to A12 in sequence. The composition of the upper row to be tested pin group 21 is described as follows. The two ground pins GND are located at A1 and A12. The first signal pins D+, D-, which conform to the first communication protocol (especially the USB 2.0 communication protocol), are located at A6 and A7. The second signal pins TX1+, TX1-, RX2-, RX2+ that conform to the second communication protocol (especially the USB 3.1 communication protocol) are located at A2, A3, A10, A11. The first channel configuration detection pin CC1' is located at A5. One or more power pins VBus are located at A4, A9. The pin located at A8 can be left open or other pin SBU1 used for other functions.

As shown in FIG. 5 , the lower row of pin groups 22 to be tested are marked with relative positions B1 to B12 in sequence, and the arrangement direction of B1 to B12 is opposite to the arrangement direction of A1 to A12, so that the upper row of pin groups 21 to be tested and After the lower row of the pin groups 22 to be tested are turned upside down, the same pin arrangement relationship can still be formed on the insertion surface of the C-type universal serial bus connector 2 . The composition of the lower row of the foot group to be tested 22 is described as follows. The two ground pins GND are located at B1 and B12. The first signal pins D+ and D- that conform to the first communication protocol (especially the USB 2.0 communication protocol) are located at B6 and B7. The second signal pins TX2+, TX2-, RX1-, RX1+ that conform to the second communication protocol (especially conform to USB 3.1) are located at B2, B3, B10, B11. The second channel configuration detection pin CC2' is located at B5. One or more power pins VBus are located at B4, B9. The pin located at B8 can be left open or other pin SBU2 used for other functions.

Referring to FIG. 6 , the pin configuration of the cable 200 is substantially the same as the pin configuration of the test end connector 100 , and is different from the Type-C cable in the prior art. In the Type-C cable of the prior art, the Vconn pin of the B5 pin is either empty, and the B6 and B7 are also empty without a wire configuration. In the present invention, B5 of the cable 200 is actually connected and defined as the second channel configuration setting pin CC2, and B6 and B7 are also connected and defined as the first signal pins D+, D-. Therefore, as shown in FIG. 4 , FIG. 5 and FIG. 6 , through the connection of the cable 200 , the upper row of the pin set 21 to be tested of the C-type universal serial bus connector 2 can be docked to the upper row of the test end connector 100 One of the test pin set 110 and the lower test pin set 120, and the lower test pin set 22 is connected to the other one of the upper test pin set 110 and the lower test pin set 120, so that C The pins of the type universal serial bus connector 2 can be all butted to the pins of the test terminal connector 100, leaving no empty pins.

As shown in FIG. 1 and FIG. 7 , the first configuration channel switch 310 and the second configuration channel switch 320 are used to selectively switch the first channel configuration setting pin CC1 or the second channel configuration setting pin CC2 through the pull-down resistor Rd. Sexual grounding.

As shown in FIG. 1 , the first configuration channel switch 310 and the second configuration channel switch 320 are electrically connected to the programmable control chip 400 . The programmable control chip 400 is used to control the first configuration channel switch 310 and the second configuration channel switch 320 to switch. The programmable control chip 400 is connected to the first signal pins D+ and D- of the upper test pin group 110 and the lower test pin group 120, and is used for performing the USB 2.0 signal processing function. The connector testing fixture 1 may further include an input connector 900 electrically connected to the programmable control chip 400 . The input connector 900 is used for connecting to an external device to read and write to the programmable control chip 400 and to change the program code of the programmable control chip 400 .

As shown in FIG. 1 , the bus master chip 500 is electrically connected to the second signal pins (TX1+, TX1-, RX2-, RX2+ and TX2+, TX2-, RX1-, RX1+) to perform USB 3.1 signal processing. Repeaters 510 and 520 (Re-Driver) can be arranged between the bus-bar main control chip 500 and the second signal pin to improve the signal quality. The aforementioned USB 3.1 signal processing function is performed by the pairing of TX1/RX1 and TX2/RX2, that is, when executing the USB 3.1 signal processing function, the upper test pin group 110 and the lower test pin group 120 are used respectively. The second signal pin.

As shown in FIG. 1 , the power storage device 600 is electrically connected to the power pins VBus of the upper test pin group 110 and the lower test pin group 120 to obtain the driving power USB through the C-type universal serial bus connector 2 5V. The driving power USB 5V is usually 5V direct current that conforms to the USB specification. The power storage device 600 can be charged by the driving power USB 5V, and discharged to provide the working power Vcc 5V. The above-mentioned USB 5V and Vcc 5V are for the convenience of drawing and distinguishing, and are not used to limit the source of the driving power USB 5V or the voltage of the driving power USB 5V/working power Vcc 5V. The power storage device 600 can be, but not limited to, a secondary battery, a super capacitor, or other devices that can be charged and discharged.

As shown in FIG. 1 , the programmable control chip 400 , the bus master chip 500 , the first configuration channel switch 310 and the second configuration channel switch 320 are respectively electrically connected to the power storage device 600 to obtain the working power Vcc 5V. That is to say, the power requirements of the programmable control chip 400 , the bus master chip 500 , and the first configuration channel switch 310 and the second configuration channel switch 320 are obtained through the power storage device 600 to obtain the operating power Vcc 5V, rather than directly Adopt drive power USB 5V. Therefore, when the driving power USB 5V is interrupted, the programmable control chip 400 , the bus master chip 500 , the first configuration channel switch 310 and the second configuration channel switch 320 can still operate. When the voltage demand is lower than 5V, such as 3.3V, the working power Vcc 5V can be transmitted to the voltage converter 700 to reduce the voltage to 3.3V first, and then transmitted to the required components.

Referring to FIGS. 8A-8B and FIGS. 9A-9C , the method for testing the C-type universal serial bus connector 2 performed by the connector testing fixture 1 is further described below. The processes shown in FIGS. 8A to 8B and FIGS. 9A to 9C are the steps performed by the electronic device 3 to be tested and the connector testing jig 1 , respectively.

As shown in FIG. 8A , at the beginning of the test, the electronic device 3 , such as a computer motherboard, is firstly activated, and the C-type universal serial bus connector 2 to be tested is initialized, as shown in step S101 .

At this time, the computer motherboard continues to apply voltage to the first channel configuration detection pin CC1' and the second channel configuration detection pin CC2' through the pull-up resistor Rp. Next, the electronic device 3 continuously detects whether a voltage drop occurs at the first channel configuration detection pin CC1' and the second channel configuration detection pin CC2', as shown in step S102.

As shown in FIG. 8A and FIG. 9A , then, the C-type universal serial bus connector 2 and the test end connector 100 of the connector test fixture 1 are connected by cables 200 , as in steps S103 and S201 .

Referring to FIG. 4 and FIG. 5 , when connecting the C-type universal serial bus connector 2 and the test-end connector 100, it is not limited whether the test-end connector 100 is forward or reversed with respect to the C-type universal serial bus connector 2 . As long as the upper row of the test pin group 21 is docked to one of the upper row of the test pin group 110 and the lower row of the test pin group 120, and the lower row of the test pin group 22 is docked to the upper row of the test pin group 110 and The other one of the lower row of test pin groups 120 . Therefore, during the test, the test operator does not need to pay attention to whether the cable 200 is plugged into the C-type universal serial bus connector 2 forwardly or backwardly.

In the above-mentioned plug-in relationship, there may be two plug-in states: state 1, the upper row of test pin groups 21 are docked to the upper row of test pin groups 110, and the lower row of test pin groups 22 are docked to the lower row of test pins Pin group 120 ; state 2, the upper row of the test pin group 21 is docked to the lower row of the test pin group 120 , and the lower row of the under-test pin group 22 is docked to the upper row of the test pin group 110 . State 1 will be described below.

As shown in FIG. 7 and FIG. 9A , the programmable control chip 400 controls the first configuration channel switch 310 to switch the first channel configuration setting pin CC1 to be electrically grounded through the pull-down resistor Rd, as shown in step S202 . In this step, since the electronic device 3 has not yet provided the driving power USB 5V, the working power Vcc 5V required by the connector test fixture 1 at this time is provided by the power stored by the power storage device 600 .

As shown in FIG. 8A , the electronic device 3 continues to detect the voltage drop of the first channel configuration detection pin CC1 ′ and the second channel configuration detection pin CC2 ′, and according to the first channel configuration detection pin CC1 ′ or The second channel is configured to detect the voltage drop of the pin CC2', and activate the power pin VBus of the corresponding upper row of the pin group 21 to be tested or the lower row of the pin group to be tested 22, as shown in step S104. Taking the aforementioned connection method as an example, the electronic device 3 will detect the voltage drop of the first channel configuration detection pin CC1 ′, and enable the power pin VBus of the corresponding upper row of the pin group 21 to be tested to output driving power. USB 5V.

As shown in FIG. 8A , then, the first signal pins D+ and D- of the pin group 21 to be tested in the upper row of the electronic device 3 send a USB 2.0 test signal, and determine whether a response is received within a certain period of time, as in step S105 shown.

As shown in FIG. 9A , after the connector test fixture 1 receives the operating power Vcc 5V through the power pin VBus of the upper test pin group 110 , the programmable control chip 400 enables the USB 2.0 communication function, as shown in step S203 .

As shown in FIG. 9A , next, the first signal pins D+ and D- of the test pin group 110 in the upper row of the programmable control chip 400 receive the USB 2.0 test signal and respond to the USB 2.0 test signal, as shown in step S204 . In steps S105 and S203 , it is mainly to test whether the corresponding upper row of pin groups 21 to be tested can normally perform USB 2.0 communication. If the first signal pins D+ and D- of the upper row of the pin group 21 to be tested cannot send and receive signals normally, the programmable control chip 400 cannot respond to the USB 2.0 test signal, so that the electronic device 3 judges that the test has failed and interrupts the test process, and record Type C Universal Serial Bus Connector 2 as defective.

As shown in FIG. 9A , after step S204 , the programmable control chip 400 of the connector test fixture 1 measures the voltage of the first channel configuration setting pin CC1 for the electronic device 3 to determine the corresponding upper row of the pins to be tested Whether the power output capability of the bit group 21 or the lower row to be tested pin group 22 is normal, as shown in step S205.

The electronic device 3, such as a computer motherboard, continuously applies a voltage to the first channel configuration detection pin CC1' and the second channel configuration detection pin CC2' through the pull-up resistor Rp, and the voltage is outputted by the power pin VBus. Drive power USB 5V related. The first channel configuration setting pin CC1 and the second channel configuration setting pin CC2 of the connector test fixture 1 are grounded through the pull-down resistor Rd. At this time, the voltage drop generated by the pull-up resistor Rp can be obtained, and the power supply capability (Power Delivery) of the electronic device 3 can be obtained to determine whether the driving power USB 5V output by the power pin VBus is normal, and the type-C universal serial bus. The power output specification that connector 2 conforms to.

As shown in Figure 7, the specific detection method is to directly detect the voltage of the first channel configuration detection pin CC1' and the second channel configuration detection pin CC2'. As shown in FIG. 8, detecting the voltage of the first channel configuration setting pin CC1 and the second channel configuration setting pin CC2 of the connector test fixture 1 is also equivalent to detecting the first channel configuration detection pin CC1' And the second channel is configured to detect the voltage of the pin CC2'.

Taking the power supply capability of USB 5V output from the power pin VBus as 5V/3A (vRd-3.0) as an example, the C-type universal serial bus connector 2 can provide the CC1'/CC2' pins under the specification requirements. 330µA current. The resistance value of the pull-down resistor Rd is 5.1k. At this time, the voltage of the first channel configuration setting pin CC1 or the second channel configuration setting pin CC2 is 330μA * 5.1k=1.683V. Therefore, if the measured voltage of the first channel configuration setting pin CC1 or the second channel configuration setting pin CC2 is 1.683V (measured at the node pointed to by CC1/CC2 in Figure 7), or it falls within a certain range Within, the power supply capability of the C-type universal serial bus connector 2 and the specifications it meets can be determined.

The power supply capacity and the corresponding voltage range are shown in Table 1 below: detect Minimum voltage maximum voltage Voltage threshold upper limit vRd-USB 0.25V 0.61V 0.66V vRd-1.5 0.70V 1.16V 1.23V vRd-3.0 1.31V 2.04V Table I

Therefore, the connector test fixture 1 can measure the voltage of the first channel configuration setting pin CC1 or the second channel configuration setting pin CC2, and send the result through the USB 2.0 communication function and the first signal pins D+, D- After the transmission is sent to the electronic device 3, the electronic device 3 can determine whether the power output capability of the corresponding upper row to be tested pin group 21 or lower row to be tested pin group 22 is normal, as shown in step S106. Likewise, if the electronic device 3 determines that the power supply capability fails, the testing process is interrupted, and the C-type universal serial bus connector 2 is recorded as a defective product.

As shown in FIG. 8B , after the test is completed, the electronic device 3 waits for a certain period of time to send a signal to the second signal pin (TX1+, TX1-, RX1-, RX1+) corresponding to the first channel configuration detection pin CC1' USB 3.1 test signal, and determine whether a response is received within a certain period of time, as shown in step S107.

As shown in FIG. 9A and FIG. 9B , the programmable control chip 400 disables the USB 2.0 communication function, and controls the bus master chip 500 to enable a USB 3.1 communication function, as shown in step S206 . Next, the connector test fixture 1 receives the USB 3.1 test signal through the second signal pin (TX1+, TX1-, RX1-, RX1+) corresponding to the first channel configuration setting pin CC1, and transmits the USB 3.1 test signal to the bus master chip 500 for Respond to the USB 3.1 test signal, as shown in step S207.

In steps S107 and S207, it is mainly to test whether the second signal pins of each group can perform USB 3.1 communication normally. If the second signal pins of the C-type universal serial bus connector 2 are (or TX2+, TX2-, RX2-, RX2+) cannot send and receive signals normally, then the bus master chip 500 cannot respond to the USB 3.1 test signal, so that the electronic device 3 judges that the test has failed, interrupts the test process, and records the type-C common Serial bus connector 2 is defective.

As shown in FIG. 9B , the programmable control chip 400 controls the bus master chip 500 to disable the USB 3.1 communication function, as shown in step S208 . The programmable control chip 400 controls the first configuration channel switch 310 and the second configuration channel switch 320 to switch the first channel configuration setting pin CC1 to stop grounding, and switch to the second channel configuration setting pin CC2 through another The pull-up resistor Rd is electrically grounded, as shown in step S209. This step is equivalent to unplugging the cable 200 and then re-inserting, but in fact, it is not necessary to perform re-insertion, which can prevent the tester from forgetting to perform re-insertion or incorrectly inserting in the testing process.

As shown in FIG. 8B , at this time, the electronic device 3 stops outputting the driving power USB 5V from the power pin VBus of the upper row of the pin group 21 to be tested, so the connector test fixture 1 uses the power stored by the power storage device 600 instead. Continue to provide working power Vcc 5V. The electronic device 3 continues to detect the voltage drop of the first channel configuration detection pin CC1' and the second channel configuration detection pin CC2', and according to the first channel configuration detection pin CC1' or the second channel configuration detection pin CC1' When the voltage of the test pin CC2' drops, the power pin VBus of the corresponding upper row under test pin group 21 or lower row under test pin group 22 is activated to output the driving power USB 5V, as shown in step S108. Taking the aforementioned connection method as an example, the electronic device 3 will detect the voltage drop of the second channel configuration detection pin CC2', and enable the power pin VBus of the lower row of the pin group 22 to be tested to output the driving power USB 5V. .

As shown in FIG. 8B , the electronic device 3 then sends a USB 2.0 test signal from the first signal pins D+ and D- of the pin group 22 to be tested in the lower row, and determines whether a response is received within a certain period of time, as in step S109 shown.

As shown in FIG. 9B , after the connector test fixture 1 receives the operating power Vcc 5V through the power pin VBus of the lower test pin group 120 , the programmable control chip 400 enables the USB 2.0 communication function, as shown in step S210 .

As shown in FIG. 9B , next, the first signal pins D+ and D- of the lower test pin group 120 of the programmable control chip 400 receive the USB 2.0 test signal and respond to the USB 2.0 test signal, as shown in step S211 . Steps S109 and S211 are used to test whether the lower test pin group 22 can normally perform USB 2.0 communication. If the first signal pins D+ and D- of the lower test pin group 120 cannot send and receive signals normally, it can be programmed The control chip 400 cannot respond to the USB 2.0 test signal, so that the electronic device 3 judges that the test has failed and interrupts the test process, and records the C-type universal serial bus connector 2 as a defective product.

As shown in FIG. 8B and FIG. 9B , after step S211 , the programmable control chip 400 of the connector test fixture 1 measures the voltage of the second channel configuration setting pin CC2 to determine the lower row of the pin group 22 to be tested Whether the power output capability is normal, as shown in step S212. The connector test fixture 1 transmits the voltage of the second channel configuration setting pin CC2 to the electronic device 3 through the USB 2.0 communication function and the first signal pins D+, D-, and the electronic device 3 can determine the lower row of the pins to be tested. Whether the power output capability of the group 22 is normal is shown in step S110.

As shown in FIG. 8B , after the test is completed, the electronic device 3 waits for a certain period of time, sends a USB 3.1 test signal from the second signal pin corresponding to the second channel configuration detection pin CC2 ′, and determines whether it is within a certain period of time A response is received, as shown in step S111.

As shown in FIG. 9C , the programmable control chip 400 then disables the USB 2.0 communication function, and controls the bus master chip 500 to enable a USB 3.1 communication function, as shown in step S213 . Next, the second signal pin of the lower test pin group 120 of the connector test fixture 1 receives the USB 3.1 test signal and transmits it to the bus master chip 500 to respond to the USB 3.1 test signal, as shown in step S214.

In steps S111 and S214, it is mainly to test whether the second signal pins TX2+, TX2-, RX2-, RX2+ can normally carry out USB 3.1 communication, if the second signal pins TX2+, TX2-, RX2-, RX2+ cannot send and receive normally signal, the bus master chip 500 cannot respond to the USB 3.1 test signal, so that the electronic device 3 judges that the test fails and interrupts the test process, and records the C-type universal serial bus connector 2 as a defective product.

At this point, the test operation is completed, and the programmable control chip 400 controls the bus master chip 500 to disable the USB 3.1 communication function, as shown in step S215. The programmable control chip 400 can further control the first configuration channel switch 310 and the second configuration channel switch 320 to switch the first channel configuration setting pin CC1 to be electrically grounded, and switch the second channel configuration setting pin CC2 to stop grounding , to restore the initial state, as shown in step S216. Similarly, after completing the test of the lower row of pin groups 22 to be tested, the electronic device 3 also stops the test and records that the C-type universal serial bus connector 2 is normal, as shown in steps S112 and S217 .

So far, the forward insertion and reverse insertion tests of the C-type universal serial bus connector 2 can be completed without plugging or unplugging the cable 200 .

As shown in FIG. 8B , when the electronic device 3 determines that the C-type universal serial bus connector 2 is normal, that is, step S111 is completed without interrupting the test process, the electronic device 3 can return to step S102 and re-execute the test process to Repeatedly carry out multiple tests, each test can be recorded in the record file, including the time of responding to the USB 2.0, 3.1 test signal, and the voltage obtained by the first/second channel configuration setting pin CC1/CC2. Alternatively, the plurality of C-type universal serial bus connectors 2 of the electronic device 3 can be respectively connected to different connector test fixtures 1 for simultaneous testing, and a record file is used to record the data of each C-type universal serial bus connector 2 Test Results.

Referring to FIG. 1 , FIG. 2 and FIG. 3 , the connector testing fixture 1 may further include an expansion connector 800 , and the expansion connector 800 includes necessary electrical connectors and signal conversion chips. The expansion connector 800 is connected to the bus master chip 500 and is used for a storage device 4 to be plugged in. After steps S107 and S111, the electronic device 3 can further perform a data read/write test on the storage device 4 through the second signal pins TX1+, TX1-, RX1-, RX1 (or +TX2+, TX2-, RX2-, RX2+) , to test the correctness of data reading and writing and the reading and writing rate.

The aforementioned test does not require repeated plugging and unplugging of the cable 200, which reduces the time required for plugging and unplugging, and avoids plugging and unplugging errors. At the same time, the test process is sequentially executed by the programmable control chip 400 and the busbar master chip 500 of the connector test fixture 1 , which reduces the hysteresis of signal conversion, shortens the time of each test, and improves the overall efficiency.

1: Connector test fixture 100: Test end connector 110: Upper row test pin group 120: Lower row test pin group 200: Cable 310: The first configuration channel switch 320: Second configuration channel switch 400: Programmable control chip 500: bus master chip 510, 520: Repeater 600: Power storage device 700: Voltage Converter 800: Expansion Connector 900: Input Connector 2: Type C Universal Serial Bus Connector 21: The upper row of pins to be tested 22: The lower row of pins to be tested 3: Electronic device 4: Storage device A1~A12, B1~B12: Position markers CC1: The first channel configuration setting pin CC2: The second channel configuration setting pin CC1’: The first channel configuration detection pin CC2’: The second channel configuration detection pin GND: ground pin D+, D-: The first signal pin TX1+, TX1-, TX2+, TX2-, RX1-, RX1+, RX2-, RX2+: The second signal pin VBus: power pin SBU1, SBU2: other pins USB 5V: drive power Vcc 5V: working power Rp: pull-up resistor Rd: pull-down resistor S101~S112, S201~S217: Steps

FIG. 1 is a circuit block diagram of a connector testing fixture according to an embodiment of the present invention. FIG. 2 is a schematic diagram of the layout of the connector test fixture disposed on the circuit board according to the embodiment of the present invention. 3 is a schematic diagram of a connector test fixture connected to an electronic device and a storage device according to an embodiment of the present invention. FIG. 4 is the pin configuration viewed from the insertion surface of the test end connector according to the embodiment of the present invention. FIG. 5 is the pin configuration viewed from the insertion surface of the C-type universal serial bus connector according to the embodiment of the present invention. FIG. 6 is a schematic circuit diagram of a cable according to an embodiment of the present invention. 7 is a schematic circuit diagram of a first configuration channel switch and a second configuration channel switch according to an embodiment of the present invention. FIG. 8A and FIG. 8B are a test flow performed by an electronic device according to an embodiment of the present invention. 9A to FIG. 9C are the test flow performed by the electrical connector test fixture according to the embodiment of the present invention.

1: Connector test fixture

100: Test end connector

310: The first configuration channel switch

320: Second configuration channel switch

400: Programmable control chip

500: bus master chip

510, 520: Repeater

600: Power storage device

700: Voltage Converter

800: Expansion Connector

900: Input Connector

4: Storage device

USB 5V: drive power

Vcc 5V: working power

D+, D-: The first signal pin

Claims (8)

A method for testing a connector is used for testing a C-type universal serial bus connector of an electronic device, wherein the C-type universal serial bus connector has an upper row of pins to be tested and a lower row of pins to be tested A set of pins to be tested in the upper row and the set of pins to be tested in the lower row respectively have a first channel configuration detection pin and a second channel configuration detection pin; the method includes: providing a test terminal Connector; wherein, the test end connector has an upper row of test pin sets and a lower row of test pin sets; the upper row of test pin sets and the lower row of test pin sets respectively have a first row of test pins that conform to a first communication protocol. a signal pin, a second signal pin conforming to a second communication protocol, at least one power pin, and at least one ground pin, the upper test pin group has a first channel configuration setting pin, and the lower test pin group A row of test pin sets has a second channel configuration setting pin; a cable is used to connect the C-type universal serial bus connector and the test end connector; wherein the upper row of the pin set to be tested and the lower row The pin group to be tested is respectively connected to one of the upper test pin group and the lower test pin group; the first channel configuration setting pin is switched to be electrically grounded through a pull-down resistor; the upper test pin is used The at least one power pin of the bit group receives a driving power and enables the communication function of the first communication protocol; the first signal pin of the upper row test pin group receives a first communication protocol test signal, and returns a test signal of the first communication protocol. should test the signal of the first communication protocol; disable the communication function of the first communication protocol, and enable the communication function of the second communication protocol; Receive a second communication protocol test signal with the second signal pin corresponding to the first channel configuration setting pin and respond to the second communication protocol test signal; disable the communication function of the second communication protocol; switch the second communication protocol The channel configuration setting pin is electrically grounded through another pull-down resistor; the driving power is received by the at least one power pin of the lower row of test pin groups, and the communication function of the first communication protocol is enabled; the lower row is used to test the first signal pin of the pin group receives the first communication protocol test signal and responds to the first communication protocol test signal; disables the communication function of the first communication protocol and enables the communication function of the second communication protocol; receiving the second communication protocol test signal and responding to the second communication protocol test signal with the second signal pin corresponding to the configuration setting pin of the second channel; deactivating the communication function of the second communication protocol; using the electronic device Continue to apply voltage to the first channel configuration detection pin and the second channel configuration detection pin, and continue to detect whether the first channel configuration detection pin and the second channel configuration detection pin occur The voltage drops to activate the at least one power pin of the corresponding upper row of pins to be tested or the lower row of pins to be tested to provide the driving power; the electronic device passes through the corresponding upper row of pins to be tested sending the first communication protocol test signal from the first signal pin of the pin group or the lower row of the pin group to be tested, and determining whether a response is received within a certain period of time; and The electronic device sends the second communication protocol test signal through the corresponding first channel configuration detection pin or the second signal pin of the second channel configuration detection pin, and judges whether the signal is received within a certain period of time. to the response. The method for testing a connector according to claim 1, further comprising providing a power storage device, receiving the driving power for charging, and discharging to provide a working power. The method for testing a connector according to claim 1, further comprising: after responding to the first communication protocol test signal, measuring the voltage of the corresponding first channel configuration setting pin or the second channel configuration setting pin , and transmit the result to the electronic device through the communication function of the first communication protocol. The method for testing a connector according to claim 1, further comprising providing an expansion connector for plugging a storage device, and using the electronic device to read and write data to the storage device through the second signal pin test. A connector test fixture is used for testing a C-type universal serial bus connector of an electronic device; wherein, the C-type universal serial bus connector has an upper row of pins to be tested and a lower row of pins to be tested group, and the upper row of pins to be tested and the lower row of pins to be tested have a first channel configuration detection pin and a second channel configuration detection pin; the connector test fixture includes: A test terminal connector has an upper row of test pin sets and a lower row of test pin sets; wherein the upper row of test pin sets and the lower row of test pin sets respectively have a first communication protocol conforming to a first communication protocol. a signal pin, a second signal pin conforming to a second communication protocol, at least one power pin, and at least one ground pin; the upper row of test pin groups has a first channel configuration setting pin, and the lower row The test pin group has a second channel configuration setting pin; a cable for connecting the C-type universal serial bus connector and the test terminal connector; wherein the upper row of the test pin group and the lower row of the test pin group are respectively connected to the upper row of test pins One of the bit group and the lower test pin group; a first configuration channel switch and a second configuration channel switch for selectively switching the first channel configuration setting pin or the second channel configuration setting pin Potentially grounded; a programmable control chip for providing a control function to control the first configuration channel switch and the second configuration channel switch, and the programmable control chip is connected to the upper row of test pins The first signal pin of the group and the lower test pin group is used for receiving a first communication protocol test signal and responding to the first communication protocol test signal; wherein, when the first channel configuration setting pin is electrically grounded , the programmable control chip receives the first communication protocol test signal and responds to the first communication protocol test signal through the first signal pin of the upper row test pin group; when the second channel is configured to set the electrical properties of the pins grounded, the programmable control chip receives the first communication protocol test signal through the first signal pin of the lower row test pin group and responds to the first communication protocol test signal; a bus-bar main control chip is connected to the The upper test pin group and the second signal pin group of the lower test pin group are used for receiving a second communication protocol test signal and responding to the second communication protocol test signal; wherein, when the first channel is configured The setting pin is electrically grounded, and the bus-bar main control chip receives the second communication protocol test signal and responds to the second communication protocol test signal through the second signal pin corresponding to the first channel configuration setting pin; The two-channel configuration setting pin is electrically grounded, and the bus master chip receives the second communication protocol test signal through a second signal pin corresponding to the second channel configuration setting pin and responds to the second communication protocol test signal; a power storage device for receiving a driving power through the power pins for charging, and discharging to provide a working power, the programmable control chip and the busbar master chip are respectively electrically connected to the power storage device, to obtain the operating power; wherein, when the first channel configuration setting pin is electrically grounded, the power storage device receives the driving power through the power pin of the upper row test pin group; when the second channel configuration setting pin is electrically grounded Potentially grounded, the power storage device receives the driving power through the power pins of the lower test pin group; and an input connector electrically connected to the programmable control chip for connecting to an external device , to read and write the programmable control chip, and change the program code of the programmable control chip. The connector testing jig as claimed in claim 5 further includes two repeaters, which are respectively disposed between the bus-bar main control chip and the corresponding second signal pins, so as to improve the signal quality. The connector test fixture of claim 5, wherein after responding to the first communication protocol test signal, the programmable control chip is further used to measure the corresponding first channel configuration setting pin or the first channel The two-channel configuration sets the voltage of the pin, and outputs the result through the communication function of the first communication protocol. The connector testing jig according to claim 5, further comprising providing an expansion connector electrically connected to the programmable control chip, the expansion connector is used for a storage device to be plugged in, and the storage device is connected to the expansion connector. Conduct data reading and writing tests.

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