TWI753660B - Display panel - Google Patents

Abstract

A display panel is provided. The display panel includes a driving circuit, a first pixel and a second pixel. The driving circuit has a driving terminal and is configured to generate a driving current according to a mode selection signal and a voltage on the driving terminal. The first pixel includes a plurality of first sub-pixels. The second pixel is adjacent to the first pixel, and the second pixel includes a plurality of second sub-pixels. When the mode selection signal indicates a power saving display mode, at least one first selected sub-pixel in the first pixel is lit, and at least one second selected sub-pixel in the second pixel is lit, and a display wavelength of the at least one first selected sub-pixel is different from a display wavelength of the at least one second selected sub-pixel.

Description

display panel

The present invention relates to a display panel, and more particularly, to a display panel capable of switching display modes and effectively reducing power consumption.

With the vigorous development of liquid crystal display panels, panel technologies with low power consumption have gradually become popular. However, in the application of wearable electronic products and automotive electronic products, when the power of the battery in the electronic product is about to be exhausted, if the screen displayed by the electronic product is still in the normal operation mode (for example, high frequency and high-resolution color display mode) to display, it will make the battery power consumption faster, thereby affecting the use time of electronic products.

In view of this, how to adjust the display mode of the display screen of the display panel according to the power state of the battery so as to reduce the overall power consumption will be a key subject for those skilled in the art.

The present invention provides a display panel capable of switching display modes and effectively reducing the overall power consumption.

The present invention provides a display panel. The display panel includes a driving circuit, a first pixel and a second pixel. The driving circuit has a driving terminal for generating a driving current according to the mode selection signal and the voltage on the driving terminal. The first pixel includes a plurality of first sub-pixels. The second pixel is adjacent to the first pixel, and the second pixel includes a plurality of second sub-pixels. When the mode selection signal indicates the power saving display mode, at least one first selected sub-pixel in the first pixel is lit, and at least one second selected sub-pixel in the second pixel is lit, And the display wavelength of at least one first selected sub-pixel is different from the display wavelength of at least one second selected sub-pixel.

Based on the above, the display panels according to the embodiments of the present invention can partially light up some sub-pixels or light-emitting elements in the power-saving display mode, so that these sub-pixels or light-emitting elements only display black or white light. In this way, the display panel of the present invention can effectively reduce the overall power consumption, so as to achieve the effect of power saving.

The term "coupled (or connected)" as used throughout this specification (including the scope of the application) may refer to any direct or indirect means of connection. For example, if it is described in the text that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be connected to the second device through another device or some other device. indirectly connected to the second device by a connecting means. Also, where possible, elements/components/steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements/components/steps that use the same reference numerals or use the same terminology in different embodiments may refer to relative descriptions of each other.

FIG. 1 is a schematic diagram of a display panel according to a first embodiment of the present invention. Referring to FIG. 1 , in this embodiment, the display panel 100 includes a driving circuit 110 , pixel selection switches T1 - T5 , pixels PX1 - PX5 , and auxiliary switches B11 , B12 and B21 . The display panel 100 can select corresponding pixels PX1 to PX5 through the pixel selection switches T1 to T5 to light up a sub-pixel of the selected pixels. In addition, the pixels PX1 to PX5 in this embodiment may share the same driving circuit 110 .

Regarding the circuit configuration of the driving circuit 110 , in this embodiment, the driving circuit 110 includes a driving transistor MP, a capacitor CD1 , a data writing circuit 111 , a laser circuit 112 , an initialization circuit 113 and a voltage holding circuit 114 . The first terminal of the driving transistor MP is coupled to the power supply voltage ELVDD, and the driving terminal PD of the driving transistor MP is coupled to the second terminal of the capacitor CD1. The driving transistor MP is based on the power supply voltage ELVDD and generates the driving current ID according to the voltage on the driving terminal PD.

The data writing circuit 111 includes a transistor M1. The first terminal of the transistor M1 is coupled to the data voltage VDATA, the second terminal of the transistor M1 is coupled to the first terminal of the capacitor CD1, and the control terminal of the transistor M1 receives the write control signal WR. Laser circuit 112 includes transistor M2. The first end of the transistor M2 is coupled to the operating voltage VBP, the second end of the transistor M2 is coupled to the first end of the capacitor CD1, and the control end of the transistor M2 receives the control signal EMG.

The initialization circuit 113 includes transistors M3 and M4. The first end of the transistor M3 is coupled to the drive end PD of the drive transistor MP, the second end of the transistor M3 is coupled to the second end of the drive transistor MP, and the control end of the transistor M3 receives the write control signal WR . The first terminal of the transistor M4 is coupled to the reference voltage VREF, the second terminal of the transistor M4 is coupled to the second terminal of the driving transistor MP, and the control terminal of the transistor M4 receives the read control signal RD.

The voltage hold circuit 114 includes transistors M5, M6 and a capacitor CD2. The second terminal of the transistor M5 is coupled to the first terminal of the capacitor CD1, and the control terminal of the transistor M5 receives the mode selection signal AOD. The second terminal of the transistor M6 is coupled to the second terminal of the capacitor CD1, and the control terminal of the transistor M6 receives the mode selection signal AOD. The capacitor CD2 is coupled between the first end of the transistor M5 and the first end of the transistor M6.

In this embodiment, a control signal generator (not shown) disposed outside the display panel 100 can generate a corresponding mode selection signal AOD to the driving circuit 110 according to the received instruction signal. For example, if the indication signal indicates that the power of the battery in the electronic device or the display device is maintained in a normal state (for example, the power of the battery is higher than or equal to a preset threshold), the control signal generator (not shown) can generate a mode selection signal AOD that is disabled (eg, a high voltage level) to the driving circuit 110 , so that the display panel 100 can perform a display operation in a normal display mode.

On the contrary, if the indication signal indicates that the power of the battery in the electronic device or the display device is about to be exhausted (for example, the power of the battery is lower than the preset threshold), the control signal generator (not shown) ) can generate a mode selection signal AOD that is enabled (eg, a low voltage level) to the driving circuit 110 , so that the display panel 100 can perform a display operation in a power-saving display mode. In other words, the display panel 100 can switch the display mode according to the mode selection signal AOD indicating the normal display mode or the power saving display mode.

Regarding the circuit configuration of the pixel selection switches T1 ˜ T5 , in this embodiment, the pixel selection switches T1 ˜ T5 are respectively coupled between the driving circuit 110 and the pixels PX1 ˜ PX5 . For example, taking the pixel selection switch T1 as an example, the first terminal of the pixel selection switch T1 is coupled to the driving circuit 110, the second terminal of the pixel selection switch T1 is coupled to the pixel PX1, and the pixel selection switch T1 The control end of the device receives the laser control signal EM1, and the configuration relationship between the remaining pixel selection switches T2-T5 and the pixels PX2-PX5 can be deduced by analogy. The pixel selection switches T2-T5 can be controlled by the laser control signals EM2-EM5 respectively.

On the other hand, regarding the circuit configuration of the pixels PX1 to PX5, the pixels PX1 to PX5 include a plurality of sub-pixels SP11 to SP13, SP21 to SP23, SP31 to SP33, SP41 to SP42, and SP51. The pixel PX2 is adjacent to the pixel PX1, the pixel PX3 is adjacent to the pixel PX2, the pixel PX4 is adjacent to the pixel PX3, and the pixel PX5 is adjacent to the pixel PX4. For example, in this embodiment, pixel PX1 includes 3 groups of sub-pixels SP11-SP13; pixel PX2 includes 3 groups of sub-pixels SP21-SP23; pixel PX3 includes 3 groups of sub-pixels SP31-SP33; The pixel PX4 includes two groups of sub-pixels SP41-SP42; the pixel PX5 includes one group of sub-pixels SP51.

Further, in the pixel PX1 shown in FIG. 1 , the sub-pixels SP11 to SP13 include control switches A11 to A13 , light-emitting elements D11 to D13 , and capacitors C11 to C13 . Taking the sub-pixel SP11 as an example, the sub-pixel SP11 may be composed of a control switch A11 , a light-emitting element D11 and a capacitor C11 .

Specifically, the first end of the control switch A11 is coupled to the second end of the pixel selection switch T1, and the control end of the control switch A11 receives the laser control signal EM4. The anode terminal of the light emitting element D11 is coupled to the second terminal of the control switch A11 and the first terminal of the capacitor C11, and the cathode terminal of the light emitting element D11 is coupled to the second terminal of the capacitor C11 and the reference ground voltage ELVSS. The internal circuit configurations of the remaining sub-pixels SP12-SP13 can be deduced by referring to the relevant description of the sub-pixel SP11, and thus will not be repeated here. The control switches A12-A13 in the sub-pixels SP12-SP13 can be controlled by the laser control signals EM5-EM6, respectively.

On the other hand, in the pixels PX2 to PX5 shown in FIG. 1 , the sub pixels SP21 to SP23 include control switches A21 to A23, light-emitting elements D21 to D23, and capacitors C21 to C23; and the sub pixels SP31 to SP33 include control switches A21 to A23. Switches A31-A33, light-emitting elements D31-D33, and capacitors C31-C33; sub-pixels SP41-SP42 include control switches A41-A42, light-emitting elements D41-D42, and capacitors C41-C42; sub-pixel SP51 includes control switch A51, light-emitting element D51 and capacitor C51.

It is worth mentioning that the circuit configuration inside the sub-pixels SP21-SP23, SP31-SP33, SP41-SP42 and SP51 can also be analogized with reference to the relevant description of the sub-pixel SP11, so it is not repeated here.

Among them, the control switches A21-A23 in the sub-pixels SP21-SP23 can be controlled by the laser control signals EM4-EM6 respectively; the control switches A31-A33 in the sub-pixels SP31-SP33 can be controlled by the laser control signals EM4- EM6; the control switches A41-A42 in the sub-pixels SP41-SP42 can be controlled by the laser control signals EM5-EM6 respectively; the control switch A51 in the sub-pixel SP51 can be controlled by the laser control signal EM6.

It is particularly mentioned that the light-emitting elements D11-D13, D21-D23, D31-D33, D41-D42, and D51 of this embodiment may be, for example, organic light-emitting diodes (Organic Light Emitting Diode, OLED), miniature light-emitting diodes LEDs (Micro LEDs) or other light-emitting elements are not particularly limited in the present invention. These sub-pixels SP11-SP13, SP21-SP23, SP31-SP33, SP41-SP42, and SP51 can be sub-pixels corresponding to different display wavelengths (for example, sub-pixels that display the three primary colors of red, green, and blue respectively), and this implementation The example is not limited to the number and arrangement order of the sub-pixels of the three primary colors of red, green and blue in the sub-pixels SP11-SP13, SP21-SP23, SP31-SP33, SP41-SP42 and SP51. For example, in this embodiment, the sub-pixels SP11, SP21, SP31 and SP41 can be sub-pixels displaying red; the sub-pixels SP12, SP22, SP32 and SP42 can be sub-pixels displaying green; Pixels SP13, SP23, SP33 and SP51 may be sub-pixels displaying blue, but the present invention is not limited thereto.

Regarding the circuit configurations of the auxiliary switches B11, B12 and B21, in this embodiment, the first terminal of the auxiliary switch B11 is coupled to the second terminal of the pixel selection switch T1, and the second terminal of the auxiliary switch B11 is coupled to the sub-picture The anode terminal of the light-emitting element D11 of the pixel SP11, and the auxiliary switch B11 is controlled by the laser control signal EM2. The first terminal of the auxiliary switch B12 is coupled to the second terminal of the pixel selection switch T1, the second terminal of the auxiliary switch B12 is coupled to the anode terminal of the light-emitting element D12 of the sub-pixel SP12, and the auxiliary switch B12 is controlled by the laser Control signal EM3. The first terminal of the auxiliary switch B21 is coupled to the second terminal of the pixel selection switch T2, the second terminal of the auxiliary switch B21 is coupled to the anode terminal of the light-emitting element D23 of the sub-pixel SP23, and the auxiliary switch B21 is controlled by the laser Control signal EM3.

It should be noted that the embodiment of the present invention is not limited to the number and coupling method of the auxiliary switches shown in FIG.

In addition, in this embodiment, the transistors M1-M6, the driving transistor MP, the pixel selection switches T1-T5, the control switches A11-A13, A21-A23, A31-A33, A41-A42, A51 and the auxiliary switch B11 , B12 and B21 can all be implemented by P-type transistors, but the present invention is not limited thereto.

For details of the operation of the display panel 100, please refer to FIG. 1 and FIG. 2 at the same time. FIG. 2 is a timing diagram of the display panel according to an embodiment of FIG. 1 of the present invention. The upper part of FIG. 2 is a timing diagram when the display panel 100 operates in a normal display mode, and the lower part of FIG. 2 is a timing diagram when the display panel 100 operates in a power-saving display mode.

In this embodiment, a laser time interval TEM1 of the display panel 100 can be divided into a plurality of sub-laser time intervals, a plurality of initialization time intervals, and a vertical blank interval (Vertical Blank Interval). For the clarity of the diagram, FIG. 2 only uses the initialization time intervals TRW11 - TRW13 , the sub-laser time intervals T11 - T13 and the vertical blanking period BK1 as examples for illustration. For the initialization time periods, sub-laser time periods and vertical blanking periods in the laser time period TEM2 following the laser time period TEM1, reference may be made to the initialization time periods TRW11-TRW13, the sub-laser time periods T11-T13 and the vertical blanking period The relevant descriptions of the period BK1 are analogous.

Here, please refer to the timing diagrams of FIG. 1 and the upper half of FIG. 2 at the same time (ie, the normal display mode), in this embodiment, the voltage holding circuit 114 of the driving circuit 110 may be disabled (eg, high voltage level) mode selection signal AOD is turned off. Then, when the display panel 100 operates in the initialization time interval TRW11, the transistors M4 and M3 of the initialization circuit 113 can be sequentially enabled (eg, low voltage level) according to the read control signal RD and the write control signal WR is turned on to supply the reference voltage VREF to the driving terminal PD of the driving transistor MP (or the second terminal of the capacitor CD). At this time, the transistor M1 of the data writing circuit 111 can be turned on according to the enabled (eg, low voltage level) writing control signal WR to provide the data voltage VDATA to the first end of the capacitor CD.

In this regard, the driving circuit 110 may complete the initialization of the driving terminal PD during the initialization time interval TRW11. It is worth mentioning that, in this embodiment, before the display panel 100 performs an operation in each sub-laser time interval, the driving circuit 110 will perform an initialization operation once to reset the LED on the driving terminal PD again. voltage and provide the corresponding data voltage VDATA. The implementation details of the driving circuit 110 in the initialization time interval TRW12 and TRW13 can be deduced by referring to the related description of the driving circuit 110 in the initial time interval TRW11 , and thus will not be repeated.

Then, when the display panel 100 operates in the sub-laser time interval T11 after the initialization time interval TRW11 , the transistor M2 of the laser circuit 112 can be turned on according to the control signal EMG that is enabled (eg, at a low voltage level), so as to The operating voltage VBP is supplied to the first terminal of the capacitor CD. At this time, through the coupling effect of the capacitor CD, the driving circuit 110 can pull up the voltage level of the driving terminal PD to ELVDD-VTH+VBP-VDATA, where VTH is the threshold voltage of the driving transistor MP.

Further, in the sub-laser time interval T11 , the laser control signals EM1 and EM4 can be set to an enabled state (eg, a low voltage level). In this case, the pixel selection switch T1 and the control switch A11 of the sub-pixel SP11 can be turned on according to the laser control signals EM1 and EM4, respectively, and the driving circuit 110 can be based on the power supply voltage ELVDD and the voltage on the driving terminal PD. Through the conduction path of the pixel selection switch T1 and the control switch A11 , the driving current ID is selectively supplied to the sub-pixel SP11 to light the light-emitting element D11 . The gray-scale brightness of the lighted light-emitting element can be adjusted by the voltage of the data voltage VDATA.

Next, the display panel 100 will continue to perform an initialization operation in the initialization time interval TRW12 through the driving circuit 110 . Also, in the sub-laser time interval T12 after the initialization time interval TRW12 , the laser control signals EM1 and EM5 may be set to an enabled state (eg, a low voltage level). In this case, the pixel selection switch T1 and the control switch A12 of the sub-pixel SP12 can be turned on according to the laser control signals EM1 and EM5 respectively, and the driving circuit 110 can pass the conduction path of the pixel selection switch T1 and the control switch A12 , the driving current ID is selected to be supplied to the sub-pixel SP12 to light the light-emitting element D12.

Similarly, after the driving circuit 110 completes the initialization operation in the initialization time interval TRW13, the pixel selection switch T1 and the control switch A13 of the sub-pixel SP13 can be respectively enabled (eg, low) during the sub-laser time interval T13. The laser control signals EM1 and EM6 of the voltage level) are turned on. In addition, the driving circuit 110 can selectively supply the driving current ID to the sub-pixel SP13 through the conduction path of the pixel selection switch T1 and the control switch A13 to light the light-emitting element D13 .

It should be noted that, in the normal display mode of this embodiment, the operation modes of the pixel selection switches T2 to T5 and the corresponding pixels PX2 to PX5 in the remaining sub-laser time intervals in the laser time interval TEM1 can be referred to. The pixel selection switch T1 and the corresponding pixel PX1 in the sub-laser time interval T11-T13 are analogous to the related descriptions, and thus will not be repeated here.

Next, when the display panel 100 operates in the vertical blanking period BK1, the read control signal RD, the write control signal WR, the control signal EMG, and the laser control signals EM1-EM6 can all be set to a disabled state (for example, a high voltage level). In this case, the display panel 100 does not light up any sub-pixel during the vertical blanking period BK1. In addition, after the display panel 100 completes the vertical blanking period BK1, the display panel 100 will continue to perform operations in the laser time period TEM2 according to the display mode in the laser time period TEM1.

In other words, in the normal display mode of the present embodiment, the display panel 100 can light up the sub-pixels SP11-SP13, SP21-SP23, SP31-SP33, SP41-SP42 and SP51 one by one in the laser time interval TEM1. , and in a sub-laser time interval, only one sub-pixel will be lit.

On the other hand, please refer to the timing diagrams in the lower half of FIG. 1 and FIG. 2 at the same time (ie, the power-saving display mode), in this embodiment, the transistors M5 and M6 of the voltage holding circuit 114 can be activated according to It is turned on by the mode selection signal AOD that is enabled (eg, a low voltage level).

It should be noted here that, according to the characteristics between the capacitor CD1 and the driving terminal PD of the driving transistor MP, when the display panel 100 operates at a low frequency (ie, the power saving display mode) and the capacitance value of the capacitor CD1 is too small , the voltage change rate on the driving terminal PD of the driving transistor MP will be increased. In this case, the on state of the driving transistor MP is unstable due to the voltage fluctuation of the driving terminal PD.

Therefore, through the design of the voltage holding circuit 114, when the mode selection signal AOD indicates the power saving display mode, the driving circuit 110 can connect the capacitor CD2 and the capacitor C1 in the voltage holding circuit 114 in parallel according to the mode selection signal AOD, so as to Increase the overall capacitance value. Under this design, the driving circuit 110 can maintain the voltage level on the driving terminal PD of the driving transistor MP in the power-saving display mode, so as to reduce the voltage change rate, so as to prevent the driving transistor MP from being semi-conductive or A chance for a half-break.

In addition, when the transistor operates in the linear region, the on-resistance of the transistor is relatively small. Therefore, the driving transistor MP of this embodiment can operate in the linear region in the power-saving display mode, so as to effectively reduce the driving transistor MP. power consumption.

Please refer again to the timing diagrams of FIG. 1 and the lower half of FIG. 2 (ie, the power-saving display mode), in the embodiment, when the display panel 100 operates in the initialization time interval TRW11 ′, the driving circuit 110 may The drive terminal PD performs an initialization action. Wherein, the operation details of the driving circuit 110 in the initialization time interval TRW11' can be deduced with reference to the relevant description of the driving circuit 110 in the initial time interval TRW11, and thus will not be repeated.

In the sub-laser time interval T11' after the initialization time interval TRW11', the laser control signals EM1 and EM2 may be set to an enabled state (eg, a low voltage level). In this case, the pixel selection switch T1 and the auxiliary switch B11 can be turned on according to the laser control signals EM1 and EM2, respectively, and the driving circuit 110 can select through the pixels based on the power supply voltage ELVDD and the voltage on the driving terminal PD. The conduction paths of the switch T1 and the auxiliary switch B11 are selected to supply the driving current ID to the sub-pixel SP11 to light the light-emitting element D11.

Next, in the sub-laser time interval T12' following the sub-laser time interval T11', the laser control signals EM1 and EM3 may be set to an enabled state (eg, a low voltage level). In this case, the pixel selection switch T1 and the auxiliary switch B12 can be turned on according to the laser control signals EM1 and EM3 respectively, and the driving circuit 110 can select the driving current through the conduction paths of the pixel selection switch T1 and the auxiliary switch B12 The ID is supplied to the sub-pixel SP12 to light up the light-emitting element D12.

On the other hand, in the sub-laser time interval T13' following the sub-laser time interval T12', the laser control signals EM2 and EM3 may be set to an enabled state (eg, a low voltage level). In this case, the pixel selection switch T2 and the auxiliary switch B21 can be turned on according to the laser control signals EM2 and EM3 respectively, and the driving circuit 110 can select the driving current through the conduction paths of the pixel selection switch T2 and the auxiliary switch B21 The ID is supplied to the sub-pixel SP23 to light up the light-emitting element D23.

It is worth mentioning that in the power-saving display mode, since the driving circuit 110 only performs an initialization operation on the driving terminal PD of the driving transistor MP once in the laser time interval TEM1, the above-mentioned sub-pixels SP11, SP12 and SP23 all receive the same data voltage VDATA, so that the light-emitting elements D11, D12 and D23 will only display black or white light in the power-saving display mode, instead of red, green or blue light, so as to reduce the Power consumption of the display panel 100 .

Besides, a clock control signal generator (not shown) disposed outside the display panel 100 can generate the laser control signals EM1 - EM6 to the display panel 100 . In the power-saving display mode, the clock control signal generator (not shown) can set the laser control signals EM4 to EM6 to maintain a disabled state (eg, a high voltage level). In other words, in the power saving display mode, the display panel 100 only controls the switches T1, T2 and the auxiliary switches B11, B12, B21, and selects the sub-pixels SP11, SP12 and SP23 as the selected sub-pixels according to the laser control signals EM1-EM3 The sub-pixels light up the corresponding light-emitting elements D11, D12 and D23 in sequence.

In particular, in the embodiment shown in FIG. 2 , the clock control signal generator (not shown) can set the operating frequency of the laser control signals EM1 to EM3 to a first frequency (for example, 45 Hz) (Hz), but the present invention is not limited to this).

FIG. 3 is a timing diagram of a display panel according to another embodiment of FIG. 1 of the present invention. Please refer to FIG. 1 and FIG. 3 at the same time. For details of the operation of the display panel 100 when the display panel 100 operates in the timing diagram in the upper half of FIG. 3 (ie, the normal display mode), please refer to the display panel 100 mentioned in FIGS. 1 and 2 The description of the operation in the normal display mode is analogous, so it is not repeated here.

It is worth mentioning that, unlike the embodiment shown in FIG. 2 , in the power-saving display mode shown in FIG. 3 , the clock control signal generator (not shown) can control the operation of the laser control signals EM1 to EM3 The frequency is adjusted from the first frequency (for example, 45Hz) to the second frequency (for example, 90Hz, but the present invention is not limited to this), so that the light-emitting elements D11, D12 and D23 corresponding to the sub-pixels SP11, SP12 and SP23 can Light emission is repeated in the laser time interval TEM1. In this way, the present embodiment can effectively reduce the chance of the display panel 100 flickering at a low operating frequency. Wherein, the above-mentioned second frequency may be greater than the first frequency.

Wherein, for the implementation details when the display panel 100 operates in the initialization time interval TRW11' and the sub-laser time intervals T11'-T13' and T21'-T23' shown in FIG. The display panel 100 operates in the initialization time interval TRW11 ′ and the sub-laser time interval T11 ′˜T13 ′ by analogy with the relevant descriptions, and thus will not be repeated.

FIG. 4 is a schematic diagram of a display panel according to a second embodiment of the present invention. Referring to FIG. 4, in this embodiment, the display panel 400 includes a driving circuit 410, pixel selection switches T1-T5, pixels PX1-PX5, and auxiliary switches B11, B12, and B21. The display panel 400 is substantially the same or similar to the display panel 100, wherein the same or similar elements are given the same or similar reference numerals. Different from the embodiment of FIG. 1 , the driving circuit 410 includes a driving transistor MP, a capacitor CD1 , a data writing circuit 411 , a laser circuit 412 , an initialization circuit 413 , a voltage holding circuit 414 and an impedance adjusting circuit 415 .

Specifically, in this embodiment, the impedance adjustment circuit 415 includes transistors M7-M9. The first terminal of the transistor M7 is coupled to the power supply voltage ELVDD, and the control terminal of the transistor M7 receives the mode selection signal AOD. The first terminal of the transistor M8 is coupled to the driving terminal PD of the driving transistor MP, and the control terminal of the transistor M8 receives the mode selection signal AOD. The first end of the transistor M9 is coupled to the second end of the transistor M7, the second end of the transistor M9 is coupled to the initialization circuit 413, and the control end of the transistor M9 is coupled to the second end of the transistor M8.

Further, when the mode selection signal AOD is set to a disabled state (eg, a high voltage level) (ie, the display panel 400 operates in a normal display mode), the impedance adjustment circuit 415 can be adjusted according to the mode selection signal AOD disconnect. Conversely, when the mode selection signal AOD is set to an enabled state (eg, a low voltage level) (ie, the display panel 400 operates in a power saving display mode), the impedance adjustment circuit 415 can be adjusted according to the mode selection signal AOD on.

For example, when the mode selection signal AOD indicates the power-saving display mode, the transistors M7 and M8 of the impedance adjustment circuit 415 can be turned on according to the mode selection signal AOD, so that the driving transistor MP and the transistor M9 are connected in parallel with each other . In the state where the driving transistor MP and the transistor M9 are connected in parallel with each other, the width of the parallel connected transistor can be effectively increased. Therefore, when the width of the driving transistor MP is increased, the impedance adjustment circuit 415 can reduce the resistance value of the on-resistance of the driving transistor MP according to the mode selection signal AOD, thereby further reducing the power consumption of the display panel 400 .

It should be noted that, regarding the design of the impedance adjustment circuit 415, the width to length ratio of the transistor M9 may be greater than that of the transistor M7 and/or the transistor M8, but the invention is not limited thereto.

On the other hand, as shown in FIG. 4, the driving transistor MP, the capacitor CD1, the data writing circuit 411, the laser circuit 412, the initialization circuit 413, the voltage holding circuit 414, the pixel selection switches T1-T5, the pixels PX1-PX5 and Auxiliary switches B11, B12, B21 can refer to the driving transistor MP, capacitor CD1, data writing circuit 111, laser circuit 112, initialization circuit 113, voltage holding circuit 114, pixel selection switch T1 mentioned in FIG. 1 to FIG. 3 ~T5, pixels PX1~PX5, and auxiliary switches B11, B12, B21 in the normal display mode and the power-saving display mode are analogous to the related descriptions, so they will not be repeated.

FIG. 5 is a schematic diagram of a display panel according to a third embodiment of the present invention. Referring to FIG. 5 , the display panel 500 includes a driving circuit 510 and pixels PX1 - PX5 . In this embodiment, the driving circuit 510 includes a driving transistor MP, a capacitor CD1 , a data writing circuit 511 , a laser circuit 512 , an initialization circuit 513 , a voltage holding circuit 514 and an impedance adjusting circuit 515 .

Specifically, in this embodiment, the laser circuit 512 includes transistors M21 to M35. The transistors M21-M35 can be coupled in parallel between the operating voltage VBP and the first end of the capacitor CD1, and the transistors M21-M35 can be controlled by the laser control signals EM1-EM15, respectively. It should be noted that the driving circuit 510 shown in FIG. 5 can be analogized with reference to the related descriptions of the driving circuits 110 and 410 mentioned in FIG. 1 to FIG. 4 , and thus will not be repeated.

On the other hand, regarding the circuit configuration of the pixels PX1 to PX5, the pixels PX1 to PX5 include a plurality of sub-pixels. For example, in this embodiment, the pixel PX1 includes three groups of sub-pixels SP11-SP13; the pixel PX2 includes three groups of sub-pixels SP21-SP23; and the pixel PX5 includes three groups of sub-pixels SP51-SP53. It is particularly mentioned that, for the clarity of the drawing, the display panel 500 shown in FIG. 5 omits the two groups of pixels between the pixels PX2 and PX5, wherein, in the omitted two groups of pixels, adjacent The pixels in the pixel PX2 and the pixel adjacent to the pixel PX5 include 3 groups of sub-pixels, and the internal circuit configuration can be deduced by referring to the relevant descriptions of the pixels PX1, PX2 and PX5, so it is not repeated here. .

Further, in the embodiment of FIG. 5 , the sub-pixels SP11-SP13 include control switches A11-A13, light-emitting elements D11-D13, and capacitors C11-C13; the sub-pixels SP21-SP23 include control switches A21-A23, light-emitting elements Elements D21-D23 and capacitors C21-C23; sub-pixels SP51-SP53 include control switches A51-A53, light-emitting elements D51-D53 and capacitors C51-C53. Among them, the control switches A11-A13 can be controlled by the laser control signals EM1-EM3 respectively; the control switches A21-A23 can be controlled by the laser control signals EM4-EM6 respectively; the control switches A51-A53 can be controlled by the laser control signal EM13 respectively ~EM15.

It should be noted that the coupling manner of the internal elements of each sub-pixel can be analogized with reference to the related description of the sub-pixel SP11 shown in FIG.

Regarding the display mode of the display panel 500 , in this embodiment, when the mode selection signal AOD indicates the normal display mode, the laser control signals EM1 ˜ EM15 can be sequentially set to an enabled state (eg, a low voltage level) , so that the driving circuit 510 can sequentially light up the light-emitting elements corresponding to the sub-pixels SP11 to SP53 one by one. In this regard, the implementation details when the display panel 500 operates in the normal display mode can be deduced with reference to the related descriptions in FIGS. 1 to 5 , and thus will not be repeated.

FIG. 6 is a timing diagram of the display panel according to the embodiment of FIG. 5 of the present invention. Please refer to FIG. 5 and FIG. 6 at the same time, wherein FIG. 6 is a timing diagram when the display panel 500 operates in the power saving display mode. In the power-saving display mode, the clock control signal generator (not shown) can set the laser control signals EM4 to EM15 to maintain a disabled state (eg, a high voltage level), and the laser control signals EM4 to EM15 are maintained in a disabled state (eg, a high voltage level), and the sub-laser time interval T11 ′ In ~T13', the clock control signal generator (not shown) can sequentially enable (eg, low voltage level) the laser control signals EM1-EM3. In other words, in the power-saving display mode, the display panel 500 only controls the switches A11-A13 to select the sub-pixels SP11-SP13 as the selected sub-pixels according to the laser control signals EM1-EM3, so as to sequentially light up the corresponding sub-pixels Light-emitting elements D11, D12, and D13.

Similar to the embodiment of FIG. 1 , in the power-saving display mode, since the driving circuit 510 only performs an initialization operation on the driving terminal PD of the driving transistor MP once in the laser time interval TEM1, the above-mentioned sub-pixel SP11 ~ SP13 all receive the same data voltage VDATA, so that the light-emitting elements D11, D12 and D13 will only display black or white light in the power-saving display mode, instead of red, green or blue light. The power consumption of the display panel 500 is reduced.

In this regard, the implementation details when the display panel 500 operates in the power-saving display mode can be deduced with reference to the related descriptions of FIGS.

FIG. 7 is a schematic diagram of a display panel according to a fourth embodiment of the present invention. Referring to FIG. 7, the display panel 700 includes a driving circuit 710, pixel selection switches T1-T5, and pixels PX1-PX5. In this embodiment, the driving circuit 710 includes a driving transistor MP, a capacitor CD1 , a data writing circuit 711 , a laser circuit 712 , an initialization circuit 713 , a voltage holding circuit 714 and an impedance adjusting circuit 715 . It should be noted that the driving circuit 710 shown in FIG. 7 can be deduced by referring to the related descriptions of the driving circuits 110 and 410 mentioned in FIGS. 1 to 4 , and thus will not be repeated.

On the other hand, regarding the circuit configuration of the pixels PX1 to PX5, the pixels PX1 to PX5 include a plurality of sub-pixels. For example, in this embodiment, pixel PX1 includes 5 groups of sub-pixels SP11-SP15; pixel PX2 includes 4 groups of sub-pixels SP21-SP24; pixel PX4 includes 2 groups of sub-pixels SP41-SP42; The pixel PX5 includes a group of sub-pixels SP51.

It is particularly mentioned that, for the clarity of the drawing, the display panel 700 shown in FIG. 7 omits the pixels between the pixel PX2 and the pixel PX4, wherein the omitted pixel includes 3 groups of sub-pixels, and its The internal circuit configuration can be deduced by referring to the relevant descriptions of the pixels PX1, PX2, PX4 and PX5, so it is not repeated here.

In other words, the number of sub-pixels (or light-emitting elements) in the pixels PX1 to PX5 is 5, 4, 3, 2, and 1 in this order. That is, the number of sub-pixels (or light-emitting elements) in these pixels PX1 to PX5 forms an arithmetic progression.

Further, in the embodiment of FIG. 7 , the sub-pixels SP11-SP15 include control switches A11-A15, light-emitting elements D11-D15, and capacitors C11-C15; the sub-pixels SP21-SP24 include control switches A21-A24, light-emitting elements Elements D21-D24 and capacitors C21-C24; sub-pixels SP41-SP42 include control switches A41-A42, light-emitting elements D41-D42 and capacitors C41-C42; sub-pixel SP51 includes control switch A51, light-emitting element D51 and capacitor C51.

Among them, pixel selection switches T1-T5 can be controlled by laser control signals EM1-EM5 respectively; control switches A11-A15 can be controlled by laser control signals EM2-EM6 respectively; control switches A21-A24 can be controlled by laser control signals respectively Signals EM3-EM6; control switches A41-A42 can be controlled by laser control signals EM5-EM6 respectively; control switch A51 can be controlled by laser control signal EM6.

It should be noted that the coupling manner of the internal elements of each sub-pixel can be analogized with reference to the related description of the sub-pixel SP11 shown in FIG.

Regarding the display mode of the display panel 700, in this embodiment, when the mode selection signal AOD indicates the normal display mode, the pixel selection switches T1-T5 and the control switches A11-A51 of the display panel 700 can be based on the laser control signals EM1- EM5, so that the driving circuit 710 can sequentially light up the light-emitting elements corresponding to the sub-pixels SP11-SP51 one by one. In this regard, the implementation details when the display panel 700 operates in the normal display mode can be deduced with reference to the relevant descriptions of FIGS. 1 to 5 , and thus will not be repeated.

FIG. 8 is a timing diagram of the display panel according to the embodiment of FIG. 7 of the present invention. Please refer to FIG. 7 and FIG. 8 at the same time, wherein FIG. 8 is a timing diagram of the display panel 700 operating in the power-saving display mode. In the power-saving display mode, when the display panel 700 operates in the sub-laser time interval T11' after the initialization time interval TRW11', the laser control signals EM1 and EM2 can be set to an enabled state (eg, a low voltage level).

In this case, the pixel selection switch T1 and the control switch A11 can be turned on according to the laser control signals EM1 and EM2, respectively, and the driving circuit 110 can select the pixels through the pixel selection based on the power supply voltage ELVDD and the voltage on the driving terminal PD. The switch T1 and the conduction path of the control switch A11 are selected to supply the driving current ID to the sub-pixel SP11 to light the light-emitting element D11.

Next, in the sub-laser time interval T12' following the sub-laser time interval T11', the laser control signals EM1 and EM3 may be set to an enabled state (eg, a low voltage level). In this case, the pixel selection switch T1 and the control switch A12 can be turned on according to the laser control signals EM1 and EM3 respectively, and the driving circuit 110 can select the driving current through the conduction paths of the pixel selection switch T1 and the control switch A12 The ID is supplied to the sub-pixel SP12 to light up the light-emitting element D12.

On the other hand, in the sub-laser time interval T13' following the sub-laser time interval T12', the laser control signals EM2 and EM3 may be set to an enabled state (eg, a low voltage level). In this case, the pixel selection switch T2 and the control switch A21 can be turned on according to the laser control signals EM2 and EM3 respectively, and the driving circuit 110 can select the driving current through the conduction paths of the pixel selection switch T2 and the control switch A21 The ID is supplied to the sub-pixel SP21 to light up the light-emitting element D21.

In other words, in the power-saving display mode, the display panel 700 only selects the sub-pixels SP11, SP12, and SP21 according to the laser control signals EM1-EM3 through the pixel selection switches T1, T2 and the control switches A11, A12, A21 as the selections. The neutron pixels light up the corresponding light-emitting elements D11, D12 and D21 in sequence.

Similar to the embodiment in FIG. 1 , in the power-saving display mode, since the driving circuit 710 only performs an initialization operation on the driving terminal PD of the driving transistor MP once in the laser time interval TEM1, the above-mentioned sub-pixel SP11 , SP12 and SP21 all receive the same data voltage VDATA, so that the light-emitting elements D11, D12 and D21 will only display black or white light in the power-saving display mode, instead of red, green or blue light. , thereby reducing the power consumption of the display panel 700 .

It can be known from the descriptions of the above-mentioned embodiments in FIGS. 1 to 8 that when the display panel operates in the normal display mode, the display panel can select the desired sub-pixel or light-emitting element according to the timing state of the laser control signal, So that the driving circuit can sequentially light up the sub-pixels or light-emitting elements in each pixel one by one, so that the light-emitting time of the sub-pixels adjacent to each other may not completely overlap. Moreover, since the display panel does not need to perform circuit switching operations through additional multiplexers or excessive laser control lines, and each pixel can share the same driving circuit, the embodiments shown in FIGS. 1 to 8 can effectively The layout space of the display panel is greatly improved.

In addition, under the increased layout space of the display panel, the various embodiments of FIG. 1 to FIG. 8 can also increase the size of the driving transistor relatively, so that the driving transistor can generate a larger driving current to the meridian point. Bright sub-pixels or light-emitting elements. Thereby, the sub-pixels or light-emitting elements of the various embodiments of FIGS. 1 to 8 can operate at the optimum efficiency point, thereby improving the display quality.

On the other hand, when the display panel operates in the power-saving display mode, the driving circuit can maintain the voltage level on the driving terminal of the driving transistor through the voltage holding circuit, so as to reduce the voltage change rate on the driving terminal, so as to avoid driving Opportunity for a transistor to be half-on or half-off at low frequencies. In addition, the driving circuit can also reduce the resistance value of the on-resistance of the driving transistor through the impedance adjusting circuit. In addition, in the power-saving display mode, the display panel can partially light up some sub-pixels or light-emitting elements, and make these sub-pixels or light-emitting elements display only black or white light. In this way, the display panel of the present invention can effectively reduce the overall power consumption, so as to achieve the effect of power saving.

To sum up, the driving circuit of the display panel according to the embodiments of the present invention can maintain the voltage level on the driving terminal of the driving transistor through the voltage holding circuit in the power-saving display mode, so as to reduce the voltage variation on the driving terminal rate, thereby stabilizing the conduction state of the drive transistor when operating at low frequencies. In addition, the drive circuit can also reduce the resistance value of the on-resistance of the drive transistor through the impedance adjustment circuit. In addition, the display panel can partially light up some sub-pixels or light-emitting elements in the power-saving display mode, so that these sub-pixels or light-emitting elements only display black or white light. In this way, the display panel of the present invention can effectively reduce the overall power consumption, so as to achieve the effect of power saving.

100, 400, 500, 700: Display panel 110, 410, 510, 710: drive circuit 111, 411, 511, 711: Data writing circuit 112, 412, 512, 712: Laser circuits 113, 413, 513, 713: initialization circuit 114, 414, 514, 714: Voltage hold circuit 415, 515, 715: Impedance adjustment circuit AOD: mode selection signal A11～A13, A21～A23, A31～A33, A41～A42, A51～A53: Control switch B11, B12, B21: Auxiliary switch BK1: Vertical blanking period C11～C13, C21～C23, C31～C33, C41～C42, C51～C53, CD1, CD2: Capacitors D11～D13, D21～D23, D31～D33, D41～D42, D51～D53: Light-emitting element ELVSS: Reference Ground Voltage EMG: control signal ELVDD: Supply voltage EM1～EM15: Laser control signal ID: drive current M1～M9, M21～M35: Transistor MP: drive transistor PD: drive end PX1～PX5: pixel RD: read control signal SP11～SP13, SP21～SP23, SP31～SP33, SP41～SP42, SP51～SP53: Sub pixel T1～T5: pixel selection switch TEM1, TEM2: Laser time interval T11～T13, T11'～T13', T21'～T23': Sub-laser time interval TRW11～TRW13, TRW11': Initialization time interval VDATA: data voltage VBP: operating voltage VREF: reference voltage WR: write control signal

FIG. 1 is a schematic diagram of a display panel according to a first embodiment of the present invention. FIG. 2 is a timing diagram of the display panel according to an embodiment of FIG. 1 of the present invention. FIG. 3 is a timing diagram of a display panel according to another embodiment of FIG. 1 of the present invention. FIG. 4 is a schematic diagram of a display panel according to a second embodiment of the present invention. FIG. 5 is a schematic diagram of a display panel according to a third embodiment of the present invention. FIG. 6 is a timing diagram of the display panel according to the embodiment of FIG. 5 of the present invention. FIG. 7 is a schematic diagram of a display panel according to a fourth embodiment of the present invention. FIG. 8 is a timing diagram of the display panel according to the embodiment of FIG. 7 of the present invention.

100: Display panel

110: Drive circuit

111: Data writing circuit

112: Laser circuit

113: Initialization circuit

114: Voltage hold circuit

AOD: mode selection signal

A11~A13, A21~A23, A31~A33, A41~A42, A51: Control switch

B11, B12, B21: Auxiliary switch

C11~C13, C21~C23, C31~C33, C41~C42, C51, CD1, CD2: Capacitors

D11~D13, D21~D23, D31~D33, D41~D42, D51: Light-emitting element

ELVSS: Reference Ground Voltage

EMG: control signal

ELVDD: Supply voltage

EM1~EM6: Laser control signal

ID: drive current

M1~M6: Transistor

MP: drive transistor

PD: drive end

PX1~PX5: pixel

RD: read control signal

SP11~SP13, SP21~SP23, SP31~SP33, SP41~SP42, SP51: Sub pixel

T1~T5: pixel selection switch

VDATA: data voltage

VBP: operating voltage

VREF: reference voltage

WR: write control signal

Claims (13)

A display panel, comprising: a driving circuit having a driving terminal for generating a driving current according to a mode selection signal and a voltage on the driving terminal; a first pixel including a plurality of first sub-pixels; A second pixel, adjacent to the first pixel, including a plurality of second sub-pixels; a plurality of first auxiliary switches, coupled to the driving circuit and the first pixel; and at least one second auxiliary switch a switch, coupled to the driving circuit and the second pixel, wherein when the mode selection signal indicates a power-saving display mode, at least a first selected sub-pixel in the first pixel is lit , at least one second selected sub-pixel in the second pixel is lit, and the display wavelength of the at least one first selected sub-pixel is different from the display wavelength of the at least one second selected sub-pixel , when the mode selection signal indicates the power-saving display mode, the first auxiliary switches and the at least one second auxiliary switch are turned on in sequence, so that the at least one first selected element in the first pixel is The pixel and the at least one second selected sub-pixel in the second pixel are sequentially lit. The display panel as set forth in claim 1, wherein the display panel further comprises a plurality of third pixels, the third pixels comprise a plurality of third sub-pixels, wherein When the mode selection signal indicates a normal display mode, the first sub-pixels, the second sub-pixels and the third sub-pixels are sequentially lit one by one in a laser time interval. The display panel as set forth in claim 2, wherein the first pixel, the second pixel or each of the third pixels comprises: N light-emitting elements; and N control switches, respectively coupled to the N light-emitting elements element, the N control switches are controlled by N laser control signals, where N is a positive integer. The display panel as set forth in claim 1, wherein the first auxiliary switches and the at least one second auxiliary switch are respectively controlled by a plurality of laser control signals, wherein when the mode selection signal indicates the power saving display mode, The operating frequencies of the laser control signals are adjusted from a first frequency to a second frequency, wherein the second frequency is greater than the first frequency. The display panel of claim 1, wherein the driving circuit comprises: a data writing circuit for providing a data voltage according to a writing control signal; a laser circuit, coupled to the data writing circuit, and providing an operating voltage according to a control signal; a first capacitor, the first end of which is coupled to the data writing circuit, and the second end of which is coupled to the drive end; a drive transistor, which has the drive end, and The first end of the driving transistor is coupled to a power supply voltage; an initialization circuit, coupled to the second terminal of the driving transistor, the driving terminal of the driving transistor, the first pixel and the second pixel, and according to the write control signal and a read control signal to provide a reference voltage; and a voltage holding circuit, coupled between the first terminal and the second terminal of the first capacitor, and used for maintaining the voltage on the driving terminal of the driving transistor according to the mode selection signal . The display panel of claim 5, wherein the driving circuit further comprises: an impedance adjustment circuit coupled to the driving transistor and the initialization circuit, wherein when the mode selection signal indicates the power saving display mode, the The impedance adjustment circuit adjusts the resistance value of the on-resistance of the driving transistor according to the mode selection signal. The display panel of claim 6, wherein the impedance adjustment circuit comprises: a first transistor, the first end of which is coupled to the first end of the driving transistor, and the control end of which receives the mode selection signal; a first transistor Two transistors, the first terminal of which is coupled to the driving terminal of the driving transistor, and the control terminal of which receives the mode selection signal; and a third transistor, the first terminal of which is coupled to the first terminal of the first transistor Two terminals, the second terminal of which is coupled to the initialization circuit, and the control terminal of which is coupled to the second terminal of the second transistor. The display panel of claim 7, wherein the width-to-length ratio of the third transistor is greater than the width-to-length ratio of the first transistor or the width-to-length ratio of the second transistor. The display panel of claim 5, wherein the voltage holding circuit comprises: a first transistor, the second terminal of which is coupled to the first terminal of the first capacitor, and the control terminal of which receives the mode selection signal; a first transistor Two transistors, the second terminal of which is coupled to the second terminal of the first capacitor, and the control terminal of which receives the mode selection signal; and a second capacitor, the first terminal of which is coupled to the first terminal of the first transistor terminal, the second terminal of which is coupled to the first terminal of the second transistor. The display panel of claim 5, wherein the data writing circuit includes a first transistor, wherein a first end of the first transistor is coupled to the data voltage, and a second end of the first transistor is coupled to the data voltage Connected to the first end of the first capacitor, the control end of the first transistor receives the write control signal. The display panel of claim 5, wherein the laser circuit includes a first transistor, wherein a first end of the first transistor is coupled to the operating voltage, and a second end of the first transistor is coupled to The first end of the first capacitor and the control end of the first transistor receive the control signal. The display panel of claim 5, wherein the initialization circuit includes a first transistor and a second transistor, wherein the first end of the first transistor is coupled to the drive end of the drive transistor, the The second end of the first transistor is coupled to the second end of the driving transistor, and the control end of the first transistor receives the write control control signal, and the first end of the second transistor is coupled to the reference voltage, the second end of the second transistor is coupled to the second end of the driving transistor, and the control end of the second transistor receives the read control signal. The display panel of claim 5, wherein when the mode selection signal indicates the power saving display mode, the driving transistor operates in a linear region.

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