TWI753644B - Memory device and method of fabricating the same - Google Patents

Abstract

A memory device is provided. The memory device includes a substrate, a stacked structure, and a contact. The substrate includes a memory array region and a staircase region. The stacked structure is located on the substrate in the memory array region and the staircase region. The stacked structure includes a plurality of conductive layers and a plurality of insulating layers alternately stacked on each other. Each of the plurality of conductive layers includes a main body and an end part. The main body is located in the memory array region and extends to the staircase region. The end part is connected to the main body and is located in the staircase region. A thickness of the end part is greater than a thickness of the main body. The contact lands on and is connected to the end part.

Description

Memory device and method of manufacturing the same

Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same, and more particularly, to a memory device and a method for fabricating the same.

Non-volatile memory devices (eg, flash memory) are widely used as memory devices in personal computers and other electronic devices because of the advantage that the stored data does not disappear after a power failure.

Currently, the flash memory arrays commonly used in the industry include NOR flash memory and NAND flash memory. Since the structure of the NAND flash memory is to connect the memory cells in series, its accumulation and area utilization are better than those of the NOR flash memory, and it has been widely used in a variety of electronic products. In addition, in order to further improve the integration of memory elements, a three-dimensional NAND flash memory has been developed. However, there are still many challenges associated with 3D NAND flash memory.

The present invention provides a memory device, comprising: a substrate, a stack structure, a dielectric layer and a first contact window. The substrate includes a memory array area and a stepped area. The stacked structure is located on the substrate of the memory array region and the stepped region, wherein the stacked structure includes a plurality of conductor layers and a plurality of insulating layers stacked alternately with each other. Each of the plurality of conductor layers includes: a main body portion located in the memory array region and extending to the stepped region; and an end portion connected to the main body portion and located in the stepped region, wherein the end portion The thickness of the portion is greater than the thickness of the main body portion. A dielectric layer is located on the stacked structure of the memory array region and the stepped region. The first contact window penetrates through the dielectric layer of the stepped region and the corresponding insulating layer above the end portion, and is landed on and connected to the end portion.

In one embodiment of the present invention, a method for manufacturing a memory device includes: providing a substrate, the substrate comprising a memory array region and a stepped region; on the substrate of the memory array region and the stepped region forming a stacked structure, wherein the stacked structure includes a plurality of first material layers and a plurality of second material layers stacked alternately with each other; patterning the stacked structure to form a stepped structure in the stacked structure in the stepped region; removing portions of the plurality of second material layers at the ends of the stepped structure to form a plurality of first horizontal openings; removing portions of the plurality of first material layers surrounding the plurality of first horizontal openings , to increase the height of the plurality of first horizontal openings; forming an end portion in each of the plurality of first horizontal openings, the material of the end portion is the same as the material of the plurality of second material layers, and the thickness of the end portion is greater than the thickness of the adjacent second material layer; a dielectric layer is formed on the stacked structure of the memory array region and the stepped region; and a first layer is formed on the stepped region a contact window, wherein the first contact window penetrates through the dielectric layer in the stepped region and the corresponding first material layer above the end portion, and is landed on the end portion and is connected with the end portion connect.

Based on the above, in various embodiments of the present invention, by locally increasing the thickness of the end portion of the gate electrode, in the process of forming the contact window opening with a deeper depth, the gate electrode layer below the contact window opening with a shallow depth can be avoided. etched through. The formation process of the end portion can be integrated with the existing process. In addition, the support column structure may be formed in the stacked structure in the stepped region before forming the end portion, so as to avoid the collapse of the stacked structure during the etching process for forming the end portion.

1A to FIG. 1I are schematic cross-sectional views of a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention. 2A to 2I are schematic diagrams of another cross-section of a manufacturing method of a three-dimensional memory device according to an embodiment of the present invention. Cross-sectional views of a part of the process along the line I-I' of FIG. 5A are shown in FIGS. 1A to 1I. Cross-sectional views of a part of the process along the line II-II' of Fig. 5A are shown in Figs. 2A to 2I. Sectional views of a part of the process along the line III-III' of FIG. 5B are shown in FIGS. 1A to 1I . Sectional views of a portion of the process along the line IV-IV' of FIG. 5B are shown in FIGS. 2A to 2I.

1A and 2A, a substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon-containing substrate. In one embodiment, doped regions may be formed in the substrate 100 according to design requirements. The substrate 100 has a memory array region R1 and a stepped region R2. The stepped area R2 includes an area A1 , an area A2 and an area A3 (as shown in FIG. 5A ). An element layer (not shown) and a metal interconnect structure (not shown) may be formed on the substrate 100 . The element layer may include active elements or passive elements. The active elements are, for example, transistors, diodes, and the like. Passive elements are, for example, capacitors, inductors, and the like. The metal interconnect structure may include dielectric layers, plugs and wires, and the like.

Referring to FIGS. 1A and 2A , a stacked structure 101 is formed on the substrate 100 . The substrate 100 may be a semiconductor substrate, such as a silicon substrate. The stacked structure 101 is located on the memory array region R1 and the stepped region R2. The stacked structure 101 includes a plurality of first material layers 102 and a plurality of second material layers 104 stacked alternately. The first material layer 102 may be an insulating layer, such as silicon oxide. The second material layer 104 may be an insulating layer (eg, silicon nitride) or a conductor layer (eg, doped polysilicon). In one embodiment, the material of the first material layer 102 includes silicon oxide, and the material of the second material layer 104 includes silicon nitride. In another embodiment, the material of the first material layer 102 includes silicon oxide, and the material of the second material layer 104 includes doped polysilicon. In this embodiment, the bottommost layer of the stacked structure 101 is the first material layer 102 , and the topmost layer is the second material layer 104 , but the invention is not limited thereto. In addition, in this embodiment, four layers of the second material layer 104 and four layers of the first material layer 102 are used for description, however, the present invention is not limited thereto.

Next, referring to FIG. 2A , a support structure 98 is formed in the stacked structure 101 in the stepped region R2 . The support structure 98 may also be referred to as a dummy structure. In some embodiments, support structures 98 are formed as described below. Openings 96 are formed in the stacked structure 101 . In one embodiment, the openings 96 may have substantially vertical sidewalls, as shown in FIG. 2A . In another embodiment, opening 96 may have slightly sloped sidewalls. After that, an insulating layer (not shown) is formed on the stacked structure 101 and in the opening 96 . The material of the insulating layer is different from that of the second material layer 104, such as silicon oxide. Afterwards, a planarization process, such as a chemical mechanical polishing process or an etch-back process, is performed to remove the insulating layer outside the opening 96 to form the support structure 98 in the opening 96 . The support structure 98 can prevent the stack structure 101 from collapsing in the subsequent process. The support structure 98 may have various shapes, such as pillar, fence, or wall. The support structure 98 may be formed only in the stepped region R2, or may be formed in the stepped region R2 and the memory array region R1 simultaneously. The shape and position of the support structure 98 will be described in detail below with reference to FIGS. 5A to 5D .

Referring to FIGS. 5A and 5B , the opening 96 may be a hole in the stacked structure 101 in the stepped region R2 . The support structures 98 formed in the openings may be support posts. A support structure (support column) 98 is located next to the contact window formed later. In some embodiments, please refer to FIG. 5A , the supporting structures (supporting columns) 98 may be multiple and may be arranged in a row, disposed in the area A2 between the areas A1 and A3, and located in the contact window C1 of the areas A1 and A3 between C3. In other embodiments, please refer to FIG. 5B , the supporting structures (supporting columns) 98 may be multiple and may be arranged in an array, which are respectively disposed in the regions A1 and A3, and the contact windows C1 and C3 are respectively located in the supporting structures (supporting columns). column) between 98.

Referring to FIG. 5C , in other embodiments, the opening 96 may be a trench extending from the region A2 of the step region R2 to the memory array region R1 . The support structure 98 formed in the trench may be a support wall (slit) extending continuously from the memory array region R1 to the step region R2. A single support structure (support wall) 98 is shown in FIGS. 5C and 5D, but not limited thereto. A support structure (support wall) 98 is provided in the area A2 between the contact windows C1 and C3.

Next, referring to FIGS. 1B and 2B , an insulating layer 102T is formed on the stacked structure 101 and the support structure 98 of the memory array region R1 and the stepped region R2 . The material of the insulating layer 102T is different from that of the second material layer 104 , and the material of the insulating layer 102T is the same as that of the first material layer 104 , such as silicon oxide. The insulating layer 102T and the stacked structure 101 may be collectively referred to as the stacked structure 101'.

1C and 2C, the insulating layer 102T, the second material layer 104, the first material layer 102 and the supporting structure 98 of the stacked structure 101' are patterned, so that the insulating layer 102T, the second material layer 104 and the first material layer 102 are patterned. The end of a material layer 102 forms a stepped structure 105 in the stepped region R2. In some embodiments, the support structure 98 is patterned into support structures (support columns) 98A, 98B, 98C, and 98D having different heights, as shown in FIG. 2C . In other embodiments, the support structures 98 are patterned to have different heights of support structures (support walls) 98E, as shown in Figure 5D.

Referring to FIG. 2C , in the stepped region R2 , the supporting structures 98A, 98B, 98C and 98D penetrate through the first material layer 102 and the second material layer 104 of the stepped structure 105 to reach the bottommost first material layer 102 . The top surfaces of the remaining support structures 98A, 98B and 98C are exposed except that the top surfaces of the support pillars 98D closest to the memory array region R1 are covered by the insulating layer 102T. In the stepped region R2, where the supporting structures 98A, 98B, 98C and 98D are not formed, the second material layer 104 of the stepped structure 105 is covered by the first material layer 102 and the insulating layer 102T, as shown in FIGS. 1C and 2C . That is, the topmost layer of the stepped structure 105 exposes the insulating layer 102T, but does not expose the support structure 98D. The remaining layers of the stepped structure 105 expose the top surface of the first material layer 102 and the top surfaces of the supporting structures 98A, 98B, and 98C. The top surfaces of the first material layers 102 are, for example, coplanar with the support structures 98A, 98B, and 98C. In addition, the sidewalls of the stepped structure 105 expose the insulating layer 102T, the first material layer 102 and the second material layer 104 .

5D, the support structure 98 is patterned into a support structure (support wall) 98E. The support structure (support wall) 98E extends continuously from the memory array region R1 to the step region R2. The support structures (support walls) 98E in the memory array region R1 have the same height and are covered by the insulating layer 102T. The support structures (support walls) 98E in the stepped region R2 have different heights. The topmost step of the stepped structure 105 exposes the insulating layer 102T without exposing the support structure 98E. The remaining steps of the stepped structure 105 expose the top surface of the first material layer 102 and the top surface of the support structure 98E, and the top surfaces of the first material layers 102 are, for example, coplanar with the support structure 98E. In addition, the sidewalls of the stepped structure 105 expose the insulating layer 102T, the first material layer 102 , the second material layer 104 and the support structure 98E. For the convenience of description, the following process will still be described with the support structure 98. The support structure 98 may be the support structures 98A, 98B, 98C and 98D or the support structure 98E.

Referring to FIGS. 1D and 2D , a pullback process, such as a selective etching process, is performed to remove the end portion of the second material layer 104 of the stepped structure 105 to form a plurality of horizontal openings 107 . In some embodiments, the pull-back process may be performed on all end portions of the second material layer 104, as shown in FIGS. 1D and 2D. The pull-back process can also be performed for a single layer or several layers of the end portion of the second material layer 104 (not shown). For example, the second material layer 104 of the lower layer 1 to 2 of the stack structure 101 ′ can be covered by a mask layer, so that the pullback process is only performed on the second layer 1 to 2 of the upper layer of the stacked structure 101 ′. The material layer 104 is performed so that the horizontal opening 107 is formed at the end of the second material layer 104 of 1 to 2 layers above the stacked structure 101 ′.

The pullback process is, for example, a selective etching process. The selective etching process can be a dry or wet etching process. In some embodiments, the second material layer 104 is silicon nitride, and the wet etching process uses hot phosphoric acid as an etchant. In some embodiments, the second material layer 104 is doped polysilicon, and the wet etching process uses ammonia water as an etchant. The support structure 98 can support the insulating layer 102T and the first material layer 102 to prevent the stepped structure 105 from collapsing during the selective etching process. The thickness of the first material layer 102 between two adjacent horizontal openings 107 is, for example, 20 nm or more.

1E and 2E, a flaring process, such as a selective etching process, is performed to remove the first material layer 102 and the insulating layer 102T exposed by the plurality of horizontal openings 107, so that the height of the plurality of horizontal openings 107 is increased, Thus, a plurality of horizontal openings 107' are formed. The selective etching process is, for example, a dry or wet etching process. In the selective etching process, for example, hydrofluoric acid can be used as an etchant. The first material layer 102 between the two adjacent horizontal openings 107' has a sufficient thickness to avoid collapse due to being too thin. In order to prevent the collapse of the first material layer 102 and the insulating layer 102T, the ratio of the thickness T4 of the first material layer 102 to the pullback amount (ie the width D) of the second material layer 104 after the horizontal opening 107 flaring process has been performed is less than or Equal to 1:10. For example, if the thickness of the remaining first material layer 104 is 10 nm, the pullback amount of the second material layer 102 should be less than or equal to 100 nm. If the support structure 98 is formed, the ratio of the thickness T4 of the first material layer 102 to the pullback amount (ie the width D) of the second material layer 104 after the flaring process of the horizontal opening 107 has been performed may be greater than or equal to 1:40 .

Referring to FIGS. 1F and 2F, a filling layer 104E is formed on the insulating layer 102T and in the plurality of horizontal openings 107'. The filling layer 104E can be made of the same material as the second material layer 104 . The filling layer 104E is, for example, a conformal layer, which can conformally cover the insulating layer 102T and fill in the plurality of horizontal openings 107'. The filling layer 104E has good trench filling properties and can be filled into the plurality of horizontal openings 107'. In some embodiments, the filling layer 104E may have seams, and these seams may form multiple voids due to the aggregation of the filling layer 104E in the subsequent thermal process.

Referring to FIGS. 1F and 2F, the filling layer 104E is, for example, silicon nitride, doped polysilicon, or doped amorphous silicon. Amorphous silicon will be crystallized in a subsequent thermal process to form doped polysilicon. In the embodiment in which the filling layer 104E and the second material layer 104 are doped polysilicon or doped amorphous silicon, the dopant in the doped polysilicon of the filling layer 104E and the doped polysilicon in the second material layer 104 The dopants in them are of the same type, or even the same dopants. For example, the filling layer 104E and the second material layer 104 are both polysilicon doped with phosphorus.

1G and 2G, the filling layers 104E other than the plurality of horizontal openings 107' are removed, so that the top surfaces of the first material layer 102 and the insulating layer 102T are exposed, and the remaining filling layers 104E are separated from each other. In some embodiments, a filling layer 104E is formed at the end of each second material layer 104 . In other embodiments, the filling layer 104E forms the end of the upper second material layer 104 .

The sidewalls of the plurality of filling layers 104E are connected to the sidewalls of the second material layer 104 to form a continuous material layer 104'. The filling layer 104E is the end portion EP of the material layer 104'; the second material layer 104 is the main body portion MP of the material layer 104'. The thickness T2 of the tip end portion EP is larger than the thickness T1 of the main body portion MP. Conversely, the thickness T4 of the first material layer 102 covering the end portion EP is smaller than the thickness T3 of the first material layer 102 covering the main body portion MP. In addition, in some embodiments, in the longitudinal direction (eg, the Z direction), the end portion EP and the other end portion EP adjacent thereto may be staggered (as shown in FIG. 1G ). In other embodiments, the end portion EP and the other end portion EP adjacent thereto in the longitudinal direction (eg, the Z direction) may overlap slightly (not shown).

Referring to FIGS. 1H and 2H, next, a dielectric layer 103 is formed on the substrate 100 to cover the stacked structure 101'. Thereafter, as shown in FIG. 1H , a patterning process is performed to remove part of the stacked structure 101' of the memory array region R1 to form one or more openings 106 passing through the stacked structure 101'. In one embodiment, the opening 106 may have slightly sloped sidewalls, as shown in FIG. 1H . In another embodiment, the opening 106 may have substantially vertical sidewalls (not shown). In one embodiment, the openings 106 are also referred to as vertical channel (VC) holes. Then vertical channel pillars CP are formed in the openings 106 . The vertical channel column CP may be formed by the following methods, but not limited thereto.

Referring to FIG. 1H , a charge storage structure 108 is formed on the sidewall of the opening 106 . The charge storage structure 108 is in contact with the first material layer 102 and the second material layer 104 . The material of the charge storage structure 108 is, for example, an oxide/nitride/oxide (ONO) composite layer. In one embodiment, the charge storage structure 108 is formed on the sidewall of the opening 106 in the form of a spacer, and the bottom surface of the opening 106 is exposed.

Then, referring to FIG. 1H , a channel layer 110 is formed on the charge storage structure 108 . The material of the channel layer 110 includes, for example, polysilicon. In one embodiment, the channel layer 110 covers the charge storage structures 108 on the sidewalls of the opening 106 and covers the bottom surface of the opening 106 . Next, insulating pillars 112 are formed at the lower portion of the opening 106 . In one embodiment, the material of the insulating pillar 112 includes, for example, silicon oxide. After that, a conductor plug 114 is formed on the upper portion of the opening 106 , and the conductor plug 114 is in contact with the channel layer 110 . In one embodiment, the material of the conductor plug 114 includes, for example, doped polysilicon. The channel layer 110 and the conductor plugs 114 may be collectively referred to as vertical channel pillars CP. The charge storage structure 108 surrounds the vertical outer surface of the vertical channel pillar CP. Next, an insulating cap layer 115 is formed over the stacked structure 101'. The material of the insulating cap layer 115 includes, for example, silicon oxide.

Referring to FIGS. 1I and 2I, in the embodiment in which the second material layer 104 and the filling layer 104E are doped polysilicon, the material layer 104' jointly formed by the second material layer 104 and the filling layer 104E can be used as a gate layer. A layer of material 104' (gate layer) surrounds the sidewalls of the charge storage structure 108. In the embodiment in which the second material layer 104 and the filling layer 104E are made of silicon nitride, a gate replacement process must be further performed to form the gate layer 126 , which will be referred to later with reference to FIGS. 3A to 3C and FIGS. 4A to 4A . 4C will explain it in detail.

Afterwards, please refer to FIG. 1I and FIG. 5A , in the embodiment in which the second material layer 104 and the filling layer 104E are doped polysilicon, or the second material layer 104 and the filling layer 104E are respectively doped polysilicon and doped polysilicon. In the amorphous silicon embodiment, after the insulating cap layer 115 is formed, a plurality of contact windows C1 and C3 are respectively formed in the region A1 and the region A3 of the step region R2 (as shown in FIGS. 1I and 5A ), and the memory A plurality of contact windows C2 are formed in the body array region R1 (as shown in FIG. 1I ). The contact windows C1 and C3 penetrate through the insulating cap layer 115 , the dielectric layer 103 , the insulating layer 102T and the first material layer 102 , and land on the end portion EP of the material layer 104 ′ (gate layer) and are electrically connected thereto, such as shown in Figures 1I and 5A. The contact window C2 passes through the insulating cap layer 115 and the stacked structure 101', and is electrically connected to the conductor plug 114, as shown in FIG. 1I.

1I, in one embodiment, each of the contacts C1 includes a barrier layer 128 and a conductor layer 131; each of the contacts C2 includes a barrier layer 129 and a conductor layer 132; and the contacts C3 Each of these includes a barrier layer and a conductor layer (not shown). In one embodiment, the material of the barrier layers 128 and 129 includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof, and the material of the conductor layers 131 and 132 includes Tungsten (W).

Referring to FIG. 1I and FIG. 5A, 5B or 5C, the contact windows C1, C2 and C3 may be formed simultaneously or separately. The contact windows C1, C2 and C3 can be formed using the method described below. For example, photolithography and etching processes are performed to form a plurality of contact openings OP1 and OP2. The contact opening OP1 passes through the insulating cap layer 115 , the dielectric layer 103 and the insulating layer 102T (or the first material layer 102 ) in the region A of the stepped region R2 . The contact opening OP2 passes through the insulating cap layer 115 in the memory array region R1. After that, a barrier layer and a conductor layer are formed in the plurality of contact openings OP1 and OP2. The contact window C3 in the region A3 of the stepped region R2 can also be formed simultaneously by the above-mentioned method.

Referring to FIG. 1I , the contact window openings OP1 in the stepped region R2 include contact window openings OP1A, OP1B, OP1C and OP1D. The contact window opening OP1A exposes the bottommost end portion EP; the contact window opening OP1D exposes the topmost end portion EP. The depth of the contact opening OP1A farthest from the memory array region R1 is the deepest, and the depth of the contact opening OP1D closest to the memory array region R1 is the shallowest. During the etching process, the contact opening OP1D is formed first, and the end portion EP of the topmost material layer 104' (gate layer) is exposed. Subsequently, etching is continued to form contact openings OP1C, OP1B and OP1A in sequence. In the process of continuing to etch to form the contact openings OP1C, OP1B and OP1A, since the end portion EP of the material layer 104 ′ (gate layer) has a sufficient thickness T2 , and there is a gap between the material layer 104 ′ and the dielectric layer 103 With sufficient etching selectivity, even if the end portion EP is exposed to the contact opening OP1D, it will not be etched through by continuous exposure to the etchant. Therefore, the process yield can be increased by forming the end portion EP.

In the embodiment in which the second material layer 104 and the filling layer 104E are made of silicon nitride, before the above-mentioned contact windows C1 , C2 and C3 are formed, a gate replacement process must be performed first, please refer to FIGS. 3A to 3C and FIG. 4A 4C, the detailed description is as follows.

3A to 3C are schematic cross-sectional views of a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention. 4A to 4C are another schematic cross-sectional view of a manufacturing method of a three-dimensional memory device according to another embodiment of the present invention. Sectional views of a part of the process along the line I-I' of FIG. 5A are shown in FIGS. 3A to 3C . Sectional views of a part of the process along the line II-II' of FIG. 5A are shown in FIGS. 4A to 4C . Cross-sectional views of part of the process along the line III-III' of FIG. 5B are shown in FIGS. 3A to 3C . Cross-sectional views of a portion of the process along the line IV-IV' of FIG. 5B are shown in FIGS. 4A to 4C .

1H, 2H, 3A and 4A, after the dielectric layer 103 and the insulating cap layer 115 are formed according to the method described above with reference to FIGS. 1H and 2H, a selective etching process is performed to remove the memory array region R1 and the stepped region R2 The second material layer 104 and the filling layer 104E are formed to form a plurality of horizontal openings 121 . The horizontal opening 121 exposes part of the charge storage structure 108 , the first material layer 102 and the insulating layer 102T in the memory array region R1 . During the etching process, the supporting structures 98A, 98B, 98C and 98D in the stepped region R2 can avoid the collapse of the stacked structure 101'. The selective etching process may be an isotropic etching process, such as a wet etching process. The etchant used in the wet etching process is, for example, hot phosphoric acid. In some embodiments, after the insulating cap layer 115 is formed and before the plurality of horizontal openings 121 are formed, a dummy pillar may be formed in the stepped region R2 first. In some embodiments, dummy patterns (not shown) may pass through the insulating capping layer 115 and the dielectric layer 103 . Dummy patterns can be dummy pillars or dummy fences. The dummy pattern may be in contact with the top surfaces of any or all of the support posts 98A, 98B, 98C, 98D, or not at all. In other embodiments, the dummy pattern may pass through the insulating cap layer 115 , the dielectric layer 103 and the stepped structure 105 to reach the bottommost first material layer 102 of the stepped structure 105 . The material of the dummy pattern is different from that of the second material layer 104, such as silicon oxide. The dummy pattern can support the stacked structure 101' during the process of forming the plurality of horizontal openings 121 and prevent the stacked structure 101' from collapsing.

Referring to FIG. 3B and FIG. 4B , a conductor layer is formed in the horizontal opening 121 . The conductor layer includes, for example, a barrier layer 122 and a metal layer 124 . In one embodiment, the material of the barrier layer 122 includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof, and the material of the metal layer 124 includes tungsten (W ). The conductor layer in the horizontal opening 121 serves as the gate layer 126 .

Referring to FIGS. 3C , 4C and 5A, a plurality of contact windows C1 and C3 are respectively formed in the region A1 and the region A3 of the stepped region R2 according to the above method, as shown in FIGS. 3C and 5A , and in the memory array region A plurality of contact windows C2 are formed in R1, as shown in FIG. 3C.

In the above embodiments, the support pillar structures 98 , 98A, 98B, 98C, 98D and/or 98E may be formed in the stacked structure 101 or 101 ′ of the stepped region R2 before forming the end portion EP to avoid the stacked structure 101 'The collapse occurred during the etching process to form the end portion EP. In another embodiment, if the stacked structure 101' does not collapse during the etching process for forming the end portion EP, it may not be necessary to form the support pillar structures 98, 98A, 98B, 98C, 98D and/or 98E.

In various embodiments of the present invention, locally increasing the thickness of the end portion of the second material layer (eg, silicon nitride or doped polysilicon) in the stepped region can avoid forming contact openings with different depths. During the process, the gate layer below the shallower contact openings is etched through. Therefore, by forming the end portion, the process window can be increased to increase the yield of the process. The end portion can be formed by multiple selective etching and backfilling, and its process can be integrated with the existing process. In addition, the support column structure may be formed in the stacked structure in the stepped region before forming the end portion, so as to avoid the collapse of the stacked structure during the etching process for forming the end portion.

96, 106: Opening 98, 98A, 98B, 98C, 98D, 98E: Support structure 100: base 101, 101': Stacked structure 102: The first material layer 102T: Insulation layer 103: Dielectric layer 104: Second material layer 104E: Filler Layer 104': Material Layer 105: Ladder Structure 107, 107', 121: Horizontal opening 108: Charge Storage Structures 110: channel layer 112: Insulation column 114: Conductor plug 115: Insulation top cover 122, 128, 129: Barrier layer 124: metal layer 126: gate layer 131, 132: Conductor layer A1, A2, A3: Area C1, C2, C3: Contact window CP: Vertical Channel Column EP: terminal MP: main body OP1, OP2, OP1A, OP1B, OP1C, OP1D: Contact window openings R1: Memory array area R2: Step area T1, T2, T3, T4: Thickness I-I', II-II', III-III', IV-IV': Tangent

1A to FIG. 1I are schematic cross-sectional views of a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention. 2A to 2I are schematic diagrams of another cross-section of a manufacturing method of a three-dimensional memory device according to an embodiment of the present invention. 3A to 3C are schematic cross-sectional views of a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention. 4A to 4C are another schematic cross-sectional view of a manufacturing method of a three-dimensional memory device according to another embodiment of the present invention. 5A-5C are top views of intermediate stages of a three-dimensional memory device according to an embodiment of the present invention. FIG. 5D is a partial perspective view of FIG. 5C .

100: base

102: The first material layer

103: Dielectric layer

108: Charge Storage Structures

112: Insulation column

115: Insulation top cover

122, 128, 129: Barrier layer

124: metal layer

126: gate layer

131, 132: Conductor layer

C1, C2: Contact window

CP: Vertical Channel Column

EP: terminal

MP: main body

OP1, OP2, OP1A, OP1B, OP1C, OP1D: Contact window openings

R1: Memory array area

R2: Step area

Claims (10)

A memory device comprising: a substrate, including a memory array area and a stepped area; A stacked structure, located on the substrate of the memory array region and the stepped region, wherein the stacked structure includes a plurality of conductor layers and a plurality of insulating layers stacked alternately with each other, and each of the plurality of conductor layers include: a main body portion located in the memory array region and extending to the stepped region; and an end portion, connected with the main body portion, located in the stepped region, wherein the thickness of the end portion is greater than the thickness of the main body portion; a dielectric layer on the stacked structure of the memory array region and the stepped region; and The first contact window penetrates through the dielectric layer in the stepped region and the corresponding insulating layer above the end portion, and is landed on the end portion and connected with the end portion. The memory device of claim 1, further comprising: A support column, disposed beside the first contact window, penetrates the end portion from the corresponding insulating layer located above the end portion, and extends to the bottommost insulating layer of the stacked structure. The memory device of claim 1, further comprising: A second contact window, disposed beside the first contact window, penetrates the dielectric layer in the stepped region and the corresponding insulating layer above the end portion, and is landed on the end portion and connected to the end portion; and A support wall, extending from the memory array area to the step area, is disposed between the first contact window and the second contact window and penetrates through the stack structure. The memory device of claim 1, further comprising: A second contact window, disposed beside the first contact window, penetrates the dielectric layer in the stepped region, landed on the end portion and connected with the end portion; and a support column disposed between the first contact window and the second contact window and passing through the corresponding insulating layer above the end portion and the insulation from the end portion to the bottommost layer of the stack structure Floor. A method of manufacturing a memory device, comprising: providing a substrate, the substrate includes a memory array region and a stepped region; forming a stacked structure on the substrate of the memory array region and the stepped region, wherein the stacked structure includes a plurality of first material layers and a plurality of second material layers stacked alternately with each other; patterning the stacked structure to form a stepped structure in the stacked structure in the stepped region; removing portions of the plurality of second material layers at ends of the stepped structure to form a plurality of first horizontal openings; removing the plurality of first material layers of portions around the plurality of first horizontal openings to increase the height of the plurality of first horizontal openings; forming an end portion in each of the plurality of first horizontal openings, and the thickness of the end portion is greater than the thickness of the adjacent second material layer; forming a dielectric layer on the stacked structure of the memory array region and the stepped region; and A first contact window is formed in the stepped area, wherein the first contact window penetrates through the dielectric layer in the stepped area and the corresponding first material layer above the end portion, and is landed on the end portion and connected to the end portion. The method of manufacturing a memory device according to claim 5, wherein the method of forming the end portion in each of the plurality of first horizontal openings comprises: forming a third material layer on the stacked structure and among the plurality of first horizontal openings; and A third material layer other than the plurality of first horizontal openings is removed to form the end portion in each of the plurality of first horizontal openings. The method for manufacturing a memory device as claimed in claim 6, further comprising: before forming the first contact window in the stepped region, removing the second material layer and the end portion to form a plurality of second horizontal openings; and A plurality of conductor layers are formed in the plurality of second horizontal openings. The method for manufacturing a memory device according to claim 5, further comprising: Before forming the stepped structure, a support structure is formed in the stacked structure of the stepped region. The method for manufacturing a memory device according to claim 8, wherein the method for forming the support structure comprises: forming an opening in the stacked structure of the stepped area to expose the bottommost first material layer of the stacked structure; and An insulating layer is formed in the opening to form the support structure. The method for manufacturing a memory device according to claim 8, wherein the method for forming the support structure comprises: forming a trench in the stacked structure of the memory array region and the stepped region, exposing the bottommost first material layer of the stacked structure; and An insulating layer is formed in the trench to form the support structure.

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