TWI753545B - Air spacer structures - Google Patents

Abstract

The present disclosure generally relates to semiconductor structures and, more particularly, to air spacer structures and methods of manufacture. The structure includes: a plurality of gate structures comprising active regions; contacts extending to the active regions; a plurality of anchor structures between the active regions; and air spacer structures adjacent to the contacts.

Description

air spacer

The present disclosure relates generally to semiconductor structures, and more particularly to air spacer structures and methods of fabrication.

As semiconductor processes continue to shrink in size (eg, shrink), the required spacing (ie, pitch) between features also becomes smaller. To this end, in these smaller technology nodes, it is becoming increasingly difficult to fabricate features due to critical dimension (CD) scaling and process capabilities.

In radio frequency (RF) applications, device performance is limited by parasitic gate-to-source/drain (S/D) capacitance. This is because the high-frequency performance indicators (such as Ft and Fmax) of RF transistors are related to the value of the gate structure to S/D contact capacitance (ie gate-to-drain capacitance (C _gd ) and gate-to-source capacitance ( C _gs ) ) is inversely proportional. The parasitic gate-to-S/D capacitance can be manifested from: (i) the spacer material of the gate structure; and (ii) the metal stack between the gate structure's metal stack and the metal fill of the S/D contacts Relatively lower quality oxides can be flowable chemical vapor deposition (FCVD).

Conventional components that attempt to address parasitic gate-to-S/D capacitance involve a self-aligned contact (SAC) integration process. However, the SAC flow need not be the preferred integration for technology nodes with relatively large contacted poly pitch (CPP) because the space between gate structures is large enough to use only patterned and The etching process reliably forms the trench contacts. Therefore, there is no need to self-align the trench contacts with the gate structures. An example of such a relaxed CPP element can be found in RF technology, where the space between adjacent gate structures is maintained large enough without the need for a SAC integration process. For RF components, the trench contacts are etched directly into the low quality FCVD oxide. However, most of these proposed air-gap spaced volumes are derived from the SAC process and are not necessarily compatible with relaxed CPP volumes. The present invention provides a solution to this problem.

In aspects of the disclosed content, a structure includes: gate structures including active regions; contacts extending into the active regions; anchor structures between the active regions; and air spacer structures adjacent to the contacts.

In aspects of the disclosed content, a structure includes: gate structures including source and drain (S/D) regions; contacts extending to the S/D regions; anchor structures, It is between the S/D regions; and an air spacer structure adjacent the contacts and the anchoring structures.

In aspects of the disclosed disclosure, a method includes: forming at least one gate structure; forming a plurality of active regions adjacent to the at least one gate structure; forming encapsulating the at least one gate structure and the a double liner for active regions; depositing an insulator material over the double liner; forming anchor structures between the active regions; forming contacts in electrical contact with the active regions; etching the double liner at least one liner layer; etching selected portions of the insulator material to form at least one air gap; and depositing a second liner layer within the air gaps to form an air gap structure.

The present disclosure relates generally to semiconductor structures, and more particularly to air spacer structures and methods of fabrication. In various embodiments, the processes and structures provided herein utilize liners and anchors to form a space for air between the gate structures and the source/drain (S/D) contacts Structure air gap. Advantageously, by forming the air spacer structure, parasitic gate pair S/D capacitance can be reduced due to the low-k nature of air, thereby improving radio frequency (RF) device performance.

The processes and structures described herein take into account the dielectric constant of the separation between the gate structure and the S/D junction in order to reduce the parasitic gate-to-S/D capacitance to the target value required by RF technology (ie, reduce The gate-to-drain capacitance (C _gd ) and gate-to-source capacitance (C _gs ) ) are designed and fabricated in a specified manner. In various embodiments, relatively large air gap structures are formed to account for these RF target values (eg, Ft and Fmax for RF transistors) being achieved because Ft and Fmax are related to the capacitance values of the gate structure to the S/D junction (ie C _gd and C _gs ) are inversely proportional. In further embodiments, the processes and structures described herein are compatible with non-self-aligned contact (SAC) processes and can be applied to any contact poly that can be critical to RF FinFETs Foot pitch (CPP). In this way, the structures and processes described herein improve the overall performance of the RF element at any CPP.

A method includes forming a dual (bottom liner and top liner) contact etch stop liner (CESL) to encapsulate the gate structure of the device. Anchoring structures are formed between the active regions (ie, S/D regions) of the device, and an interlayer dielectric cap is formed over the CESL from the same material as the anchoring structures. The method further includes a selective etch to etch the top liner of the dual CESL in order to access the interlayer dielectric. The ILD system is selectively etched to remove the ILD between the gate structures and the S/D contacts, thereby forming air gaps. By depositing a conformal low-k liner within the air gaps, relatively large air gap structures are formed from the air gaps.

A structure including an air spacer structure with a spacer of the gate structure and a relatively large air gap between the S/D contacts. The structure has no air gaps in the equal spacing of the gate structure. Also, the air gap cap is in spaced contact with the S/D contacts and the gate structure. In various embodiments, the structure includes a single air gap or a double air gap encapsulating between the dielectric pillars of the anchoring structures, the S/D regions, and the S/D contacts. Furthermore, the S/D contacts are anchored through the dielectric pillars of the anchoring structures, wherein the anchoring structures are between the active regions.

The structures disclosed herein can be fabricated in a variety of ways using a variety of different tools. In general, however, such methods and tools are used to form structures with dimensions on the micro and nano scales. The methods (ie, techniques) employed to fabricate the structures disclosed herein have been introduced from integrated circuit (IC) technology. For example, these structures are built on a wafer and implemented in a film of material that is patterned over the wafer by a photolithography process. In particular, the fabrication of this structure uses three basic building blocks: (i) deposition of thin films of material on a substrate; (ii) application of a patterned mask over the films by photolithography; and (iii) the photolithography The mask selectively etches the films.

1A-1C show lead-in structures and respective processes according to aspects of the present disclosure. Specifically, FIG. 1A depicts a top view of the structure 100, FIG. 1B depicts the structure 100 along the X axis, and FIG. 1C depicts the structure 100 along the Y axis. Referring to FIGS. 1A-1C , structure 100 includes fin structure 110 , which is composed of a suitable semiconductor material 105 . For example, the fin structures 110 may be composed of any suitable semiconductor material 105 including, but not limited to, Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and the like.

The fin structures 110 can be fabricated using sidewall image transfer (SIT) technology. In the example of SIT technology, mandrel material, such as _SiO2 , is deposited on the substrate using conventional chemical vapor deposition (CVD) processes. Photoresist is formed on the mandrel material and exposed to form patterns (openings). Reactive ion etching (RIE) is performed through the openings to form the mandrels. In various embodiments, the mandrels may have different widths and/or spacings depending on the desired dimensions of the fin structures. Spacers are formed on the sidewalls of the mandrels (which are preferably of a different material than the mandrels and formed using conventional deposition processes known to those skilled in the art). The spaces may have widths that match, for example, the dimensions of the fin structures. The mandrels are removed or stripped using conventional etching processes that are selective to the mandrel material. Etching is then performed within the spacing of the spacings to form the sub-lithographic features (eg, fin structures). The sidewall spacers can then be peeled off.

Still referring to FIGS. 1A-1C , gate structures 120 are formed on the fin structures 110 and shallow trench isolation (STI) regions 115 . The STI regions 115 can be formed by conventional etching and deposition processes, followed by a planarization process (eg, chemical mechanical planarization (CMP)). In various embodiments, the gate structures 120 are composed of a dummy gate material 125 (eg, amorphous silicon (α-Si) ) and a capping layer 130 . The capping layer 130 may be formed of any suitable hard mask material, such as SiN, among other examples.

Dummy gate material 125 and capping layer 130 are deposited by CVD, followed by conventional patterning steps. The gate structures 120 further include sidewall spacers 135 (eg, low-k dielectrics), which may be deposited on the sidewalls of the patterned materials 125, 130. The sidewall spacers 135 may be deposited by a conventional chemical vapor deposition (CVD) process, followed by a patterning process (eg, an anisotropic etching process) to remove any material from the horizontal surfaces of the structure 100 .

Source and drain (S/D) regions 140 are formed on the sides of the gate structures 120 (eg, the sidewall spacers 135 ) on the fin structures 110 using, for example, any conventional method. For example, the S/D regions 140 may be elevations formed by doped epitaxial growth of material on the surfaces of the fin structures 110 within the openings between the gate structures 120 formula S/D area. In further embodiments, the S/D regions 140 may be formed by an ion implantation process, a doping process, or a diffusion process as known to those skilled in the art, so that the present invention can be understood without further explanation. The invention disclosed.

FIGS. 2A and 2B show dual contact etch stop liner (CESL) 145 deposited over the gate structures 120 and the S/D regions 140 . In various embodiments, the dual CESL 145 may consist of a bottom liner 150 and a top liner 155 . In this way, the etch stop liner is a dual etch stop liner (ie, dual CESL 145 ), including a bottom liner 150 and a top liner 155 . Bottom liner 150 may be composed of any suitable low-k material such as SiBCN. In further embodiments, the bottom liner 150 may be composed of the same low-k material as the sidewall spacers 135 . The top liner 155 may also be composed of a low-k material such as SiN. Accordingly, the bottom liner and the top liner are composed of low-k materials. Bottom liner 150 and top liner 155 may be deposited by atomic layer deposition (ALD) or CVD processes.

Bottom liner 150 and top liner 155 may each have a thickness in the range of 2 nm to 5 nm. In this manner, the dual CESL 145 can be formed with a thickness in the range of about 4 nm to 10 nm; however other dimensions are contemplated herein. An interlevel dielectric (ILD) 160 is deposited over the S/D regions 140 and the dual CESL 145 . The ILD 160 can be deposited by a CVD process and is composed of oxides, for example. After deposition, the ILD 160 is planarized to the height of the capping layer 130 by a CMP process, thereby removing the dual CESL 145 directly above the capping layer 130 .

Figures 3A and 3B show anchoring structures 165 formed between the active regions of the element. In various embodiments, an organic planarization layer (OPL) is applied by a spin coating process to overly deposit the OPL material over the top surface of ILD 160 and the top surface of capping layer 130 . The ILD 160 is patterned by a selective etching process such as RIE to form trenches within the ILD 160 . The OPL material is etched away by a conventional etching process, such as an oxygen ashing process.

Anchor structure 165 is formed by depositing fill material 170 through an ALD or CVD process within the trench, within the trench of ILD 160 between the active regions (ie, S/D regions 140 ) and over dual CESL 145 form. In this way, the structure includes an etch stop liner (ie, dual CESL 145 ) below the anchor structures 165 . In various embodiments, the fill material 170 may be composed of SiC and may be ground through a CMP process that stops on the ILD 160 due to the selectivity between the fill material 170 and the ILD 160 .

In various embodiments, the anchoring structures 165 prevent the structure 100 from collapsing during subsequent etching of the bottom liner 150 , the top liner 155 , and/or the ILD 160 . After the anchoring structures 165 are formed, the capping layer 130 is etched (removed) using conventional etching techniques, such as the RIE process. In this way, the dummy gate material 125 is exposed. In alternative embodiments, the anchor structures 165 may be formed after the replacement gate structures are formed.

FIGS. 4A and 4B show replacement gate structures 175 formed over the fin structures 110 . In various embodiments, the dummy gate material 125 is removed by conventional etching techniques, such as the RIE process. In this manner, the gate structures 175 include sidewall spacers 135 and an etch stop liner (ie, dual CESL 145 ) adjacent to the sidewall spacers 135 . The replacement gate structures 175 include a gate stack 180 that includes a dielectric material and a gate metal.

The gate dielectric material may be, for example, a high-k gate dielectric material (eg, a hafnium-based dielectric). In various embodiments, the high-k dielectric materials may include, but are not limited to: Al ₂ O ₃ , Ta ₂ O ₃ , TiO ₂ , La ₂ O ₃ , SrTiO ₃ , LaAlO ₃ , ZrO ₂ , Y ₂ O ₃ , Gd ₂ O ₃ , and combinations including multiple layers thereof. The gate metal of gate stack 180 may depend on the particular application and these design parameters, including any metal or any combination of metals (eg, TiN, TiC, tungsten (W) ). A gate cap 185 is deposited over the gate stack 180 . In various embodiments, gate stack 180 and gate cap 185 may be deposited between the sidewall spacers 135 using a CVD process, followed by a CMP process.

FIGS. 5A and 5B show the air gap cap 190 deposited over the ILD 160 and the anchoring structures 165 . In various embodiments, prior to deposition of air gap cap 190, ILD 160 is recessed through a selective RIE process, thereby forming trenches. The trenches are filled with material 195 to form air gap caps 190 (which are deposited by a CVD process followed by a CMP process). In various embodiments, the material 195 is the same material as the fill material 170 of the anchoring structures 165 (ie, SiC). In this manner, the cap (ie, air gap cap 190 ) is composed of the same material as the anchoring structures 165 .

6A and 6B show the S/D contacts 200, among other features. In various embodiments, trenches are formed in ILD 160 using conventional lithography and etching techniques, such as RIE processes. In various embodiments, the trench formation may be a maskless process due to the materials performed. The etch exposes the dual CESL 145 over the S/D regions 140 for subsequent selective chemical etching of the S/D regions 140 .

In various embodiments, trenches are formed by selectively etching air gap cap 190 and ILD 160 using an RIE process, thereby exposing dual CESL 145 . Then, dual CESL 145 is etched from the top surface of the S/D regions 140 , thereby exposing the S/D regions 140 . Removal of the dual CESL 145 can be an alternative maskless process by wet or dry etching, which uses chemical methods to remove material such as the liners 150, 155 (selective to the remaining material). The S/D contacts 200 will be formed in contact with the exposed portions of the S/D regions 140 . More specifically, the metal material 205 of the S/D contacts 200 will directly contact the S/D regions 140 .

A salicide liner is deposited in the trenches over the S/D regions 140 and then subjected to a silicide process. As will be understood by those skilled in the art, the silicide process begins by depositing a thin transition metal layer (eg, nickel, cobalt, or titanium) over a fully formed and patterned semiconductor device (eg, S/D region 140 ). After depositing the material, the structure is heated, allowing the transition metal and exposed silicon (or as described herein) in the active regions of the semiconductor element (eg, source, drain, gate contact regions) other semiconductor materials) to form low-resistance transition metal silicides. After the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts in the active regions of the device. Those skilled in the art will understand that when the gate structures are composed of metallic materials, no silicide contacts are required on the devices.

The salicide liner can be deposited using physical vapor deposition (PVD) or CVD processes. After the silicide process, metal material 205 is deposited on the transition metal silicide, thereby forming the S/D contacts 200 . The S/D contacts 200 are formed in contact with the exposed portions of the S/D regions 140 . More specifically, the metal materials 205 of the S/D contacts 200 directly contact the S/D regions 140 . The metal material 205 may be composed of, for example, cobalt (Co) or tungsten (W) or ruthenium (Ru).

Depositing metal material 205 is followed by a CMP process of the gate cap 185 material. In this manner, forming the S/D contacts 200 is a non-self-aligned contact (SAC) process. In various embodiments, the S/D contacts 200 are anchored through the anchoring structures 165, thereby providing further stability to the S/D contacts 200 during subsequent etching processes. Specifically, the contacts 200 are anchored into the anchoring structures 165 .

FIGS. 7A and 7B show the air gap 210 formed by removing the top liner 155 of the dual CESL 145 and selected portions of the ILD 160 . In various embodiments, removal of top liner 155 is a maskless process by vapor etch that uses selective chemical methods to remove materials such as top liner 155 (SiO ₂ material for ILD 160, the anchors The SiC material of the fixed structure 165 and the low-k value material SiBCN of the bottom liner 150 are selective).

The SiO ₂ material of the ILD 160 is removed using selective etching (eg, vapor phase etching) selective to the SiC material of the anchoring structures 165 and the low-k material SiBCN of the bottom liner 150 . Specifically, selected portions of the ILD 160 between the replacement gate structures 175 and the S/D contacts 200 are etched away, while other portions of the ILD 160 remain. In this way, air gaps 210 are formed between the replacement gate structures 175 and the S/D contacts 200, while the bottom liner 150 of the dual CESL 145 remains intact. In various embodiments, a portion of the top liner 155 and a portion of the bottom liner 150 are covered by the anchoring structures 165 and thus remain under the anchoring structures 165 . In this way, the etch stop liner (ie dual CESL 145 ) extends under the anchor structures 165 .

In various embodiments, the dielectric pillars of the anchoring structures 165 provide stability to the structure 100 by anchoring the S/D contacts 200 in the anchoring structures, thereby preventing the element from Collapse in the layers. Accordingly, the structure 100 will not collapse due to the weight of the S/D contacts 200 when the selected portions of the ILD 160 are removed.

8A and 8B illustrate the formation of an air spacer structure 220 (ie, a single or double air space structure). Accordingly, the structures and processes described herein include gate structures 175, which include active regions (ie, S/D regions 140); and contacts 200, which extend into the active regions. Again, the structure includes anchor structures 165 between the active regions; and air spacer structures 220 adjacent to the contacts 200 .

The air spacer structures 220 are formed by depositing a low-k liner 215 on the sidewalls of the air gaps 210 to form the air spacer structures 220, followed by an isotropic etch back process. In this manner, the air spacer structures 220 include a liner (ie, the low-k liner 215 ) and the air gap 210 . The low-k liner 215 may be composed of any suitable low-k material (eg, SiBCN) deposited by a CVD process (as an example). In various embodiments, a low-k liner 215 is deposited over the air gaps 210 to form the air space structures 220 . Accordingly, the air spacer structures 220 include air gaps 210 between the gate structures 175 and the contacts 200 . In various embodiments, a low-k liner 215 lines the anchoring structures 165 and an air gap cap 190 is tied over the air gap structures 220 .

The low-k nature of the air contained within the air spacer structures 220 allows for the reduction of the parasitic gate pair S/D capacitance, thereby improving RF device performance. Also, the air gap caps 190 over the air spacer structures 220 allow for the further integrity of the air spacer structures 220 . In this manner, the structure includes a plurality of gate structures 175 that include source and drain (S/D) regions 140 ; and contacts 200 that extend to the S/D regions 140 . Also, anchoring structures 165 are tied between the S/D regions 140 , with air spacer structures 220 adjacent to the contacts 200 and the anchoring structures 165 .

The processes and structures described herein take into account the dielectric constant of the spacer structure between the replacement gate structures 175 and the S/D contacts 200, in order to reduce the parasitic gate pair S/D capacitance to the level required by RF technology. It needs to be designed and manufactured with the target value (ie reducing the gate-to-drain capacitance (C _gd ) and gate-to-source capacitance (C _gs ) ). In various embodiments, the relatively large air spacer structures 220 are formed taking into account the achievement of these RF target values (eg, Ft and Fmax for RF transistors) because Ft and Fmax are related to the gate structure-to-S/D contact capacitance The values of C _gd and C _gs are inversely proportional. Also, the processes and structures described herein are compatible with non-self-aligned contact (SAC) processes and can be applied to any contact poly-pitch (CPP) that may be critical to, for example, RF FinFETs . In this way, the structures and processes described herein improve the overall performance of the RF element at any CPP.

In general, the structures and processes described herein are compatible with recording integrated processes and processes for relatively large CPPs. Also, the structures and processes described herein address the relatively low quality between the gate stacks 180 and gate caps 185 of the replacement gate structures 175 and the metal material 205 of the S/D contacts 200 Parasitic gate-to-S/D capacitance due to flowable chemical vapor deposition (FCVD) of oxides. By removing the low quality FCVD oxide of these RF elements with relaxed CPP and forming air gaps instead, the parasitic capacitances can be greatly reduced and the overall RF performance improved. Furthermore, the structures and processes described herein are not limited to having small air gaps formed only within the sidewall spacers 135 of the replacement gate structures 175; The relatively large air spacer structures 220 adjacent to the equal sidewall spacings 135 of the gate structures 175 are equally replaced.

9A-10B show alternative structures according to aspects of the present disclosure. Similar to the processes illustrated in FIGS. 1A-8B , FIGS. 9A and 9B show the removal of the bottom liner 150 and the replacement gate structures 175 in addition to the removal of the top liner 155 as illustrated in FIGS. 7A and 7B . The sidewalls are spaced 135 . Accordingly, the air gaps 210a are larger than the air gaps 210 of FIGS. 7A and 7B . In this manner, due to the increased size of the air gaps 210 created by removing the bottom liner 150 and the sidewall spacers 135, the air spacer structures 220a shown in FIGS. 10A and 10B are relatively larger than those of FIGS. 8A and 8B . The air spacer structures 220 . In this manner, the processes described herein include forming at least one gate structure 175 ; and forming a plurality of active regions (ie, S/D regions 140 ) adjacent to at least one gate structure 175 . Also, the process includes forming a double liner (ie, double CESL 145) overlying the at least one gate structure and the active regions; and depositing an insulator material (ie, ILD 160) over the double liner.

In addition, the process includes forming a plurality of anchor structures 165 between the active regions; and forming a plurality of contacts 200 in electrical contact with the active regions. In various embodiments, the process ends by etching at least one liner of the dual liner (ie, bottom liner 150 or top liner 155 ); etching selected portions of the insulator material to form at least one air gap 210 ; and depositing a second liner (ie, the low-k liner 215 ) in the air gaps 210 to form the air gap structure. In further embodiments, the etching of the at least one liner is the top liner 155 of the dual liner.

Integrated circuit chips are fabricated using the method(s) as described above. The manufacturer may distribute the resulting integrated circuit chips in raw wafer form (ie, as a single wafer with multiple unpackaged chips), as bare dies, or in packaged form. In this latter case, in a single-die package (such as a plastic carrier with leads attached to a motherboard or other higher-level carrier) or in a multi-die package (such as with either surface interconnects or buried interconnects) or both) to encapsulate the wafer. In any event, the chip is then integrated with other chips, individual circuit units, and/or other signal processing devices as part of either (a) an intermediate product (eg, a motherboard) or (b) an end product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to high-end computer products with displays, keyboards, or other input devices, and central processing units.

These descriptions of the various embodiments of the present disclosure have been described for purposes of illustration, but are not intended to be comprehensive or limited to the embodiments disclosed. Numerous modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used in the text have been chosen to best explain the principles of the specific embodiments, the practical application or technical improvement of the technologies seen in the market, or to enable other ordinary skilled in the art to understand the specific implementations disclosed in the text. example.

100: Structure 105: Semiconductor Materials 110: Fins 115: Shallow Trench Isolation (STI) Region 120: Gate structure 125: Virtual gate material 130: Overlay 135: Sidewall Spacing 140: Source and drain (S/D) regions 145: Double Contact Etch Stop Liner (CESL) 150: Bottom liner 155: top liner 160: Interlayer Dielectric (ILD) 165: Anchor Structure 170: Filler material 175: Replacement gate structure 180: Gate stack 185: Gate cap 190: Air Gap Cap 195: Materials 200: S/D contact 205: Metal Materials 210, 210a: Air gap 215: Low-k liner 220, 220a: Air spacer structure

Reference is made to the referenced plural drawings by way of non-limiting examples of exemplary embodiments of the present disclosure, which is described in the following detailed description.

1A-1C show, among other features, dummy gate structures and respective processes in accordance with aspects of the present disclosure.

2A and 2B show, among other features, bottom and top contact etch stop liner (CESL) and respective processes in accordance with aspects of the present disclosure.

3A and 3B show, among other features, anchoring structures and respective processes in accordance with aspects of the present disclosure.

4A and 4B show, among other features, alternate gate structures and respective processes in accordance with aspects of the present disclosure.

5A and 5B show, among other features, an air gap cover layer and respective processes in accordance with aspects of the present disclosure.

6A and 6B show, among other features, source/drain (S/D) metallization features and respective processes in accordance with aspects of the present disclosure.

7A and 7B show, among other features, air gaps and respective processes in accordance with aspects of the present disclosure.

8A and 8B show, among other features, air spacer structures and respective processes in accordance with aspects of the present disclosure.

9A-10B show alternative structures and respective processes in accordance with aspects of the present disclosure.

105: Semiconductor Materials

110: Fins

140: Source and drain (S/D) regions

180: Gate stack

185: Gate cap

190: Air Gap Cap

200: S/D contact

205: Metal Materials

215: Low-k liner

220, 220a: Air spacer structure

Claims (8)

A semiconductor structure, comprising: a plurality of gate structures, including a plurality of active regions; a plurality of contacts extending to the active regions; a plurality of anchor structures interposed between the active regions; and a plurality of air spacer structures and the active regions The contacts are adjacent; wherein: the upper surfaces of the anchoring structures are lower than the upper surfaces of the contacts and the gate structures; the contacts are anchored through the anchoring structures; the air spacers The structures include air gaps between the gate structures and the contacts; the air spacer structures include a low-k liner; the gate structures include sidewall spacers and an etch stop liner, which is the sidewalls are spaced apart; the etch stop liner extends under the anchoring structures; the etch stop liner is a dual etch stop liner comprising a bottom liner and a top liner; and each of the The air spacer structure includes an upper air gap and a lower air gap, which are separated from each other by the low-k liner. The structure of claim 1, wherein the low-k liner lines the anchoring structures. The structure of claim 1 wherein the bottom liner and the top liner are composed of a low-k material. The structure of claim 1, further comprising a cap over the air space structures. The structure of claim 4, wherein the cap is composed of the same material as the anchoring structures. A semiconductor structure, comprising: a plurality of gate structures including source and drain (S/D) regions; a plurality of contacts extending to the S/D regions; and a plurality of anchor structures between the between the S/D regions and between the contacts so that one of the adjacent S/D regions and one of the adjacent contacts are separated from each other; and a plurality of air spacers and The sidewalls of the S/D regions, the sidewalls of the contacts and the sidewalls of the anchoring structures are adjacent; wherein: the air spacers are adjacent to the sidewalls of the S/D regions and the anchoring structures the sidewalls are separated; the contacts are anchored into the anchoring structures; wherein the air spacer structures comprise air gaps between the gate structures and the contacts; the anchors The upper surfaces of the fixed structures are lower than the upper surfaces of the contacts and the gate structures; wherein the air spacer structures comprise a low-k liner; the gate structures comprise sidewall spacers and an etch stop liner, it is spaced adjacent to the sidewalls; the etch stop liner extends under the anchoring structures; the etch stop liner is a dual etch stop liner comprising a bottom liner and a top liner; and Each of the air spacer structures includes an upper air gap and a lower air gap separated from each other by the low-k liner. A method of manufacturing a semiconductor structure, comprising: forming a plurality of gate structures including a plurality of active regions; forming a plurality of contacts extending to the active regions; forming a plurality of anchor structures between the active regions; A plurality of air spacer structures adjacent to the contacts; wherein: the upper surfaces of the anchor structures are lower than the upper surfaces of the contacts and the gate structures; the contacts pass through the anchor structures anchoring; the contacts and the upper surfaces of the gate structures do not have any of the anchoring structures; the air spacer structures include a low-k liner; the gate structures include sidewall spacers and an etch stop a liner spaced adjacent to the sidewalls; the etch stop liner extends below the anchoring structures; the etch stop liner is a dual etch stop liner comprising a bottom liner and a top liner; and each of the air spacer structures includes an upper air gap and a lower air gap separated from each other by the low-k liner. The method of claim 7, wherein etching the at least one liner is a top liner of the dual liner.

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