TWI752755B - Supporting structure of semiconductor device, display panel, manufacturing method of supporting structure of semiconductor device and fixing method of accommodating structure of semiconductor device - Google Patents

Abstract

A supporting structure of semiconductor device includes a first substrate, a first electrode, a second electrode, a first hole, a third electrode and a semiconductor device. The first electrode and the second electrode are disposed on the first substrate. The first electrode and the second electrode are disposed relatively to each other. The first hole is disposed between the first electrode and the second electrode. The third electrode is disposed on the first electrode and the second electrode. The shape of the third electrode is the ring shape and the third electrode is provided with a second hole. The first hole is exposed by the second hole. The semiconductor device is disposed on the third electrode.

Description

Semiconductor element carrier structure, display panel, semiconductor element carrier structure Forming method and repairing method of accommodating structure of semiconductor device

The present invention relates to a semiconductor element carrier structure using annular electrodes to carry semiconductor elements, a display panel, a method for forming a semiconductor element carrier structure, and a repair method for a semiconductor element accommodating structure.

Recently, the progress of display technology has been advancing by leaps and bounds, and the requirements for the picture quality of the display are also getting higher and higher, and the current display is a light-emitting diode (LED) display and an organic light-emitting diode display (organic light-emitting diode display). Diode, OLED) displays are the main ones. Although the pixels of organic light-emitting diode displays are high, the lifespan of organic light-emitting diodes is not long; although the pixels of light-emitting diode displays are lower than those of organic light-emitting diode displays , but the life of the light-emitting diode is higher. Therefore, recently, manufacturers want to reduce the size of light-emitting diodes to micro light-emitting diodes (micro-LEDs) and apply the micro-light-emitting diodes to displays. The size of the micro-LED is on the order of micrometers, and it is bound to need the assistance of sacrificial structures to perform mass transfer to smoothly transfer the micro-LEDs to the circuit board of the display. can never be improved.

In view of the foregoing, the inventors of the present invention have considered and designed a carrier structure for a semiconductor device and a method for forming the same, with a view to improving the deficiencies of the prior art, thereby enhancing the implementation and utilization in the industry.

Based on the above objectives, the present invention provides a semiconductor device carrier structure and a method for forming the same, so as to solve the problems faced in the prior art.

Based on the above objective, the present invention provides a semiconductor element carrier structure, which includes a first substrate, a first electrode, a second electrode, a first hole, a third electrode, and a semiconductor element. The first electrode and the second electrode are arranged on the first substrate, and the first electrode and the second electrode are arranged oppositely. The first hole is disposed between the first electrode and the second electrode. The third electrode is disposed on the first electrode and the second electrode, the third electrode is annular and has a second hole, and the second hole exposes the first hole. The semiconductor element is arranged on the third electrode.

In an embodiment of the present invention, the present invention further includes a transistor layer, the transistor layer is disposed on the first substrate, the transistor layer includes a first transistor and a second transistor, and the first transistor is disposed on the first substrate and Between the first electrodes, the second transistor is arranged between the first substrate and the second electrode.

In an embodiment of the present invention, the third electrode has a first conductive region and a second conductive region, the first conductive region corresponds to the first electrode and partially covers the first electrode, and the second conductive region corresponds to the second electrode and partially covers the second conductive region The electrode, the first conductive area and the second conductive area are electrically connected to the semiconductor element.

In the embodiment of the present invention, the first electrode and the second electrode are in the same film layer.

In the embodiment of the present invention, the rotation range of the semiconductor element around the second hole is -108 degrees to 108 degrees.

In the embodiment of the present invention, the cross-sectional shape of the third electrode is a circle or a polygon.

Based on the above object, the present invention provides a display panel including a first area and a second area. The first region includes the aforementioned carrier structure for the semiconductor element. The second region includes a accommodating structure of the semiconductor element, and the accommodating structure of the semiconductor element includes a second substrate, a fourth electrode, a fifth electrode, a third hole and an initial semiconductor element. The fourth electrode is disposed on the second substrate. The fifth electrode is arranged on the second substrate, and the fourth electrode and the fifth electrode are arranged oppositely. The third hole is disposed between the fourth electrode and the fifth electrode. The initial semiconductor element is disposed in the third hole.

In an embodiment of the present invention, the accommodating structure of the semiconductor element includes a third transistor and a fourth transistor, the third transistor and the fourth transistor are arranged on the second substrate, and the third transistor is arranged on the second substrate and the fourth electrode, the fourth transistor is arranged between the second substrate and the fifth electrode.

In the embodiment of the present invention, the fourth electrode and the fifth electrode are disposed in the same film layer, and the third transistor and the fourth transistor are disposed in the same film layer.

Based on the above object, the present invention provides a method for forming a carrier structure for a semiconductor element, which includes: (1) respectively forming a first electrode and a second electrode on a substrate, the first electrode and the second electrode are oppositely disposed, and the first electrode and the second electrode are opposite to each other. There are first holes between the second electrodes. (2) A third electrode is formed on the first electrode and the second electrode. The third electrode is annular and has a second hole, and the second hole exposes the first hole. (3) Adhering the semiconductor element on the third electrode.

In the embodiment of the present invention, before the step of forming the first electrode and the second electrode respectively, a transistor layer is formed on the substrate, the transistor layer includes a first transistor and a second transistor, and the first transistor is disposed on the substrate Between the substrate and the first electrode, the second transistor is arranged between the substrate and the second electrode.

In the embodiment of the present invention, after adhering the semiconductor element, the third electrode is cut to divide it into a first conductive region and a second conductive region, the first conductive region corresponds to the first electrode and partially covers the first electrode, and the second conductive region The conductive area corresponds to the second electrode and partially covers the second electrode.

In the embodiment of the present invention, the first electrode and the second electrode are in the same film layer.

In the embodiment of the present invention, the rotation range of the semiconductor element around the second hole is -108 degrees to 108 degrees.

In the embodiment of the present invention, if it is detected that the first semiconductor element is abnormal, the first semiconductor element is peeled off and the normal first semiconductor element is reattached on the third electrode.

Based on the above objects, the present invention provides a method for repairing a accommodating structure of a semiconductor element, which includes: (1) respectively forming a first electrode and a second electrode on a substrate, the first electrode and the second electrode are arranged opposite to each other, and the first electrode There is a first hole between the second electrode. (2) Disposing the initial semiconductor element in the first hole. (3) When it is detected that the initial semiconductor is abnormal, the initial semiconductor element is peeled off. (4) A third electrode is formed on the first electrode and the second electrode. The third electrode is annular and has a second hole, and the second hole exposes the first hole. (5) Adhering the semiconductor element on the third electrode.

In an embodiment of the present invention, before the step of forming the first electrode and the second electrode respectively, the first transistor and the second transistor are formed on the substrate, and the first transistor is disposed between the substrate and the first electrode, The second transistor is disposed between the substrate and the second electrode.

In the embodiment of the present invention, the first electrode and the second electrode are arranged in the same film layer, and the first transistor and the second transistor are arranged in the same film layer.

In the embodiment of the present invention, after adhering the semiconductor element, the third electrode is cut to divide it into a first conductive region and a second conductive region, the first conductive region corresponds to the first electrode and partially covers the first electrode, and the second conductive region The conductive area corresponds to the second electrode and partially covers the second electrode.

In the embodiment of the present invention, the rotation range of the semiconductor element with the second hole as the center is -108 degrees to 108 degrees.

Based on the above, the carrier structure of the semiconductor element and the method for forming the same of the present invention utilize the annular arrangement of the third electrode, so that the present invention can tolerate the increase of the rotational deviation of the semiconductor element and improve the process yield.

10: Substrate

10A: The first substrate

10B: Second substrate

21, 21A: the first electrode

22, 22A: the second electrode

23: Fourth electrode

24: Fifth electrode

30, 30A: the third electrode

31, 31A: the first conductive area

32, 32A: the second conductive area

41, 41A: the first transistor

42, 42A: the second transistor

43: The third transistor

44: Fourth transistor

AS: accommodating structure of semiconductor components

BS: Bearing Structure for Semiconductor Components

DP: Display Panel

DS: Display area

H1, H11, H12: the first hole

H2: The second hole

NDS: non-display area

OSD: Initial Semiconductor Device

R1: District 1

R2: Zone 2

SD: Semiconductor Components

S11~S15, S21~S27: Steps

FIG. 1 is a configuration diagram of a display panel of the present invention.

FIG. 2 is a configuration diagram of the carrier structure of the semiconductor element of the present invention.

FIG. 3 is a configuration diagram of the accommodating structure of the semiconductor element of the present invention.

FIG. 4 is a schematic diagram of the first embodiment of the third electrode of the present invention.

FIG. 5 is a schematic diagram of a second embodiment of the third electrode of the present invention.

FIG. 6 is a flow chart of a method for forming a carrier structure for a semiconductor element of the present invention.

FIG. 7 is a flow chart of the repairing method of the accommodating structure of the semiconductor device according to the present invention.

The advantages, features, and technical means of achieving the present invention will be more easily understood by being described in more detail with reference to the exemplary embodiments and the accompanying drawings, and the present invention may be implemented in different forms, so it should not be construed as being limited to what is described herein. Rather, the embodiments are provided so that this disclosure will be thorough, complete and complete to convey the scope of the invention to those of ordinary skill in the art, and the invention will only be appended Defined by the scope of the patent application.

It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections You should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer and/or section from another element, component, region, layer and/or section. Thus, "first element", "first feature", "first region", "first layer" and/or "first portion" discussed below may be referred to as "second element", "second feature" , "Second Area", "Second Layer" and/or "Second Section" without departing from the spirit and teachings of the present invention.

Additionally, the terms "comprising" and/or "comprising" refer to the presence of stated features, regions, integers, steps, operations, elements and/or components, but do not exclude one or more other features, regions, integers, steps, operations , elements, components and/or the presence or addition of combinations thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed as having definitions consistent with their meanings in the context of the related art and the present invention, and will not be construed as idealized or overly formal meaning, unless expressly defined as such herein.

Please refer to FIG. 1 , which is a configuration diagram of the display panel of the present invention. As shown in FIG. 1, the display panel DP of the present invention includes a display area DS and a non-display area NDS, and the non-display area NDS surrounds the display area DS. The display area DS includes a first area R1 and a second area R2, the first area R1 includes a semiconductor element supporting structure BS, and the second area R2 includes a semiconductor element accommodating structure AS.

Please refer to FIG. 2 , which is a configuration diagram of the carrier structure of the semiconductor device of the present invention. As shown in FIG. 1 , the carrier structure BS of the semiconductor device of the present invention includes a first substrate 10A, a first electrode 21 , a second electrode 22 , a first hole H1 , a third electrode 30 and a semiconductor device SD. first electrode The first electrode 21 and the second electrode 22 are disposed on the first substrate 10A, and the first electrode 21 and the second electrode 22 are disposed opposite to each other. The first hole H1 is disposed between the first electrode 21 and the second electrode 22 . The third electrode 30 is disposed on the first electrode 21 and the second electrode 22 . The third electrode 30 is annular and has a second hole H2 (as shown in FIG. 4 and FIG. 5 ), and the second hole H2 exposes the first Hole H1. The semiconductor element SD is provided on the third electrode 30 .

The carrier structure BS of the semiconductor element of the present invention further includes a transistor layer, the transistor layer includes a first transistor 41 and a second transistor 42, and the first transistor 41 and the second transistor 42 are disposed on the first substrate 10A, The first transistor 41 is disposed between the first substrate 10A and the first electrode 21 , the second transistor 42 is disposed between the first substrate 10A and the second electrode 22 , and the first hole H1 is also located between the first transistor 41 and the second electrode 22 . between the second transistors 42 . The first electrode 21 and the second electrode 22 are located in the same film layer, and the first transistor 41 and the second transistor 42 are also located in the same film layer.

Please refer to FIG. 3 , which is a configuration diagram of the accommodating structure of the semiconductor device of the present invention. As shown in FIG. 3, the accommodating structure AS of the semiconductor device of the present invention includes a second substrate 10B, a third transistor 43 and a fourth transistor 44, a fourth electrode 23, a fifth electrode 24, and a third hole H3 and the initial semiconductor element OSD. The third transistor 43 and the fourth transistor 44 are provided on the second substrate 10B, and the fourth electrode 23 is provided on the third transistor 43 and extends from the surface of the third transistor 43 to the third transistor 43 and the second transistor 43 At the junction of the substrate 10B, the fifth electrode 24 is disposed on the fourth transistor 44; that is, the third transistor 43 is disposed between the second substrate 10B and the fourth electrode 23, and the fourth transistor 44 is disposed on the second between the substrate 10B and the fifth electrode 24 . The third hole H3 is disposed between the third transistor 43 and the fourth transistor 44 , and the third hole H3 is also disposed between the fourth electrode 23 and the fifth electrode 24 . The initial semiconductor element OSD is disposed in the third hole H3. The fourth electrode 23 and the fifth electrode 24 are arranged on the same film layer, and the third transistor 43 and the fourth transistor 44 are arranged on the same film layer.

The first substrate 10A and the second substrate 10B may include, for example, a glass substrate, a quartz substrate, a substrate formed of a polymer resin, or a flexible substrate formed of a flexible material such as polyimide. The material of the polymer resin may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAT), polyetherimide (PEI), poly-2,6 naphthalene Polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate (polyallylate), polyimide ( polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT or TAC), cellulose acetate propionate (CAP) or a combination thereof, the first substrate 10A and the second substrate 10B may be substrates of the same or different materials. Materials of the first electrode 21 , the second electrode 22 , the third electrode 30 , the fourth electrode 23 and the fifth electrode 24 may include, for example, indium (In), tin (Sn), aluminum (Al), gold (Au), platinum (Pt), indium (In), zinc (Zn), germanium (Ge), silver (Ag), lead (Pb), palladium (Pd), copper (Cu), gold beryllium (AuBe), germanium beryllium ( At least one of BeGe), nickel (Ni), lead tin (PbSn), chromium (Cr), gold zinc (AuZn), titanium (Ti), tungsten (W) and titanium tungsten (TiW) . The first transistor 41 , the second transistor 42 , the third transistor 43 and the fourth transistor 44 may include thin film transistors (TFTs), bottom-gate transistors, top-gate transistors A top-gate transistor or a vertical TFT. The semiconductor element SD and the initial semiconductor element OSD can be, for example, horizontal light emitting diodes, flip chip light emitting diodes, vertical light emitting diodes or other electronic components, and are not limited to the scope of the present invention.

Please refer to FIG. 4 and FIG. 5 , which are schematic diagrams of the first embodiment of the third electrode of the present invention and a schematic diagram of the second embodiment of the third electrode of the present invention. As shown in FIG. 4 , the third electrode 30 is circular and has a second hole H2 , the cross-sectional shape of the second hole H2 is also circular, and the semiconductor element SD is disposed on the third electrode 30 . According to the arrangement position of the semiconductor element SD, the first conductive region 31 and the The second conductive region 32, the first conductive region 31 corresponds to the first electrode 21 and partially covers the first electrode 21, the second conductive region 32 corresponds to the second electrode 22 and partially covers the second electrode 22; the semiconductor element SD has a second hole H2 The rotation range of the center is -105 degrees to 105 degrees, and the present invention can tolerate the rotation deviation of the semiconductor element SD, thereby improving the process yield.

As shown in FIG. 5 , the third electrode 30 is a square ring and has a second hole H2 , the cross-sectional shape of the second hole H2 is also a square, and the semiconductor element SD is disposed on the third electrode 30 . Similarly, according to the arrangement position of the semiconductor element SD, the first conductive region 31 and the second conductive region 32 are divided, the first conductive region 31 corresponds to the first electrode 21 and partially covers the first electrode 21, and the second conductive region 32 corresponds to the second conductive region 32. The electrode 22 partially covers the second electrode 22; the rotation range of the semiconductor element SD around the second hole H2 is -108 degrees to 108 degrees. The present invention can tolerate the rotation deviation of the semiconductor element SD, thereby improving the process yield.

Wherein, according to the requirements of the semiconductor element SD, the cross-sectional shape of the third electrode 30 can be a circle or a polygon, which is not limited to the scope of the present invention. In one embodiment, the polarity of the first conductive region 31 and the first electrode 21 is positive, and the polarity of the second conductive region 32 and the second electrode 22 is negative; The polarity of one electrode 21 is negative, and the polarity of the second conductive region 32 and the second electrode 22 is positive.

Please refer to FIG. 6 , which is a flow chart of the method for forming the carrier structure of the semiconductor device of the present invention. As shown in FIG. 6 , together with FIGS. 1 and 4 , the method for forming the carrier structure of the semiconductor device of the present invention is described as follows: Step S11 : forming the first transistor 41 and the second transistor 42 on the substrate 10 On the top, the first hole H11 is located between the first transistor 41 and the second transistor 42, and the first transistor 41 and the second transistor 42 are disposed opposite to each other.

Step S12 : respectively forming the first electrode 21 and the second electrode 22 on the first transistor 41 and the second transistor 42 , and the first hole H11 is also located between the first electrode 21 and the second electrode 22 .

Step S13 : forming a third electrode 30 on the first electrode 21 and the second electrode 22 , the third electrode 30 is annular and has a second hole (as shown in FIG. 4 ), and the second hole exposes the first hole H11 .

Step S14 : adhering the semiconductor element SD on the third electrode 30 .

Step S15: According to the setting position of the semiconductor element SD, the third electrode 30 is cut to be divided into a first conductive region 31 and a second conductive region 32, the first conductive region 31 corresponds to the first electrode 21 and partially covers the first electrode 21 , the second conductive region 32 corresponds to the second electrode 22 and partially covers the second electrode 22 .

If it is detected that the semiconductor element SD is abnormal, the semiconductor element SD is peeled off and the normal semiconductor element SD is re-attached on the third electrode 30 . Among them, as a method of peeling off the semiconductor element SD, for example, laser peeling or wet peeling can be used.

Please refer to FIG. 7 , which is a flowchart of the repairing method of the accommodating structure of the semiconductor device of the present invention. As shown in FIG. 7 , the repairing method of the accommodating structure of the semiconductor device of the present invention is described as follows: Step S21 : respectively forming the first transistor 41A and the second transistor 42A on the substrate 10 , and the first hole H12 is located in the first Between the transistor 41A and the second transistor 42A, the first transistor 41A and the second transistor 42A are disposed opposite to each other. The first transistor 41A and the second transistor 42A are disposed in the same film layer.

Step S22 : forming the first electrode 21A on the first transistor 41A, the first electrode 21A extending from the surface of the first transistor 41A to the junction of the first transistor 41A and the substrate 10 .

Step S23: disposing the initial semiconductor element OSD in the first hole H12, forming a second electrode 22A on the second transistor 42A, and the first electrode 21A and the second electrode 22A electrically contact the positive and negative electrodes of the initial semiconductor element OSD, respectively. Wherein, the first electrode 21A and the second electrode 22A are disposed in the same film layer.

Step S24: if it is detected that the initial semiconductor OSD is abnormal, the initial semiconductor element OSD is peeled off.

Step S25 : forming a third electrode 30A on the first electrode 21A and the second electrode 22A, the third electrode 30A is annular and has a second hole (as shown in FIG. 4 ), and the second hole exposes the first hole H12 .

Step S26: Re-adhere the normal semiconductor element SD on the third electrode 30A.

Step S27: Cutting the third electrode 30A to divide it into a first conductive area 31A and a second conductive area 32A, the first conductive area 31A corresponds to the first electrode 21A and partially covers the first electrode 21A, and the second conductive area 32A corresponds to the first conductive area 31A. The two electrodes 22A partially cover the second electrodes 22A.

Based on the above, the carrier structure of the semiconductor device and the method for forming the same of the present invention utilize the annular arrangement of the third electrode 30 , so that the present invention can tolerate the increase of the rotational deviation of the semiconductor device SD and improve the process yield.

The above description is exemplary only, not limiting. Any equivalent modifications or changes that do not depart from the spirit and scope of the present invention shall be included in the appended patent application scope.

10A: The first substrate

21: The first electrode

22: Second electrode

30: Third electrode

41: The first transistor

42: The second transistor

BS: Bearing Structure for Semiconductor Components

H1: The first hole

SD: Semiconductor Components

Claims (20)

A carrier structure for a semiconductor element, comprising: a first substrate; a first electrode disposed on the first substrate; a second electrode disposed on the first substrate, the first electrode and the second electrode Oppositely arranged, the polarities of the first electrode and the second electrode are different; a first hole is arranged between the first electrode and the second electrode; a third electrode is arranged between the first electrode and the second electrode On the two electrodes, the third electrode is annular and has a second hole, and the second hole exposes the first hole; and a semiconductor element is disposed on the third electrode. The semiconductor device carrier structure of claim 1, further comprising a transistor layer disposed on the first substrate, the transistor layer comprising a first transistor and a second transistor, the first transistor The second transistor is arranged between the first substrate and the first electrode, and the second transistor is arranged between the first substrate and the second electrode. The carrier structure for a semiconductor device according to claim 1, wherein the third electrode has a first conductive region and a second conductive region, the first conductive region corresponds to the first electrode and partially covers the first electrode, and the first conductive region Two conductive regions correspond to the second electrode and partially cover the second electrode, and the first conductive region and the second conductive region are electrically connected to the semiconductor element. The carrier structure for a semiconductor device as claimed in claim 1, wherein the first electrode and the second electrode are disposed on the same film layer. The carrier structure for a semiconductor element as claimed in claim 1, wherein the rotation range of the semiconductor element with the second hole as the center is -108 degrees to 108 degrees. The semiconductor device carrier structure according to claim 1, wherein the cross-sectional shape of the third electrode is a circle or a polygon. A display panel, comprising: a first area including a semiconductor element carrying structure as claimed in claim 1 to claim 6; and a second area including a semiconductor element accommodating structure, the semiconductor element The accommodating structure includes: a second substrate; a fourth electrode arranged on the second substrate; a fifth electrode arranged on the second substrate, the fourth electrode and the fifth electrode are oppositely arranged; A third hole, the third hole is disposed between the fourth electrode and the fifth electrode; and an initial semiconductor element is disposed in the third hole. The display panel of claim 7, wherein the accommodating structure of the semiconductor element includes a third transistor and a fourth transistor, and the third transistor and the fourth transistor are disposed on the second substrate, The third transistor is arranged between the second substrate and the fourth electrode, and the fourth transistor is arranged between the second substrate and the fifth electrode. The display panel according to claim 8, wherein the fourth electrode and the fifth electrode are arranged in the same film layer, and the third transistor and the fourth transistor are arranged in the same layer film layer. A method for forming a carrier structure for a semiconductor element, comprising: respectively forming a first electrode and a second electrode on a substrate, the first electrode and the second electrode are oppositely arranged, the first electrode and the second electrode There is a first hole therebetween; a third electrode is formed on the first electrode and the second electrode, the third electrode is annular and has a second hole, and the second hole exposes the first hole; and A semiconductor element is adhered on the third electrode. According to the method for forming a carrier structure of a semiconductor device according to claim 10, before the step of forming the first electrode and the second electrode respectively, a transistor layer is formed on the substrate, and the transistor layer includes a first electrode A transistor and a second transistor, the first transistor is arranged between the substrate and the first electrode, and the second transistor is arranged between the substrate and the second electrode. According to the method for forming a carrier structure for a semiconductor element as claimed in claim 10, after the semiconductor element is adhered, the third electrode is cut to divide it into a first conductive area and a second conductive area, the first conductive area The second conductive region corresponds to the first electrode and partially covers the first electrode, and the second conductive region corresponds to the second electrode and partially covers the second electrode. The method for forming a semiconductor device carrier structure according to claim 10, wherein the first electrode and the second electrode are in the same film layer. The method for forming a carrier structure for a semiconductor device according to claim 10, wherein the rotation range of the semiconductor device with the second hole as the center is -108 degrees to 108 degrees. According to the method for forming a carrier structure for a semiconductor element as described in claim 10, if it is detected that the semiconductor element is abnormal, the semiconductor element is peeled off and the normal semiconductor element is re-attached on the third electrode. A method for repairing an accommodating structure of a semiconductor element, comprising: respectively forming a first electrode and a second electrode on a substrate, the first electrode and the second electrode are oppositely arranged, the first electrode and the second electrode There is a first hole between the electrodes; an initial semiconductor element is arranged in the first hole; if it is detected that the initial semiconductor is abnormal, the initial semiconductor element is peeled off; a third electrode is formed on the first electrode and the second electrode On the top, the third electrode is annular and has a second hole, the second hole exposes the first hole; and a semiconductor element is adhered on the third electrode. According to the repairing method of the accommodating structure of a semiconductor element as claimed in claim 16, before the step of forming the first electrode and the second electrode respectively, a first transistor and a second transistor are formed on the substrate, The first transistor is arranged between the substrate and the first electrode, and the second transistor is arranged between the substrate and the second electrode. The method for repairing the accommodating structure of a semiconductor element as claimed in claim 17, wherein the first electrode and the second electrode are arranged in the same film layer, and the first transistor and the second transistor are arranged in the same film layer. According to the repairing method of the accommodating structure of the semiconductor element according to claim 16, after the semiconductor element is adhered, the third electrode is cut to divide it into a first conductor An electrical area and a second conductive area, the first conductive area corresponds to the first electrode and partially covers the first electrode, and the second conductive area corresponds to the second electrode and partially covers the second electrode. The method for repairing the accommodating structure of a semiconductor element as claimed in claim 16, wherein the rotation range of the semiconductor element with the second hole as the center is -108 degrees to 108 degrees.

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