TWI748613B - Switch - Google Patents

Abstract

A switch is provided. The switch includes a plurality of absorb queues, a plurality of egress ports and an absorb scheduler. Each of the egress ports has a plurality of egress queues, and each of the egress queues is connected to a different one of the absorb queues. The switch generates an urgency for each of the egress queues of each of the egress ports, the urgency is used to reflect the degree that the corresponding egress queue is about no packet to send soon, and the urgency of the absorb queue could be retrieved from the urgency of each of the connected egress queues. The absorb scheduler selects one of the absorb queues to send its stored packet to target egress queues of target egress ports according to the urgency of each of the absorb queues.

Description

switch

The invention relates to a scheduling method, and in particular to a scheduling method of an exchange.

When the switch forwards packets, in order to distinguish the transmission sequence of different data streams, the egress port has multiple egress queues. Each egress queue is used to store packets of different priority levels, and is assigned different egress queue weights to determine the transmission ratio of packets of different priority levels. In other words, the egress port can use the scheduler to determine which egress queue to choose to send packets, and according to the egress queue weight, decide how many packets to grab from the selected egress queue for transmission.

As shown in Figure 1, the egress port P0 has two egress queues Q0 and Q1 to store packets with priority S1 and S2 respectively, and when the egress queues Q0 and Q1 of the egress port P0 have the weights of the egress queues respectively 1 and 2, ie {Q0:Q1}=1:2, the scheduler 10 of the exit port P0 decides to grab the one with priority S1 from the exit queue Q0 of the exit port P0 based on the above-mentioned exit queue weight The packet is sent, and it is decided to grab the two packets with priority S2 from the egress queue Q1 of the egress port P0 for transmission. If the scheduler of the egress port wants to grab a packet from the selected egress queue, but when there is no packet to send in the selected egress queue, the scheduler will grab the packet in the next egress queue for transmission , So that the weight of the export queue is out of balance.

In addition, forwarding packets can be divided into Unicast, Multicast and Broadcast. Unicast means that a packet can only be sent to a single egress queue and a single egress port, while multicast and broadcast It means that a packet can be sent to multiple egress queues and multiple egress ports. In high-bandwidth switches, in order to save memory space for storing and forwarding packets, a central memory architecture is generally adopted for common use by all egress queues. However, this architecture is limited by the bandwidth capability of the memory. Therefore, for multicast/broadcast packets, the switch takes multiple times to send the multicast/broadcast packets to multiple egress queues of multiple egress ports to which it needs to go. In order to make up for this part of the operational inefficiency, the switch is designed to store multicast/broadcast packets in the central buffer memory (Central Absorb Memory). At the same time, in response to the export queue weight of the export queue, the central buffer memory can be Configured with multiple buffer queues (Absorb Queue) and buffer schedulers.

Each buffer queue is also used to store packets of different priorities, and different buffer queue weights are assigned to determine the transmission ratio of packets of different priorities. Generally speaking, there will be a corresponding relationship between the cache queue and the egress queue, so that packets can be sent from the cache queue to the corresponding egress queue, and the cache scheduler sends the packets in the cache queue according to the weight of the cache queue Go to the exit queue of the exit port you need to go to. As shown in Figure 2, the cache queue AQ0 is connected to the egress queue Q0 of the egress ports P0, P1 and P2, and the cache queue AQ1 is connected to the egress queue Q1 of the egress ports P0, P1 and P2. The buffer queue AQ0 stores two packets. The first packet is sent to the egress queue Q0 of the egress ports P0 and P1, and the second packet is sent to the egress queue Q0 of the egress ports P0 and P2. In addition, the buffer queue AQ1 also stores two packets, but these two packets must be sent to the egress queue Q1 of the egress ports P0, P1, and P2. For the convenience of the following description, FIG. 2 has shown the storage appearance of these packets in the buffer queues AQ0 and AQ1 after being sent to the exit queue of the desired exit port through the buffer scheduler 13.

In order not to affect the egress queue weight of the egress queue, the cache scheduler 13 may configure appropriate cache queue weights for the cache queues AQ0 and AQ1. As shown in Figure 3A, when the cache queues AQ0 and AQ1 store packets to be sent to the egress port P0, and the egress queue weights of the egress queues Q0 and Q1 of the egress port P0 are 1 and 8, respectively, the cache scheduler 13. The cache queue weights of the configurable cache queues AQ0 and AQ1 are 1 and 8, respectively, that is, {AQ0:AQ1}=1:8. Similarly, as shown in Figure 3B, when the cache queues AQ0 and AQ1 store packets to be sent to the egress port P1, and the egress queue weights of the egress queues Q0 and Q1 of the egress port P1 are 8 and 1, respectively, the cache The scheduler 13 can configure the cache queue weights of the cache queues AQ0 and AQ1 to be 8 and 1, respectively, that is, {AQ0:AQ1}=8:1.

In addition, as shown in Figure 3C, when the buffer queues AQ0 and AQ1 store packets to be sent to the egress ports P1 and P2, and the egress queue weights of the egress queues Q0 and Q1 of the egress port P2 are 4 and 1, respectively, The cache scheduler 13 will take the average of the egress queue weight of the egress queue Q0 of the egress port P1 and the egress queue weight of the egress queue Q0 of the egress port P2 as the cache queue weight of the cache queue AQ0, and Take the average of the egress queue weight of the egress queue Q1 of the egress port P1 and the egress queue weight of the egress queue Q1 of the egress port P2 as the cache queue weight of the cache queue AQ1, namely {AQ0:AQ1}={ (8+4)/2: (1+1)/2}=6:1. In other words, when the target of the cache scheduler 13 is multiple egress ports, and the egress queue weights configured for these egress ports are the same, the cache queue weights of the cache queues AQ0 and AQ1 can be easily configured Basically, but when the egress queue weights configured for multiple egress ports served by the cache scheduler 13 are very different, the cache scheduler 13 will not be able to configure a suitable cache queue weight.

As shown in Figure 3D, because {Q0:Q1} of outlet port P0 and {Q0:Q1} of outlet port P1 are averaged 1:1, that is, {AQ0:AQ1}={(1+8)/2:( 8+1)/2}=1:1, so the buffer queues AQ0 and AQ1 store the packets to be sent to the egress ports P0 and P1 at a ratio of 1:1, but the scheduler 10 of the egress port P0 is It is expected to send out the packets of the egress queue Q0 and Q1 of the egress port P0 with a ratio of 1:8, so that the packets of the egress queue Q1 of the egress port P0 will be sent faster, and the egress queue Q1 of the egress port P0 is likely to be empty. If there is no packet to send, and once the egress queue is empty, the weight of the egress queue will be unbalanced. Therefore, how to design a switch scheduling method to avoid the imbalance of the export queue weight has become an important issue in this field.

In view of this, an embodiment of the present invention provides a scheduling method for forwarding packets, which is used in a switch that includes multiple cache queues, multiple egress ports, and a cache scheduler. Each egress port has multiple egress queues, each egress queue of each egress port is connected to a different one of these cache queues, and the scheduling method includes the following steps. First, an urgency is generated for each egress queue of each egress port, and the urgency is used to reflect the degree to which the corresponding egress queue is about to be out of packets. Then, according to the urgency of each egress queue, the cache scheduler selects one of these cache queues to send the stored packets to the target egress queue of the desired egress port.

In addition, the embodiment of the present invention further provides a switch including a plurality of cache queues, a plurality of egress ports, and a cache scheduler. Each egress port has multiple egress queues, and each egress queue of each egress port is connected to a different one of these cache queues. The switch can generate an urgency for each egress queue of each egress port, and the urgency is used to reflect the degree to which the corresponding egress queue is about to be out of packets. The cache scheduler selects one of these cache queues according to the urgency of each egress queue to send the stored packets to the target egress queue of the desired egress port.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings about the present invention. However, the provided drawings are only for reference and description, and are not used to limit the present invention.

The following are specific specific examples to illustrate the implementation of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content provided in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be based on different viewpoints and applications, and various modifications and changes can be made without departing from the concept of the present invention. In addition, the drawings of the present invention are merely schematic illustrations, and are not drawn according to actual size, and are stated in advance. The following embodiments will further describe the related technical content of the present invention in detail, but the provided content is not intended to limit the protection scope of the present invention.

It should be understood that although terms such as “first”, “second”, and “third” may be used herein to describe various elements or signals, these elements or signals should not be limited by these terms. These terms are mainly used to distinguish one element from another, or one signal from another signal. In addition, the term "or" used in this text should include any one or a combination of more of the associated listed items depending on the actual situation.

Please refer to FIG. 4 and FIG. 5 at the same time. FIG. 4 is a flowchart of the steps of the scheduling method provided by an embodiment of the present invention, and FIG. 5 is a first schematic diagram of the switch provided by an embodiment of the present invention using the scheduling method of FIG. 4 . As shown in FIG. 5, the switch 5 may include multiple cache queues, multiple egress ports, and a cache scheduler 53. As mentioned earlier, each buffer queue is used to store packets of different priorities, each egress port has multiple egress queues, and each egress queue of each egress port is connected to a different one of these cache queues , So it is also used to store packets of different priorities.

For the convenience of the following description, FIG. 5 only takes two cache queues AQ0, AQ1 and three egress ports as an example, but the present invention is not limited thereto. Therefore, each egress port in Figure 5 has two egress queues Q0 and Q1, and the egress queues Q0 and Q1 of each egress port are respectively connected to the buffer queues AQ0 and AQ1 to store packets of different priorities. . In addition, the switch 5 can generate an urgency Q n _URG for each egress queue of each egress port. Taking FIG. 5 as an example, n is 0 or 1, and the urgency Q n _URG is used to reflect the degree to which the corresponding egress queue Q n is about to be out of packets.

In practice, each exit queue can be individually configured with high and low thresholds, namely the high threshold THR_HIGH and the low threshold THR_LOW. Then, the switch 5 can use the currently accumulated number of packets in each egress queue as its queue usage, and generate the urgency Q n _URG according to the comparison result of the number of packets and the two thresholds. For example, when the current accumulated number of packets in the egress queue Q0 of the egress port P1 is less than or equal to the low threshold THR_LOW, the switch 5 can generate an urgency Q0_URG of 1 for the egress queue Q0 of the egress port P1.

In addition, when the number of packets currently accumulated in the egress queue Q1 of the egress port P0 is greater than the low threshold THR_LOW and less than or equal to the high threshold THR_HIGH, the switch 5 can generate an urgency Q1_URG of 2 for the egress queue Q1 of the egress port P0. In contrast, when the number of packets currently accumulated in the egress queue Q0 of the egress port P0 is greater than the high threshold THR_HIGH, the switch 5 can generate an urgency Q0_URG of 3 for the egress queue Q0 of the egress port P0, but the present invention does not apply This is a limitation. In summary, in this embodiment, the urgency Q n _URG of each exit queue can be generated based on the comparison result of its queue usage and at least a threshold value, and this embodiment assumes that the lower the urgency Q n is, _URG represents the corresponding egress queue Q n, the sooner there will be no packets to be sent.

On the other hand, when the number of packets currently accumulated in each egress queue is the same, the faster the egress queue Q n with the faster flow rate, the sooner no packets will be sent. Therefore, in other embodiments, the urgency Q n _URG of each exit queue can also be generated based on the comparison result of its queue usage and flow rate. Anyway, as long as the queue usage is used to determine the urgency Q n _URG It can conform to the technical spirit of the present invention. Similarly, the switch 5 using the number of packets as the queue usage amount is just an example, and the present invention does not limit the specific implementation manner of the switch 5 in calculating the queue usage amount. In other embodiments, the switch 5 can also use Byte Count as the queue usage. Anyway, as long as the cache scheduler 53 schedules the cache queue according to the queue usage of each egress queue. It can conform to the technical spirit of the present invention. That is to say, according to the urgency Q n _URG of each egress queue, the cache scheduler 53 can select one of multiple cache queues to send the stored packets to the target egress queue of the target egress port to which it needs to go. .

In this embodiment, each egress queue can return the urgency Q n _URG to the connected cache queue AQ n . Then, according to the urgency Q n _URG of each connected egress queue, the switch 5 can determine a forwarding packet urgency AQ n _URG of each buffer queue, and the forwarding packet urgency AQ n _URG is used to reflect the corresponding cache The degree to which the queue AQ n urgently needs to send its stored packets. Taking Figure 5 as an example, the exit queue Q0 of the exit ports P0, P1, and P2 returns the urgency Q0_URG with values of 3, 1, and 3 to the connected buffer queue AQ0, and the switch 5 can select the emergency with the lowest value. The degree Q0_URG is used as the urgency degree AQ0_URG of the forwarded packet of the buffer queue AQ0, that is, AQ0_URG=1. It should be understood that, in order to reflect the degree to which the buffer queue AQ0 urgently needs to send packets, the switch 5 selects the lowest urgency Q0_URG as the forwarding packet urgency AQ0_URG of the buffer queue AQ0, but the present invention is not limited by this.

In the same way, the exit queue Q1 of the exit ports P0, P1, and P2 returns the urgency Q1_URG with values of 2, 3, and 3 to the connected cache queue AQ1, and the switch 5 can select the lowest urgency Q1_URG from among them. The urgency of forwarding packets in the buffer queue AQ1 is AQ1_URG, that is, AQ1_URG=2. Therefore, for the urgency of forwarding packets AQ0_URG of FIG. 5 is 1 and the urgency of forwarding packets AQ1_URG is 2, the buffer scheduler 53 will prioritize the scheduling of the buffer queue AQ0 to send the stored packets to the desired egress port. The exit queue of P m is Q0. Take Figure 5 as an example, m is 0, 1, or 2, anyway, it depends on which exit port the sent packet needs to go to. In other words, according to the urgency of forwarding packets AQ n _URG of each buffer queue, the buffer scheduler 53 can select the buffer queue that needs to send the packet most urgently for scheduling.

The present invention does not limit the specific implementation of the cache scheduler 53, and for the convenience of the following description, the cache scheduler 53 in the figure will mostly be represented by a frame between the cache queue and the exit queue. Further, each time a packet from the queue buffer queue AQ n Q n to the outlet, the outlet will allow Queue amount Q n queue changed and thus affecting the degree of urgency queues outlet of Q n Q n _URG, and also affect the cache forwards the packet queue AQ n the urgency of the AQ n _URG. Therefore, each exit queue will always return the urgency of Q n _URG to cache the connection queue AQ n, so that the cache queue AQ n packet forwarding the urgency of AQ n _URG also been updated, and when the cache schedule When the server 53 needs to schedule multiple buffer queues, the buffer scheduler 53 can use the most immediate forwarding packet urgency AQ n _URG as a selection basis.

It can be seen that, compared with the prior art, the cache scheduler 53 does not need to configure the cache queue weights for the cache queues AQ0 and AQ1, and does not need to schedule the cache queues AQ0 and AQ1 according to the cache queue weights. It is possible to schedule the cache queues AQ0 and AQ1 according to the queue usage of each egress queue. Therefore, as shown in FIG. 4, in step S410, the switch 5 can generate an urgency Q n _URG for each exit queue of each exit port, and the urgency Q n _URG is used to reflect the corresponding exit queue Q n There will be no packet delivery soon. Then, in step S430, according to the urgency Q n _URG of each egress queue, the cache scheduler 53 can select one of the multiple cache queues to send the stored packets to the destination of the desired egress port Export queue.

As mentioned above, because each egress queue can return the urgency Q n _URG to the connected cache queue AQ n , the method in FIG. 4 may further include step S420, but step S420 may also be omitted. In step S420, according to the urgency Q n _URG of each egress queue of the connection, the switch 5 can determine the urgency of forwarding packets AQ n _URG of each buffer queue, and the urgency of forwarding packets AQ n _URG is used to reflect the corresponding The extent to which the buffer queue AQ n urgently needs to send the stored packets. In contrast, in step S430, "according to the urgency Q n _URG of each egress queue, the cache scheduler 53 selects one of the multiple cache queues" can refer to the forwarding packet urgency AQ of each cache queue. n _URG, the buffer scheduler 53 selects the buffer queue that needs to send the packet most urgently. Since the details are as stated in the foregoing content, I will not repeat them here.

On the other hand, when the cache scheduler 53 selects one of the multiple cache queues, if the urgency of forwarding packets in these cache queues with more than two forwarded packets all reflects that the corresponding cache queues most urgently need to send the packet, The cache scheduler 53 selects one of these cache queues in a round robin or random manner. Taking Figure 6 as an example, n is changed to 0, 1, or 2. That is, each egress port has three egress queues Q0, Q1, and Q2, and the egress queues Q0, Q1, and Q2 of each egress port are connected to the cache queues AQ0, AQ1, and AQ2, respectively. Therefore, when the urgency of forwarding packets AQ0_URG and AQ1_URG are both 1, and the urgency of forwarding packets AQ2_URG is 2, the cache scheduler 53 should prioritize the scheduling of the cache queues AQ0 and AQ1. Conceptually, the cache scheduler 53 of FIG. 6 can schedule the cache queues AQ0 and AQ1 in turn, and only schedule the cache queues AQ0 or AQ1 each time to send a packet stored in it to the exit of the desired exit port P m Queue Q0 or Q1, but in fact, because the change of the urgency Q n _URG will affect the selection result of the cache scheduler 53, the cache scheduler 53 in FIG. 6 can also select the cache queue AQ0 in a random manner. Or AQ1 sends a packet stored in it to the exit queue Q0 or Q1 of the desired exit port P m.

From another point of view, if a single cache queue always sends the stored packets to a certain egress queue, it may starve other egress queues to the point that there are no packets to send, resulting in an imbalance in the weight of the egress queue. Taking Figure 6 as an example, the forwarding packet urgency levels AQ0_URG and AQ1_URG are determined according to the urgency level Q0_URG of the egress queue Q0 of the egress port P1 and the egress queue Q1 urgency Q1_URG of the egress port P0, respectively. Therefore, if the cache scheduler 53 preferentially schedules the cache queue AQ0 to send its stored packets to the egress queue Q0 of the egress port P1, and the egress queue Q0 of the egress port P1 has a larger weight, even absolute With Strict Priority (SP), the egress queue Q0 of the egress port P1 will always be scheduled by the scheduler 51 of the egress port P1, so that the urgency of forwarding packets AQ0_URG may always be 1. In addition, the cache scheduler 53 always schedules the cache queue AQ0, and has no opportunity to schedule the cache queue AQ1, so that the egress queue Q1 of the egress port P0 is prone to no packet transmission.

In addition, in this embodiment, the urgency Q n _URG of 1 means that the current accumulated number of packets in the corresponding egress queue Q n is less than or equal to the low threshold THR_LOW, and there are two situations that result in the accumulated packets in the egress queue Q n The number is less than or equal to the low threshold THR_LOW. The first situation is that the accumulated packets in the egress queue Q n are about to be delivered, so the buffer queue AQ n urgently needs to send the packets to the egress queue Q n , and the second situation is that no packets have been sent to the egress queue. Q n , so the cache scheduler 53 can postpone scheduling the cache queue AQ n . Taking Figure 7 as an example, each cache queue of the central cache memory 64 can also count the packets sent to each egress port, and determine the absence of each egress queue of each egress port based on the counting result Meaning state value P m Q n _EMP_STA.

For example, when the buffer queue AQ n counts the packets sent to the egress port P m , and the result of the count is equal to 0, this embodiment determines the meaningless state value of the egress queue Q n of the egress port P m P m Q n _EMP_STA is established (TRUE). Conversely, when the buffer queue AQ n counts the packets sent to the egress port P m , and the result of the count is not equal to 0, this embodiment determines the meaningless state value P of the egress queue Q n of the egress port P m m Q n _EMP_STA is not established (FALSE). In other words, the meaningless status value P m Q n _EMP_STA can be used to indicate whether no packets are sent to the egress queue Q n of the egress port P m . As shown in Figure 7, the buffer queue AQ0 will only send packets to the egress port P0 and P2, but not the egress port P1. Therefore, the meaningless state values P0Q0_EMP_STA and P2Q0_EMP_STA of the egress queue Q0 of the egress ports P0 and P2 are both FALSE, and the meaningless state value P1Q0_EMP_STA of the egress queue Q0 of the egress port P1 is TRUE.

In addition, each cache queue of FIG. 7 can be further configured with a logic circuit for receiving the meaningless state value P m Q n _EMP_STA of each egress queue of each egress port connected to the corresponding cache queue AQ n and the degree of urgency backhaul Q n _URG, to determine the cache queue AQ n the degree of urgency of the packet forwarding AQ n _URG, and the buffer queue AQ n the degree of urgency of the packet forwarding AQ n _URG conveyed to scheduler buffer 53. In this embodiment, each logic circuit uses the meaningless state value P m Q n _EMP_STA to pre-process the urgency Q n _URG of the egress queue Q n of the egress port P m to exclude the corresponding cache queue. The situation where the row AQ n never sends a packet to the egress queue Q n . That is to say, according to the meaningless state value P m Q n _EMP_STA, the logic circuit can adjust the urgency Q n _URG returned by the exit queue Q n of the exit port P m.

For example, when the meaningless state value P m Q n _EMP_STA is TRUE, the logic circuit can adjust the urgency Q n _URG of the exit queue Q n of the exit port P m to a special value, such as 4 to indicate the exit port P m exit queue buffer queue Q n AQ n need not service. As shown in FIG. 7, because the meaningless state value P1Q0_EMP_STA is TRUE, the logic circuit 65 can adjust the urgency Q0_URG of the exit queue Q0 of the exit port P1 from 1 to 4. In this way, the urgency Q0_URG returned by the exit queue Q0 of the exit ports P0 and P2 is 3 and 3 respectively, and the adjusted urgency Q0_URG of the exit queue Q0 of the exit port P1 is 4, and the logic circuit 65 can The lowest urgency Q0_URG is selected as the forwarding packet urgency AQ0_URG of the buffer queue AQ0, that is, AQ0_URG=3. Since the details are as stated in the foregoing content, I will not repeat them here.

On the other hand, it can be seen from the foregoing that the threshold will affect the corresponding value of the urgency Q n _URG, so in practice, the present invention can set the link speed (Link Speed), the current limit speed (Rate Limit), and the weight of the exit queue, And whether the exit queue is assigned SP and other factors as the basis for the configuration of the threshold. Taking Figure 8 as an example, although the connection speeds of the egress ports P0, P1, and P2 are all 1Gbps, the egress queue Q1 of the egress port P2 is given SP to be selected to transmit packets first, so the egress queue of the egress port P2 can be expected Q1 will not accumulate too many packets, so its threshold needs to be configured higher to allow the cache scheduler to more actively schedule packets to the egress queue Q1, such as the high threshold THR_HIGH and low of the egress queue Q1 of the egress port P2 Threshold value THR_LOW, to truly reflect the demand of SP queue.

In addition, when the outlet queue weights of the outlet queues Q0 and Q1 of the outlet port P0 are 1 and 8, respectively, the outlet queue Q1 of the outlet port P0 will be 8 times more likely than the outlet queue Q0 of the outlet port P0. Select the transmission packet. Then, in order to maintain the packet transmission ratio of 1:8, the switch 5 hopes that the egress queue Q1 of the egress port P0 will always accumulate packets to be sent out. Therefore, the packet demand of the egress queue Q1 of the egress port P0 is greater than the packet demand of the egress queue Q0 of the egress port P0, and the threshold of the egress queue Q1 of the egress port P0 can be configured to be higher than that of the egress queue of the egress port P0 The threshold of Q0 is high to allow the cache scheduler to more actively schedule packets to the egress queue Q1. All in all, the present invention does not limit the specific implementation manner of configuring the threshold.

In summary, the switch provided by the embodiment of the present invention does not need to configure the cache queue weight for the cache queue, and does not need to schedule the cache queue according to the cache queue weight, but can be based on each egress queue. The queue usage of the row is used to schedule the cache queue. Therefore, the present invention can meet the needs of different egress queues, and real-time services require a packaged egress queue, so that the weight of the egress queue will not be unbalanced, and the cache scheduler can operate more efficiently.

The content provided above is only the preferred and feasible embodiments of the present invention, and does not limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the description and schematic content of the present invention are included in the application of the present invention. Within the scope of the patent.

5: Switch P0, P1, P2: Outlet port Q0, Q1, Q2: Exit queue AQ0, AQ1, AQ2: cache queue 10,11,12,50,51,52: Scheduler for exit port 13,53: Cache Scheduler THR_HIGH, THR_LOW: threshold Q0_URG, Q1_URG, Q2_URG: Urgency AQ0_URG, AQ1_URG, AQ2_URG: urgency of forwarding packets S410~S430: Process steps 64: Central cache memory P0Q0_EMP_STA~P2Q0_EMP_STA: meaningless status value 65, 66, 67: logic circuit

Figure 1 is a schematic diagram of the egress port using the scheduler to determine how many packets are captured from the egress queue for transmission based on the egress queue weight.

Fig. 2 is a schematic diagram of the egress queue of packets in the cache queue that are sent to the egress port they need to go to through the existing cache scheduler.

3A to 3D are schematic diagrams of the existing cache scheduler configuring the cache queue weight for the cache queue.

Fig. 4 is a flowchart of the steps of a scheduling method provided by an embodiment of the present invention.

FIG. 5 is a first schematic diagram of a switch provided by an embodiment of the present invention using the scheduling method of FIG. 4.

FIG. 6 is a second schematic diagram of a switch provided by an embodiment of the present invention using the scheduling method of FIG. 4.

FIG. 7 is a third schematic diagram of a switch provided by an embodiment of the present invention using the scheduling method of FIG. 4.

FIG. 8 is a fourth schematic diagram of a switch provided by an embodiment of the present invention using the scheduling method of FIG. 4.

5: Switch

P0, P1, P2: Outlet port

Q0, Q1: Exit queue

AQ0, AQ1: cache queue

50, 51, 52: Scheduler of the exit port

53: Cache Scheduler

THR_HIGH, THR_LOW: threshold

Q0_URG, Q1_URG: Urgency

AQ0_URG, AQ1_URG: The urgency of forwarding packets

Claims (9)

A switch including: Multiple cache queues; A plurality of egress ports, each of the egress ports has a plurality of egress queues, each of the egress queues of each of the egress ports is connected to a different one of the cache queues, wherein the switch is for each of the Each of the exit queues of the exit ports generates a degree of urgency, and the degree of urgency is used to reflect the degree to which the corresponding exit queue is about to be out of packets; and A cache scheduler, according to the urgency of each of the egress queues, selects one of the cache queues to send the stored packet to the target egress queue of the target egress port to which it needs to go. The switch according to claim 1, wherein the urgency of each of the exit queues is generated based on the comparison result of the queue usage and at least a threshold. The switch according to claim 1, wherein the urgency of each of the exit queues is generated based on the comparison result of the queue usage and the flow rate. The switch according to claim 1, wherein each of the exit queues returns the urgency to the connected cache queue, and the switch is further used to: According to the urgency of each of the egress queues of the connection, determine the urgency of a forwarded packet for each of the cache queues, and the urgency of the forwarded packet is used to reflect that the corresponding cache queue urgently needs to be sent out for storage The extent of the packet. The switch according to claim 4, wherein the step of the cache scheduler selecting one of the cache queues according to the urgency of each of the exit queues includes: According to the urgency of the forwarded packet in each of the buffer queues, the buffer scheduler selects the buffer queue that needs to send the packet most urgently. The switch according to claim 5, wherein when the urgency of the forwarded packets with more than two packets in the cache queues reflects that the corresponding cache queues most urgently need to send the packet, the cache scheduler adopts Select one of the corresponding cache queues in a round-robin or random manner. The switch according to claim 5, wherein each of the buffer queues further counts the packets sent to each of the egress ports, and determines each of the egress ports according to the result of the counting. A meaningless status value for these exit queues. The switch according to claim 7, wherein the meaningless status value is used to indicate whether the packet is not sent to the egress queue of the corresponding egress port. The switch according to claim 8, wherein each of the cache queues is further configured with a logic circuit to adjust the urgency of the egress queue return of the corresponding egress port according to the meaningless state value.

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