TWI748333B - Interference cancelling circuit and associated interference cancelling method - Google Patents

Interference cancelling circuit and associated interference cancelling method Download PDF

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TWI748333B
TWI748333B TW109102111A TW109102111A TWI748333B TW I748333 B TWI748333 B TW I748333B TW 109102111 A TW109102111 A TW 109102111A TW 109102111 A TW109102111 A TW 109102111A TW I748333 B TWI748333 B TW I748333B
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signal
frequency
filter
circuit
generate
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TW109102111A
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TW202129633A (en
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謝志農
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瑞昱半導體股份有限公司
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Priority to US17/146,500 priority patent/US11303313B2/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
    • H04B1/1018—Means associated with receiver for limiting or suppressing noise or interference noise filters connected between the power supply and the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
    • H04B1/1027—Means associated with receiver for limiting or suppressing noise or interference assessing signal quality or detecting noise/interference for the received signal
    • H04B1/1036—Means associated with receiver for limiting or suppressing noise or interference assessing signal quality or detecting noise/interference for the received signal with automatic suppression of narrow band noise or interference, e.g. by using tuneable notch filters

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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Noise Elimination (AREA)

Abstract

The present invention discloses an interference cancelling circuit comprising a PAPR detection circuit, a control circuit and a filter. In the operations of the interference cancelling circuit, the PAPR detection circuit is configured to detect a PAPR in a spectrum of a signal in a real-time manner to generate a detection result. The control circuit is configured to generate a control signal according to the detection result. The filter determines a filtering frequency according to the control signal, and the filter filters the signal to generate an output signal.

Description

干擾消除電路及相關的干擾消除方法 Interference elimination circuit and related interference elimination method

本發明係有關於干擾消除電路，尤指一種應用於無線通訊中的單頻干擾消除電路。 The present invention relates to interference cancellation circuits, especially a single-frequency interference cancellation circuit used in wireless communications.

在應用在無線通訊的接收電路中，通常會設有干擾消除電路以消除或抑制接收訊號中的干擾。然而，若是在頻域作干擾的偵測及消除，由於需要利用多個區塊的偵測結果來做判斷，因此若是干擾發生改變時(例如，干擾頻率或強度發生改變)，則通常無法即時地消除這些改變後的干擾訊號。特別是，在某些情況下若是接收訊號帶有頻率會快速移動的單頻干擾時，無法即時地消除改變後干擾訊號的問題會更加嚴重。 In the receiving circuit used in wireless communication, an interference cancellation circuit is usually provided to eliminate or suppress the interference in the received signal. However, if the interference is detected and eliminated in the frequency domain, it is necessary to use the detection results of multiple blocks to make judgments. Therefore, if the interference changes (for example, the interference frequency or intensity changes), it is usually not real-time To eliminate these altered interference signals. In particular, in some cases, if the received signal has single-frequency interference with a fast-moving frequency, the problem of not being able to immediately eliminate the interference signal after the change will be more serious.

因此，本發明的目的之一在於提出一種干擾消除電路，其可以快速有效地偵測並消除單頻干擾，以解決先前技術中所述的問題。 Therefore, one of the objectives of the present invention is to provide an interference cancellation circuit that can quickly and effectively detect and eliminate single-frequency interference to solve the problems described in the prior art.

在本發明的一個實施例中，揭露了一種干擾消除電路，其包含有一峰值對均值功率比偵測電路、一控制電路以及一濾波器。在該干擾消除電路的 操作中，該峰值對均值功率比偵測電路用以即時地偵測一訊號在頻譜上之一峰值對均值功率比，以產生一偵測結果；該控制電路用以根據該偵測結果來產生一控制訊號；以及該濾波器用以根據該控制訊號來決定該濾波器的一過濾頻點，並對該訊號進行濾波以產生一輸出訊號。 In an embodiment of the present invention, an interference cancellation circuit is disclosed, which includes a peak-to-average power ratio detection circuit, a control circuit, and a filter. In the interference cancellation circuit In operation, the peak-to-average power ratio detection circuit is used to detect the peak-to-average power ratio of a signal in the spectrum in real time to generate a detection result; the control circuit is used to generate a detection result based on the detection result A control signal; and the filter is used to determine a filtering frequency point of the filter according to the control signal, and filter the signal to generate an output signal.

在本發明的另一個實施例中，揭露了一種干擾消除方法，其包含有以下步驟：即時地偵測一訊號在頻譜上之一峰值對均值功率比，以產生一偵測結果；根據該偵測結果來產生一控制訊號；以及根據該控制訊號來決定一濾波器的一過濾頻點，並對該訊號進行濾波以產生一輸出訊號。 In another embodiment of the present invention, an interference cancellation method is disclosed, which includes the following steps: real-time detection of a signal's peak-to-average power ratio on the spectrum to generate a detection result; The measurement result is used to generate a control signal; and a filtering frequency point of a filter is determined according to the control signal, and the signal is filtered to generate an output signal.

100:電路 100: Circuit

102:天線 102: Antenna

110:類比數位轉換器 110: Analog-to-digital converter

120:混波器 120: mixer

130:時序回復電路 130: timing recovery circuit

140:濾波器 140: filter

150:干擾消除電路 150: interference cancellation circuit

152:緩衝器 152: Buffer

154:快速傅立葉轉換電路 154: Fast Fourier Transformation Circuit

156:PAPR偵測電路 156: PAPR detection circuit

158:控制電路 158: control circuit

159:濾波器 159: filter

200~216:步驟 200~216: steps

410:第一複數乘法器 410: The first complex multiplier

420:濾波電路 420: filter circuit

430:第二複數乘法器 430: second complex multiplier

600~606:步驟 600~606: steps

Vin:類比輸入訊號 Vin: analog input signal

Din:數位輸入訊號 Din: Digital input signal

Din’:混波後訊號 Din’: Signal after mixing

Din”:訊號 Din": Signal

P_info:偵測結果 P_info: detection result

Vc:控制訊號 Vc: control signal

Dout:輸出訊號 Dout: output signal

第1圖為根據本發明一實施例之電路的示意圖。 Figure 1 is a schematic diagram of a circuit according to an embodiment of the invention.

第2圖為根據本發明一實施例之控制電路之確認機制的流程圖。 Figure 2 is a flow chart of the confirmation mechanism of the control circuit according to an embodiment of the present invention.

第3圖為濾波器的頻率響應以及包含單頻干擾的訊號內容的示意圖。 Figure 3 is a schematic diagram of the frequency response of the filter and the signal content including single-frequency interference.

第4圖為之本發明一實施例之濾波器的示意圖。 Figure 4 is a schematic diagram of a filter according to an embodiment of the present invention.

第5圖為第4圖所示之濾波器的頻率響應以及包含單頻干擾的訊號內容的示意圖。 Figure 5 is a schematic diagram of the frequency response of the filter shown in Figure 4 and the signal content including single-frequency interference.

第6圖為根據本發明一實施例之一種干擾消除方法的流程圖。 Fig. 6 is a flowchart of an interference cancellation method according to an embodiment of the present invention.

第1圖為根據本發明一實施例之電路100的示意圖。如第1圖所示，電路100包含了一天線102、一類比數位轉換器110、一混波器120、一時序回復電路130、一濾波器140以及一干擾消除電路150，其中干擾消除電路150包含了一 緩衝器152、一快速傅立葉轉換電路154、一峰值對均值功率比(Peak-to-Average Power Ratio，PAPR)偵測電路156、一控制電路158以及一濾波器159。在本實施例中，電路100係可以應用在一解調器(demodulator)中，例如設置在電視或是機上盒內的解調器中。 FIG. 1 is a schematic diagram of a circuit 100 according to an embodiment of the invention. As shown in Figure 1, the circuit 100 includes an antenna 102, an analog-to-digital converter 110, a mixer 120, a timing recovery circuit 130, a filter 140, and an interference cancellation circuit 150, wherein the interference cancellation circuit 150 Contains a The buffer 152, a fast Fourier transform circuit 154, a peak-to-average power ratio (PAPR) detection circuit 156, a control circuit 158, and a filter 159. In this embodiment, the circuit 100 can be used in a demodulator, such as a demodulator installed in a TV or a set-top box.

在電路100的操作中，首先，類比數位轉換器110自天線102接收一類比輸入訊號Vin，並對類比輸入訊號Vin進行類比數位轉換操作以產生一數位輸入訊號Din，而混波器120接著對數位輸入訊號進行混波操作(降頻操作)以產生一混波後訊號Din’。時序回復電路130對混波後訊號Din’進行內插補點操作以產生一補點後訊號，且濾波器140在本實施例中可以是一平方根升餘弦(Square Root Raised Cosine，SRRC)濾波器，以對該補點後訊號進行濾波操作以產生一訊號Din”。需注意的是，由於類比數位轉換器110、混波器120、時序回復電路130以及濾波器140等前端電路的操作已為本領域具有通常知識者所熟知，且本發明的重點在於後續的干擾消除電路150，因此上述元件的操作細節在此不贅述。 In the operation of the circuit 100, first, the analog-to-digital converter 110 receives an analog input signal Vin from the antenna 102, and performs an analog-to-digital conversion operation on the analog input signal Vin to generate a digital input signal Din, and the mixer 120 then The digital input signal undergoes a mixing operation (down-frequency operation) to generate a mixed signal Din'. The timing recovery circuit 130 performs an interpolation point operation on the mixed signal Din' to generate a post-compensation signal, and the filter 140 in this embodiment may be a Square Root Raised Cosine (SRRC) filter , To perform a filtering operation on the signal after the complement point to generate a signal Din". It should be noted that the operation of the front-end circuits such as the analog-to-digital converter 110, the mixer 120, the timing recovery circuit 130, and the filter 140 has been It is well known by those with ordinary knowledge in the art, and the focus of the present invention is the subsequent interference cancellation circuit 150, so the operation details of the above-mentioned components will not be repeated here.

在干擾消除電路150的操作中，緩衝器152會依序接收來自濾波器140的訊號Din”並暫存在其中，且等到緩衝器152所儲存的資料量達到快速傅立葉轉換電路154所能處理的一區塊時，快速傅立葉轉換電路154會對該區塊進行快速傅立葉轉換操作，以得到該區塊的頻譜狀態。接著，PAPR偵測電路156根據該區塊的頻譜狀態以計算出一峰值對均值功率比(PAPR)，並據以產生一偵測結果P_info。在一實施例中，偵測結果P_info係包含了在該區塊之PAPR高於一臨界值時之一峰值的位置(亦即，該峰值所對應到的頻率)，詳細來說，若是該區塊的PAPR低於該臨界值，則偵測結果P_info便指出該區塊不具有單頻干擾；而若是該區塊的PAPR高於該臨界值，則偵測結果P_info便指出該區塊具有單頻干擾並 提供該區塊之峰值的位置。 During the operation of the interference cancellation circuit 150, the buffer 152 sequentially receives the signal Din" from the filter 140 and temporarily stores it in it, and waits until the amount of data stored in the buffer 152 reaches a level that can be processed by the fast Fourier transform circuit 154. During the block, the fast Fourier transform circuit 154 will perform the fast Fourier transform operation on the block to obtain the spectrum state of the block. Then, the PAPR detection circuit 156 calculates a peak-to-average value according to the spectrum state of the block Power ratio (PAPR), and generate a detection result P_info accordingly. In one embodiment, the detection result P_info includes the position of a peak when the PAPR of the block is higher than a threshold value (that is, The frequency corresponding to the peak). In detail, if the PAPR of the block is lower than the critical value, the detection result P_info indicates that the block does not have single-frequency interference; and if the PAPR of the block is higher than the threshold This threshold, the detection result P_info indicates that the block has single-frequency interference and Provide the peak position of the block.

在接收到偵測結果P_info之後，控制電路158便可以根據偵測結果P_info來決定是否需要產生一控制訊號Vc以調整濾波器159的過濾頻點。具體來說，若是偵測結果P_info指出該區塊不具有單頻干擾，則控制電路158可以產生控制訊號Vc以使得濾波器159不會濾除來自緩衝器之該區塊的實質有效內容；若是偵測結果P_info指出該區塊具有單頻干擾，且所提供該區塊之峰值的位置相同於目前濾波器之過濾頻點，則控制電路158可不需要產生控制訊號Vc來改變濾波器159的過濾頻點、或是控制電路158產生相同的控制訊號Vc並維持濾波器159目前的過濾頻點；若是偵測結果P_info指出該區塊具有單頻干擾，且所提供該區塊之峰值的位置不同於目前濾波器之過濾頻點，則控制電路158產生控制訊號Vc來改變/調整濾波器159的過濾頻點。 After receiving the detection result P_info, the control circuit 158 can determine whether a control signal Vc needs to be generated to adjust the filtering frequency of the filter 159 according to the detection result P_info. Specifically, if the detection result P_info indicates that the block does not have single-frequency interference, the control circuit 158 can generate a control signal Vc so that the filter 159 will not filter out the substantial effective content of the block from the buffer; if it is The detection result P_info indicates that the block has single-frequency interference, and the position of the peak value of the block provided is the same as the filtering frequency point of the current filter, so the control circuit 158 does not need to generate the control signal Vc to change the filtering of the filter 159 Frequency, or the control circuit 158 generates the same control signal Vc and maintains the current filtering frequency of the filter 159; if the detection result P_info indicates that the block has single-frequency interference, and the position of the peak value of the block provided is different At the filtering frequency point of the current filter, the control circuit 158 generates a control signal Vc to change/adjust the filtering frequency point of the filter 159.

在一實施例中，為了避免PAPR偵測電路156在偵測上的偶發錯誤而導致濾波器159的過濾頻點被不適當的改變，控制電路158可以具有一確認機制以避免上述狀況。具體來說，控制電路158可以持續接收對應到多個連續區塊的偵測結果P_info，且當該多個連續區塊的偵測結果都指出具有單頻干擾以及相同/鄰近的峰值位置時，才會產生控制訊號Vc來改變濾波器159的過濾頻點。舉例來說，參考第2圖所示之控制電路158之確認機制的流程圖，在步驟200中，流程開始。在步驟202中，將一參數SUM設為零。在步驟204中，控制電路158接收來自PAPR偵測電路156所產生的偵測結果P_info，在此係假設偵測結果P_info指出該區塊具有單頻干擾並提供該區塊之峰值的位置。在步驟206中，控制電路158接收來自PAPR偵測電路156所產生的下一筆偵測結果P_info。在步驟208，控制電路158判斷在步驟206中所接收到的偵測結果P_info是否具有單頻干擾，若是， 流程進入步驟210；若否，流程回到步驟202。在步驟210，控制電路158判斷偵測結果P_info所包含之區塊的峰值位置fp與前一個偵測結果P_info所包含之前一個區塊的峰值位置fp_p之間的差距是否在一預設範圍之內，例如該預設範圍可以是5kHz，若是，流程進入步驟212；若否，流程回到步驟202。在步驟212中，控制電路158將參數SUM加上“1”。在步驟214中，控制電路158判斷參數SUM是否到達一臨界值TH，若是，流程進入步驟216；若否，流程回到步驟206。在步驟216，控制電路158根據上述偵測結果P_info所包含之區塊的峰值位置，例如可以根據最後一次所接收到之偵測結果P_info所包含之區塊的峰值位置、或是根據所接收到之多個偵測結果P_info所包含之區塊的峰值位置中的至少其一，來產生控制訊號Vc以調整濾波器159的過濾頻點。 In one embodiment, in order to avoid accidental errors of the PAPR detection circuit 156 in detection, the filter frequency of the filter 159 may be inappropriately changed, the control circuit 158 may have a confirmation mechanism to avoid the above situation. Specifically, the control circuit 158 can continuously receive the detection results P_info corresponding to multiple consecutive blocks, and when the detection results of the multiple consecutive blocks all indicate that there is single-frequency interference and the same/adjacent peak position, Only then can the control signal Vc be generated to change the filtering frequency point of the filter 159. For example, referring to the flowchart of the confirmation mechanism of the control circuit 158 shown in FIG. 2, in step 200, the process starts. In step 202, a parameter SUM is set to zero. In step 204, the control circuit 158 receives the detection result P_info generated by the PAPR detection circuit 156. Here, it is assumed that the detection result P_info indicates that the block has single-frequency interference and provides the peak position of the block. In step 206, the control circuit 158 receives the next detection result P_info generated by the PAPR detection circuit 156. In step 208, the control circuit 158 determines whether the detection result P_info received in step 206 has single-frequency interference, and if so, The process proceeds to step 210; if not, the process returns to step 202. In step 210, the control circuit 158 determines whether the difference between the peak position fp of the block included in the detection result P_info and the peak position fp_p of the previous block included in the previous detection result P_info is within a preset range For example, the preset range may be 5kHz, if yes, the process goes to step 212; if not, the process returns to step 202. In step 212, the control circuit 158 adds "1" to the parameter SUM. In step 214, the control circuit 158 determines whether the parameter SUM has reached a threshold value TH, if so, the process proceeds to step 216; if not, the process returns to step 206. In step 216, the control circuit 158 is based on the peak position of the block included in the detection result P_info, for example, based on the peak position of the block included in the detection result P_info received last time, or based on the At least one of the peak positions of the blocks included in the plurality of detection results P_info is used to generate the control signal Vc to adjust the filtering frequency of the filter 159.

關於濾波器159的操作，濾波器159可以是一個無限脈衝響應(Infinite Impulse Response，IIR)帶拒濾波器，且濾波器159可以具有多組可選擇的接頭係數(tap coefficient)，而控制電路158可以產生控制訊號Vc來控制濾波器159採用不同的接頭係數以具有不同的過濾頻點，以濾除訊號Din”中所帶有單頻干擾。參考第3圖所繪示之濾波器159的頻率響應以及訊號Din”之包含單頻干擾的訊號內容的示意圖，透過將濾波器159的過濾頻點移至訊號Din”的峰值位置fp，濾波器159可以有效地將Din”中的單頻干擾消除以產生乾淨的輸出訊號Dout。 Regarding the operation of the filter 159, the filter 159 may be an Infinite Impulse Response (IIR) band rejection filter, and the filter 159 may have multiple sets of selectable tap coefficients, and the control circuit 158 The control signal Vc can be generated to control the filter 159 to adopt different joint coefficients to have different filtering frequency points to filter out the single-frequency interference contained in the signal Din". Refer to the frequency of the filter 159 shown in Figure 3 The response and the schematic diagram of the signal content of the signal Din" including single-frequency interference. By moving the filtering frequency point of the filter 159 to the peak position fp of the signal Din", the filter 159 can effectively eliminate the single-frequency interference in Din" To produce a clean output signal Dout.

然而，雖然濾波器159的過濾頻點可以透過改變接頭係數來完成，但其整體速度並不快，且在單頻干擾的頻率變化較快時可能會影響到單頻干擾消除的效果。因此，在另一實施例中，濾波器159內可以另外具有兩個複數乘法器，並透過改變Din”之頻率的方式來完成單頻干擾消除的效果。具體來說，參考第4圖所示之本發明一實施例之濾波器159的示意圖以及第5圖所示之濾波電路420 的頻率響應以及訊號Din”之包含單頻干擾的訊號內容的示意圖，其中濾波器159包含了一第一複數乘法器410、一濾波電路420以及一第二複數乘法器430，且濾波電路420的過濾頻點不會因為偵測結果而改變，例如濾波電路420具有固定的過濾頻點fc。在第4圖所示之濾波器159的操作中，控制電路158或是濾波器159根據濾波電路420之頻點fc以及訊號Din”的峰值位置fp的差距fd以決定出複數乘法器410的一乘數ej2 π fdt，亦即第一複數乘法器410係用來將訊號Din”的頻率右移fd以使得訊號Din”的峰值位置fp對齊濾波電路420之頻點fc，並據以產生一移頻後訊號；接著，濾波電路420便對該移頻後訊號進行濾波操作以將訊號Din”之單頻干擾移除，以產生一濾波後訊號；最後，第二複數乘法器430使用乘數e-j2 π fdt以將訊號Din”的頻率左移fd以使得訊號Din”回到原有的頻帶以產生輸出訊號Dout。 However, although the filtering frequency of the filter 159 can be accomplished by changing the joint coefficients, the overall speed is not fast, and when the frequency of single-frequency interference changes rapidly, it may affect the effect of single-frequency interference elimination. Therefore, in another embodiment, the filter 159 may additionally have two complex multipliers, and the single-frequency interference cancellation effect can be achieved by changing the frequency of Din". Specifically, refer to Figure 4 The schematic diagram of the filter 159 of an embodiment of the present invention and the frequency response of the filter circuit 420 shown in FIG. The multiplier 410, a filter circuit 420, and a second complex multiplier 430, and the filter frequency of the filter circuit 420 will not change due to the detection result. For example, the filter circuit 420 has a fixed filter frequency fc. In the operation of the filter 159 shown in FIG. 4, the control circuit 158 or the filter 159 determines a value of the complex multiplier 410 according to the frequency point fc of the filter circuit 420 and the difference fd of the peak position fp of the signal Din". The multiplier e j2 π fdt , that is, the first complex multiplier 410 is used to shift the frequency of the signal Din" right by fd so that the peak position fp of the signal Din" is aligned with the frequency point fc of the filter circuit 420, and accordingly generates a The frequency-shifted signal; then, the filter circuit 420 performs a filtering operation on the frequency-shifted signal to remove the single-frequency interference of the signal Din" to generate a filtered signal; finally, the second complex multiplier 430 uses the multiplier e -j2 π fdt to shift the frequency of the signal Din” to the left by fd so that the signal Din” returns to the original frequency band to generate the output signal Dout.

在以上的實施例中，PAPR偵測電路156以及控制電路158是持續地在運作，亦即干擾消除電路150可以即時地偵測訊號Din”中是否有單頻干擾並快速有效地消除/抑制此單頻干擾。 In the above embodiments, the PAPR detection circuit 156 and the control circuit 158 are continuously operating, that is, the interference cancellation circuit 150 can instantly detect whether there is single-frequency interference in the signal Din" and quickly and effectively eliminate/suppress it. Single frequency interference.

第6圖為根據本發明一實施例之一種干擾消除方法的流程圖。同時參考以上實施例所述的內容，干擾消除方法的流程如下所述。 Fig. 6 is a flowchart of an interference cancellation method according to an embodiment of the present invention. With reference to the content described in the above embodiments at the same time, the flow of the interference cancellation method is as follows.

步驟600：流程開始。 Step 600: The process starts.

步驟602：即時地偵測一訊號在頻譜上之一峰值對均值功率比，以產生一偵測結果。 Step 602: Detect the peak-to-average power ratio of a signal in the spectrum in real time to generate a detection result.

步驟604：根據該偵測結果來產生一控制訊號。 Step 604: Generate a control signal according to the detection result.

步驟606：根據該控制訊號來決定一濾波器的一過濾頻點，並對該訊號進行濾波以產生一輸出訊號。 Step 606: Determine a filtering frequency point of a filter according to the control signal, and filter the signal to generate an output signal.

簡要歸納本發明，在本發明之干擾消除電路以及干擾消除方法中，透過即時偵測目前訊號是否具有單頻干擾，並根據所偵測到之單頻干擾的頻率來動態地調整濾波器的過濾頻點，可以快速有效地消除/抑制此單頻干擾，改善訊號品質。 Summarizing the present invention briefly, in the interference cancellation circuit and interference cancellation method of the present invention, it detects whether the current signal has single-frequency interference in real time, and dynamically adjusts the filtering of the filter according to the frequency of the detected single-frequency interference The frequency point can quickly and effectively eliminate/inhibit this single-frequency interference and improve the signal quality.

以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

100:電路 100: Circuit

102:天線 102: Antenna

110:類比數位轉換器 110: Analog-to-digital converter

120:混波器 120: mixer

130:時序回復電路 130: timing recovery circuit

140:濾波器 140: filter

150:干擾消除電路 150: interference cancellation circuit

152:緩衝器 152: Buffer

154:快速傅立葉轉換電路 154: Fast Fourier Transformation Circuit

156:PAPR偵測電路 156: PAPR detection circuit

158:控制電路 158: control circuit

159:濾波器 159: filter

Vin:類比輸入訊號 Vin: analog input signal

Din:數位輸入訊號 Din: Digital input signal

Din’:混波後訊號 Din’: Signal after mixing

Din”:訊號 Din": Signal

P_info:偵測結果 P_info: detection result

Vc:控制訊號 Vc: control signal

Dout:輸出訊號 Dout: output signal

Claims (7)

一種干擾消除電路，包含有：一峰值對均值功率比偵測電路，用以即時地偵測一訊號在頻譜上之一峰值對均值功率比(Peak-to-Average Power Ratio，PAPR)，以產生一偵測結果；一控制電路，耦接於該峰值對均值功率比偵測電路，用以根據該偵測結果來產生一控制訊號；以及一濾波器，耦接於該控制電路，用以根據該控制訊號來決定該濾波器的一過濾頻點，並對該訊號進行濾波以產生一輸出訊號；其中該控制電路根據該偵測結果以判斷該訊號是否具有一單頻干擾，並據以產生該控制訊號以決定該濾波器的該過濾頻點，以濾除該訊號的該單頻干擾以產生該輸出訊號。 An interference cancellation circuit, including: a peak-to-average power ratio detection circuit for real-time detection of a signal in the frequency spectrum of a peak-to-average power ratio (Peak-to-Average Power Ratio, PAPR) to generate A detection result; a control circuit, coupled to the peak-to-average power ratio detection circuit, for generating a control signal according to the detection result; and a filter, coupled to the control circuit, for generating a control signal according to the The control signal determines a filtering frequency point of the filter, and filters the signal to generate an output signal; wherein the control circuit determines whether the signal has a single frequency interference according to the detection result, and generates it accordingly The control signal determines the filtering frequency point of the filter to filter out the single-frequency interference of the signal to generate the output signal. 如申請專利範圍第1項所述之干擾消除電路，其中該偵測結果至少包含了該峰值對均值功率比，且該控制電路根據該峰值對均值功率比是否高於一臨界值以判斷該訊號是否具有該單頻干擾。 The interference cancellation circuit described in the first item of the scope of patent application, wherein the detection result at least includes the peak-to-average power ratio, and the control circuit determines the signal according to whether the peak-to-average power ratio is higher than a critical value Whether there is this single-frequency interference. 如申請專利範圍第1或2項所述之干擾消除電路，其中該偵測結果包含了該訊號在頻譜上之一峰值所對應到的頻率，且該控制電路根據該偵測結果以產生該控制訊號以使得該濾波器的該過濾頻點對應到該峰值所對應到的頻率，以濾除該訊號的該單頻干擾以產生該輸出訊號。 The interference cancellation circuit described in item 1 or 2 of the scope of patent application, wherein the detection result includes the frequency corresponding to a peak of the signal in the frequency spectrum, and the control circuit generates the control according to the detection result Signal so that the filtering frequency point of the filter corresponds to the frequency corresponding to the peak, so as to filter out the single-frequency interference of the signal to generate the output signal. 如申請專利範圍第1項所述之干擾消除電路，其中該峰值對均值功率比偵測電路即時地偵測該訊號之連續多個區塊在頻譜上之該峰值對均 值功率比(Peak-to-Average Power Ratio，PAPR)，以產生多個偵測結果；以及只有在該控制電路根據該多個偵測結果判斷出該多個區塊都具有該單頻干擾時，且該單頻干擾的頻率不同於該該濾波器的過濾頻點時，該控制電路才會產生該控制訊號以改變該濾波器的該過濾頻點。 Such as the interference cancellation circuit described in the first item of the scope of patent application, wherein the peak-to-average power ratio detection circuit detects the peak-to-average value of consecutive blocks of the signal in real time on the spectrum Peak-to-Average Power Ratio (PAPR) to generate multiple detection results; and only when the control circuit determines that the multiple blocks have the single-frequency interference based on the multiple detection results And when the frequency of the single-frequency interference is different from the filtering frequency of the filter, the control circuit will generate the control signal to change the filtering frequency of the filter. 如申請專利範圍第1項所述之干擾消除電路，其中該濾波器根據該控制訊號來調整該濾波器的多個接頭係數以決定該過濾頻點，並對該訊號進行濾波以產生該輸出訊號。 For example, the interference cancellation circuit described in item 1 of the scope of patent application, wherein the filter adjusts multiple joint coefficients of the filter according to the control signal to determine the filtering frequency point, and filters the signal to generate the output signal . 如申請專利範圍第1項所述之干擾消除電路，其中該濾波器包含有：一第一複數乘法器，用以將該訊號與一第一乘數相乘以產生一移頻後訊號，其中該第一乘數係根據該偵測結果所產生；一濾波電路，用以對該移頻後訊號進行濾波以產生一濾波後訊號；以及一第二複數乘法器，用以將該濾波後訊號與一第二乘數相乘以產生該輸出訊號；其中若是該偵測結果指出該訊號具有該單頻干擾，該第一複數乘法器係將該訊號與該第一乘數相乘，以使得該濾波電路的該過濾頻點相同於該單頻干擾的頻率，並據以產生該移頻後訊號；其中該濾波電路的過濾頻點不會根據該偵測結果而改變，該第二乘數係根據該偵測結果所產生，且該第二複數乘法器將該濾波後訊號與該第二乘數相乘以移頻回與該訊號具有相同頻帶的該輸出訊號。 For example, the interference cancellation circuit described in claim 1, wherein the filter includes: a first complex multiplier for multiplying the signal by a first multiplier to generate a frequency shifted signal, wherein The first multiplier is generated according to the detection result; a filter circuit for filtering the frequency shifted signal to generate a filtered signal; and a second complex multiplier for the filtered signal Is multiplied by a second multiplier to generate the output signal; wherein if the detection result indicates that the signal has the single-frequency interference, the first complex multiplier multiplies the signal with the first multiplier to make The filter frequency of the filter circuit is the same as the frequency of the single-frequency interference, and the frequency-shifted signal is generated accordingly; wherein the filter frequency of the filter circuit does not change according to the detection result, the second multiplier It is generated according to the detection result, and the second complex multiplier multiplies the filtered signal and the second multiplier to shift the frequency back to the output signal having the same frequency band as the signal. 一種干擾消除方法，包含有： 即時地偵測一訊號在頻譜上之一峰值對均值功率比(Peak-to-Average Power Ratio，PAPR)，以產生一偵測結果；根據該偵測結果來產生一控制訊號以判斷該訊號是否具有一單頻干擾；以及根據該控制訊號來決定一濾波器的一過濾頻點，並對該訊號進行濾波以濾除該訊號的該單頻干擾產生一輸出訊號。 A method of interference cancellation, including: Real-time detection of a signal's peak-to-average power ratio (PAPR) in the spectrum to generate a detection result; according to the detection result, a control signal is generated to determine whether the signal is There is a single-frequency interference; and a filter frequency point of a filter is determined according to the control signal, and the signal is filtered to filter out the single-frequency interference of the signal to generate an output signal.
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