TWI748173B - Semiconductor structure and method for semiconductor processing - Google Patents

Abstract

The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

Description

Semiconductor structure and manufacturing method of semiconductor structure

The embodiments of the present invention are related to semiconductor manufacturing technology, in particular to semiconductor structures and manufacturing methods thereof.

The semiconductor integrated circuit (IC) industry has experienced rapid growth. The advancement of integrated circuit materials and design technology has created generations of integrated circuits, each generation of circuits being smaller and more complex than the previous generation. In the development of integrated circuits, when the geometric size (that is, the smallest component (or line) that can be produced by the process) shrinks, the functional density (that is, the number of interconnected devices per chip area) generally increases. This miniaturization process generally provides the benefits of increasing production efficiency and reducing related costs.

With the miniaturization of devices, manufacturers have begun to use new and different materials and/or material combinations to promote the miniaturization of devices. The miniaturization alone and the miniaturization in combination with new and different materials have also brought challenges that were not present in the previous generations with larger geometric dimensions.

The embodiment of the present invention provides a semiconductor structure. The semiconductor structure includes a dielectric layer on the substrate, and conductive components disposed through the dielectric layer. The dielectric layer has a lower surface close to the substrate and a top surface away from the substrate. The conductive component directly contacts the dielectric layer, and the dielectric layer includes a cloth plant material. The concentration of the cloth material in the dielectric layer has a peak concentration near the top surface of the dielectric layer, and the concentration of the cloth material decreases from the peak concentration in the direction toward the lower surface of the dielectric layer.

The embodiment of the present invention provides a method for manufacturing a semiconductor structure. This method includes depositing conductive features in a dielectric layer. The conductive member directly contacts the dielectric layer. The method further includes, after depositing the conductive component, planting a cloth plant material into the dielectric layer, and after planting the cloth plant material, removing a part of the conductive component by a first planarization process.

The embodiment of the present invention provides another method for manufacturing a semiconductor structure. The method includes depositing a dielectric material on a substrate, wherein the substrate has a conductive material, an opening is formed in the dielectric material to expose the conductive material, and a conductive component is deposited in the opening, and the conductive component directly contacts the conductive material. Material, perform a first planting process to plant a plant material in the dielectric material, and after performing the first planting process, perform a first planarization process to remove part of the conductive components.

The following disclosure provides many different embodiments or examples to demonstrate different features of the present disclosure. The following will disclose specific examples of the components and their arrangement in this specification to simplify the description of this disclosure. Of course, these specific examples are not used to limit this disclosure. For example, if the following invention content of this specification describes that the first part is formed on or above the second part, it means that it includes an embodiment in which the formed first and second parts are in direct contact, and also includes Additional components can be formed between the above-mentioned first and second components, and the first and second components are embodiments that are not in direct contact. In addition, the various examples in this disclosure may use repeated reference symbols and/or words. The purpose of these repeated symbols or words is for simplification and clarity, and is not used to limit the relationship between the various embodiments and/or the configurations.

Furthermore, in order to facilitate the description of the relationship between one element or component and another element or component(s) in the diagram, spatial relative terms can be used, such as "below", "below", "lower", "above" , "Upper" and the like. In addition to the orientation shown in the diagram, the relative terms of space also cover different orientations of the device in use or operation. When the device is turned in different directions (for example, rotated by 90 degrees or other directions), the spatially relative adjectives used therein will also be interpreted according to the turned position.

In general, the embodiments of the present invention provide a method for forming a conductive member in a semiconductor device, and a conductive member formed by the method. Specifically, some embodiments provide a method for forming a conductive plug in an interlayer dielectric to connect with a conductive structure under the interlayer dielectric. The above method includes filling the opening through the interlayer dielectric with a conductive filling material without using an adhesion layer or a barrier layer, and removing the above by implanting the interlayer dielectric. Gaps and cracks between conductive filling materials and interlayer dielectrics. The implantation can create compression stress between the conductive filling material and the interlayer dielectric to close the gaps and cracks between the materials, thus preventing the subsequent planarization process (such as chemical mechanical Polishing (chemical mechanical polishing, CMP) process), the loss of the conductive structure under the conductive filling material. The embodiments herein can be used in any suitable situation to remove voids between two materials.

The exemplary embodiments described in the embodiments of the present invention are described in the context of forming conductive components in a Back End of the Line (BEOL) and/or Middle End of the Line (MEOL) process. The embodiments described in this disclosure are described in the context of forming a conductive component to a Fin Field Effect Transistor (Fin Field Effect Transistor, FinFET) (for example, to a gate structure of a Fin Field Effect Transistor). Other embodiments can be implemented in other contexts, such as using different devices, such as planar FETs, vertical gate all around FETs (VGAA) field effect transistors, and horizontal FETs. Horizontal gate all around FETs (HGAA) field effect transistors, bipolar junction transistors (BJTs), diodes, capacitors, inductors, resistors, etc. In some embodiments, the above-mentioned conductive component may be located in an intermetallization dielectric in the back-end process. Some aspects of the present disclosure can be used in other manufacturing processes and/or in other devices.

Some changes to the example method and structure are described here. Those with ordinary knowledge in the art will easily understand that other modifications can be made within the scope of other embodiments. Although some of the method embodiments discussed are performed in a specific order, various other method embodiments can be performed in another logical order, and may include fewer or more steps than those discussed herein. In some drawings, the symbol of some components or parts shown therein may be omitted to avoid confusion with other components or parts; this is for the convenience of depicting these drawings.

Figure 1 is a three-dimensional view of an intermediate structure at a stage during an example method for forming a conductive component, according to some embodiments. FIGS. 2-9 are schematic cross-sectional diagrams illustrating corresponding intermediate structures at corresponding stages during an exemplary method for forming a conductive member according to some embodiments.

As described below, the intermediate structure of FIG. 1 is used in the embodiment of the fin-type field effect transistor. Other structures can be implemented in other example embodiments. The aforementioned intermediate structure includes first and second fins 46 formed on the semiconductor substrate 42, and corresponding isolation regions 44 are provided on the semiconductor substrate 42 between adjacent fins 46. The aforementioned semiconductor substrate 42 may be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or a similar substrate, which may be doped (for example, using p-type or n-type). Type dopant (dopant)) or undoped. In some embodiments, the semiconductor material of the semiconductor substrate 42 may include elemental semiconductors such as silicon (Si) or germanium (Ge); compound semiconductors; alloy semiconductors; or combinations thereof.

The fin 46 is formed on the semiconductor substrate 42, for example, by etching a trench in the semiconductor substrate 42 to form the fin 46. The fin 46 may be patterned in the semiconductor substrate 42 by any suitable method. For example, one or more photolithography processes may be used to pattern the fins 46, including double-patterning or multi-patterning processes. Generally speaking, double patterning or multiple patterning processes combine photolithography and self-aligned processes. Compared to, for example, the pitch obtained using a single, direct photolithography process, this can create Patterns with a smaller pitch. For example, in some embodiments, a sacrificial layer is formed on the substrate, and the sacrificial layer is patterned using a photolithography process. A self-aligned process is used to form spacers along the patterned sacrificial layer. This sacrificial layer is then removed, and the remaining spacers can be used to pattern the fin 46.

Isolation regions 44 are formed, and each isolation region 44 is located in a corresponding trench. The isolation region 44 may include or be an insulating material, such as an oxide (such as silicon oxide), a nitride, a similar material, or a combination thereof, and a suitable deposition process may be used to deposit the insulating material. The above-mentioned insulating material may be recessed after deposition to form the above-mentioned isolation region 44. The insulating material is etched so that the fins 46 protrude from between the adjacent isolation regions 44, so that at least a part of the fins 46 can be defined as active regions on the semiconductor substrate 42. In addition, the top surface of the isolation region 44 may have a flat surface, a convex surface, a concave surface (such as a dish (dishing)), or a combination of the above as shown in the figure, which can be Caused by the etching process. Those with ordinary knowledge in the art will easily understand that the process described above is only an example of how the fin 46 can be formed. In other examples, the fin 46 may be formed by other processes, and may include heteroepitaxial and/or homoepitaxial structures.

In the embodiment shown in FIG. 1, a dummy gate stack is formed along the corresponding sidewalls of the fin 46 and above the fin 46. As described here, the above-mentioned dummy gate stack is used in the replacement gate process. The above-mentioned dummy gate stack extends longitudinally perpendicular to the longitudinal direction of the corresponding fin 46. The dummy gate stack includes an interface dielectric 48 along the fin 46 and on the fin 46, a dummy gate 50 on the interface dielectric 48, and a dummy gate 50 located on the dummy gate 50.上的mask52.

The above-mentioned interface dielectric 48 may include or be silicon oxide, silicon nitride, similar materials, or the above-mentioned multilayer film. The above-mentioned dummy gate 50 may include or be silicon (for example, polysilicon) or other materials. The mask 52 may include or be silicon nitride, silicon oxynitride, silicon carbon nitride, similar materials, or a combination thereof. The film layers of the interface dielectric 48, the dummy gate 50, and the mask 52 for the dummy gate stack can be sequentially deposited or formed, for example, by any allowable deposition technique, and then these films are patterned It is a dummy gate stack, for example, using photolithography technology and one or more etching processes.

Figure 1 further depicts the reference section used in subsequent drawings. The cross-section A-A lies in a plane along the channel in the fin 46 between, for example, opposing source/drain regions. FIGS. 2-9 illustrate schematic cross-sectional diagrams corresponding to the cross-section A-A at different stages of the process in the exemplary method. Figure 2 is a schematic cross-sectional view of the intermediate structure of Figure 1 at the section A-A.

Figure 3 illustrates the gate spacer 54 and the epitaxial source/drain region 56, the contact etch stop layer (CESL) 60, and the first interlayer dielectric (ILD) The formation of 62. The gate spacer 54 is formed along the sidewalls of the dummy gate stack (for example, the sidewalls of the interface dielectric 48, the dummy gate 50, and the mask 52) and on the fin 46. For example, the gate spacer 54 can be formed by conformally depositing one or more film layers for the gate spacer 54 and etching the one or more film layers anisotropically. The above-mentioned one or more film layers for the gate spacer 54 may include or be silicon nitride, silicon oxynitride, silicon carbonitride, similar materials, multiple layers of the above, or a combination of the above.

After the gate spacers 54 are formed, grooves are formed in the fins 46 located on both sides of the dummy gate stack by an etching process (for example, the dummy gate stacks and the gate spacers 54 described above are used as shields). cover). The above-mentioned epitaxial source/drain region 56 is formed in the groove by an appropriate epitaxial growth or deposition process. The epitaxial source/drain region 56 may include or be silicon germanium, silicon carbide, silicon phosphorus, silicon carbon phosphorus, pure or substantially Pure germanium, group three and five compound semiconductors, group two and six compound semiconductors, or similar materials. In some embodiments, the above-mentioned etch and epitaxial growth can be omitted, and the above-mentioned dummy gate stack and gate spacer 54 can be used as a mask by implanting dopants into the above-mentioned fin 46. The above-mentioned epitaxial source/drain region 56 is formed.

After the epitaxial source/drain region 56, the contact etch stop layer 60 is conformably deposited on the surface of the epitaxial source/drain region 56 and the gate spacer 54 by an appropriate deposition process. On the side walls and top surface, on the top surface of the mask 52, and on the top surface of the isolation region 44. Generally speaking, the etch stop layer (ESL) can provide a mechanism to stop the etching process when a contact or a via is formed, for example. The etch stop layer may be formed of a dielectric material having a different etch selectivity from the adjacent film layer or component. The contact etching stop layer 60 may include or be silicon nitride, silicon carbonitride, silicon oxycarbide, carbon nitride, similar materials, or a combination thereof.

Then, by a proper deposition process, the first interlayer dielectric 62 is deposited on the contact etch stop layer 60. The first interlayer dielectric 62 may include or be silicon dioxide, low-k dielectric materials (for example, materials with a lower dielectric constant than silicon dioxide), oxynitride Silicon, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (undoped silicate) glass, USG), fluorinated silicate glass (FSG), organosilicate glasses (OSG), SiOxCy, carbon silicon materials, the above-mentioned compound (compound), the above-mentioned compound (composite), similar materials, or a combination of the above.

In FIG. 4, a planarization process such as chemical mechanical polishing can be performed to make the top surface of the first interlayer dielectric 62 and the contact etch stop layer 60 flush with the top surface of the dummy gate 50. The dummy gate 50 is removed by one or more etching processes. The replacement gate structure may be formed in the groove formed by the removal of the dummy gate stack. As shown, the aforementioned replacement gate structure includes an interface dielectric 70, a gate dielectric layer 72, one or more selective conformal layers 74, and a gate conductive filling material 76. The aforementioned interface dielectric 70 is formed on the sidewall and top surface of the fin 46 along the channel region. For example, the interface dielectric 70 may be the interface dielectric 48 (if not removed), an oxide (for example, silicon oxide) formed by the thermal or chemical oxidation of the fin 46, and/or oxidation (E.g., silicon oxide), nitride (e.g., silicon nitride), and/or other dielectric layers.

It can be in the groove formed by removing the dummy gate stack (for example, on the top surface of the isolation region 44, on the interface dielectric 70, and the sidewalls of the gate spacer 54) and in the first interlayer. The above-mentioned gate dielectric layer 72 is conformably deposited on the top surface of the dielectric 62, the contact etch stop 60, and the gate spacer 54. The gate dielectric layer 72 may be or include silicon oxide, silicon nitride, high-k dielectric materials, the above-mentioned multilayer films, or other dielectric materials. High dielectric constant dielectric materials can include hafnium (hafnium, Hf), aluminum (aluminum, Al), zirconium (zirconium, Zr), lanthanum (lanthanum, La), magnesium (magnesium, Mg), barium (barium, Ba) , Titanium (Ti), Lead (Pb), the above multilayer film, or a combination of the above metal oxide or metal silicate (metal silicate).

Then, one or more selective conformal layers 74 described above may be deposited conformally (and sequentially, if more than one) on the gate dielectric layer 72. The one or more selective conformal layers 74 may include one or more barrier and/or capping layers and one or more work function adjustment layers. The one or more barrier and/or capping layers may include tantalum and/or titanium nitride, silicide nitride, carbide nitride, and/or aluminum nitride; tungsten Nitride, nitrogen carbide, and/or carbide; similar materials; or a combination of the above. The one or more work function adjustment layers may include or be titanium and/or tantalum nitride, silicon nitride, carbonitride, aluminum nitride, aluminum oxide, and/or aluminum carbide; tungsten nitride, Nitrogen carbides, and/or carbides; cobalt; platinum; similar materials; or a combination of the above.

The gate conductive filling material 76 is formed on the one or more selective conformal layers 74 (if implemented) and/or the gate dielectric layer 72. The aforementioned gate conductive filling material 76 can fill the remaining part of the groove formed by removing the dummy gate stack. The gate conductive filling material 76 may be or include a metal-containing material, such as tungsten (W), cobalt (Co), aluminum, ruthenium, copper, the foregoing multilayer film, and a combination of the foregoing , Or similar materials. For example, chemical mechanical polishing is used to remove the gate conductive filling material 76 located above the top surface of the first interlayer dielectric 62, the contact etch stop layer 60, and the gate spacer 54, one or more options The compliant layer 74 and the gate dielectric layer 72. As a result, the replacement gate structure including the gate conductive filling material 76, one or more selective conformal layers 74, the gate dielectric layer 72, and the interface dielectric 70 as shown in FIG. 4 can be formed.

In FIG. 5, an etch stop layer (ESL) 78 is deposited on the above-mentioned first interlayer dielectric 62, contact etch stop layer 60, gate spacer 54, and replacement gate structure. The etch stop layer 78 may include or be silicon nitride, silicon carbonitride, carbon nitride, similar materials, or a combination thereof. In some embodiments, the etch stop layer 78 has a thickness ranging from about 20 angstroms (Å) to about 500 angstroms, for example, about 200 angstroms.

A second interlayer dielectric layer 80 is deposited on the above-mentioned etch stop layer 78. The second interlayer dielectric layer 80 may include or be silicon dioxide, low-k dielectric material, silicon oxynitride, phosphosilicate glass (PSG), boron Silicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (fluorinated Silicate glass (FSG), organosilicate glasses (OSG), SiOxCy, carbon silicon material, the above-mentioned compound, the above-mentioned composite (composite), similar materials, or a combination of the above. In some embodiments, the above-mentioned second interlayer dielectric layer 80 has a thickness ranging from about 20 angstroms to about 500 angstroms, for example, about 350 angstroms. In some embodiments, the etch stop layer 78 may not be implemented, and the second interlayer dielectric layer 80 may be directly deposited on the first interlayer dielectric 62, the contact etch stop layer 60, and the gate spacer 54 , And replace the gate structure.

Next, an opening 82 is formed through the second interlayer dielectric 80 and the etching stop layer 78 to expose at least a part of the replacement gate structure. The opening 82 can be used to pattern the second interlayer dielectric 80 and the etch stop layer 78, for example, using photolithography or one or more etching processes.

In FIG. 5, a conductive member 84 is formed in the opening 82 described above. The conductive member 84 is directly formed in the opening 82 to connect to the replacement gate structure without using any adhesive layer and/or barrier layer between them. The conductive member 84 is grown on the top surface of the gate conductive filling material 76 and gradually fills the opening 82 from the bottom in a bottom-up manner. After the opening 82 is filled, the conductive member 84 "overflows" out of the opening 82, forming an overfilled portion 84o. The overfilled portion 84o is located above the top surface of the second interlayer dielectric 80. The above-mentioned overfilled portion 84o generally has a larger diameter than the opening 82. The bottom-up formation enables direct connection between the above-mentioned conductive member 84 and the gate conductive filling material 76, which can reduce the connection resistance. This bottom-up filling method can also reduce unexpected defects, such as voids or seams. For example, since the bottom-up formation can reduce the possibility of the opening 82 being closed early, voids or sealing can be avoided.

In some embodiments, chemical vapor deposition (CVD), selective atomic layer deposition (atomic layer deposition, ALD), electroless deposition (ELD), electroplating (electroplating), physical Vapor deposition (physical vapor deposition, PVD) or other deposition techniques are used to deposit the above-mentioned conductive component 84. In some embodiments, the bottom-up formation of the conductive member 84 can be achieved by physical vapor deposition sputtering. In other embodiments, the above-mentioned conductive component can be realized by using a self-aligned monolayer (SAM) inhibitor on the dielectric surface during chemical vapor deposition growth on the conductive surface 84's bottom-up formation. In some embodiments, the above-mentioned conductive member 84 may be or include tungsten (W), cobalt (Co), copper (Cu), ruthenium (Ru), aluminum (Al), gold (gold, Au), silver (silver, Ag), the above alloys, similar materials, or a combination of the above.

Fig. 10 is a partial enlarged view of Fig. 6, showing details around the conductive member 84. Since there is no adhesion layer or barrier layer between the conductive component 84 and the second interlayer dielectric 80, a gap 86 may exist between the conductive component 84 and the second interlayer dielectric 80. This gap 86 may cause undesired behavior in subsequent manufacturing processes. For example, process chemicals from subsequent processes can penetrate the gap 86 and interact with the underlying materials. The above-mentioned conductive materials (such as copper or cobalt) may be attacked by chemical attack in an acidic environment, and reduce the electrical performance of the device. For example, in the subsequent chemical mechanical polishing process, the above-mentioned void 86 may allow the polishing slurry to penetrate into the underlying film layer, such as the above-mentioned gate conductive filler material 76. The above-mentioned polishing slurry may react with the gate conductive filling material 76, resulting in loss of the gate conductive filling material 76. Similarly, the above-mentioned gap 86 may also expose the film layer underneath to the etching chemistry and plasma process environment in the subsequent process. In some embodiments, one or more implanting processes can be used to reduce or close the above-mentioned gap 86.

Generally speaking, in some embodiments, a conductive component is first formed in the interlayer dielectric layer without any adhesion layer or barrier layer, and then an implantation process is performed to apply pressure between the conductive component and the interlayer dielectric layer. , To close any gaps caused by the absence of the above-mentioned adhesive layer or the absence of the above-mentioned barrier layer.

FIG. 7 schematically shows an implantation process for eliminating or reducing the gap 86 between the conductive component 84 and the surrounding dielectric material (for example, the second interlayer dielectric 80 and the etching stop layer 78). In some embodiments, after forming the above-mentioned conductive component, the ion beam 88 of one or more species of neutral element is directed toward the above-mentioned dielectric material (for example, the above-mentioned second interlayer) by an implantation process. The dielectric 80 and the etch stop layer 78) are projected. In some embodiments, the neutral element is implanted on the second interlayer dielectric 80 and the etching stop layer 78 to modify the physical properties, such as volume and stress, but does not change significantly. One or more substances of the aforementioned neutral elements are implanted with the required depth and the required concentration to close the path from the top surface of the aforementioned conductive member 84 to the film layer below it. In some embodiments, the one or more substances of the aforementioned neutral elements include germanium (Ge), silicon (silicon, Si), nitrogen (nitrogen, N), or other materials having a larger atomic volume than other implant materials. element.

In some embodiments, according to the design (for example, the original thickness and final thickness of the second interlayer dielectric 80), the implantation process is performed at an energy level ranging from about 10 keV to about 80 keV. When other parameters remain unchanged, a higher energy level results in a deeper implantation peak. In some embodiments, the ^{implantation process is performed at a dose level ranging from about 5x10 13} counts/cm ² (times/cm 2) to about 5x10 ¹⁶ counts/cm ² , which may depend on the size of the gap to be closed . A higher dose can correspond to a larger expansion in the above-mentioned dielectric layer to close larger gaps. In some embodiments, the above-mentioned implantation process is performed at a temperature ranging from about -100°C to about 450°C. Optionally, an annealing process is performed after the implantation process to adjust the crystal structure in the implanted film layer and reduce the damage in the implanted film layer caused by the implantation process.

FIG. 11 is a partial enlarged view of FIG. 7, showing the details around the conductive member 84 after the implantation process. The substance implanted in the implanted second interlayer dielectric 80i and the implanted etch stop layer 78i causes the implanted second interlayer dielectric 80i and the implanted etch stop layer 78i to expand. The aforementioned expansion can occur in all directions. As shown in Figure 11, the above expansion induces compression at the interface 92 between (i) the conductive member 84 and (ii) the implanted second interlayer dielectric 80i or the implanted etching stop layer 78i to close the above Gap 86. The aforementioned expansion can occur along the z-direction, which is along the direction of depth. In some embodiments, the expansion along the z-direction can be measured to indicate the total amount of expansion, so as to determine the compression between the conductive member 84 and the electrical boundary layer.

The concentration profiles 94a-96e are the plant material concentration profiles along the depth of the implanted second interlayer dielectric 80i and the implanted etch stop layer 78i in some examples of Ge implantation. The aforementioned density profiles 94a-94d are the profiles of the implantation process using the same dosage and increased power level. Points 96a-96d (also referred to as density profiles 96a-96d) are the peak density points corresponding to the aforementioned density profiles 94a-94d. The concentration profiles 94a-94d show that when the dose remains constant, the above-mentioned peak concentration point deepens as the power level increases. The density profile 94e is a profile for the implantation process using the same power level and lower dose as the density profile 94d. The density profiles 94e and 94d have substantially the same shape.

The concentration of the implanted part value is the highest at the peak concentration points 96a-96e (also referred to as the concentration profile 96a-96e), and the induced compression toward the conductive member 84 may also be the highest. Line 98 indicates the depth level at which the subsequent chemical mechanical polishing process is terminated. A portion of the second interlayer dielectric 80 below the line 98 remains in the device, and a portion of the second interlayer dielectric 80 above the line 98 is removed during the above-mentioned process. In some embodiments, the implantation process is designed so that the peak concentration point is located at a depth level above the aforementioned line 98. The above configuration can ensure that the part where the second interlayer dielectric 80 interacts with the chemical mechanical polishing slurry has a high compression toward the conductive member 84 to cut off the path of the slurry to the underlying film layer.

Compared with the second interlayer dielectric 80, the conductive member 84 with a denser crystal structure is more difficult to penetrate by the cloth plant material. As a result, compared to the second interlayer dielectric 80, the above-mentioned cloth material is concentrated in the conductive member 84 at a shallower depth. In some embodiments, the cloth material in the conductive member 84 is mainly located above the line 98, and therefore will be removed by the above-mentioned planarization process.

In some embodiments, the ion beam 88 may be directed toward the substrate at an angle to guide the substance to the area covered by the overfilled portion 84o of the conductive member 84.

In FIG. 8, a barrier layer 100 is formed on the remaining portion of the conductive member 84 and the implanted second interlayer dielectric layer 80 i that is not covered by the conductive member 84. The barrier layer 100 may be or include titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, similar materials, or a combination of the foregoing, and may be used Deposited by atomic layer deposition, chemical vapor deposition, or other deposition techniques. By forming a blanket conductive layer 102 on the barrier layer 100 described above. The blanket conductive layer 102 can fill other grooves or openings in the second interlayer dielectric layer 80. In some embodiments, the above-mentioned conductive material may be deposited by chemical vapor deposition, atomic layer deposition, electroless electroplating (ELD), physical vapor deposition (PVD), electroplating, or other deposition techniques. Layer 102 (also referred to as blanket conductive layer 102). In some embodiments, the conductive layer 102 may be or include tungsten (W), cobalt (Co), copper (Cu), ruthenium (Ru), aluminum (Al), gold (gold, Au), silver (silver, Ag), the above alloys, similar materials, or a combination of the above. In some embodiments, the conductive layer 102 and the conductive component 84 may include the same material. The blanket conductive layer 102 also puts the surface of the substrate under the conditions of the chemical mechanical polishing process.

In FIG. 9, a planarization process such as chemical mechanical planarization is performed to remove the excess conductive layer 102, the barrier layer 100, the implanted second interlayer dielectric layer 80i, and the conductive component 84. In some embodiments, after the above-mentioned planarization process, the above-mentioned implanted second interlayer dielectric layer 80i has a thickness ranging from about 20 angstroms to about 500 angstroms, for example, about 50 angstroms. Since the implanted second interlayer dielectric layer 80i and the implanted etching stop layer 78i are compressed toward the conductive member 84, the chemical mechanical polishing slurry can be prevented from penetrating into the void around the conductive member 84, thereby causing the underlying The film is not damaged.

Fig. 12 is a partial enlarged view of Fig. 9 showing the components adjacent to the conductive member 84 after the planarization process. The concentration profiles 104a-104e are the concentration profiles of the plant material in the implanted second interlayer dielectric 80i and the implanted etching stop layer 78i after the above-mentioned planarization process. In some embodiments, the above-mentioned implanted second interlayer dielectric 80i and implanted etch stop layer 78i have a concentration profile of the implanted vegetation that decreases with the depth. Specifically, after the above-mentioned planarization process, the concentration profile of the cloth plant material in the remaining implanted second interlayer dielectric 80i and the implanted etching stop layer 78i is reduced from the peak concentration of the cloth plant material, and the peak concentration Close to the top surface 80t of the remaining implanted second interlayer dielectric 80i to face the underlying film layer in the substrate (for example, the lower surface 80l of the implanted second interlayer dielectric 80i is implanted and terminated by implant etching The direction of the lower surface 78l) of the layer 78i decreases. The surface of the implanted second interlayer dielectric 80i is far away from the substrate. In some embodiments, the above-mentioned implanted second interlayer dielectric 80i has a concentration of a fabric material, such as a Ge concentration, in the range of about 8× ^{10 18} atoms/cm ³ to 1 ^{×10 21} atoms/cm ³ . In some embodiments, the above-mentioned implanted etch stop layer 78i has a concentration of a cloth material, such as a Ge concentration, in the range of about 2×10 ¹⁸ atoms/cm ³ to 6× ^{10 20} atoms/cm ³ . Experiments indicate that in the insulation function of the second interlayer dielectric 80, the presence of the cloth plant matter in the second interlayer dielectric 80 usually does not have a detectable effect. Any remaining fabric material in the conductive member 84 generally does not affect the conductivity of the conductive member 84.

13 to 16 are schematic cross-sectional views illustrating corresponding intermediate structures at corresponding stages during another exemplary method for forming conductive components according to some embodiments. Before proceeding with the process described in Figure 13 as described below, perform the process described in Figures 1 to 6 as described above. FIGS. 13 to 16 show schematic cross-sectional views corresponding to the cross-section A-A at different stages of the process in the exemplary method.

Generally speaking, in some embodiments, a conductive component is first formed in the interlayer dielectric layer without any adhesion layer or without any barrier layer, and then the first implantation process is performed to form the conductive component and the interlayer dielectric layer. Pressure is applied at a shallow depth between the gaps to close any gaps, then a first planarization process is performed to remove the overfilled part of the above-mentioned conductive components, and a second implantation process is performed to between the remaining conductive components and the interlayer dielectric layer. Pressure is applied to close any gaps, and then a second planarization process is performed to remove any excess portions of the aforementioned conductive features and interlayer dielectric layer.

In Fig. 13, after the conductive member 84 is formed as shown in Figs. 2-6, the first planting process is performed. The first planting process is similar to the planting process described in FIG. 7, except that the first planting process is configured to have a relatively shallow concentration peak point to remove the conductive member 84. When the overfilled part is 84o, it prevents damage to the underlying film layer.

In some embodiments, after the conductive member 84 is formed, the ion beam 106 of one or more neutral elements is directed toward the dielectric material (for example, the second interlayer dielectric 80 and the etching End layer 78) Projection. One or more substances of the aforementioned neutral elements are implanted with the required depth and the required concentration to close the path from the top surface of the aforementioned conductive member 84 to the film layer below it. In some embodiments, the one or more substances of the aforementioned neutral elements include germanium (Ge), silicon (silicon, Si), nitrogen (nitrogen, N), or other materials having a larger atomic volume than other implant materials. element. The energy level, dose, and angle of the first implantation process are such that the gap between the second interlayer dielectric layer 80 immediately below the overfilled portion 84o can be closed.

Since the overfilled portion 84o generally has a larger diameter than the portion in the opening 82, and the conductive member 84 generally has a denser crystal structure than the second interlayer dielectric layer 80, the overfilled portion 84o can It acts like an umbrella to prevent the cloth material from reaching the second interlayer dielectric layer 80 under the overfilled portion 84o. In some embodiments, the ion beam 106 may be directed toward the substrate at an angle to reach the second interlayer dielectric layer 80 shielded by the overfilled portion 84o. In Figure 13, the ion beam 106 is guided at an angle 110 with respect to the axial direction 108, which is perpendicular to the top surface of the substrate. During operation, the substrate 42 is rotated, for example, around the axial direction 108. When the substrate 42 rotates around the axial direction 108, the second interlayer dielectric layer 80 under the overfilled portion 84o around the conductive member 84 can be implanted with the ion beam 106 at an angle 110. In some embodiments, the aforementioned angle 110 ranges from about greater than 0 degrees to about 45 degrees.

In some embodiments, the first implantation process is performed at an energy level ranging from about 5 keV to about 40 keV. Higher energy levels can correspond to deeper implantation peaks.

In some embodiments, the first implantation process is performed at a dose level ranging from about 5×10 ¹³ counts/cm ² to about 5× ^{10 16} counts/cm ² , which may depend on the size of the gap to be closed. A higher dose can correspond to a larger expansion in the above-mentioned dielectric layer to close larger gaps.

In some embodiments, the first planting process is performed at a temperature ranging from about -100°C to about 450°C. Optionally, an annealing process is performed after the above-mentioned first implantation process to adjust the crystal structure in the implanted film layer and reduce the damage in the implanted film layer caused by the implantation process.

FIG. 17 is a partial enlarged view of FIG. 13, showing the details around the conductive member 84 after the first implantation process. The concentration profile 112 is the plant material concentration profile along the depth of the implanted second interlayer dielectric layer 80i. The point 114 is the peak density point of the aforementioned density profile 112. In some embodiments, the peak concentration point is located at a distance 116 below the top surface of the second interlayer dielectric layer 80. In some embodiments, the aforementioned distance 116 is located at a depth ranging from greater than about 0 angstroms to about 500 angstroms. The maximum pressure between the second interlayer dielectric layer 80 and the conductive member 84 may occur near the peak concentration point. The compression near the peak concentration point described above can cut off the path through the gap 86 to the underlying film layer. When polishing above the above peak concentration point, the chemical mechanical polishing slurry may not be able to penetrate the void 86 to reach the underlying film layer.

In Fig. 14, similar to Fig. 8, a barrier layer 100 is formed on the remaining portion of the conductive member 84 and the implanted second interlayer dielectric layer 80i that is not covered by the conductive member 84, and then the barrier layer 100 is formed on the conductive member 84. A blanket conductive layer 102 is formed on the barrier layer 100.

In Figure 15, a first planarization process such as chemical mechanical polishing is performed to remove the excess conductive layer 102, the barrier layer 100, the overfilled portion 84o of the implanted second interlayer dielectric layer 80i, and the conductive components 84. Since after the above-mentioned first implantation process, the path under the overfilled portion 84o through the gap 86 to the underlying film layer can be closed, it can prevent the above-mentioned chemical mechanical polishing slurry from penetrating into the gap around the conductive member 84, Therefore, the lower film layer is not damaged in the above-mentioned first planarization process.

In FIG. 15, a second implantation process is performed to eliminate or reduce the gap 86 between the conductive component 84 and the surrounding dielectric material (for example, the second interlayer dielectric layer 80 and the etching stop layer 78). The second planting process described above is similar to the planting process described in Figure 7, except that it may be at a lower energy level, because when the overfilled part 84o is removed, the plant material can penetrate into the above-mentioned medium more easily. Electric materials.

The ion beam 118 of one or more substances such as the aforementioned neutral element is projected toward the aforementioned dielectric material (for example, the aforementioned second interlayer dielectric 80 and the etching stop layer 78). In some embodiments, according to the design (for example, the original thickness and final thickness of the second interlayer dielectric 80), the second implantation process is performed at an energy level ranging from about 7keV to about 56keV. In some embodiments, the second implantation process is performed at a dose level ranging from about 5×10 ¹³ counts/cm ² to about 5× ^{10 16} counts/cm ² , which may depend on the size of the gap to be closed. In some embodiments, the second planting process is performed at a temperature ranging from about -100°C to about 450°C. Optionally, an annealing process is performed after the above-mentioned second implantation process to adjust the crystal structure in the implanted film layer and reduce damage in the implanted film layer caused by the implantation process.

Fig. 18 is a partial enlarged view of Fig. 16, showing details around the conductive member 84 after the second implantation process. The substance implanted in the implanted second interlayer dielectric 80i and the implanted etch stop layer 78i causes the implanted second interlayer dielectric 80i and the implanted etch stop layer 78i to expand. The aforementioned expansion can occur in all directions. As shown in Figure 18, the aforementioned expansion induces compression at the interface 92 between (i) the conductive member 84 and (ii) the implanted second interlayer dielectric 80i or the implanted etch stop layer 78i to close the aforementioned Gap 86. The aforementioned expansion can occur along the z-direction. In some embodiments, the expansion along the z-direction can be measured to indicate the total amount of expansion, so as to determine the compression between the conductive member 84 and the electrical boundary layer.

According to some embodiments, the concentration profile 120 is an exemplary plant material concentration profile along the depth of the implanted second interlayer dielectric 80i and the implanted etch stop layer 78i. Point 122 is the peak concentration point, where the cloth plant matter concentration is the highest, and where the induced compression toward the conductive member 84 may be the highest. Line 98 indicates the depth level at which the subsequent chemical mechanical polishing process is terminated. A portion of the second interlayer dielectric 80 below the line 98 remains in the device, and a portion of the second interlayer dielectric 80 above the line 98 is removed during the above-mentioned process. In some embodiments, the implantation process is designed so that the peak concentration point is located at a depth level above the aforementioned line 98. The above configuration can ensure that the part where the second interlayer dielectric 80 interacts with the chemical mechanical polishing slurry has a high compression toward the conductive member 84 to cut off the path of the slurry to the underlying film layer.

Similar to the planarization process described in Figure 9, after the second implantation process, a planarization process such as chemical mechanical planarization is performed to remove the excess conductive layer 102, the barrier layer 100, and the second implantation process. Two interlayer dielectric layers 80i and conductive members 84.

Although the embodiments of the present invention are discussed in the context of forming conductive components to gate conductive filling materials, the embodiments can be used in any case where conductive components are formed in a dielectric layer without an adhesion layer and no barrier layer, such as In the case of forming a contact to the active region in the fin-type field effect transistor device, in the case of forming a metal plug in the interlayer metallization dielectric layer, or the like.

The embodiment of the present invention provides a method for forming a conductive component in a dielectric layer without an adhesive layer or a barrier layer, and a device formed thereby. By not using the adhesive layer or barrier layer, the resistance between the conductive component and the conductive material under the dielectric layer can be reduced. After forming the above-mentioned conductive component, the above-mentioned dielectric layer can be implanted in one or more passes to close the gap between the above-mentioned conductive component and the dielectric layer. The above-mentioned gap may be due to the absence of the above-mentioned adhesive layer or the absence of the above-mentioned barrier layer. Caused by. The implantation process can prevent the film layer and the conductive components under the dielectric layer from being exposed to the process environment in the subsequent process, such as chemical mechanical polishing slurry, etching chemicals, and plasma for etching, deposition or cleaning.

Some embodiments provide a semiconductor structure including a dielectric layer on a substrate, and conductive components disposed through the dielectric layer. The dielectric layer has a lower surface close to the substrate and a top surface away from the substrate. The conductive component directly contacts the dielectric layer, and the dielectric layer includes a cloth plant material. The concentration of the cloth material in the dielectric layer has a peak concentration near the top surface of the dielectric layer, and the concentration of the cloth material decreases from the peak concentration in the direction toward the lower surface of the dielectric layer. In one embodiment, the aforementioned cloth plant material includes at least one of germanium (Ge), silicon (Si), and nitrogen (N). In one embodiment, the peak concentration of the above-mentioned cloth plant material ranges from about 8× ^{10 18} atoms/cm ³ to 1 ^{×10 21} atoms/cm ³ . In one embodiment, it further includes an etch stop layer, wherein the dielectric layer is disposed on the etch stop layer, and the conductive component is disposed through the etch stop layer. In one embodiment, the etching stop layer includes the cloth plant material, and the concentration of the cloth plant material in the etching stop layer ranges from about 2×10 ¹⁸ atoms/cm ³ to about 6× ^{10 20} atoms/cm ³ . In one embodiment, the above-mentioned dielectric layer includes silicon oxide, silicon oxynitride, silicon oxycarbide, or a combination thereof.

Some embodiments provide a method of manufacturing a semiconductor structure. This method includes depositing conductive features in a dielectric layer. The conductive member directly contacts the dielectric layer. The method further includes, after depositing the conductive component, planting a cloth plant material into the dielectric layer, and after planting the cloth plant material, removing a part of the conductive component by a first planarization process. In one embodiment, the aforementioned cloth plant material includes at least one of germanium (Ge), silicon (Si), and nitrogen (N). In one embodiment, the step of planting the cloth plant material includes expanding the dielectric layer, and the expanded dielectric layer exerts a compressive force on the conductive component. In one embodiment, the peak concentration point of the cloth material in the dielectric layer is located in a part of the dielectric layer removed by the first planarization process. In one embodiment, the method further includes forming an opening through the dielectric layer to expose the conductive material in the film layer under the dielectric layer, wherein depositing the conductive component includes depositing the conductive component in the opening from bottom to top Way to grow the above-mentioned conductive parts. In one embodiment, after removing the conductive parts of the above-mentioned part, planting the another cloth material into the dielectric layer, and after planting the other cloth material, by a second planarization process To remove another part of the above-mentioned conductive component and dielectric layer. In one embodiment, the planting of the cloth plant material into the dielectric layer is performed at an angle with the axis perpendicular to the surface of the dielectric layer, and the angle is greater than zero.

Some embodiments provide a method of manufacturing a semiconductor structure. The method includes depositing a dielectric material on a substrate, wherein the substrate has a conductive material, an opening is formed in the dielectric material to expose the conductive material, and a conductive component is deposited in the opening, and the conductive component directly contacts the conductive material. Material, perform a first planting process to plant a plant material in the dielectric material, and after performing the first planting process, perform a first planarization process to remove part of the conductive components. In one embodiment, the step of depositing the conductive component includes growing the conductive component in the opening in a bottom-up manner. In one embodiment, the dielectric material includes an etch stop layer and an interlayer dielectric layer located above the etch stop layer. In one embodiment, the step of planting the plant material includes planting a neutral element in the dielectric material to expand the dielectric material so as to apply pressure around the conductive component. In one embodiment, the step of performing the first planting process includes guiding the plant material to the dielectric material at a non-zero angle relative to the axial direction perpendicular to the surface of the dielectric material, and the surface of the dielectric material Stay away from the above-mentioned substrates. In one embodiment, the step of depositing the conductive component forms an overfilled portion on the dielectric material, and the first planarization process is performed to remove the overfilled portion of the conductive material. In one embodiment, it further includes performing a second implantation process after performing the first planarization process to implant another substance in the dielectric material, and performing the second implantation process after performing the second implantation process. The second planarization process is to remove part of the above-mentioned dielectric material and part of the above-mentioned conductive material.

The above briefly describes the features of the several embodiments of the present disclosure, so that those with ordinary knowledge in the technical field can understand the present disclosure more easily. Anyone with ordinary knowledge in the relevant technical field should understand that this specification can easily be used as a basis for modification or design of other structures or processes to perform the same purpose and/or obtain the same advantages as the embodiments of the present disclosure. Anyone with ordinary knowledge in the technical field can also understand that the structure or manufacturing process equivalent to the above does not deviate from the spirit and scope of the disclosure, and can be changed or substituted without departing from the spirit and scope of the disclosure. And retouch.

42‧‧‧Semiconductor substrate 44‧‧‧Isolation area 46‧‧‧Fin 48‧‧‧Interface dielectric 50‧‧‧Dummy gate 52‧‧‧Mask 54‧‧‧Gate spacer 56‧ ‧‧Epitaxial source/drain region 60‧‧‧Contact etching stop layer 62‧‧‧First interlayer dielectric 70‧‧‧Interface dielectric 72‧‧‧Gate dielectric layer 74‧‧‧ One or more selective conformal layer 76‧‧‧Gate conductive filling material 78‧‧‧Etch stop layer 78i‧‧After implantation of the etch stop layer 78l‧‧‧Lower surface 80‧‧‧Second interlayer dielectric Layer 80i‧‧‧Second interlayer dielectric 80t‧‧‧Top surface 80l‧‧‧Lower surface 82‧‧‧Opening 84‧‧‧Conductive component 84o‧‧‧Overfilling part 86‧‧‧Void 88 ,106,118‧‧‧Ion beam 92‧‧‧Interface 94a-94e,104a-104e,112,120‧‧‧Concentration profile 96a-96e,114,122‧‧‧point 98‧‧‧line 100‧‧‧ Barrier layer 102‧‧‧Carpet-covered conductive layer 108‧‧‧Axial 110‧‧‧Angle 116‧‧‧Distance

The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be noted that, according to standard practices in the industry, the various features are not drawn to scale and are only used for illustration and illustration. In fact, it is possible to arbitrarily enlarge or reduce the size of the element to clearly show the features of the present disclosure. Figure 1 is a three-dimensional view of an intermediate structure at a stage during an example method for forming a conductive component, according to some embodiments. FIGS. 2-9 are schematic cross-sectional diagrams illustrating corresponding intermediate structures at corresponding stages during an exemplary method for forming a conductive member according to some embodiments. Figure 10 is a partial enlarged view of Figure 6. Figure 11 is a partial enlarged view of Figure 7. Figure 12 is a partial enlarged view of Figure 9. 13 to 16 are schematic cross-sectional views illustrating corresponding intermediate structures at corresponding stages during another exemplary method for forming conductive components according to some embodiments. Figure 17 is a partial enlarged view of Figure 13. Figure 18 is a partial enlarged view of Figure 16.

72‧‧‧Gate Dielectric Layer

74‧‧‧One or more selective conformal layers

76‧‧‧Gate conductive filling material

78‧‧‧Etching stop layer

80‧‧‧Second interlayer dielectric layer

84‧‧‧Conductive parts

84o‧‧‧Overfilling part

86‧‧‧Gap

106‧‧‧Ion beam

112‧‧‧Concentration profile

114‧‧‧points

116‧‧‧Distance

Claims (14)

A semiconductor structure includes: a dielectric layer on a substrate, wherein the dielectric layer has a lower surface close to the substrate and a top surface away from the substrate; and a conductive component disposed through the dielectric layer , Wherein the conductive component directly contacts the dielectric layer, and the dielectric layer includes a cloth plant material, the concentration of the cloth plant material in the dielectric layer increases from the top surface of the dielectric layer to the dielectric layer A peak concentration below the top surface of the layer, and the concentration of the cloth plant matter decreases from the peak concentration in a direction toward the lower surface of the dielectric layer. According to the semiconductor structure described in item 1 of the scope of patent application, the fabric material includes at least one of germanium (Ge), silicon (Si), and nitrogen (N). According to the semiconductor structure described in item 1 or 2 of the scope of patent application, the peak concentration of the fabric material is in the range of 8× ^{10 18} atoms/cm ³ to 1 ^{×10 21} atoms/cm ³ . The semiconductor structure described in item 1 or 2 of the scope of the patent application further includes an etch stop layer, wherein the dielectric layer is disposed on the etch stop layer, and the conductive component is disposed through the etch stop layer. The semiconductor structure according to claim 4, wherein the etching stop layer includes the cloth plant material, and the concentration of the cloth plant material in the etching stop layer ranges from 2x10 ¹⁸ atoms/cm ³ to 6x10 ²⁰ atoms/cm ³ . The semiconductor structure described in item 1 or 2 of the scope of patent application, wherein the dielectric layer includes silicon oxide, silicon oxynitride, silicon oxycarbide, or a combination of the above. A method for manufacturing a semiconductor structure, the method comprising: depositing a conductive component in a dielectric layer, wherein the conductive component directly contacts the dielectric layer; after depositing the conductive component, planting a cloth plant material on the dielectric layer Layer After planting the cloth plant material, remove a part of the conductive part by a first planarization process; after removing the part of the conductive part, plant another cloth plant material into the dielectric layer; and After planting the other cloth plant material, another part of the conductive component and the dielectric layer are removed by a second planarization process. According to the manufacturing method of the semiconductor structure described in claim 7, wherein the cloth plant material includes at least one of germanium (Ge), silicon (Si), and nitrogen (N). According to the manufacturing method of the semiconductor structure described in claim 7, wherein the step of planting the cloth plant material includes expanding the dielectric layer, and the expanded dielectric layer applies a compressive force to the conductive member . The method for manufacturing a semiconductor structure as described in claim 7, wherein a peak concentration point of the cloth plant matter in the dielectric layer is located in the part of the dielectric layer removed by the second planarization process . The method for manufacturing a semiconductor structure as described in claim 7 further includes forming an opening through the dielectric layer to expose a conductive material in a film layer under the dielectric layer, wherein the The conductive member is included in the opening to grow the conductive member in a bottom-up manner. The method for manufacturing a semiconductor structure according to any one of items 7-11 in the scope of the patent application, wherein the planting of the cloth plant material into the dielectric layer is from an axial direction perpendicular to a surface of the dielectric layer At an angle, the angle is greater than zero. A method for manufacturing a semiconductor structure, the method comprising: depositing a dielectric material on a substrate, wherein the substrate has a conductive material; forming an opening in the dielectric material to expose the conductive material; in the opening Deposit a conductive part, and the conductive part directly contacts the conductive material, wherein the sink The step of depositing the conductive component forms an overfill part above the dielectric material; performing a first planting process to plant a plant material in the dielectric material; after performing the first planting process, A first planarization process is performed to remove a part of the conductive component, wherein the first planarization process is performed to remove the overfilled portion of the conductive material; after the first planarization process is performed, a second planarization process is performed A second planting process to plant another plant material in the dielectric material; and after performing the second planting process, a second planarization process is performed to remove a part of the dielectric material and Part of the conductive material. According to the manufacturing method of the semiconductor structure described in claim 13, wherein the step of planting the cloth plant material includes planting a neutral element in the dielectric material to expand the dielectric material. A compressive force is applied around the conductive part.

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