TWI747778B - Semiconductor device - Google Patents

Abstract

A semiconductor device includes at least one transistor, a shallow well region, a guard ring, and a plurality of first and second doped regions. The transistor is on a substrate and includes a source structure, a gate structure, and a drain structure. The shallow well region surrounds the transistor. The shallow well region has a first conductivity type. The guard ring surrounds the shallow well region. The guard ring has the first conductivity type. The first and second doped regions are disposed within the guard ring and surround the well region. The first doped regions and the second doped regions are alternately arranged in a shape of a loop. Each of the first doped regions and each of the second doped regions have opposite conductivity types.

Description

Semiconductor device

The embodiment of the present invention relates to a semiconductor device, and particularly relates to an integrated circuit having a guard ring for an electrostatic discharge system.

Semiconductor devices can be used in various fields, such as display driver ICs, power management ICs (or high-power power management ICs), discrete power devices, sensing devices, fingerprint sensor ICs, memory, etc. . Semiconductor devices are usually manufactured in the following manner: an insulating or dielectric layer, a conductive layer, and a semiconductor material layer are sequentially deposited on a semiconductor substrate, and various material layers are patterned using lithography technology to form circuit components and element.

Many challenges have arisen in the process of continuing to shrink semiconductor devices. For example, during the manufacturing process, manufacturing, assembly, shipping, packaging, testing, or operation, the semiconductor device may be damaged by electrostatic discharge (ESD). Therefore, semiconductor devices require electrostatic discharge protection to prevent possible electrostatic discharge damage and improve device reliability. Although the ESD protection of existing semiconductor devices has generally met the requirements, it is not completely satisfactory in all aspects.

An embodiment of the present invention provides a semiconductor device, including: at least one transistor on a substrate, the at least one transistor including a source structure, a gate structure, and a drain structure; a shallow well region surrounding the at least one transistor , Wherein the shallow well region has the first conductivity type; the guard ring surrounds the shallow well region, wherein the guard ring has the first conductivity type; and a plurality of first doped regions and a plurality of second doped regions are arranged in the guard ring and surround A shallow well region, wherein the first doped regions and the second doped regions are alternately arranged to form a ring shape, and each of the first doped regions and each of the second doped regions Has the opposite conductivity type.

The following disclosure provides many embodiments or examples for implementing different elements of the embodiments of the present invention. Specific examples of the components and their configurations are described below to simplify the description of the embodiments of the present invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that the first element is formed on the second element, it may include an embodiment in which the first and second elements are in direct contact, or may include additional elements formed between the first and second elements. , So that they do not directly touch the embodiment. In addition, the embodiment of the present invention may repeat reference numerals and/or letters in various examples. Such repetition is for the purpose of conciseness and clarity, and is not used to indicate the relationship between the different embodiments and/or configurations discussed.

In addition, in some embodiments of the present invention, terms related to joining and connecting, such as "connected", "interconnected", etc., unless specifically defined, can mean that two structures are in direct contact, or can also refer to two The structures are not in direct contact, and there are other structures located between the two structures. Moreover, the terms of joining and connecting can also include the case where both structures are movable or both structures are fixed. Furthermore, the term "coupled" includes direct or indirect electrical connection by any method.

Furthermore, spatially relative terms may be used, such as "below", "below", "lower", "above", "higher" and other similar terms to facilitate the description of the picture The relationship between one part(s) or feature(s) and another part(s) or feature(s) in the formula. Spatial relative terms are used to include the different orientations of the device in use or operation, as well as the orientation described in the diagram. When the device is turned in different directions (rotated by 90 degrees or other directions), the spatially relative adjectives used in it will also be interpreted according to the turned position.

The terms "about", "approximately" and "approximately" used in the text usually mean within ±20% of a given value, preferably within ±10%, and more preferably within ±5%, Or within ±3%, or within ±2%, or within ±1%, or within ±0.5%. The values given in the text are approximate values. In the absence of specific instructions, the given value can still imply the meaning of "approximately", "approximately", and "approximately".

Some embodiments of the present invention are described below. Before, during, and/or after the stages described in these embodiments, additional steps may be provided. Some of the stages described can be replaced or omitted in different embodiments. Additional components can be added to the semiconductor device of the embodiment of the present invention. Some components described below can be replaced or deleted in different embodiments. Although some of the discussed embodiments are performed in a specific order of operations, these operations can still be performed in another logical order.

An embodiment of the present invention provides a semiconductor device. A plurality of doped regions with opposite conductivity types arranged on the guard ring of the semiconductor device are alternately arranged. This configuration can improve the reliability of electrostatic discharge protection and semiconductor devices, and reduce the area occupied by the guard ring.

For the convenience of description, some embodiments of the present invention are described in terms of Metal Oxide Semiconductor (MOS) devices. But this disclosure is not limited to this. The embodiments of the present invention can also be applied to various semiconductor devices, such as laterally diffused metal oxide semiconductor (LDMOS) devices, Lateral Insulated Gate Bipolar Transistor (LIGBT), Vertically Diffused Metal Oxide Semiconductor (VDMOS) devices, Extended-Drain Metal Oxide Semiconductor (EDMOS) devices, or other semiconductor devices. In addition, the embodiments of the present invention can also be applied to other types of semiconductor devices, such as diodes, insulated gate bipolar transistors (IGBT), bipolar junction transistors (BJT), Or other semiconductor devices.

Referring to FIG. 1, according to some embodiments of the present invention, a schematic top view of the layout of the semiconductor device 10 is drawn. It should be noted that the three dots in the figure indicate that the components described below can be repeated according to the design or requirements of the desired device. The semiconductor device 10 includes: at least one transistor 119 on a substrate 100, a shallow well region 102, a guard ring 104, and a plurality of first doped regions 111 and a plurality of second doped regions 112. For the sake of clarity, the substrate 100 is not shown in the top view of FIG. 1, and will be shown in the cross-sectional view described below. The substrate 100 may be a doped (for example, doped with p-type or n-type dopants) or an undoped semiconductor substrate. For example, the substrate 100 may include: elemental semiconductors, including silicon or germanium; compound semiconductors, including gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) and/ Or indium antimonide (InSb); alloy semiconductors, including silicon germanium (SiGe) alloy, gallium arsenide (GaAsP) alloy, aluminum indium arsenic (AlInAs) alloy, aluminum gallium arsenide (AlGaAs) alloy, and indium gallium arsenide (GaInAs) alloy , Gallium indium phosphate (GaInP) alloy and/or gallium indium arsenide (GalnAsP) alloy, or a combination of the foregoing materials.

In some embodiments, the substrate 100 may also be a semiconductor-on-insulator (semiconductor-on-insulator) substrate, such as a silicon-on-insulator substrate or a silicon germanium-on-insulator (SGOI) substrate. In other embodiments, the substrate 100 may be a ceramic substrate, such as an aluminum nitride (AlN) substrate, a silicon carbide (SiC) substrate, an aluminum oxide (Al ₂ O ₃ ) substrate (also called a sapphire substrate), or others Substrate. In other embodiments, the substrate 100 may include a ceramic substrate and a pair of barrier layers respectively provided on the upper and lower surfaces of the ceramic substrate. The ceramic substrate may include a ceramic material, and the ceramic material includes an inorganic metal material. For example, the ceramic substrate may include: silicon carbide, aluminum nitride, sapphire substrate, or other suitable materials. The aforementioned sapphire substrate may be alumina.

The transistor 119 is disposed on the substrate 100 and may include a source structure 114, a gate structure 115, and a drain structure 118. In some embodiments, each of the source structure 114 and each of the drain structure 118 includes a doped region, and the doped region of the source structure 114 and the doped region of the drain structure 118 have the same conductivity type. The doping concentration of the doped region of the source structure 114 and the doped region of the drain structure 118 may be about 1E+19 cm ^-3 to 1E+21 cm ^-3 . The method of forming the doped region of the source structure 114 includes (but is not limited to): forming a patterned mask layer (not shown) on the substrate 100 using a lithography process and an etching process, wherein the patterned mask layer is exposed The predetermined area where the doped area is to be formed and covers the rest of the substrate 100; the dopant is implanted in the predetermined area where the doped area is to be formed; and the patterned mask layer is removed. The patterned mask layer can be a hard mask or a photoresist. In the embodiment where the n-type doped region is to be formed, the dopant may be an n-type dopant, such as phosphorous, arsenic, or antimony. In the embodiment where the p-type doped region is to be formed, the dopant may be p-type dopant, such as boron, indium, or BF ₂ . The method of forming the doped region of the drain structure 118 is similar to the method of forming the doped region of the source structure 114. In some embodiments, the doping concentration of the source structure 114 may be the same as the doping concentration of the drain structure 118. In an embodiment, the source structure 114 and the drain structure 118 may be formed in the same process step.

The gate structure 115 may include a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. In some embodiments, the method of forming the gate structure 115 includes: sequentially depositing a blanket dielectric material layer (used to form a gate dielectric layer) and a blanket conductive material layer (used to form a gate electrode) on the On the dielectric material layer, the dielectric material layer and the conductive material layer are respectively patterned through a lithography and etching process to form a gate dielectric layer and a gate electrode. In some embodiments, the source structure 114 and the drain structure 118 may be disposed on both sides of the gate structure 115.

Referring to FIG. 1, the shallow well region 102 surrounds the transistor 119. In some embodiments, the shallow well region 102 has the first conductivity type, which is the same as the conductivity type of the doped region 114 of the source structure S and the doped region 118 of the drain structure D. The protection ring 104 surrounds the shallow well area 102. In some embodiments, the guard ring 104 has the first conductivity type. The doping concentration of the guard ring 104 may be about 1 E+16 cm ^-3 to 1 E+17 cm ^-3 . The method of forming the shallow well region 102 and the method of forming the guard ring 104 can be similar to the method of forming the source structure 114.

A plurality of first doped regions 111 and a plurality of second doped regions 112 are formed in the guard ring 104 and surround the shallow well region 102. In the top view, the first doped regions 111 and the second doped regions 112 are alternately arranged in a ring shape. The method of forming a plurality of first doped regions 111 includes (but is not limited to): forming a patterned mask layer (not shown) on the guard ring 104 using a lithography process and an etching process, wherein the patterned mask layer Expose the predetermined area where the first doped region 111 will be formed and cover the remaining areas; implant dopants into the predetermined area where the first doped region 111 will be formed; and remove the patterned mask layer. The patterned mask layer can be a hard mask or a photoresist. The method of forming the second doped region 112 is similar to the method of forming the first doped region 111. According to some embodiments of the present invention, each of the first doped regions 111 and each of the second doped regions 112 have opposite conductivity types. For example, in an embodiment where the first doped region 111 is n-type, the dopant used to implant the second doped region 112 is a p-type dopant (for example: boron, indium or BF2) to form p Type second doped region 112; in the embodiment where the first doped region 111 is p-type, the dopant used to implant the second doped region 112 is n-type dopant (for example: phosphorus, arsenic or antimony) . The doping concentration of the first doping region 111 and the doping concentration of the second doping region 112 may be about 1E+19 cm ^-3 to 1E+21 cm ^-3 . In some embodiments, the first doped region 111 and the second doped region 112 have the same doping concentration. In some embodiments, the number of second doped regions 112 is equal to the number of first doped regions 111. In an alternative embodiment, the number of second doped regions 112 may not be equal to the number of first doped regions 111.

In some embodiments, the length of the first doped region 111 is smaller than the length of the second doped region 112, as shown in FIG. In such an embodiment, if the first doped region 111 is n-type and the second doped region 112 is p-type, the first doped region 111 and the second doped region 112 form a silicon controlled rectifier with a PNP path (Silicon controlled rectifier, SCR) structure, and the first doped region 111 is used to provide potential, so a very large first doped region 111 is not required. In some embodiments, the length ratio of the first doped region 111 to the second doped region is about 1/10. However, in other embodiments, the length of the first doped region 111 may be greater than or equal to the length of the second doped region 112. In some embodiments according to the present invention, the first doped region 111 and the second doped region 112 form a rectangular shape, as shown in FIG. 1. In addition, there is at least one first doped region 111 and at least one second doped region 112 on each side of the rectangular shape. However, in other embodiments, the shape formed by the first doped region 111 and the second doped region 112 is not limited. For example, the first doped region 111 and the second doped region 112 may form an oval shape or a stadium track shape. This shape can be adjusted according to actual needs. The first doped region 111 and the second doped region 112 can prevent electrostatic discharge damage. In some embodiments, each of the first doped regions 111 and each of the second doped regions 112 are spaced apart and separated from each other. For example, each of the first doped regions 111 and each of the second doped regions 112 may be separated by a guard ring 104. The distance between the first doped region 111 and the adjacent second doped region 112 can be adjusted according to actual needs. In some embodiments, the doping concentration of the first doping region 111 is equal to the doping concentration of the second doping region 112. In some embodiments, the doping concentration of the first doping region 111 and the doping concentration of the second doping region 112 are greater than the doping concentration of the guard ring 104. For example, the doping concentration of the first doped region 111 is about 1E+19 cm ^-3 to 1E+21 cm ^-3 , and the doping concentration of the second doped region 112 is about 1E+19 cm ^-3 to 1E +21 cm ^-3 , and the doping concentration of the guard ring 104 is about 1E+16 cm ^-3 to 1E+17 cm ^-3 . According to some embodiments of the present invention, the first doped region 111, the second doped region 112, and the drain structure 118 are electrically connected.

Referring to FIG. 1, in some embodiments, the semiconductor device 10 further includes at least two third doped regions 113, which are respectively disposed on both sides of the transistor 119, and the at least two third doped regions 113 have the same value as the first The second conductivity type with the opposite conductivity type. The doping concentration of the third doping region 113 is about 1E+19 cm ^-3 to 1E+21 cm ^-3 . In some embodiments, the second doped region 112 and the third doped region 113 have the same doping concentration. In some embodiments, the third doped region 113 can be used to form a PNPN path in the device. The function of the PNPN path will be described in more detail below. In some embodiments, the at least two third doped regions 113, the source structure 114, the gate structure 115, and the shallow well region 102 are electrically connected. In other embodiments, the at least two third doped regions 113, the source structure 114, the gate structure 115, and the shallow well region 102 are electrically connected to the ground. In some embodiments, at least one third doped region 113 is adjacent to the source structure 114.

According to some embodiments of the present invention, the semiconductor device 10 includes a plurality of transistors 119. As shown in FIG. 1, each of the transistors 119 includes a source structure 114 and a gate structure 115. In addition, a drain structure 118 is disposed between two adjacent transistors 119, so that the two adjacent transistors 119 share the drain structure 118. In some embodiments, the drain structure 118, the first doped region 111, and the second doped region 112 are electrically connected. As shown in FIG. 1, in some embodiments, the third doped region 113 is disposed on both sides of the plurality of transistors 119 and between adjacent source structures 114 of the plurality of transistors 119. In some embodiments, the third doped region 113, the source structure 114 and the gate structure 115 in the plurality of transistors 119, and the shallow well region 102 are electrically connected. In other embodiments, the third doped region 113, the source structure 114 and the gate structure 115 in the plurality of transistors 119, and the shallow well region 102 are electrically connected to the ground.

FIG. 2 is a schematic cross-sectional view of the semiconductor device 10 along the line AA in FIG. 1 according to some embodiments of the present invention. It should be understood that, for the sake of clarity, some components in Figure 2 are not shown in Figure 1. As shown in FIG. 2, the semiconductor device 10 includes a buried layer 101 provided on a substrate 100. In some embodiments, the buried layer 101 has the first conductivity type. The doping concentration of the buried layer 101 may be about 1E+16 cm ^-3 to 1E+17 cm ^-3 .

Referring to FIG. 2, the semiconductor device 10 includes well regions 105a, 105b, 105c, 106a, 106b, 107a, 107b, and 107c. In some embodiments, the well regions 105a, 105b, 105c, 107a, 107b, and 107c have the second conductivity type, and the well regions 106a and 106b have the first conductivity type. The doping concentration of the well regions 105a, 105b, 105c, 106a, and 106b may be about 1E+17 cm ^-3 to 1E+19 cm ^-3 . The doping concentration of the well regions 107a, 107b, and 107c may be about 1E+18 cm ^-3 to 1E+20 cm ^-3 . The method of forming these well regions is similar to the method of forming the doped regions of the source structure 114 described above. The well regions 105a, 105b, 105c, 106a, and 106b are provided on the buried layer 101. Each of the well regions 106a and 106b includes a drain structure 118 disposed therein. The well areas 107a, 107b, and 107c are provided in the well areas 105a, 105b, and 105c, respectively. The shallow well region 102 is disposed in the well regions 107a and 107c, and each of the well regions 107a and 107c includes a third doped region 113 and a source structure 114 disposed therein. The well region 107b includes two source structures 114 and a third doped region 113 disposed between the two source structures 114. The gate structure 115 is disposed on the well regions 106 a and 106 b and between the adjacent source structure 114 and the drain structure 118 to form a transistor 119. As described above, two adjacent transistors 119 share a drain structure 118 disposed between them. For example, the source structure 114 in the well region 107a, the drain structure 118 in the well region 106a, and the gate structure 115 between the source structure 114 and the drain structure 118 form a transistor 119. The source structure 114 in the well region 107b and adjacent to the drain structure 118 in the well region 106a, the drain structure 118 in the well region 106a, and the gate between the source structure 114 and the drain structure 118 The structure 115 forms another transistor 119. In this way, the two adjacent transistors 119 share the drain structure 118 in the well region 106a. In some embodiments, the first doped region 111, the second doped region 112, and the drain structure 118 are electrically connected to a first voltage, such as a power supply voltage VCC. In some embodiments, the shallow well region 102, the third doped region 113, the source structure 114, and the gate structure 115 are electrically connected to a second voltage, such as the power VSS or the ground GND. In some embodiments, the first voltage is the power supply voltage and the second voltage is grounded. In some embodiments, the first voltage is greater than the second voltage. In other embodiments, the first voltage is less than the second voltage. In some embodiments, the gate structure 115 is disposed on the well regions 105a and 106a, the drain structure 118 is disposed in the well region 106a, and the source structure 114, the shallow well region 102 and the at least one third doped region 113 are disposed on Well area 105a. In some embodiments, the guard ring 104, the well regions 105a, 105b, and 105c are directly connected to the buried layer. In some embodiments, the well region 107a (or 107c) in the well region 105a (or 105c) surrounds the corresponding source structure 114, the shallow well region 102, and at least one third doped region 113. In some embodiments, the semiconductor 10 may further include a field plate 117 disposed on the gate structure 115 and a dielectric layer 116 disposed between the field plate 117 and the gate structure 115, as shown in FIG. 2.

In some embodiments, the well regions 105a, 105c, 107a, 107c and the second doped region 112 have the second conductivity type, and the shallow well region 102 and the guard ring 104 have the first conductivity type, which can be removed from the second doped region 112 A PNPN path is formed to the shallow well region 102 or from the shallow well region 102 to the second doped region 112. For example, if the first conductivity type is n-type and the second conductivity type is p-type, the second doped region 112 (p-type), guard ring 104 (n-type), well regions 105a and 107a (p-type), And the shallow well area 102 (n-type) form a PNPN path. Similarly, the second doped region 112 (p-type), guard ring 104 (n-type), well regions 105c and 107c (p-type), and shallow well region 102 (n-type) form a PNPN path. Conversely, if the first conductivity type is p-type and the second conductivity type is n-type, shallow well region 102 (p-type), well regions 105a and 107a (n-type), guard ring 104 (p-type), and second doped The miscellaneous region 112 (n-type) forms a PNPN path. The PNPN path in the semiconductor device can prevent electrostatic discharge damage. The above description is only one of the objectives of the present invention, and is not intended to limit the scope of the present invention.

In some embodiments, the semiconductor device 10 includes isolation regions (not shown in FIG. 1), such as isolation regions 120, 122, 124. The isolation area 120 is arranged between the shallow well area 102 and the protection ring 104. The isolation region 122 is disposed between the shallow well region 102 and the third doping region 113 in the well regions 107a and 107c, and the isolation region 124 is disposed between the third doping region 113 and the source structure 114 in the well region 107b. In some embodiments, the isolation region 122 is disposed between the corresponding shallow well region 102 and one of the third doped regions 113 adjacent to the shallow well region 102. The isolation region may include shallow trench isolation (STI), local oxidation of silicon (LOCOS), or a combination of the foregoing. In some embodiments, the process of forming shallow trench isolation includes: forming a mask layer (not shown) on the corresponding well region and patterning the mask layer, using the patterned mask layer as an etching mask, Etch trenches (or trenches) in the substrate, perform a deposition process to fill the trenches (or trenches) with isolation material, and perform a planarization process, such as chemical mechanical polishing (CMP) Process or mechanical grinding (mechanical grinding) process to remove the excess part of the isolation material. The isolation material can include oxides, nitrides or oxynitrides, such as silicon oxide (SiO2), carbon-doped silicon oxide (SiO _x C), silicon oxynitride (SiON), silicon oxycarbonitride (silicon-oxy -carbon nitride, SiOCN), silicon carbide (SiC), silicon carbon nitride (SiCN), silicon nitride (Si _x N _y or SiN), silicon oxycarbide (SiCO), any other suitable materials, Or any combination of the foregoing. In some embodiments, the silicon partial oxidation process for forming the isolation region may include: depositing a mask layer (for example, a silicon nitride layer) on the corresponding well region, and patterning the mask layer by using a photolithography process and an etching process Exposing a portion of the corresponding well region, thermally oxidizing the exposed portion of the corresponding well region to form a silicon oxide layer, and removing the patterned mask layer. The isolation regions described can be formed in the same manufacturing process, or can be formed in different manufacturing processes.

One or more embodiments of the present invention provide many advantages for semiconductor devices. For example, compared to the comparative example shown in FIG. 3, the doped regions 121 and 123 are arranged in parallel and surround the shallow well region 102 of the semiconductor device 20. The embodiment of the present invention provides a more space-saving layout by alternately arranging doped regions 111 and 112 in the guard ring 104 surrounding the shallow well region 102 of the semiconductor 10. The device obtained by the embodiment of the present invention passed 8 kV in the Human-Body Model (HBM) test, while the comparative example failed in the human-Body Model (HBM) test over 1 kV. In addition, referring to FIGS. 4A and 4B, the transmission line pulse (TLP) test results of the comparative example and an example of the present invention are respectively shown. The bottom horizontal axis represents the transmission line pulse voltage, the top horizontal axis represents the leakage current on a logarithmic scale, and the vertical axis represents the transmission line pulse current. Compared with the comparative example, in the substantially same transmission line pulse current range, the example of the present invention has a relatively stable leakage current and provides a stable result. The embodiments of the present invention provide semiconductor devices with significantly better human body model test results (passing 8kV) and stable leakage current, so as to improve electrostatic discharge protection and device reliability. Due to the better turn-on efficiency of the silicon controlled rectifier, the present disclosure is more reliable for self-protection against electrostatic discharge. The advantages described above are examples of the purpose of the present invention, and are not intended to limit the scope of the present invention.

The components of several embodiments are summarized above, so that those with ordinary knowledge in the technical field of the present invention can more easily understand the viewpoints of the embodiments of the present invention. Those with ordinary knowledge in the technical field of the present invention should understand that they can design or modify other manufacturing processes and structures based on the embodiments of the present invention to achieve the same purposes and/or advantages as the embodiments described herein. Those with ordinary knowledge in the technical field of the present invention should also understand that such equivalent manufacturing processes and structures do not depart from the spirit and scope of the present invention, and they can do so without departing from the spirit and scope of the present invention. Make all kinds of changes, substitutions and replacements.

10: Semiconductor device 100: substrate 101: Buried layer 102: Asai District 104: Protective ring 105a, 105b, 105c, 106a, 106b, 107a, 107b, 107c: well area 111: first doped region 112: second doped region 113: third doped region 114: source structure 115: gate structure 118: Drain structure 119: Transistor 120, 122, 124: Quarantine area 121, 123: doped area 20: Semiconductor device

The embodiments of the present invention can be best understood from the following detailed description in conjunction with the accompanying drawings. According to standard practices in the industry, various features are not drawn to scale. In fact, the size of various components can be arbitrarily enlarged or reduced to clearly show the characteristics of the embodiments of the present invention. FIG. 1 is a schematic top view showing the layout of a semiconductor device according to some embodiments of the present invention. FIG. 2 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present invention. Figure 3 depicts a schematic top view of the layout of the comparative example. 4A and 4B show diagrams of the transmission line pulse test and the leakage test of the comparative example and the example of the present disclosure.

10: Semiconductor device

102: Asai District

104: Protective ring

111: first doped region

112: second doped region

113: third doped region

114: source structure

115: gate structure

118: Drain structure

119: Transistor

Claims (20)

A semiconductor device including: At least one transistor, on a substrate, at least one transistor including a source structure, a gate structure, and a drain structure; A shallow well region surrounding the at least one transistor, wherein the shallow well region has a first conductivity type; A protection ring surrounding the shallow well area, wherein the protection ring has the first conductivity type; and A plurality of first doped regions and a plurality of second doped regions are arranged in the guard ring and surround the shallow well region, wherein the first doped regions and the second doped regions are alternately arranged to form a ring Shape, and each of the first doped regions and each of the second doped regions has opposite conductivity types. The semiconductor device of claim 1, wherein the length of the first doped regions is less than or equal to the length of the second doped regions. Such as the semiconductor device of claim 1, further comprising at least one third doped region disposed adjacent to the source structure. The semiconductor device of claim 3, wherein the second doping regions and the at least one third doping region have the same doping concentration. For example, the semiconductor device of claim 1, further comprising a buried layer disposed on the substrate, wherein the buried layer has the first conductivity type. For example, the semiconductor device of claim 5, further comprising a first well region having the first conductivity type and a second well region having a second conductivity type opposite to the first conductivity type, wherein the gate structure is provided On the first well region and the second well region, the drain structure is disposed in the first well region, and the source structure, the shallow well region, and the at least one third doped region are disposed on the first well region. In the Erjing District. The semiconductor device of claim 6, wherein the guard ring and the second well region are directly connected to the buried layer. According to claim 6, the semiconductor device further includes a third well region disposed in the second well region and surrounding the source structure, the shallow well region and the at least one third doped region. The semiconductor device of claim 8, wherein the second doped regions, the guard ring, the second well region and the third well region, and the shallow well region form a PNPN structure. The semiconductor device of claim 1, wherein each of the first doped regions and each of the second doped regions are separated. The semiconductor device of claim 1, wherein the doping concentration of the first doping regions and the doping concentration of the second doping regions are greater than the doping concentration of the guard ring. The semiconductor device of claim 1, wherein the drain structure, the first doped regions, and the second doped regions are electrically connected. The semiconductor device of claim 1, wherein the at least one transistor is a plurality of transistors, each of the transistors includes the source structure and the gate structure, wherein two adjacent transistors are shared in The drain structure between the two. For example, the semiconductor device of claim 13, further comprising at least two third doped regions, which are respectively arranged on both sides of the transistors, wherein the at least two third doped regions have a conductivity type opposite to that of the first conductivity type. A second conductivity type. For example, the semiconductor device of claim 14 further includes an isolation region disposed between the shallow well region and one of the third doped regions adjacent to the shallow well region. The semiconductor device of claim 14, wherein the drain structure, the first doped regions, and the second doped regions are electrically connected to a first voltage. The semiconductor device of claim 16, wherein the at least two third doped regions, the source structure, the gate structure, and the shallow well region are electrically connected to a second voltage. The semiconductor device of claim 17, wherein the first voltage is greater than the second voltage. For example, the semiconductor device of claim 1, further comprising an isolation region disposed between the shallow well region and the first doped regions and the second doped regions. For example, the semiconductor device of claim 1, further comprising: a field plate disposed on the gate structure, and a dielectric layer disposed between the field plate and the gate structure.

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