TWI747442B - Semiconductor memory device and its reading method - Google Patents

Abstract

The embodiments of the present invention provide a semiconductor memory device and a reading method thereof that can suppress the occurrence of read errors. The semiconductor memory device of the embodiment includes: a NAND string having first and second memory cells connected in series and adjacent to each other; a first character line connected to the gate of the first memory cell; and a second character line , Which is connected to the gate of the second memory cell; bit line, which is connected to the NAND string; and a sense amplifier, which includes a sense node, a first transistor connected between the sense node and the bit line, And latch circuit. The semiconductor memory device can perform a reading operation including a first reading operation and a second reading operation. In the read operation of selecting the first word line, in the first read operation, the first read voltage is applied to the second word line, and the sensing node is passed through the first read voltage during the period when the first read voltage is applied. 1 The transistor is connected to the bit line. After the sensing node is connected to the bit line via the first transistor, the first data based on the voltage of the sensing node is stored in the latch circuit. During the second read operation, The second read voltage is applied to the first word line. During the period when the second read voltage is applied, the sensing node is connected to the bit line via the first transistor at the first time, and the sensing node is connected to the bit line via the first transistor at the first time. After the crystal is connected to the bit line at the first time, the second data based on the voltage of the sensing node is stored in the latch circuit. After the second data is stored in the latch circuit, during the period when the second read voltage is applied, Connect the sensing node to the bit line through the first transistor at a second time different from the first time. After the sensing node is connected to the bit line at the second time through the first transistor, it will be based on the sensing node The third data of the voltage is stored in the latch circuit.

Description

Semiconductor memory device and its reading method

The embodiment relates to a semiconductor memory device and a reading method thereof.

Known are NAND (Not AND) type flash memory that can store data non-volatilely.

The embodiment provides a semiconductor memory device and a reading method thereof capable of suppressing the occurrence of read errors.

The semiconductor memory device of the embodiment includes: a NAND string having first and second memory cells connected in series and adjacent to each other; a first character line connected to the gate of the first memory cell; and a second character line , Which is connected to the gate of the second memory cell; bit line, which is connected to the NAND string; and a sense amplifier, which includes a sense node, a first transistor connected between the sense node and the bit line, And latch circuit. The semiconductor memory device can perform a reading operation including a first reading operation and a second reading operation. In the read operation of selecting the first word line, in the first read operation, the first read voltage is applied to the second word line, and the sensing node is passed through the first read voltage during the period when the first read voltage is applied. 1 The transistor is connected to the bit line. After the sensing node is connected to the bit line via the first transistor, the first data based on the voltage of the sensing node is stored in the latch circuit. During the second read operation, The second read voltage is applied to the first word line. During the period when the second read voltage is applied, the sensing node is connected to the bit line via the first transistor at the first time, and the sensing node is connected to the bit line via the first transistor at the first time. After the crystal is connected to the bit line at the first time, the second data based on the voltage of the sensing node is stored in the latch circuit. After the second data is stored in the latch circuit, during the period when the second read voltage is applied, Connect the sensing node to the bit line through the first transistor at a second time different from the first time. After the sensing node is connected to the bit line at the second time through the first transistor, it will be based on the sensing node The third data of the voltage is stored in the latch circuit.

Hereinafter, the embodiments will be described with reference to the drawings. Each embodiment illustrates an apparatus and method for realizing the technical idea of the invention. The drawings are schematic or conceptual drawings, and the sizes and proportions of the drawings are not necessarily the same as the actual objects. The technical idea of the present invention is not specified by the shape, structure, and arrangement of the constituent elements.

In addition, in the following description, components having substantially the same function and configuration are denoted by the same reference numerals. The digits after the characters constituting the reference symbol are referenced by the reference symbol containing the same character, and are used to distinguish elements with the same composition from each other. When there is no need to distinguish the elements represented by the reference signs containing the same characters from each other, these elements are respectively referred to by the reference signs containing only the characters.

[1] The first embodiment Hereinafter, the semiconductor memory device 1 of the first embodiment will be described.

[1-1] Configuration of semiconductor memory device 1 [1-1-1] Overall structure of semiconductor memory device 1 FIG. 1 shows a configuration example of the semiconductor memory device 1 of the first embodiment. The semiconductor memory device 1 is a NAND flash memory capable of non-volatile storage of data, and can be controlled by an external memory controller 2. As shown in FIG. 1, the semiconductor memory device 1 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a column decoder module 15, and a sense amplifier. Module 16.

The memory cell array 10 includes a plurality of blocks BLK0-BLK(N-1) (N is an integer greater than 1). The block BLK includes a collection of a plurality of memory cells capable of non-volatile memory data, for example, used as a data erasure unit. In addition, a plurality of bit lines and a plurality of character lines are arranged in the memory cell array 10. Each memory cell is associated with, for example, one bit line and one character line. The detailed structure of the memory cell array 10 will be described in detail below.

The command register 11 holds the command CMD received by the semiconductor memory device 1 from the memory controller 2. The command CMD includes, for example, a command for the sequencer 13 to perform a read operation, a write operation, an erase operation, and the like.

The address register 12 holds the address information ADD received by the semiconductor memory device 1 from the memory controller 2. The address information ADD includes, for example, a block address BAd, a page address PAd, and a row address CAd. For example, the block address BAd, the page address PAd and the row address CAd are respectively used for the selection of the block BLK, the word line and the bit line.

The sequencer 13 controls the overall operation of the semiconductor memory device 1. For example, the sequencer 13 controls the driver module 14, the column decoder module 15, and the sense amplifier module 16, etc., based on the command CMD held in the command register 11, and performs reading, writing, and erasing operations. In addition to actions and so on.

The driver module 14 generates voltages used in reading operations, writing operations, and erasing operations. In addition, the driver module 14 applies the generated voltage to the signal line corresponding to the selected word line based on the page address PAd held in the address register 12, for example.

The column decoder module 15 selects a block BLK in the corresponding memory cell array 10 based on the block address BAd held in the address register 12. In addition, the column decoder module 15 transmits the voltage applied to the signal line corresponding to the selected character line to the selected character line in the selected block BLK, for example.

In the write operation, the sense amplifier module 16 applies a desired voltage to each bit line according to the write data DAT received from the memory controller 2. In addition, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line during the read operation, and transmits the determination result to the memory controller 2 in the form of read data DAT.

The communication between the semiconductor memory device 1 and the memory controller 2 supports the NAND interface standard, for example. For example, in the communication between the semiconductor memory device 1 and the memory controller 2, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal WEn, the read enable signal REn, Ready/busy signal RBn and input/output signal I/O.

The command latch enabling signal CLE is a signal indicating that the input/output signal I/O received by the semiconductor memory device 1 is the command CMD. The address latch enable signal ALE is a signal indicating that the input/output signal I/O received by the semiconductor memory device 1 is the address information ADD. The write enable signal WEn is a signal that commands the input of the input/output signal I/O to the semiconductor memory device 1. The read enable signal REn is a signal that commands the output of the input/output signal I/O to the semiconductor memory device 1. The ready/busy signal RBn is a signal that informs the memory controller 2 which of the ready state and the busy state of the semiconductor memory device 1 is. The ready state is the state in which the semiconductor memory device 1 accepts commands, and the busy state is the state in which the semiconductor memory device 1 does not accept commands. The input and output signal I/O is, for example, an 8-bit width signal, which may include command CMD, address information ADD, data DAT, etc.

The semiconductor memory device 1 and the memory controller 2 described above can also be combined to form one semiconductor device. Examples of such semiconductor devices include memory cards such as SD (Secure Digital) ^TM cards, and SSD (solid state drive).

[1-1-2] Circuit configuration of semiconductor memory device 1 (About the circuit configuration of the memory cell array 10) FIG. 2 shows an example of the circuit configuration of the memory cell array 10 included in the semiconductor memory device 1 of the first embodiment by selecting one block BLK among the plurality of blocks BLK included in the memory cell array 10. As shown in FIG. 2, the block BLK includes, for example, four string units SU0 to SU3.

Each string unit SU includes a plurality of NAND strings NS respectively associated with bit lines BL0 to BLm (m is an integer greater than or equal to 1). Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, and select transistors ST1 and ST2. The memory cell transistor MT includes a control gate and a charge storage layer, and holds data non-volatilely. The selection transistors ST1 and ST2 are respectively used for the selection of the string unit SU during various actions.

In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series. The drain of the selected transistor ST1 is connected to the associated bit line BL, and the source of the selected transistor ST1 is connected to one end of the memory cell transistors MT0 to MT7 connected in series. The drain of the selective transistor ST2 is connected to the other end of the memory cell transistors MT0 to MT7 connected in series. The source of the selective transistor ST2 is connected to the source line SL.

In the same block BLK, the control gates of the memory cell transistors MT0～MT7 are respectively connected to the word lines WL0～WL7 in common. The gates of the selection transistors ST1 in the string units SU0 to SU3 are respectively connected to the selection gate lines SGD0 to SGD3 in common. The gates of the selection transistors ST2 included in the same block BLK are commonly connected to the selection gate line SGS.

In the circuit configuration of the memory cell array 10 described above, the bit line BL is shared by the NAND strings NS assigned the same row address in each string unit SU. The source line SL is, for example, shared by a plurality of blocks BLK.

An example of a collection of a plurality of memory cell transistors MT connected to the common word line WL in a string unit SU is called a cell unit CU. For example, the memory capacitor including the cell unit CU of the memory cell transistor MT that respectively stores 1 bit of data is defined as "1 page of data". The cell unit CU can correspond to the number of bits of the data stored in the memory cell transistor MT, and has a memory capacitor with more than 2 pages of data.

Furthermore, the circuit configuration of the memory cell array 10 included in the semiconductor memory device 1 of the first embodiment is not limited to the configuration described above. For example, the number of string units SU included in each block BLK, or the number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS may be any number, respectively.

(About the circuit configuration of column decoder module 15) FIG. 3 shows an example of the circuit configuration of the row decoder module 15 included in the semiconductor memory device 1 of the first embodiment. As shown in FIG. 3, the column decoder module 15 includes, for example, column decoders RD0 to RD(N-1), and is connected to the driver module 14 via signal lines CG0 to CG7, SGDD0 to SGDD3, SGSD, USGD, and USGS. The column decoders RD0-RD(N-1) are respectively associated with the blocks BLK0-BLK(N-1).

Hereinafter, focusing on the column decoder RD0 corresponding to the block BLK0, the detailed circuit configuration of the column decoder RD will be described. The column decoder RD includes, for example, a block decoder BD, transmission gate lines TG and bTG, and transistors TR0 to TR17.

The block decoder BD decodes the block address BAd. In addition, the block decoder BD applies predetermined voltages to the transmission gate lines TG and bTG, respectively, based on the decoding result. The voltage applied to the transmission gate line TG and the voltage applied to the transmission gate line bTG have a complementary relationship. In other words, the inverted signal of the transmission gate line TG is input to the transmission gate line bTG.

The transistors TR0 to TR17 are high voltage N-type MOS (Metal Oxide Semiconductor) transistors. The respective gates of the transistors TR0 to TR12 are commonly connected to the transmission gate line TG. The respective gates of the transistors TR13 to TR17 are commonly connected to the transmission gate line bTG. In addition, each transistor TR is connected between the signal line wired from the driver module 14 and the wiring provided on the corresponding block BLK.

Specifically, the drain of the transistor TR0 is connected to the signal line SGSD. The source of the transistor TR0 is connected to the select gate line SGS. The drains of the transistors TR1 to TR8 are respectively connected to the signal lines CG0 to CG7. The respective sources of the transistors TR1 to TR8 are respectively connected to the word lines WL0 to WL7. The drains of the transistors TR9 to TR12 are respectively connected to the signal lines SGDD0 to SGDD3. The respective sources of the transistors TR9 to TR12 are respectively connected to the selection gate lines SGD0 to SGD3. The drain of the transistor TR13 is connected to the signal line USGS. The source of the transistor TR13 is connected to the select gate line SGS. The respective drains of the transistors TR14 to TR17 are commonly connected to the signal line USGD. The respective sources of the transistors TR14 to TR17 are respectively connected to the selection gate lines SGD0 to SGD3.

That is, the signal lines CG0 to CG7 are used as global word lines shared by a plurality of blocks BLK, and the word lines WL0 to WL7 are used as local word lines provided for each block BLK. In addition, the signal lines SGDD0 ~ SGDD3 and SGSD are used as global transmission gate lines shared by a plurality of blocks BLK, and the selection gate lines SGD0 ~ SGD3 and SGS are used as local transmission gates for each block BLK. String.

According to the above configuration, the column decoder module 15 can select the block BLK. Specifically, in various actions, the block decoder BD corresponding to the selected block BLK applies the voltages of the "H (High, high)" level and the "L (Lower, low)" level to The transmission gate lines TG and bTG, and the block decoder BD corresponding to the non-selected block BLK applies voltages at the "L" level and "H" level to the transmission gate lines TG and bTG, respectively.

Furthermore, the circuit configuration of the decoder module 15 described above is only an example, and can be changed as appropriate. For example, the number of transistors TR included in the column decoder module 15 is designed based on the number of wires arranged in each block BLK.

(About the circuit configuration of the sense amplifier module 16) FIG. 4 shows an example of the circuit configuration of the sense amplifier module 16 included in the semiconductor memory device 1 of the first embodiment. As shown in FIG. 4, each sense amplifier unit SAU includes, for example, a bit line connection portion BLHU, a sense amplifier portion SA, a logic circuit LC, and latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and XDL.

The bit line connection part BLHU includes a high-resistance piezoelectric crystal connected between the associated bit line BL and the sense amplifier part SA. The sense amplifier section SA, the logic circuit LC, and the latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and XDL are commonly connected to the bus LBUS. The latch circuits SDL, ADL, BDL, CDL, DDL, EDL and XDL can send and receive data to and from each other.

The control signal STB generated by the sequencer 13, for example, is input to each sense amplifier section SA. Furthermore, the sense amplifier section SA determines whether the data read to the associated bit line BL is "0" or "1" based on the time when the control signal STB is validated. That is, the sense amplifier section SA judges the data stored in the selected memory cell based on the voltage of the bit line BL.

The logic circuit LC uses the data held in the latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and XDL connected to the common bus LBUS to perform various logic operations. Specifically, for example, the logic circuit LC can use the data held by two latch circuits of the latch circuits provided in each sense amplifier unit SAU to perform AND operation, OR operation, and NAND operation. , NOR (NOT-OR, inverse OR) operation, EXNOR (Exclusive-NOR, mutually exclusive OR) operation, etc.

The latch circuits SDL, ADL, BDL, CDL, DDL, EDL and XDL respectively temporarily hold data. The latch circuit XDL is used for the input and output of the data DAT between the input/output circuit of the semiconductor memory device 1 and the sense amplifier unit SAU. In addition, the latch circuit XDL can also be used as, for example, the cache memory of the semiconductor memory device 1. As long as at least the latch circuit XDL is idle, the semiconductor memory device 1 can become a ready state.

FIG. 5 shows an example of the circuit configuration of the sense amplifier unit SAU of the semiconductor memory device 1 of the first embodiment. As shown in FIG. 5, for example, the sense amplifier section SA includes transistors 20-27 and a capacitor 28, and the bit line connection section BLHU includes a transistor 29. The transistor 20 is a P-type MOS transistor. The transistors 21-27 are respectively N-type MOS transistors. Transistor 29 is an N-type MOS transistor with a higher withstand voltage than each of transistors 20-27.

The source of the transistor 20 is connected to the power line. The drain of the transistor 20 is connected to the node ND1. The node of the transistor 20 is connected to, for example, the node SINV in the latch circuit SDL. The drain of the transistor 21 is connected to the node ND1. The source of the transistor 21 is connected to the node ND2. The control signal BLX is input to the node of the transistor 21. The drain of the transistor 22 is connected to the node ND1. The source of the transistor 22 is connected to the node SEN. The control signal HLL is input to the node of the transistor 22.

The drain of the transistor 23 is connected to the node SEN. The source of the transistor 23 is connected to the node ND2. The control signal XXL is input to the node of the transistor 23. The drain of the transistor 24 is connected to the node ND2. The control signal BLC is input to the node of the transistor 24. The drain of the transistor 25 is connected to the node ND2. The source of the transistor 25 is connected to the node SRC. The node of the transistor 25 is connected to, for example, the node SINV in the latch circuit SDL.

The source of the transistor 26 is grounded. The node of the transistor 26 is connected to the node SEN. The drain of the transistor 27 is connected to the bus LBUS. The source of the transistor 27 is connected to the drain of the transistor 26. The control signal STB is input to the node of the transistor 27. One electrode of the capacitor 28 is connected to the node SEN. The clock CLK is input to the other electrode of the capacitor 28.

The drain of the transistor 29 is connected to the source of the transistor 24. The source of the transistor 29 is connected to the bit line BL. The control signal BLS is input to the node of the transistor 29.

The latch circuit SDL includes, for example, inverters 30 and 31 and N-type MOS transistors 32 and 33. The input node of the inverter 30 is connected to the node SLAT, and the output node of the inverter 30 is connected to the node SINV. The input node of the inverter 31 is connected to the node SINV, and the output node of the inverter 31 is connected to the node SLAT. One end of the transistor 32 is connected to the node SINV, the other end of the transistor 32 is connected to the bus LBUS, and the control signal STI is input to the node of the transistor 32. One end of the transistor 33 is connected to the node SLAT, the other end of the transistor 33 is connected to the bus LBUS, and the control signal STL is input to the node of the transistor 33. For example, the data held at the node SLAT is equivalent to the data held in the latch circuit SDL, and the data held at the node SINV is equivalent to the inverted data of the data held in the node SLAT.

The circuit configuration of the latch circuits ADL, BDL, CDL, DDL, EDL, and XDL is the same as the circuit configuration of, for example, the latch circuit SDL. For example, the latch circuit ADL holds data at the node ALAT, and holds its inverted data at the node AINV. Also, for example, the control signal ATI is input to the node of the transistor 32 of the latch circuit ADL, and the control signal ATL is input to the node of the transistor 33 of the latch circuit ADL. The description of the latch circuits BDL, CDL, DDL, EDL, and XDL is omitted.

In the circuit configuration of the sense amplifier unit SAU described above, for example, the power supply voltage VDD is applied to the power supply line connected to the source of the transistor 20. For example, the ground voltage VSS is applied to the node SRC. The control signals BLX, HLL, XXL, BLC, STB and BLS, and the clock CLK are respectively generated by the sequencer 13, for example. The node SEN may be referred to as a sensing node of the sense amplifier section SA.

Furthermore, the sense amplifier module 16 included in the semiconductor memory device 1 of the first embodiment is not limited to the circuit configuration described above. For example, the number of latch circuits included in each sense amplifier unit SAU can be appropriately changed based on the number of pages memorized in one cell unit CU. If only the latch circuit in the sense amplifier unit SAU can perform logic operations, the logic circuit LC in the sense amplifier unit SAU can be omitted.

[1-1-3] Structure of semiconductor memory device 1 Hereinafter, an example of the structure of the memory cell array 10 included in the semiconductor memory device 1 of the first embodiment will be described. Furthermore, in the drawings referred to below, the X direction corresponds to the extension direction of the selection gate line SGD, the Y direction corresponds to the extension direction of the bit line BL, and the Z direction corresponds to the vertical direction relative to the surface of the semiconductor substrate ( Laminating direction), the semiconductor substrate is used for the formation of the semiconductor memory device 1. In the cross-sectional view, the hatching of the insulator layer, etc., is appropriately omitted to prevent the drawing from becoming complicated. The top view is appropriately hatched to facilitate the observation of the diagram. The hatching added in the top view does not necessarily have to be related to the materials or characteristics of the constituent elements with the hatching added.

(About the cross-sectional structure of the memory cell transistor MT) Hereinafter, an example of the structure of the semiconductor memory device 1 of the first embodiment will be described using FIG. 6. Figure 6 is a cross-sectional view of a partial area of the block BLK.

As shown in FIG. 6, a p-well region (p-well) 130 is provided in the semiconductor layer. A plurality of NAND strings NS are arranged on the p-type well region 130. That is, on the p-type well region 130, a wiring layer 131 functioning as a selective gate line SGS, an 8-layer wiring layer 132 functioning as a word line WL0 to WL7, and a selective gate line SGD are sequentially stacked The wiring layer 133. Furthermore, an insulator layer is inserted between adjacent wiring layers.

The memory hole 134 is provided through the wiring layers 131, 132, and 133, and the bottom of the memory hole 134 reaches the well region 130. A columnar semiconductor layer (semiconductor column) 135 is arranged in the memory hole 134. On the side surface of the semiconductor pillar 135, an insulating film (tunnel insulating film) 136, an insulating film (charge storage layer) 137, and an insulating film (barrier insulating film) 138 are sequentially provided. These components constitute the memory cell transistor MT and the selection transistors ST1 and ST2. The semiconductor pillar 135 functions as a current path of the NAND string NS, and is an area for forming a channel of each transistor. The upper end of the semiconductor pillar 135 is connected to the metal wiring layer 140 functioning as the bit line BL via the contact plug 139.

On the surface area of the well area 130, an n+ type diffusion area 141 into which a high concentration of n type impurity is introduced is provided. A contact plug 142 is provided on the n + type diffusion region 141. The contact plug 142 is connected to the metal wiring layer 143 functioning as the source line SL. Furthermore, in the surface region of the well region 130, a p+-type diffusion region 144 into which a high-concentration p-type impurity is introduced is provided. On the p+ type diffusion region 144, a contact plug 145 is provided. The contact plug 145 is connected to the metal wiring layer 146 which functions as the well wiring CPWELL. The well wiring CPWELL is a wiring for applying voltage to the semiconductor pillar 135 via the well region 130.

The above structures are arranged in plural in the depth direction (X direction) of the paper surface in FIG. 6. In addition, the string unit SU includes a set of a plurality of NAND strings NS arranged in the X direction.

(About the planar structure of the memory cell transistor MT) FIG. 7 shows the structure of the memory cell transistor MT included in each block BLK viewed from the Z direction. More specifically, an example of a cross-sectional structure of a plane including the X direction and the Y direction of the memory hole 134 and the wiring layer 132 (character line WL) when viewed from the Z direction is shown.

In the cross-section shown in the figure, for example, the semiconductor layer 135 is disposed at the center of the memory hole 134. The tunnel insulating film 136 surrounds the side surface of the semiconductor layer 135. The charge storage layer 137 surrounds the side surface of the tunnel insulating film 136. The barrier insulating film 138 surrounds the side surface of the charge storage layer 137. In addition, the wiring layer 132 (word line WL) surrounds the barrier insulating film 138. That is, the wiring layer 132 (word line WL) surrounds the memory hole 134. Thereby, the portion where the memory hole 134 and the wiring layer 132 (word line WL) intersect functions as a memory cell transistor MT.

The memory hole 134 and the wiring layer 131 (selection gate line SGS) also have the same cross-sectional structure as the cross-section including the character line WL in the plane including the X direction and the Y direction. That is, the portion where the memory hole 134 and the wiring layer 131 (select gate line SGS) intersect functions as the selection transistor ST2.

In addition, the memory hole 134 and the wiring layer 133 (selection gate line SGD) also have the same cross-sectional structure as the cross-section including the character line WL in the plane including the X direction and the Y direction. That is, the portion where the memory hole 134 and the wiring layer 133 (selection gate line SGD) intersect functions as the selection transistor ST1.

[1-1-4] About the way of memorizing data In the semiconductor memory device 1 of the first embodiment, a plurality of threshold distributions are set corresponding to the number of bits of data that can be memorized by one memory cell transistor MT. In addition, the threshold voltage of each memory cell transistor MT is arranged in any region of a plurality of threshold distributions according to the type of data to be written. Hereinafter, the plurality of threshold distributions assigned to different data are referred to as "states".

FIG. 8 shows an example of the threshold distribution, read voltage, and verification voltage of the memory cell transistor MT of the semiconductor memory device 1 of the first embodiment. Furthermore, in the threshold distribution diagram referred to below, NMTs on the vertical axis corresponds to the number of memory cell transistors MT, and Vth on the horizontal axis corresponds to the threshold voltage of the memory cell transistor MT.

As shown in FIG. 8, in the semiconductor memory device 1 of the first embodiment, for example, 8 types of threshold distributions are formed based on a plurality of memory cell transistors MT. The eight types of threshold distributions are called "Er" state, "A" state, "B" state, "C" state, "D" state, "E" state, and "F" in the order of threshold voltage from low to high. "State, "G" state. The "Er" state corresponds to the erased state of the memory cell transistor MT. "A" state ~ "G" state respectively correspond to the state of writing data to the memory cell transistor MT.

In addition, different 3-bit data is allocated to each of the "Er" state to the "G" state, and it is set that only one bit of data is different between the two adjacent states. Such a method of making a memory cell transistor to store 3-bit data is called a TLC (Triple-Level Cell) method, for example. The following is an example of data allocation for the 8 threshold distributions. "Er" status: "111 (upper bit/middle bit/lower bit)" data "A" status: "110" data "B" status: "100" data "C" status: "000" data "D" status: "010" data "E" status: "011" data "F" status: "001" data "G" status: "101" data.

Set the verification voltage used in the write operation for adjacent states. Specifically, the verification voltage AV is set between the "Er" state and the "A" state. Set the verification voltage BV between the "A" state and the "B" state. Set the verification voltage CV between the "B" state and the "C" state. Set the verification voltage DV between the "C" state and the "D" state. Set the verification voltage EV between the "D" state and the "E" state. Set the verification voltage FV between the "E" state and the "F" state. Set the verification voltage GV between the "F" state and the "G" state. In the writing operation, when the semiconductor memory device 1 detects that the threshold voltage of the memory cell transistor MT storing a certain data exceeds the verification voltage corresponding to the data, the programming of the memory cell transistor MT is completed.

The read voltage used in the read operation is also set separately for adjacent states. Specifically, the read voltage AR is set between the "Er" state and the "A" state. Set the read voltage BR between the "A" state and the "B" state. Set the reading voltage CR between the "B" state and the "C" state. Set the read voltage DR between the "C" state and the "D" state. Set the reading voltage ER between the "D" state and the "E" state. Set the read voltage FR between the "E" state and the "F" state. Set the reading voltage GR between the "F" state and the "G" state. Each read voltage is used to distinguish between the lower and upper states of the threshold voltage of the memory cell transistor MT of the read object based on the read voltage. In addition, the read pass voltage VREAD is set for a voltage higher than the uppermost "G" state. The gate electrode is applied with the read pass voltage VREAD and the memory cell transistor MT becomes conductive regardless of the memorized data. In the reading operation, the semiconductor memory device 1 uses the reading voltage to determine the state of the distribution of the memory cell transistor MT, thereby confirming the reading of data.

For example, when the data allocation shown in Figure 8 is applied, a page of read data (lower page data) composed of lower bits is based on the read result using the read voltage AR and the read using the read voltage ER The result is certain. One page of read data (middle page data) composed of middle bits is based on the reading result using the reading voltage BR, the reading result using the reading voltage DR, and the reading result using the reading voltage FR And ok. One page of read data (upper page data) composed of upper bits is determined based on the read result using the read voltage CR and the read result using the read voltage GR. In the reading operation, the logic circuit LC appropriately executes arithmetic processing using a plurality of reading results to confirm reading data.

Furthermore, the number of bits of the data memorized by one memory cell transistor MT described above is an example, and it is not limited to this. For example, the memory cell transistor MT can also store data of 1 bit, 2 bits or more than 4 bits. In the semiconductor memory device 1, the number of threshold distributions formed, or the read voltage, read pass voltage, verification voltage, etc. can be appropriately set according to the number of bits stored in the memory cell transistor MT.

In this specification, the “read result” corresponds to the data captured into the sense amplifier unit SAU by the effective control signal STB. "Reading data" corresponds to the data output from the semiconductor memory device 1 to the memory controller 2 in the reading operation. The operation for obtaining one or more reading results corresponding to one reading voltage is called "reading processing". The reading process of reading the voltages AR to GR is also referred to as the reading process of the "A" to "G" states, respectively. The number of reading results obtained in each reading process corresponds to the number of times the control signal STB is validated in the reading process.

[1-2] Operation of semiconductor memory device 1 Next, the operation of the semiconductor memory device of the first embodiment will be described. In addition, in the following description, only reference signs are used to describe voltages applied to various wirings as appropriate. The memory cell transistor MT contained in the cell unit CU of the reading target is called a selected memory cell. In the reading operation, the selected word line WL is called WLsel, and the non-selected word line WL is called WLusel. Applying a voltage to the word line WL corresponds to the driver module 14 applying a voltage to the wiring via the signal line CG and the column decoder module 15. The n-th (n is an integer greater than or equal to 0) word line WL is referred to as a word line WLn. The memory cell transistor MT connected to the n+1th word line WLn+1 is referred to as an adjacent memory cell relative to the word line WLn.

[1-2-1] About write operation In the semiconductor memory device 1 of the first embodiment, in accordance with the sequence shown in FIG. 9(A), a write operation is performed on the memory cell transistors MT included in each block BLK. That is, in the first embodiment, in a certain string of cells SU, the data stored in the memory cell transistor MT connected to the word line WLn+1 is after the data stored in the memory cell transistor MT connected to the word line WLn be recorded. That is, in a certain string of cells SU, from the memory cell transistor MT connected to the word line WL0 closest to the source side selection gate line SGS to the word line connected to the word line closest to the drain side selection gate line SGD Up to the memory cell transistor MT of WL7, the writing operation is performed sequentially, layer by layer, character line by line.

Furthermore, the order of performing the write operation is not limited to this. For example, the memory cell transistor MT included in each block BLK of the semiconductor memory device 1 can also be written in the sequence shown in FIG. 9(B). In this case, in a certain string of cells SU, the data stored in the memory cell transistor MT connected to the word line WLn-1 is written after the data stored in the memory cell transistor MT connected to the word line WLn enter. That is, in a certain string of cells SU, from the memory cell transistor MT connected to the word line WL7 closest to the drain side selection gate line SGD to the word line connected to the word line closest to the source side selection gate line SGS Up to the memory cell transistor MT of WL0, the writing operation is performed sequentially, layer by character line.

FIG. 10 is an example of the voltage of each wiring in the write operation of the semiconductor memory device 1 of the first embodiment, respectively showing the state of the input/output signal I/O and the voltage of the selected word line WLsel. As the input and output signal I/O, it shows the period during which the semiconductor memory device 1 becomes in the ready state and receives the command set (command, address and data) from the external memory controller 2 and the period during which the semiconductor memory device 1 is in the busy state .

When the input/output signal I/O of the semiconductor memory device 1 is input from the external memory controller 2 to the instruction to instruct the execution of the write operation, the address of the memory cell that stores the data, and the instruction set containing the write data, The semiconductor memory device 10 performs a write operation after transitioning from the ready state to the busy state.

In the writing operation, the sequencer 13 first executes the programming operation. Specifically, a voltage VSS is applied to the sense amplifier module 16 and the bit line BL corresponding to the memory cell transistor MT of the writing target, and the voltage VSS is applied to the bit line corresponding to the memory cell transistor MT whose writing is inhibited. For example, the voltage VINH. The voltage VINH is higher than VSS, and the NAND string NS corresponding to the bit line BL to which the voltage VINH is applied is turned off by the selective transistor ST1, and for example, becomes a floating state. In addition, the driver module 14 and the column decoder module 15 apply the programming voltage VPGM to the selected word line WLsel. The programming voltage VPGM is a high voltage that can inject electrons into the charge storage layer of the memory cell transistor MT.

Then, in the memory cell transistor MT to be written, electrons are injected into the charge storage layer by the potential difference between the gate and the channel, and the threshold voltage is increased. On the other hand, in the memory cell transistor MT with write-inhibited, for example, the potential difference between the gate and the channel is reduced due to the channel boost of the NAND string NS in the floating state, thereby suppressing the increase of the threshold voltage.

Secondly, the sequencer 13 performs verification actions. Specifically, the driver module 14 and the column decoder module 15 apply the verification voltage VFY to the selected word line WLsel. As the verification voltage VFY, for example, the verification voltage AV shown in FIG. 8 is used.

Then, the memory cell transistor MT connected to the selected word line WLsel is turned on or off according to its threshold voltage. In addition, each sense amplifier unit SAU determines whether the threshold voltage of the corresponding memory cell transistor MT exceeds the desired verification voltage based on the voltage of the corresponding bit line BL.

Then, when the sequencer 13 detects that the threshold voltage of the corresponding memory cell transistor MT exceeds the desired verification voltage, it sets the verification of the memory cell transistor MT to pass, and makes the memory cell in the subsequent programming action Transistor MT is write prohibited.

On the other hand, when the sequencer 13 detects that the threshold voltage of the corresponding memory cell transistor MT is lower than the desired verification voltage, it is assumed that the verification of the memory cell transistor MT has failed, and is used in the subsequent programming operation The memory cell transistor MT is the writing object.

For example, the sequencer 13 can cause the driver module 14 and the column decoder module 15 to continuously apply a plurality of verification voltages to the selected word line WLsel in a single verification operation, so that the sense amplifier module 16 continuously executes a plurality of verification voltages. Verification of the level. In addition, the sequencer 173 can appropriately change the type and number of verification voltages applied in one verification operation in accordance with the progress of the write operation. Furthermore, the sequencer 13 can also make it possible to apply only one verification voltage from the driver module 14 and the column decoder module 15 to the selected word line WLsel in one verification operation, so that the sense amplifier module 16 performs 1 Verification of the level.

The combination of the above-mentioned programming action and verification action is equivalent to a cycle. The sequencer 13 repeatedly executes this cycle, so that the programming voltage VPGM rises by ΔVPGM every time in each programming cycle. In addition, after the sequencer 13 repeatedly executes the programming cycle a plurality of times (for example, 19 times), the writing operation is ended and the semiconductor memory device 1 is changed from the busy state to the ready state.

Here, as shown in FIG. 6, in the semiconductor memory device 1 of the first embodiment, in a certain string of cells SU, the memory cell transistor MT connected to a certain word line WLn and the adjacent word line WLn are connected The -1 memory cell transistor MT and the memory cell transistor MT connected to the adjacent character line WLn+1 are in close proximity. Therefore, the threshold of the memory cell transistor MT connected to a certain word line WLn is affected by the electrons held in the charge storage layer of the memory cell transistor MT connected to the word lines WLn-1 and WLn+1 on both sides.

Here, when the write operation is performed in the order shown in FIG. 9(A), after the write operation is performed on the word line WLn-1, the write operation is performed on the word line WLn. That is, at the time when the write operation is performed on the memory cell transistor MT connected to the word line WLn, the amount of electrons held in the charge storage layer of the memory cell transistor MT connected to the word line WLn-1 is already Sure. That is, thereafter, the amount of electrons held in the charge storage layer of the memory trench MT hardly changes. Therefore, the influence of the electrons held in the charge storage layer of the memory cell transistor MT connected to the word line WLn-1 on the threshold voltage of the memory cell transistor MT connected to the word line WLn will be considered during the verification operation. , So that the influence can be substantially eliminated.

On the other hand, the write operation to the word line WLn+1 is performed after the write operation to the word line WLn. At the time point when the write operation is performed on the memory cell transistor MT connected to the word line WLn (more specifically, when the verification operation is performed), in the charge storage layer of the memory cell transistor MT connected to the word line WLn+1 The amount of electrons held has not yet been determined, and the possibility of subsequent changes is high. More specifically, after performing a write operation on the memory cell transistor MT connected to the word line WLn, the threshold voltage of the memory cell transistor MT connected to the word line WLn+1 may change from the "Er" state to "G "Status etc."

Therefore, the influence of the electrons held in the charge storage layer of the memory cell transistor MT connected to the word line WLn+1 on the threshold voltage of the memory cell transistor MT connected to the word line WLn is difficult to perform the writing operation. exclude.

Furthermore, when the write operation is performed in the order shown in FIG. 9(B), the relationship between the word line WLn-1 and the word line WLn+1 is reversed. That is, the influence of the electrons held in the charge accumulation layer of the memory cell transistor MT connected to the word line WLn+1 on the threshold voltage of the memory cell transistor MT connected to the word line WLn will be considered during the verification operation. This effect can be substantially eliminated. However, since the write operation to the word line WLn-1 is performed after this, it is difficult to exclude the memory cell transistor MT at the time when the write operation is performed on the memory cell transistor MT connected to the word line WLn The impact on the threshold voltage.

[1-2-2] About reading action The semiconductor memory device 1 of the first embodiment can perform at least two types of read operations. For example, the plurality of read operations that can be performed by the semiconductor memory device 1 include normal read operations and DLA (Direct Look Ahead) read operations.

Normally, the reading operation is a reading operation in which the number of readings for each reading voltage used is 1 time. The DLA reading action uses the reading result of the adjacent memory cell adjacent to the selected memory cell to determine the reading action of the reading result of the selected memory cell. That is, the DLA read operation includes the read operation of adjacent memory cells and the read operation of selected memory cells. The details of the DLA reading action will be described below.

FIG. 11 shows an example of the command sequence of the read operation of the semiconductor memory device 1 of the first embodiment. The upper side of Fig. 11 corresponds to the command sequence of the normal read operation. The lower side of Fig. 11 corresponds to the instruction sequence of the DLA reading action.

As shown on the upper side of FIG. 11, when the memory controller 2 causes the semiconductor memory device 1 to perform a normal read operation, for example, the command "00h", the address information ADD, and the command "30h" are sequentially sent to the semiconductor memory Device 1. The command “00h” is a command to instruct the semiconductor memory device 1 to perform a read operation. The address information ADD includes the address corresponding to the cell unit CU of the read object. Address information ADD can use multiple cycles of input and output signal I/O. The command "30h" is a command to instruct the semiconductor memory device 1 to start the read operation.

On the other hand, as shown on the bottom side of FIG. 11, when the memory controller 2 causes the semiconductor memory device 1 to perform the DLA read operation, for example, the command "xxh", the command "00h", the address information ADD and The command "30h" is sent to the semiconductor memory device 1 in sequence. The command "xxh" is a prefix command that instructs the semiconductor memory device 1 to execute the DLA read operation. The difference between the command sequence of the normal read action and the command sequence of the DLA read action is the presence or absence of the command "xxh".

The semiconductor memory device 1 transitions from the ready state to the busy state based on receiving the command "30h". In addition, the semiconductor memory device 1 executes the normal read operation when the command "xxh" is not received, and executes the DLA read operation when the command "xxh" is received, for example. The time tR1 during which the semiconductor memory device 1 performs a normal read operation is shorter than the time tR2 during which the semiconductor memory device 1 performs a DLA read operation. The reason is that, as described below, the DLA reading operation includes the reading operation of the adjacent memory cell and the reading operation of the selected memory cell.

The semiconductor memory device 1 changes from the busy state to the ready state after the reading operation is completed. In addition, when the memory controller 2 instructs the semiconductor memory device 1 to execute the read operation, and detects that the semiconductor memory device 1 has transitioned from the busy state to the ready state, it instructs the semiconductor memory device 1 to read data DAT output. Then, the semiconductor memory device 1 outputs the read data DAT to the memory controller 2 based on the instruction of the memory controller 2.

[1-2-3] Details about DLA reading action Hereinafter, a specific example of the DLA reading operation in the semiconductor memory device 1 of the first embodiment will be described by taking the case of reading the lower page data as a representative. 12 is an example of a timing chart of the DLA reading operation of the lower bit page data of the semiconductor memory device 1 of the first embodiment, showing the word lines WLn, WLn+1 and WUsel, control signals BLX, BLC, HLL, XXL and STB, And the respective voltages of node SEN. In this example, the word line WLn is set as the selected word line WLsel. That is, the memory cell transistor MT connected to the word line WLn is a selective memory cell, and the memory cell transistor MT connected to the word line WLn+1 is an adjacent memory cell.

As shown in FIG. 12, before the DLA reading operation starts, the voltages of the word lines WLn, WLn+1, and WLusel, and the control signals BLX and BLC are, for example, the ground voltage VSS, and the control signals HLL, XXL, and STB, and the node SEN, respectively The voltage is, for example, the "L" level. In the DLA reading operation, the sequencer 13 executes the first reading during the period from time t0 to t4, and executes the second reading during the period from time t4 to t16, for example.

The first reading is a reading operation in which the adjacent memory cell adjacent to the selected memory cell that is the reading target of the DLA reading operation is set as the target. In the first reading of this example, the adjacent memory cell is set as the target, and the reading operation using the reading voltage XR is performed. As the read voltage XR, for example, the read voltage DR is used. Furthermore, as the reading voltage XR, other reading voltages may be used, or voltages different from the reading voltages AR to GR may be used.

The second reading is a reading operation in which the selected memory cell is set as the target. In the second reading of this example, the selected memory cell is set as the target, and the reading operation using the reading voltages AR and ER is performed. Furthermore, in the second reading, the reading process of each state includes two readings (data determination process, that is, the process of validating the control signal STB) executed with mutually different settings. Hereinafter, the details of each of the first reading and the second reading will be described in order.

(About the first reading) First, at time t0, the read pass voltage VREAD is applied to the word lines WLn, WLn+1, and WUsel. Furthermore, at time t0, the sequencer 13 increases the voltage of the control signal BLX from VSS to VblxL, and increases the voltage of the control signal BLC from VSS to VblcL. The voltage value of VblcL is lower than VblxL, for example. Then, the transistor 21 to which VblxL is applied to the gate and the transistor 24 to which VblcL is applied to the gate are respectively turned on.

Thereby, the voltage of the bit line BL rises based on, for example, the voltage of the control signal BLC and the threshold voltage of the transistor 24. Then, when the voltages of the word lines WLn, WLn+1, and WLusel rise to VREAD, and the voltages of the control signals BLX and BLC rise to VblxL and VblcL, respectively, all transistors in the NAND string NS are turned on. As a result, the residual electrons in the channel of the NAND string NS included in the selected string unit SU are removed.

Next, at time t1, the read voltage XR is applied to the word line WLn+1. Furthermore, at time t1, the sequencer 13 increases the voltage of the control signal BLX from VblxL to Vblx, and increases the voltage of the control signal BLC from VblcL to Vblc. The voltage value of Vblc is lower than Vblx, for example. Then, the voltage of the bit line BL changes in accordance with the state of the adjacent memory cell connected to the word line WLn+1. Specifically, when the adjacent memory cell is in the ON state, the voltage of the bit line BL connected to the adjacent memory cell drops. On the other hand, when the adjacent memory cell is in the disconnected state, the voltage of the bit line BL connected to the adjacent memory cell remains unchanged.

Furthermore, at time t1, the sequencer 13 increases the voltage of the control signal HLL from the "L" level to the "H" level. As a result, the gate electrode of the transistor 22 to which the voltage of the "H" level is applied is turned on. As a result, the voltage of the node SEN rises from the "L" level to the "H" level. That is, the node SEN is charged via the transistor 22. In addition, after the node SEN is charged, the sequencer 13 drops the control signal HLL from the "H" level to the "L" level, so that the transistor 22 is turned off.

Secondly, at time t2, the sequencer 13 increases the voltage of the control signal XXL from the "L" level to the "H" level. Then, the gate electrode of the transistor 23 to which the voltage of the "H" level is applied is turned on. Thereby, a current path between the node SEN and the bit line BL is formed, and the voltage of the node SEN changes corresponding to the voltage of the bit line BL connected to the NAND string NS. Specifically, when the adjacent memory cell connected to the word line WLn+1 is in the ON state, the voltage of the node SEN corresponding to the adjacent memory cell drops (FIG. 12, the conductive cell). On the other hand, when the adjacent memory cell is in the disconnected state, the voltage of the node SEN corresponding to the adjacent memory cell maintains the "H" level (FIG. 12, disconnected cell).

Then, the sequencer 13 reduces the voltage of the control signal XXL from the "H" level to the "L" level after the voltage based on the voltage of the bit line BL is reflected to the node SEN after a specific time has elapsed. Then, the transistor 23 is turned off, and the voltage of the node SEN is fixed. Hereinafter, the time during which the voltage of the control signal XXL is maintained at the "H" level is also referred to as the discharge time of the node SEN.

After that, the sequencer 13 activates the control signal STB, and judges the threshold voltage of the adjacent memory cell connected to the word line WLn+1. Specifically, the sense amplifier unit SAU determines whether the threshold voltage of the adjacent memory cell is greater than or equal to the read voltage XR, and holds the determination result in, for example, the latch circuit ADL. Hereinafter, the reading result obtained by the first reading is also referred to as DLA data.

Next, at time t3, the sequencer 13 restores the voltages of the word lines WLn, WLn+1, and WUsel, the control signals BLX, BLC, HLL, XXL, and STB, and the node SEN to the state before the first reading starts. Thereby, the sequencer 13 completes the first reading and moves to the second reading.

(About the second reading) First, at time t4, similar to time t0, the read pass voltage VREAD is applied to the word lines WLn, WLn+1, and WLusel, and the sequencer 13 increases the voltages of the control signals BLX and BLC to VblxL and VblcL, respectively. As a result, similar to time t0, residual electrons in the channel of the NAND string NS included in the selected string unit SU are removed.

Next, from time t5 to t10, the sequencer 13 executes the reading process of reading the voltage AR. Specifically, at time t5, the read voltage AR is applied to the word line WLn, and as at time t1, the sequencer 13 increases the voltages of the control signals BLX and BLC to Vblx and Vblc, respectively. Then, the voltage of the bit line BL changes in accordance with the state of the selected memory cell connected to the word line WLn. Specifically, when the selected memory cell is in the ON state, the voltage of the bit line BL connected to the selected memory cell drops. On the other hand, when the selected memory cell is in the off state, the voltage of the bit line BL connected to the selected memory cell remains unchanged.

Furthermore, at time t5, similar to time t1, the sequencer 13 raises the voltage of the control signal HLL to the "H" level, and turns the transistor 22 into a conductive state. In this way, the node SEN is charged via the transistor 22. In addition, after the node SEN is charged, the sequencer 13 drops the control signal HLL to the "L" level, so that the transistor 22 is turned off.

Next, at time t6, the sequencer 13 raises the voltage of the control signal XXL to the "H" level as at the time t2, and turns the transistor 23 into a conducting state. Thereby, a current path between the node SEN and the bit line BL is formed, and the voltage of the node SEN changes corresponding to the voltage of the bit line BL connected to the NAND string NS. Specifically, when the selected memory cell is in the on state, the voltage of the node SEN corresponding to the selected memory cell drops. On the other hand, when the selected memory cell is in the off state, the voltage of the node SEN corresponding to the selected memory cell is maintained at the "H" level. In addition, after the time T1 has elapsed, the sequencer 13 reduces the voltage of the control signal XXL from the "H" level to the "L" level. Then, the transistor 23 is turned off, and the voltage of the node SEN is fixed.

Furthermore, in FIG. 12, according to the read voltage of each state, the two types of memory cell transistors MT that are preferably turned on are represented as the first conductive cell and the second conductive cell, respectively. The first conducting cell corresponds to the conducting cell when the threshold voltage of the adjacent memory cell is low. The second conducting cell corresponds to the conducting cell when the threshold voltage of the adjacent memory cell is higher. For example, in the processing at time t6, the voltage drop amount of the node SEN corresponding to the second conductive cell is smaller than the voltage drop amount of the node SEN corresponding to the first conductive cell. In this example, it is assumed that through the processing at time t6, the voltage of the node SEN connected to the first conduction cell is fixed to a state lower than the threshold voltage of the transistor 26, and the voltage of the node SEN connected to the second conduction cell is fixed to be lower than the threshold voltage of the transistor 26. The state where the threshold voltage of the transistor 26 is high.

After that, the sequencer 13 activates the control signal STB, and judges the threshold voltage of the selected memory cell connected to the word line WLn+1. Specifically, the sense amplifier unit SAU determines whether the threshold voltage of the selected memory cell is greater than or equal to the read voltage AR, and holds the determination result in, for example, the latch circuit BDL. Then, the sequencer 13 resets the voltage of the node SEN to the "L" level.

Next, at time t8 to t10, the sequencer 13 performs processing similar to that at time t5 to t7. Between the processing at time t5 to t7 and the processing at time t8 to t10, the discharge time of the node SEN is different. Specifically, the discharge time "T2" of the node SEN in the processing at time t9 is set to be longer than the discharge time "T1" of the node SEN in the processing at time t6. In this example, it is assumed that through the processing at time t9, the voltage of the node SEN connected to the first conducting cell and the voltage of the node SEN connected to the second conducting cell are respectively fixed to a state lower than the threshold voltage of the transistor 26. In addition, the sequencer 13 holds the determination result of using the read voltage AR in the processing at time t9 in, for example, the latch circuit CDL. Then, the sequencer 13 resets the voltage of the node SEN to the "L" level. The other processing at time t8 to t10 is the same as the processing at time t5 to t7, for example.

Next, from time t11 to t16, the sequencer 13 executes the reading process of reading the voltage ER. The voltage applied to the word line WLn is different from the processing at time t11 to t16 and the processing at time t5 to t10. Specifically, at time t11, the read voltage ER is applied to the word line WLn. The sequencer 13 holds the determination result of using the read voltage ER in the processing at time t12 in, for example, the latch circuit DDL. In addition, the sequencer 13 holds the determination result of using the read voltage ER in the processing at time t15 in, for example, the latch circuit EDL.

Then, at time t16, the sequencer 13 restores the voltages of the word lines WLn, WLn+1, and WLusel, the control signals BLX, BLC, HLL, XXL, and STB, and the node SEN to the state before the start of the second reading. The other processing at time t11 to t16 is the same as the processing at time t5 to t10, for example. Thereby, the sequencer 13 completes the second reading.

As described above, after the first read and the second read in the DLA read operation are completed, the sequencer 13 executes the latch circuits BDL, CDL, DDL, and DDL based on the DLA data held in the latch circuit ADL, for example. Operational processing of data held in EDL. Hereinafter, the read result when the discharge time of the node SEN is "T1" is referred to as the first data, and the read result when the discharge time of the node SEN is "T2" is referred to as the second data. That is, in this example, the latch circuits BDL and CDL hold the first and second data corresponding to the read voltage AR, respectively. The latch circuits DDL and EDL hold the first and second data corresponding to the read voltage ER, respectively.

For example, when the DLA data held in the latch circuit ADL is "1", the sequencer 13 uses the first data of the read voltage AR held in the latch circuit BDL and the first data held in the latch circuit DDL Read the first data of the voltage ER to confirm the reading data of the lower page. In addition, the sequencer 13 holds the read data of the determined lower page in the latch circuit XDL.

On the other hand, when the DLA data held in the latch circuit ADL is "0", the sequencer 13 uses the second data of the read voltage AR held in the latch circuit CDL and the second data in the latch circuit EDL. The second data of the maintained read voltage ER determines the read data of the lower page. In addition, the sequencer 13 holds the read data of the determined lower page in the latch circuit XDL.

When the determined read data is held in the latch circuit XDL, the sequencer 13 completes the DLA read operation, so that the semiconductor memory device 1 changes from the busy state to the ready state. Thereafter, the sequencer 13 outputs the read data stored in the latch circuit XDL to the memory controller 2 based on the instruction of the memory controller 2.

As described above, the semiconductor memory device 1 of the first embodiment can perform the DLA reading operation of the lower page data. In each read operation of the middle and upper positions, the semiconductor memory device 1 of the first embodiment can appropriately execute the DLA read operation in the same manner as the reading operation of the lower page data. Furthermore, the semiconductor memory device 1 can perform a DLA read operation even when the data stored in one memory cell transistor MT is other than 3 bits.

[1-3] Effects of the first embodiment According to the semiconductor memory device 1 of the first embodiment described above, the occurrence of read errors can be suppressed. Hereinafter, the details of the effects of the semiconductor memory device 1 of the first embodiment will be described.

In a semiconductor memory device, the threshold voltage of a plurality of memory cells after a write operation has a deviation close to the normal distribution. In addition, for example, when data is written to the memory cell and then the adjacent memory cell is written, the threshold voltage of the memory cell sometimes changes according to the coupling between the adjacent word lines WL.

Here, using FIG. 13, an example of the change in the threshold distribution of the memory cell transistor MT based on the threshold voltage of the adjacent memory cell will be described. The upper side of FIG. 13 corresponds to the threshold distribution formed by the plurality of memory cell transistors MT connected to the word line WLn and the threshold voltage of the adjacent memory cell is in the "Er" state. The lower side of FIG. 13 corresponds to the threshold distribution formed by a plurality of memory cell transistors MT connected to the word line WLn and the threshold voltage of the adjacent memory cell is in the "G" state.

As shown on the upper side of FIG. 13, when the threshold voltages of adjacent memory cells are in the "Er" state, the change in the threshold distribution of the memory cell transistor MT of the word line WLn after writing is suppressed. On the other hand, when the threshold voltage of the adjacent memory cell is in the "G" state as shown on the bottom side of FIG. 13, the threshold voltage of the memory cell transistor MT of the word line WLn after the writing operation shifts to positive side. For example, the higher the threshold voltage of an adjacent memory cell, the greater the offset of the threshold voltage affected by the adjacent memory cell.

The threshold distribution of the memory cell can be expanded according to the change in the threshold voltage of the memory cell corresponding to the data memorized by the adjacent memory cell. In addition, the expansion of the threshold distribution will cause the reliability, write performance, or read performance of the semiconductor memory device to decrease. Therefore, the expansion of the threshold distribution is preferably suppressed. As a method to reduce the influence of the threshold voltage of adjacent memory cells, it can be considered to perform a DLA read operation.

When the DLA read operation reads the specific state of the memory cell connected to the word line WLn, the read of the word line WLn+1 is performed at least once. The reading of the word line WLn+1 is performed to check the threshold voltage of adjacent memory cells. Moreover, in the reading of the word line WLn, each state performs at least two readings using different reading pass voltages.

FIG. 14 shows an example of a timing chart of the DLA reading operation of the lower bit page data of the semiconductor memory device 1 of the comparative example of the first embodiment. As shown in FIG. 14, the difference between the DLA reading operation in the comparative example of the first embodiment and the first embodiment is that the discharge time of the node SEN during the second reading is fixed, so that it is applied to adjacent memories. The voltage variation of the word line WLn+1 of the cell connection.

In short, in the second reading of the DLA reading operation of the comparative example of the first embodiment, the sequencer 13 applies the reading pass voltage VREADL to the word line WLn+1 when reading the first data. On the other hand, when the sequencer 13 reads the second data, it applies the read pass voltage VREADH to the word line WLn+1. VREADH is a voltage higher than VREADL. VREADL and VREADH can be the same voltage as VREAD, or different voltages.

When it is detected by the first reading that the threshold voltage of the adjacent memory cell is low, it is estimated that the offset of the threshold voltage of the selected memory cell is small. On the other hand, when it is detected by the first reading that the threshold voltage of the adjacent memory cell is higher, it is estimated that the shift amount of the threshold voltage of the selected memory cell is larger. Therefore, the sequencer 13 of the comparative example of the first embodiment modifies the effective threshold voltage of the selected memory cell by applying VREADL or VREADH to the word line WLn+1. For example, the higher the read pass voltage applied to the word line WLn+1, the more effective the threshold voltage of the selected memory cell can be lowered.

Thereby, the semiconductor memory device 1 of the comparative example of the first embodiment can selectively use the first data and the second data that suppress the influence of adjacent memory cells, and can suppress the occurrence of read errors. On the other hand, in the DLA reading operation as in the comparative example of the first embodiment, the number of transitions of the voltage of the word line WL in the second reading increases. For example, in the semiconductor memory device 1 in which memory cells are stacked in three dimensions, the parasitic resistance and parasitic capacitance of the word line WL are relatively large. Therefore, in the DLA reading operation of the comparative example of the first embodiment, the reading time may become longer due to the increase in the number of transitions of the voltage of the word line WL.

Therefore, in the semiconductor memory device 1 of the first embodiment, in the DLA read operation, in a state where the voltage of the word line WLn+1 is fixed, reads are performed multiple times for each state. In addition, the semiconductor memory device 1 of the first embodiment changes the discharge time of the node SEN in a plurality of readings of each state. Extending the discharge time of the node SEN corresponds to increasing the voltage of the word line WLn+1 in the comparative example of the first embodiment.

For example, when the discharge time of the node SEN is short (for example, the discharge time "T1"), the selected memory cell with a relatively low threshold voltage, that is, the selected memory cell connected to the fast-discharged node SEN, can be sensed. On the other hand, when the discharge time of the node SEN is longer (for example, the discharge time "T2"), the selected memory cell with a relatively high threshold voltage can be sensed, that is, the selected memory cell connected to the slow-discharged node SEN.

As a result, similar to the comparative example of the first embodiment, the semiconductor memory device 1 of the first embodiment can selectively use the second reading used in the calculation of reading data based on the result of the first reading. Take the result (the first data or the second data). Therefore, the semiconductor memory device 1 of the first modification of the first embodiment can suppress the occurrence of read errors, and can improve the reliability of the semiconductor memory device 1.

In addition, the semiconductor memory device 1 of the first embodiment modifies the threshold voltage of the selected memory cell by controlling the discharge time of the node SEN, that is, controlling the control signal XXL. Compared with the word line WL, it is easy to design the signal transmission delay of the control signal XXL to be smaller. Therefore, the voltage of the control signal XXL can be changed at a high speed compared with the voltage of the word line WL. Therefore, the semiconductor memory device 1 of the first embodiment can control the expansion of the threshold distribution caused by the coupling between adjacent word lines, and perform a higher-speed DLA reading operation than the comparative example of the first embodiment.

In addition, the above description is based on FIG. 9(A), from the word line WL0 closest to the source-side select gate line SGS to the word line WL7 closest to the drain-side select gate line SGD. It is assumed that the layers sequentially perform write operations. As shown in Figure 9(B), from the word line WL7 closest to the drain-side selection gate line SGD to the nearest word line SGS to the source-side selection gate line When the writing operation is sequentially performed layer by layer up to the word line WL0, instead of the word line WLn+1, the same voltage is applied to the word line WLn-1. Also, in this case, the same voltage as the non-selected word line WUsel is applied to the word line WLn+1. In this way, this embodiment can be applied by appropriately changing the word line concerned in addition to selecting the word line WLsel even when the sequence of performing the writing operation has been changed.

[1-4] Variations of the first embodiment The DLA reading operation of the semiconductor memory device 1 of the first embodiment described above can be changed in various ways. Hereinafter, similar to the first embodiment, taking the time of reading the lower page data as a representative, the specific examples of the DLA reading operation of the first modification example, the second modification example, and the third modification example of the first embodiment are sequentially described. Be explained.

(The first modification of the first embodiment) FIG. 15 shows an example of a timing chart of the DLA reading operation of the semiconductor memory device 1 of the first modification of the first embodiment. As shown in FIG. 15, the DLA reading operation of the first modification of the first embodiment is different from the setting of the discharge time of the node SEN in the second reading of the DLA reading operation of the first embodiment.

Specifically, in the first modification of the first embodiment, in the second reading, the time during which the control signal XXL is maintained at the "H" level is set to switch between the time T1 and the time T2. That is, the sequencer 13 of the first modification of the first embodiment executes the data determination processing in the order of the second data and the first data in the reading processing of each state of the second reading. The other operations of the first modification of the first embodiment are the same as those of the first embodiment.

In this case, similar to the first embodiment, the semiconductor memory device 1 of the first modification of the first embodiment can selectively use the first used in the calculation of reading data based on the result of the first reading. 2 Read the reading result. Therefore, similar to the first embodiment, the semiconductor memory device 1 of the first modification of the first embodiment can suppress the occurrence of read errors, and can improve the reliability of the semiconductor memory device 1.

(The second modification of the first embodiment) FIG. 16 shows an example of a timing chart of the DLA reading operation of the semiconductor memory device 1 of the second modification of the first embodiment. As shown in FIG. 16, in the DLA reading operation of the second modification of the first embodiment, compared with the DLA reading operation of the first embodiment, the order of the execution of the first reading and the second reading is switched.

Specifically, the sequencer 13 of the second modification of the first embodiment executes the processing at the time t4 to t16 in the first embodiment, and then executes the processing at the time t0 to t3. That is, the sequencer 13 acquires the DLA data through the first read after acquiring the first data and the second data of each state through the second read. The other operations of the second modification of the first embodiment are the same as those of the first embodiment.

In this case, the semiconductor memory device 1 of the second modification of the first embodiment, similar to the first embodiment, can selectively use the second used in the calculation of reading data based on the result of the first reading. Read the read result. Therefore, the semiconductor memory device 1 of the second modified example of the first embodiment can suppress the occurrence of read errors, and can improve the reliability of the semiconductor memory device 1 as in the first embodiment.

(The third modification of the first embodiment) FIG. 17 shows an example of a timing chart of the DLA reading operation of the semiconductor memory device 1 of the third modification of the first embodiment. As shown in FIG. 17, the DLA reading operation of the third modification of the first embodiment is compared with the DLA reading operation of the first embodiment in that the order of the reading voltage applied in the second reading is switched.

Specifically, the sequencer 13 of the third modification of the first embodiment executes the reading process in the order of the voltage from high to low. That is, when the sequencer 13 reads the lower page data, for example, the read process of the second read is executed in the order of the read voltages ER and AR. The other operations of the third modification of the first embodiment are the same as those of the first embodiment.

In this case, the semiconductor memory device 1 of the third modification of the first embodiment is also the same as the first embodiment. Based on the result of the first reading, the second used in the calculation of reading the data can be selectively used. 2 Read the reading result. Therefore, the semiconductor memory device 1 of the third modification example of the first embodiment can suppress the occurrence of read errors and can improve the reliability of the semiconductor memory device 1 as in the first embodiment.

[2] Second embodiment The semiconductor memory device 1 of the second embodiment has the same configuration as the semiconductor memory device 1 of the first embodiment. In addition, the semiconductor memory device 1 of the second embodiment performs the DLA reading operation after combining the first embodiment and the comparative example of the first embodiment. Hereinafter, regarding the semiconductor memory device 1 of the second embodiment, differences from the first embodiment will be described.

[2-1] DLA reading action Hereinafter, a specific example of the DLA reading operation of the semiconductor memory device 1 of the second embodiment will be described, taking the case of reading the lower page data as a representative. FIG. 18 shows an example of a timing chart of the DLA reading operation of the lower bit page data of the semiconductor memory device 1 of the second embodiment. As shown in FIG. 18, the DLA reading operation of the second embodiment has a configuration in which the operation of the character line WLn+1 of the comparative example of the first embodiment is combined with the operation of the first embodiment other than the character line WLn+1.

Specifically, in the DLA reading operation of the second embodiment, the sequencer 13 sets the charging time of the node SEN to "T1" during the reading process corresponding to the judgment process of the first data. The word line WLn+1 connected to adjacent memory cells is applied with a read pass voltage VREADL. Similarly, the sequencer 13 sets the charging time of the node SEN to "T2" during the reading process corresponding to the judgment process of the second data, and applies the read pass voltage to the word line WLn+1 connected to the adjacent memory cell VREADH. The other operations of the DLA reading operation of the second embodiment are the same as those of the first embodiment.

[2-2] Effects of the second embodiment As described above, the semiconductor memory device 1 of the second embodiment performs a DLA reading operation combining the first embodiment and the comparative example of the first embodiment. In short, the second reading of the first embodiment maintains the voltage of the word line WLn+1 connected to the adjacent memory cell at VREAD. On the other hand, in the second reading of the second embodiment, the voltage of the word line WLn+1 is appropriately changed to VREADL or VREADH. In addition, the second reading of the second embodiment changes the voltage of the word line WLn+1 and also changes the discharge time of the node SEN.

Thereby, the semiconductor memory device 1 of the second embodiment can expand the correction range of the threshold voltage of the selected memory cell in the DLA read operation compared with the first embodiment. As a result, compared with the first embodiment, the semiconductor memory device 1 of the second embodiment can suppress the occurrence of read errors and can improve the reliability of the semiconductor memory device 1.

Furthermore, in the semiconductor memory device 1 of the second embodiment, the read pass voltage of the word line WLn+1 in the second read of the DLA read operation fluctuates, so the read speed may decrease. However, in the semiconductor memory device 1 of the second embodiment, by combining with the threshold voltage correction performed by the control signal XXL, the amplitude of the word line WLn+1 can be designed to be smaller than the comparative example of the first embodiment. Therefore, the semiconductor memory device 1 of the second embodiment can speed up the DLA reading operation as compared with the comparative example of the first embodiment.

[2-3] Variations of the second embodiment The DLA reading operation of the semiconductor memory device 1 of the second embodiment described above can be changed in various ways. Hereinafter, similar to the second embodiment, the case of reading the lower page data is representative, and specific examples of the DLA reading operation of each of the first modification and the second modification of the second embodiment will be described in order.

(The first modification of the second embodiment) FIG. 19 shows an example of a timing chart of the DLA reading operation of the semiconductor memory device 1 of the first modification of the second embodiment. As shown in FIG. 19, the DLA reading operation of the first modification of the second embodiment is different from the DLA reading operation of the second embodiment, and the setting of the discharge time of the node SEN in the second reading is different.

Specifically, in the DLA reading operation of the first modification of the second embodiment, as in the first modification of the first embodiment, the time during which the control signal XXL is maintained at the "H" level in the second reading The setting is switched between time T1 and time T2. In addition, in the second reading of the DLA reading operation of the first modification of the second embodiment, when reading the first data, the voltage applied to the word line WLn+1 connected to the adjacent memory cell is between VREADH and VREADL Switch between. That is, the sequencer 13 of the first modification of the second embodiment executes the data determination processing in the order of the second data and the first data in the reading processing of each state in the second reading. The other operations of the first modification of the second embodiment are the same as those of the first embodiment.

In this case, the semiconductor memory device 1 of the first modification of the second embodiment is the same as that of the second embodiment. Based on the result of the first reading, the second used in the calculation of reading the data can be selectively used. Read the read result. Therefore, the semiconductor memory device 1 of the first modification of the second embodiment can suppress the occurrence of read errors and improve the reliability of the semiconductor memory device 1 as in the second embodiment.

(Second modification of the second embodiment) FIG. 20 shows an example of a timing chart of the DLA reading operation of the semiconductor memory device 1 of the second modification of the second embodiment. As shown in FIG. 20, the DLA reading operation of the second modification of the second embodiment has the following structure: Compared with the DLA reading operation of the second embodiment, it is executed twice in each state in the second reading The settings corresponding to the data judgment processing are different from each other.

Specifically, the sequencer 13 of the second modification of the second embodiment executes the judgment processing in the order of the first data and the second data in the reading processing of the initial state in the second reading. In addition, the sequencer 13 executes the judgment processing in the order of the second data and the first data in the read processing of the continuous state. In this way, in the second modification of the second embodiment, the judgment processing of the second data in the read processing of the initial state and the judgment processing of the second data in the read processing of the continuation state are continuous. Therefore, the word line n+1 connected to the adjacent memory cell is continuously applied with VREADH at the time t8 to t14 of the second reading, for example. The other operations of the second modification of the second embodiment are the same as those of the first modification of the second embodiment.

In this case, the semiconductor memory device 1 of the second modification of the second embodiment, similar to the second embodiment, can selectively use the second used in the calculation of reading data based on the result of the first reading. Read the read result. Therefore, the semiconductor memory device 1 of the second modification example of the second embodiment can suppress the occurrence of read errors and can improve the reliability of the semiconductor memory device 1 as in the second embodiment.

[3] Third Embodiment The semiconductor memory device 1 of the third embodiment has the same configuration as the semiconductor memory device 1 of the first embodiment. In addition, the semiconductor memory device 1 of the third embodiment executes a DLA reading operation in which a part of the charging process of the node SEN is omitted. Hereinafter, regarding the semiconductor memory device 1 of the third embodiment, differences from the first and second embodiments will be described.

[3-1] DLA reading action Hereinafter, a specific example of the DLA reading operation of the semiconductor memory device 1 of the third embodiment will be described by taking the case of reading the lower page data as a representative. FIG. 21 shows an example of a timing chart of the DLA reading operation of the lower bit page data of the semiconductor memory device 1 of the third embodiment. As shown in FIG. 21, the DLA reading operation of the second embodiment has a configuration in which the processing at times t7, t8, t13, and t14 is omitted from the DLA reading operation of the first embodiment.

Specifically, in the second reading of the DLA reading operation of the third embodiment, for example, the voltage of the node SEN at time t9 maintains the state of being discharged by the processing at time t6. In addition, the voltage of the node SEN is continuously discharged from this state by the same processing at time t9 as in the first embodiment. Therefore, in the third embodiment, as in the first embodiment, the voltage of the node SEN connected to the second conduction cell corresponding to the read voltage AR is lower than the threshold voltage of the transistor 26 by the processing at time t9.

Similarly, in the second reading of the DLA reading operation of the third embodiment, for example, the voltage of the node SEN at time t15 maintains the state of being discharged by the processing at time t12. In addition, the voltage of the node SEN is continuously discharged from this state by the process at the time t15 as in the first embodiment. Therefore, in the third embodiment, the voltage of the node SEN connected to the second conduction cell corresponding to the read voltage ER is lower than the threshold voltage of the transistor 26 by the processing at time t15 as in the first embodiment. The other operations of the third embodiment are the same as those of the first embodiment.

Furthermore, FIG. 21 shows the case where the discharge time of the node SEN in each process at time t9 and t15 is "T2", but it is not limited to this. In the DLA reading operation of the third embodiment, in the reading process of each state in the second reading, the discharge time "T1" of the node SEN related to the first data determination process is the same as that of the first embodiment. The sum of the discharge time of the node SEN and "T1" related to the second data determination process can be set to at least the discharge time "T2" of the first embodiment or more.

[3-2] Effects of the third embodiment As described above, the DLA reading operation of the semiconductor memory device 1 of the third embodiment omits a part of the charging process of the node SEN in the second reading. In addition, in the reading process of each state of the second reading of the DLA reading operation of the third embodiment, the discharge of the node SEN associated with the second data determination process is related to the first data determination process The discharge state of the connected node SEN starts.

In this case, the semiconductor memory device 1 of the third embodiment, similar to the first embodiment, can selectively use the second reading used in the calculation of reading data based on the result of the first reading. result. In addition, the processing time of the second reading in the third embodiment can be shortened because part of the processing is omitted. Therefore, the semiconductor memory device 1 of the third embodiment can suppress the occurrence of read errors as in the first embodiment, and can shorten the time of the DLA read operation compared with the first embodiment.

[4] Other changes, etc. In the above embodiment, the case where the DLA data is 1-bit data is exemplified, but it is not limited to this. The DLA reading action can also use multiple bits of DLA data. In this case, in the first reading in the DLA reading operation, the reading process of a plurality of bits is executed. The reading voltage used in the reading process of the plurality of bits may be the same as or different from the reading voltage used in the normal reading operation. For example, in the second reading when DLA data of a plurality of bits are used, the sequencer 13 executes the data judgment processing three times or more in the reading processing of each state. The multiple read results of each state of the second read are related to the multiple bits of DLA data. Furthermore, the sequencer 13 selects the reading result of the second reading used in the operation of reading the data based on the DLA data of a plurality of bits, and confirms the reading of the data. Thereby, the semiconductor memory device 1 can improve the detection accuracy of the threshold voltage of adjacent memory cells, and can more precisely modify the effective threshold voltage of the selected memory cell.

The above-mentioned embodiments and modification examples can be combined as far as possible. For example, switching the order of the first reading and the second reading in the DLA reading operation as in the second modification of the first embodiment can also be applied to the second and third embodiments, respectively. Like the third modification of the first embodiment, changing the order of applying the reading voltage in the second reading can also be applied to the second and third embodiments, respectively. In addition, three or more embodiments and modification examples can be combined. Thereby, the semiconductor memory device 1 can obtain the respective effects of the combined embodiment and the modified example.

In the above-mentioned embodiment, the case where the normal reading operation and the DLA reading operation are used separately according to the command sequence is illustrated, but it is not limited to this. The DLA read operation can be performed according to the mode of the semiconductor memory device 1. In this case, the memory controller 2 instructs the semiconductor memory device 1 to change to the mode of performing the DLA reading operation during the reading operation. In addition, the semiconductor memory device 1 in the mode of executing the DLA reading operation executes the DLA reading operation based on receiving the command sequence used in the normal reading operation described in the first embodiment, for example.

The timing chart used for the description of the write operation in the above embodiment is only an example. For example, there may be deviations at the time when the voltage of the signal and the wiring is controlled at each time. In the DLA reading operation, the operation between time t0 and t1 and the operation between time t4 and t5 can also be omitted. In the above embodiment, the voltage applied to the various wirings in the memory cell array 10 can be estimated based on the voltage of the signal line between the driver module 14 and the column decoder module 15. For example, the voltage applied to the word line WLsel can be estimated based on the voltage of the signal line CG.

In this specification, "one end of the transistor" means the drain or source of the MOS transistor. "The other end of the transistor" means the source or drain of the MOS transistor. The so-called "connection" means electrical connection, and does not include, for example, intervening other components. The "off state" means that a voltage that does not reach the threshold voltage of the transistor is applied to the node of the corresponding transistor, and does not include the flow of a small current such as the leakage current of the transistor.

In this specification, the "H" level voltage is the voltage at which the gate is turned on by the N-type MOS transistor to which the voltage is applied, and the gate is turned off by the P-type MOS transistor to which the voltage is applied. The voltage at the "L" level is the voltage at which the gate is turned off by the N-type MOS transistor to which the voltage is applied, and the gate is turned on by the P-type MOS transistor to which the voltage is applied. "Enable" corresponds to the sequencer 13 temporarily changing the control signal of the object from the "L" level to the "H" level. The "time to discharge the sensing node through the transistor 23" corresponds to, for example, the period during which the control signal XXL is at the "H" level and the transistor 23 is turned on.

Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and their changes are included in the scope and spirit of the invention, and are included in the invention described in the scope of the patent application and its equivalent scope. [Related Application]

This application enjoys the priority of the basic application based on Japanese Patent Application No. 2020-27018 (application date: February 20, 2020). This application contains all the contents of the basic application by referring to the basic application.

1: Semiconductor memory device 2: Memory controller 10: Memory cell array 11: Command register 12: Address register 13: Sequencer 14: drive module 15: column decoder module 16: Sensing amplifier module 20～27: Transistor 28: Capacitor 29: Transistor 30, 31: inverter 32, 33: N-type MOS transistor 130: p-well area 131: Wiring layer 132: Wiring layer 133: Wiring layer 134: Memory Hole 135: Semiconductor column 136: Insulating film (tunnel insulating film) 137: Insulating film (charge storage layer) 138: Insulating film (barrier insulating film) 139: contact plug 140: Metal wiring layer 141: n+ type diffusion region 142: contact plug 143: Metal wiring layer 144: p+ type diffusion area 145: contact plug 146: Metal wiring layer BD: block decoder BL: bit line BL0～BLm: bit line BLHU: Bit line connection part BLK: block BLK0～BLK(N-1): block CG0～CG7: signal line CPWELL: Well wiring CU: Cell unit LBUS: bus LC: Logic circuit MT: Memory cell transistor MT0～MT7: Memory cell transistor ND1: Node ND2: Node NS: NAND string RD: column decoder RD0～RD(N-1): column decoder SA: Sense Amplifier Division SAU: Sense Amplifier Unit SDL, ADL, BDL, CDL, DDL, EDL, XDL: latch circuit SEN: Node SGD: select gate line SGD0～SGD3: select gate line SGDD0～SGDD3: signal line SGS: Select gate line SGSD: signal line SINV: Node SL: source line SLAT: Node SRC: Node ST1: select transistor ST2: select transistor SU: String unit SU0～SU3: String unit TG, bTG: Transmission gate line TR0～TR17: Transistor USGD: signal line USGS: signal line WL: Character line WL0～WL7: Character line WLn: Character line WLn+1: character line WLsel: character line WLusel: character line XDL: latch circuit

FIG. 1 is a block diagram showing a configuration example of the semiconductor memory device of the first embodiment. 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array included in the semiconductor memory device of the first embodiment. 3 is a circuit diagram showing an example of the circuit configuration of the row decoder module included in the semiconductor memory device of the first embodiment. 4 is a circuit diagram showing an example of the circuit configuration of the sense amplifier module included in the semiconductor memory device of the first embodiment. 5 is a circuit diagram showing an example of the circuit configuration of the sense amplifier unit included in the sense amplifier module included in the semiconductor memory device of the first embodiment. 6 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the semiconductor memory device of the first embodiment. 7 is a cross-sectional view showing an example of the cross-sectional structure of the memory pillar of the semiconductor memory device of the first embodiment. FIG. 8 is a schematic diagram showing an example of data distribution applied to the memory cell transistor in the semiconductor memory device of the first embodiment. 9(A) and (B) are tables showing an example of the sequence of performing a write operation in the semiconductor memory device of the first embodiment. FIG. 10 is a timing chart showing an example of the write operation of the semiconductor memory device of the first embodiment. FIG. 11 is a conceptual diagram showing an example of the command sequence of the read operation of the semiconductor memory device of the first embodiment. FIG. 12 is a timing chart showing an example of the DLA reading operation of the semiconductor memory device of the first embodiment. FIG. 13 is a conceptual diagram showing an example of the threshold distribution of the memory cell transistor of the semiconductor memory device of the first embodiment. FIG. 14 is a timing chart showing an example of the DLA reading operation of the semiconductor memory device of the comparative example of the first embodiment. FIG. 15 is a timing chart showing an example of the DLA reading operation of the semiconductor memory device of the first modification of the first embodiment. FIG. 16 is a timing chart showing an example of the DLA reading operation of the semiconductor memory device of the second modification of the first embodiment. FIG. 17 is a timing chart showing an example of the DLA reading operation of the semiconductor memory device of the third modification of the first embodiment. FIG. 18 is a timing chart showing an example of the DLA reading operation of the semiconductor memory device of the second embodiment. FIG. 19 is a timing chart showing an example of the DLA reading operation of the semiconductor memory device of the first modification of the second embodiment. FIG. 20 is a timing chart showing an example of the DLA reading operation of the semiconductor memory device of the second modification of the second embodiment. FIG. 21 is a timing chart showing an example of the DLA reading operation of the semiconductor memory device of the third embodiment.

SEN: Node WLn: Character line WLn+1: character line WLsel: character line WLusel: character line

Claims (16)

A semiconductor memory device, which includes: NAND string, which has first and second memory cells connected in series and adjacent to each other; The first character line is connected to the gate of the first memory cell; The second character line is connected to the gate of the second memory cell; Bit line, which is connected to the above-mentioned NAND string; and A sense amplifier, which includes a sensing node, a first transistor connected between the sensing node and the bit line, and a latch circuit; and Able to perform reading actions including the first reading action and the second reading action, In the above-mentioned reading operation of selecting the above-mentioned first character line, During the first reading operation described above, Apply the first read voltage to the second word line mentioned above, During the period when the first read voltage is applied, the sensing node is connected to the bit line via the first transistor, After the sensing node is connected to the bit line via the first transistor, the first data based on the voltage of the sensing node is stored in the latch circuit, During the second reading operation described above, Apply a second read voltage to the first word line mentioned above, During the period when the second read voltage is applied, the sensing node is connected to the bit line at the first time via the first transistor, After the sensing node is connected to the bit line at the first time through the first transistor, the second data based on the voltage of the sensing node is stored in the latch circuit, After the second data is stored in the latch circuit, during the period when the second read voltage is applied, the sensing node is connected to the bit at a second time different from the first time through the first transistor. Wire connection, After the sensing node is connected to the bit line at the second time through the first transistor, the third data based on the voltage of the sensing node is stored in the latch circuit. Such as the semiconductor memory device of claim 1, wherein in the above-mentioned reading operation, During the first reading operation described above, Apply a first read pass voltage higher than each of the first and second read voltages to the first word line, During the period when the first read voltage is applied and the first read pass voltage is applied, the sensing node is connected to the bit line via the first transistor, During the second reading operation described above, Applying a second read pass voltage higher than each of the first and second read voltages to the second word line, During the period when the second read voltage is applied and the second read pass voltage is applied, the sensing node is connected to the bit line at the first time; After the second data is stored in the latch circuit, the sensing node is connected to the bit line at the second time during the period when the second read voltage is applied and the second read pass voltage is applied. Such as the semiconductor memory device of claim 2, wherein in the above-mentioned reading operation, Based on the above-mentioned first data, one of the above-mentioned second data or the above-mentioned third data is selected, Output the read data based on the above-mentioned one of the above-mentioned second data or the above-mentioned third data. Such as the semiconductor memory device of claim 3, wherein in the above-mentioned reading operation, From the time when the operation of connecting the sensing node to the bit line via the first transistor at the first time starts, to when the sensing node is connected to the bit line via the first transistor at the second time When the bit line connection operation ends, the second read pass voltage is continuously applied to the second word line. The semiconductor memory device of claim 4, wherein the sensing amplifier further has a second transistor, and the second transistor is connected between the power supply voltage supply node and the sensing node, During the second reading operation described above, Before the operation of connecting the sensing node to the bit line via the first transistor at the first time, the second transistor is turned on, After the second transistor is in the on state, before the operation of connecting the sensing node to the bit line via the first transistor at the first time, the second transistor is turned off, After the second transistor is in the off state, and the off state is maintained, the operation of connecting the sensing node to the bit line via the first transistor at the second time is started. The semiconductor memory device of claim 1, wherein the second memory cell is arranged between the first memory cell and the bit line. The semiconductor memory device of claim 1, wherein the first memory cell is arranged between the second memory cell and the bit line. The semiconductor memory device of claim 1, wherein the data written into the second memory cell is data written after the first memory cell. Such as the semiconductor memory device of claim 1, wherein the second time is longer than the first time, In the above reading action, When the first information above is the first, Output the read data based on the second data above, When the first information above is the second, Output the read data based on the third data above. Such as the semiconductor memory device of claim 1, wherein the second time is longer than the first time, In the above reading action, According to the first information above, When it means that the threshold voltage of the second memory cell is below the first read voltage, Output the read data based on the second data above, According to the first information above, When it means that the threshold voltage of the second memory cell is higher than the first read voltage, Output the read data based on the third data above. The semiconductor memory device of claim 1, wherein in the read operation, the second read operation is performed after the first read operation. The semiconductor memory device of claim 1, wherein in the read operation, the first read operation is performed after the second read operation. Such as the semiconductor memory device of claim 1, wherein in the above-mentioned reading operation, During the first reading operation described above, During the period when the sensing node is connected to the bit line via the first transistor, Apply a first read pass voltage higher than each of the first and second read voltages to the first word line, During the second reading operation described above, During the operation period of connecting the sensing node to the bit line at the first time, Applying a second read pass voltage higher than each of the first and second read voltages to the second word line, During the operation period in which the sensing node is connected to the bit line at the second time, A third read pass voltage that is higher than each of the first and second read voltages and different from the second read pass voltage is applied to the second word line. Such as the semiconductor memory device of claim 13, wherein the second time is longer than the first time, The third read pass voltage is higher than the second read pass voltage, In the above reading action, When the first information above is the first, Output the read data based on the second data above, When the first information above is the second, Output the read data based on the third data above. Such as the semiconductor memory device of claim 14, wherein the second time is longer than the first time, The third read pass voltage is higher than the second read pass voltage, In the above reading action, According to the first information above, When it means that the threshold voltage of the second memory cell is below the first read voltage, Output the read data based on the second data above, According to the first information above, When it means that the threshold voltage of the second memory cell is higher than the first read voltage, Output the read data based on the third data above. A reading method of a semiconductor memory device, which includes a step of performing a reading operation, the reading operation includes a first reading operation and a second reading operation, The above-mentioned semiconductor memory device includes: NAND string, which has first and second memory cells connected in series and adjacent to each other; The first character line is connected to the gate of the first memory cell; The second character line is connected to the gate of the second memory cell; Bit line, which is connected to the above-mentioned NAND string; and A sense amplifier, which includes a sensing node, a first transistor connected between the sensing node and the bit line, and a latch circuit; and In the above-mentioned reading operation of selecting the above-mentioned first character line, During the first reading operation described above, Apply the first read voltage to the second word line mentioned above, During the period when the first read voltage is applied, the sensing node is connected to the bit line via the first transistor, After the sensing node is connected to the bit line via the first transistor, the first data based on the voltage of the sensing node is stored in the latch circuit, During the second reading operation described above, Apply a second read voltage to the first word line mentioned above, During the period when the second read voltage is applied, the sensing node is connected to the bit line at the first time via the first transistor, After the sensing node is connected to the bit line at the first time through the first transistor, the second data based on the voltage of the sensing node is stored in the latch circuit, After the second data is stored in the latch circuit, during the period when the second read voltage is applied, the sensing node is connected to the bit at a second time different from the first time through the first transistor. Wire connection, After the sensing node is connected to the bit line at the second time through the first transistor, the third data based on the voltage of the sensing node is stored in the latch circuit.

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