TWI744033B - Active pixel sensor circuit and driving method thereof - Google Patents

Abstract

An active pixel sensor circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor, a photodiode and a read circuit. In a compensation period, the reference voltage is transported to the second transistor through the fourth transistor until the second transistor cut off, to compensate the threshold voltage of the second transistor. In an exposure period, the photodiode is configured to generate a photo current in response to a light illumination. In a read time, the read circuit is configured to output a pixel sensing output voltage corresponded by the photo current in response to the light illumination.

Description

Active pixel sensing circuit and driving method thereof

The content of this case is about an active pixel sensing circuit, especially a voltage compensated active pixel sensing circuit.

Compared with the passive pixel sensor circuit (Passive Pixel Sensor Circuit; PPS circuit), the active pixel sensor circuit (Active Pixel Sensor Circuit; APS circuit) has the advantage of higher photosensitivity. Generally speaking, X-ray irradiation will cause the deterioration of the components of the pixel sensing circuit. Therefore, under the same light sensitivity, the active pixel sensing circuit requires less exposure time than the passive pixel sensing circuit, which can be reduced The time for receiving X-rays is to delay the deterioration of the components of the pixel sensing circuit. However, the active pixel sensing circuit will still be degraded and uniform due to X-ray irradiation, resulting in a difference in the threshold voltage of the transistor that provides the driving current, and the read pixel sensing output voltage is affected by the threshold voltage. Influence.

The present disclosure provides an active pixel sensing circuit, which includes a first transistor, a second transistor, a third transistor, a fourth transistor, a capacitor, a photodiode, and a reading circuit. The first terminal of the first transistor is electrically coupled to a first system voltage terminal; the first terminal of the capacitor is electrically coupled to the second terminal of the first transistor; the photodiode is used for generating in response to a light irradiation A photocurrent, the first terminal of which is electrically coupled to the second terminal of the capacitor, and the second terminal of which is electrically coupled to a second system voltage terminal; the gate terminal of the second transistor is electrically coupled to the first terminal of the capacitor Terminal; the first terminal of the third transistor is electrically coupled to the second terminal of the second transistor and the second terminal of the capacitor, and the second terminal is electrically coupled to a system bias terminal; and the fourth transistor , Its first end is electrically coupled to the first end of the second transistor, and its second end is electrically coupled to a reading circuit for outputting and responding to the light generated by the light A pixel corresponding to the current senses the output voltage.

In summary, the present disclosure actively makes the pixel sensing circuit compensate the threshold voltage of the second transistor, so that the pixel sensing result is not affected by the threshold voltage.

The following is a detailed description of the embodiments in conjunction with the accompanying drawings to better understand the aspect of the case, but the embodiments provided are not used to limit the scope of the case, and the description of the structure operation is not used to limit it. The order of execution, any structure that recombines components, produces a device with an equal effect, are all within the scope of this project. In addition, according to industry standards and common practices, the drawings are only for the purpose of supplementary explanation, and are not drawn in accordance with the original dimensions. In fact, the dimensions of various features can be arbitrarily increased or decreased for ease of explanation. In the following description, the same elements will be described with the same symbols to facilitate understanding.

The index 1~n in the component numbers and signal numbers used in the description and drawings of this case are just for the convenience of referring to individual components and signals, and are not intended to limit the number of the aforementioned components and signals to a specific number. In the specification and drawings of this case, if a component number or signal number is used without specifying the index of the component number or signal number, it means that the component number or signal number refers to the component group or signal group to which it belongs. Any component or signal of.

In addition, the terms "include", "include", "have", "contain", etc. used in this article are all open terms, meaning "including but not limited to". In addition, the "and/or" used in this article includes any one or more of the related listed items and all combinations thereof.

In this text, when an element is referred to as "connection" or "coupling", it can refer to "electrical connection" or "electrical coupling". "Connected" or "coupled" can also be used to mean that two or more components cooperate or interact with each other. In addition, although terms such as “first”, “second”, etc. are used to describe different elements in this document, the terms are only used to distinguish elements or operations described in the same technical terms.

Please refer to FIG. 1. FIG. 1 is a circuit structure diagram of an active pixel sensing circuit 100 according to an embodiment of the disclosure. As shown in Figure 1, the active pixel sensing circuit 100 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a capacitor C1, a reading circuit RC, and a second photoelectric device.极体110。 Polar body 110. For example, the active pixel sensing circuit 100 can be used in the photosensitive elements of cameras, mobile phones, and image sensing circuits to convert optical signals into electrical signals. Generally, a plurality of active pixel sensing circuits 100 are included in a photosensitive element or an image sensing circuit to convert optical images into electrical signals. However, this disclosure only takes one active pixel sensing circuit 100 as an example, and in some embodiments, multiple active pixel sensing circuits 100 may be included. Therefore, this disclosure is not limited to this. In the embodiment of the present disclosure, the photodiode 110 is a PIN photodiode (P-Intrinsic-N Photodiode; PIN Photodiode) as an example. However, the photodiode 110 can also be selected from photoelectric crystals, other types of photodiodes, or other light sensing elements. Therefore, this disclosure is not limited to this.

As shown in Figure 1, the first terminal of the first transistor T1 is electrically coupled to the first system voltage terminal VDD, the gate terminal of the first transistor T1 is used to receive the first control signal S1, and the first terminal of the first transistor T1 The second terminal is electrically coupled to the first terminal of the capacitor C1. The second end of the capacitor C1 is electrically coupled to the first end of the photodiode 110. The second terminal of the photodiode 110 is electrically coupled to the second system voltage terminal VCOM.

The gate terminal of the second transistor T2 is electrically coupled to the second terminal of the first transistor T1 and the first terminal of the capacitor C1, and the first terminal of the second transistor T2 is electrically coupled to the first terminal of the fourth transistor T4 The second terminal of the second transistor T2 is electrically coupled to the first terminal of the third transistor T3, the second terminal of the capacitor C1, and the first terminal of the photodiode 110. The gate terminal of the third transistor T3 is used to receive the second control signal S2, and the first terminal of the third transistor T3 is electrically coupled to the system bias terminal VBIAS. The gate terminal of the fourth transistor T4 is used for receiving the third control signal S3, and the first terminal of the fourth transistor T4 is electrically coupled to the reading circuit RC.

The reading circuit RC includes an operational amplifier OPA and a capacitor C2. The first terminal of the operational amplifier OPA is electrically coupled to the second terminal of the fourth transistor T4, the second terminal of the operational amplifier OPA is electrically coupled to the reference voltage terminal VREF, and the output terminal of the operational amplifier OPA is used to output pixel sensing The output voltage Vout. The first terminal of the capacitor C2 is electrically coupled to the output terminal of the operational amplifier OPA, and the second terminal of the capacitor C2 is electrically coupled to the first terminal of the operational amplifier OPA.

Wherein, the node N1 is the connection point between the second terminal of the first transistor T1 and the first terminal of the capacitor C1. The node N2 is the junction between the second end of the capacitor C1 and the first end of the third transistor T3. The node N3 is the junction of the first end of the second transistor T2 and the first end of the fourth transistor T4.

The aforementioned transistors respectively have a first terminal, a second terminal, and a gate terminal (Gate). When the first terminal of one of the transistors is the drain terminal (source terminal), the second terminal of the transistor is the source terminal (drain terminal). In addition, the capacitor has a first terminal and a second terminal, and the operational amplifier with OPA has a first terminal, a second terminal, and an output terminal.

FIG. 2 is a timing diagram of the control signal of the active pixel sensing circuit 100 in FIG. 1 according to an embodiment. As shown in Figure 2, a display period in the control sequence of the active pixel sensing circuit 100 can be divided into five periods, which are the reset period P1, the compensation period P2, the exposure period P3, and the adjustment period P4. And during reading P5. It should be particularly noted that the time lengths of these periods in Figure 2 are only for example, and are not used to limit the disclosure.

The first control signal S1 has a first logic level V1 (for example, a high logic level) during the reset period P1, the compensation period P2, and the exposure period P3; the first control signal S1 has a first logic level V1 during the adjustment period P4 and the read period P5. Two logic levels V2 (for example: low logic level). The second control signal S2 has the first logic level during the reset period P1, the adjustment period P4 and the reading period P5; the second control signal S2 has the second logic level during the compensation period P2 and the exposure period P3. The third control signal S3 has the first logic level during the reset period P1, the compensation period P2 and the reading period P5; the third control signal S3 has the second logic level during the exposure period P3 and the adjustment period P4.

In order to make the sorting operation of the active pixel sensing circuit 100 clearer and easier to understand, please refer to Figures 1 to 6 together below.

FIG. 3 is a circuit state diagram of the active pixel sensing circuit 100 in FIG. 1 during the compensation period P2. FIG. 4 is a circuit state diagram of the active pixel sensing circuit 100 in FIG. 1 during the exposure period P3. FIG. 5 is a circuit state diagram of the active pixel sensing circuit 100 in FIG. 1 during the adjustment period P4. FIG. 6 is a circuit state diagram of the active pixel sensing circuit 100 in FIG. 1 during the reading period P5.

During the reset period P1, since the first control signal S1, the second control signal S2, and the third control signal S3 have high logic levels, the first transistor T1, the third transistor T3, and the fourth transistor T4 are turned on.

In detail, during the reset period P1, the voltage Vdd of the first system voltage terminal VDD is transmitted to the first terminal (node N1) of the capacitor C1 through the first transistor T1, so that the voltage level of the node N1 is substantially equal to the voltage Vdd. The voltage Vbias of the system bias terminal VBIAS is transmitted to the second terminal (node N2) of the capacitor C1 through the third transistor T3, so that the voltage level of the node N2 is substantially equal to the voltage Vbias. The voltage Vref of the reference voltage terminal VREF is transmitted to the first terminal (node N3) of the second transistor T2 through the operational amplifier OPA and the fourth transistor T4, so that the voltage level of the node N3 is substantially equal to the voltage Vref. In this way, the active pixel sensing circuit 100 completes the reset operation.

In practical applications, the voltage Vdd of the first system voltage terminal VDD may be -3 volts, and the voltage Vss of the second system voltage terminal VCOM may be -8 volts. In addition, the voltage Vref at the reference voltage terminal VREF may be 1 volt, and the voltage Vbias at the system bias terminal VBIAS may be -8 volts.

Then, during the compensation period P2, since the first control signal S1 and the third control signal S3 have high logic levels, the first transistor T1 and the fourth transistor T4 are turned on. On the other hand, since the second control signal S2 has a low logic level, the third transistor T3 will be turned off.

In detail, during the compensation period P2, the voltage Vdd of the first system voltage terminal VDD is transmitted to the first terminal (node N1) of the capacitor C1 through the first transistor T1, so the voltage level of the node N1 is substantially equal to the voltage Vdd, so that The second transistor T2 is turned on. The voltage Vref of the reference voltage terminal VREF increases the voltage of the second terminal of the capacitor C2 (node N2) through the fourth transistor T4 and the second transistor T2 until the second transistor T2 is turned off. That is, when the voltage at the second terminal of the second transistor T2 and the voltage at the gate terminal differ by a threshold voltage Vth, the second transistor T2 is turned off. At this time, the voltage level of the node N2 will be lower than the voltage level of the node N1 by a threshold voltage Vth. That is, the voltage level of the node N2 is substantially equal to (Vdd-Vth). Wherein, the above-mentioned threshold voltage Vth is the threshold voltage of the second transistor T2.

Then, during the exposure period P3, the device installed in the active pixel sensing circuit 100 allows light to be irradiated to the photodiode 110 (for example, the aperture on the light entrance path or the shutter is opened to allow the ambient light to irradiate the photodiode 110). Diode 110). At this time, the photodiode 110 will have different magnitudes of photocurrent according to the intensity of the illumination. For example, the image sensor in the camera may be a plurality of active pixel sensing circuits 100 arranged in an array. When the camera shutter is opened, the ambient light irradiates the photodiodes 110 in the multiple active pixel sensing circuits 100, and the photodiodes 110 respectively generate photocurrents according to the respective optical signals in the ambient light, for example, receiving The photodiode 110 in the darker part of the ambient light generates a smaller photocurrent, and the photodiode 110 that receives the brighter part of the ambient light generates a larger photocurrent. In this way, the photodiode 110 of each active pixel sensing circuit 100 converts the optical signals from the ambient light into photocurrents of different amplitudes. In addition, in some embodiments, outside of the exposure period P3, the device installed in the active pixel sensing circuit 100 will block light (for example, closing the aperture or shutter on the light path) to irradiate the photodiode 110.

During the exposure period P3, since the first control signal S1 has a high logic level, the first transistor T1 is turned on. On the other hand, since the second control signal S2 and the third control signal S3 have low logic levels, the third transistor T3 and the fourth transistor T4 are turned off.

In detail, during the exposure period P3, the voltage Vdd of the first system voltage terminal VDD is transmitted to the first terminal (node N1) of the capacitor C1 through the first transistor T1, so that the voltage level of the node N1 is substantially equal to the voltage Vdd. In addition, the third transistor T3 and the fourth transistor T4 are turned off, so that the second transistor T2 is electrically isolated from the reference voltage terminal VREF and the system bias terminal VBIAS. At the same time, the photodiode 110 generates a photocurrent in response to a light irradiation. The photocurrent turns on the photodiode 110, causing the voltage Vcom of the second system voltage terminal VCOM to pull down the second capacitor C1 through the photodiode 110. Terminal (node N2) until the photodiode 110 is turned off. At this time, the voltage level of the node N2 will decrease by the voltage ΔVp. That is, the voltage level of the second terminal (node N2) of the second transistor T2 is substantially equal to (Vdd-Vth-ΔVp).

The aforementioned voltage ΔVp corresponds to the magnitude of the photocurrent, and the photocurrent responds to the irradiation of light. For example, the light irradiation is stronger, the photocurrent is larger, and the voltage ΔVp is larger. On the other hand, the light is weaker, the photocurrent is smaller, and the voltage ΔVp is smaller. Specifically, the photocurrent is larger, the current flowing through the photodiode 110 is larger, and the value of the voltage ΔVp reduced by the voltage level of the node N2 will be larger. On the other hand, the photocurrent is small, the current flowing through the photodiode 110 is small, and the value of the voltage ΔVp reduced by the voltage level of the node N2 will be small.

Then, during the adjustment period P4, since the second control signal S2 has a high logic level, the third transistor T3 is turned on. On the other hand, since the first control signal S1 and the third control signal S3 have low logic levels, the first transistor T1 and the third transistor T3 are turned off.

In detail, the first transistor T1 is turned off to electrically isolate the first terminal of the capacitor C1 from the first system voltage terminal VDD. The fourth transistor T4 is turned off to electrically isolate the first terminal of the second transistor T2 from the reference voltage terminal VREF. The voltage Vbias of the system bias terminal VBIAS is transmitted to the second terminal (node N2) of the capacitor C1 via the third transistor T3, so that the voltage level of the node N2 is reduced by the voltage ΔV. That is, the voltage level of the node N2 is substantially equal to the voltage Vbias. In addition, the voltage Vbias of the system bias terminal VBIAS is coupled to the first terminal (node N1) of the capacitor C1 through the capacitor C1 through capacitive coupling, which also reduces the voltage level of the node N1 by the voltage ΔV. That is, the voltage level of the first terminal of the capacitor C1 is substantially equal to the voltage (Vdd-ΔV). The voltage level of the second terminal of the capacitor C1 is substantially equal to the voltage (Vdd-Vth-ΔVp-ΔV). At this time, the voltage across the gate terminal and the source terminal of the second transistor T2 (Vgs) is (Vth+ΔVp).

Then, during the reading period P5, since the second control signal S2 and the third control signal S3 have high logic levels, the third transistor T3 and the fourth transistor T4 are turned on. On the other hand, since the first control signal S1 has a low logic level, the first transistor T1 is turned off.

In detail, during the reading period P5, since the first transistor T1 is turned off, the first terminal (node N1) of the capacitor C1 is electrically isolated from the first system voltage terminal VDD. The voltage across the gate terminal and the source terminal of the second transistor T2 (Vgs) is still (Vth+ΔVp). Moreover, since the fourth transistor T4 is turned on, the second transistor T2 can provide the driving current Id to the reading circuit RC according to the voltage across the gate terminal and the source terminal (Vgs).

Generally speaking, the driving current Id provided by the N-type transistor complies with the following formula: Id=k(Vgs-Vth) ² . Among them, k is a constant related to the element characteristics of the second transistor T2, and Vth is the threshold voltage of the second transistor T2.

Substituting the voltage across the gate terminal and the source terminal (Vgs) of the second transistor T2 into the formula of the driving current Id, the driving current Id=k((Vth+ΔVp)-Vth) ² . After finishing, the drive current Id=k(ΔVp) ² . The voltage ΔVp is the voltage level at which the photocurrent generated by the photodiode 110 during the exposure period P3 causes the node N2 to be pulled down. Therefore, if the light irradiated to the photodiode 110 during the exposure period P3 is strong, the voltage ΔVp will be large, and the drive current Id during the reading period P5 will also be large. On the other hand, if the light irradiated to the photodiode 110 during the exposure period P3 is weak, the voltage ΔVp will be small, and the driving current Id during the reading period P5 will also be small.

During the reading period P5, the driving current Id provided by the voltage across the gate terminal and the source terminal (Vgs) of the second transistor T2 is transmitted to the reading circuit RC via the fourth transistor T4, so that the output of the reading circuit RC corresponds For the pixel sensing output voltage Vout of the driving current Id, in this embodiment, the pixel sensing result generated by the reading circuit RC according to the magnitude of the driving current Id at this time is the pixel sensing output voltage Vout in the analog form.

Please refer to FIG. 7, which is a circuit structure diagram of the active pixel sensing circuit 100 according to an embodiment of the disclosure. As shown in FIG. 7, the active pixel sensing circuit 100 further includes an analog-to-digital converter (ADC). The reading circuit RC is electrically coupled to the analog-to-digital converter ADC. In detail, the output terminal of the operational amplifier OPA is electrically coupled to the second terminal of the capacitor C2 and the analog-to-digital converter ADC. In the reading period P5, the reading circuit RC transmits the pixel sensing output voltage Vout in the analog form to the analog-to-digital converter ADC. That is, the analog-to-digital converter ADC can read the pixel sensing output voltage Vout in the current mode without being affected by the threshold voltage Vth. The analog-to-digital converter ADC can be used to convert the pixel sensing output voltage Vout in analog form into a digital gray scale value, which corresponds to the light intensity on the P3 photodiode 110 during the exposure period.

Please refer to FIG. 8. FIG. 8 is a circuit structure diagram of the active pixel sensing circuit 200 according to an embodiment of the disclosure. As shown in Figure 8, the active pixel sensing circuit 200 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a capacitor C1, a photodiode 110, and a read Take the circuit RC and analog-to-digital converter ADC. Compared with the embodiment of FIG. 7, the difference between the active pixel sensing circuit 200 and the active pixel sensing circuit 100 is that the reading circuit RC includes a fifth transistor T5 and a capacitor C2. In detail, the first terminal of the fifth transistor T5 is electrically coupled to the first terminal of the fourth transistor T4, the gate terminal of the fifth transistor T5 is used to receive the control signal Vb, and the second terminal of the fifth transistor T5 The terminal is electrically coupled to the reference voltage terminal VREF. The first terminal of the capacitor C2 is electrically coupled to the second terminal of the fourth transistor T4 and the analog-to-digital converter ADC, and the second terminal of the capacitor C2 is grounded. The remaining detailed actions and connection relationships of the active pixel sensing circuit 200 are roughly similar to those of the active pixel sensing circuit 100 in FIG. 7 and will not be repeated here.

It is worth noting that during the reading period P5, the control signal Vb has a high logic level, so the fifth transistor T5 is turned on. The driving current Id flows from the reference voltage terminal VREF, the fifth transistor T5, the fourth transistor T4, the second transistor T2, and the third transistor T3 to the system bias terminal VBIAS. The current flowing through the second transistor T2 is the same as the current flowing through the fifth transistor T5. Therefore, the reading circuit RC can also transmit the pixel sensing output voltage Vout that is not affected by the threshold voltage Vth of the second transistor T2 to the analog-to-digital converter ADC. That is, the analog-to-digital converter ADC can read the pixel sensing output voltage Vout in the voltage mode without being affected by the threshold voltage Vth.

The aforementioned transistors T1 to T5 are N-type MOSFET (NMOS) switches as an example, but the disclosure is not limited to this. In another embodiment, those skilled in the art can replace the above-mentioned transistors T1 to T5 with P-type MOSFET (PMOS) switches, C-type metal oxide Semiconductor field-effect transistor (C-type MOSFET, CMOSFET) switches or other similar switching elements, and control the system voltage (for example, the first system voltage terminal VDD and the second system voltage terminal VCOM) and control signals (for example, the first system voltage terminal VCOM) The logic levels of the control signal S1, the second control signal S2, and the third control signal S3), the reference voltage terminal VREF, and the system bias terminal VBIAS are adjusted correspondingly, and the same functions as in this embodiment can also be achieved.

It is worth noting that in the circuit structure of the present disclosure, whether the second transistor T2 is an enhanced or depleted field effect transistor, it can compensate the threshold voltage of the second transistor T2, so that the pixel senses the output voltage Vout is not affected by the threshold voltage Vth.

In summary, the present disclosure actively enables the pixel sensing circuit to compensate the threshold voltage of the second transistor T2, so that the pixel sensing output voltage Vout is not affected by the threshold voltage.

Although this case has been disclosed in the above implementation mode, it is not limited to this case. Anyone who is familiar with this technique can make various changes and modifications without departing from the spirit and scope of this case. Therefore, the scope of protection of this case should be attached hereafter. Those defined in the scope of the patent application shall prevail.

In order to make the above and other objectives, features, advantages and embodiments of the present disclosure more obvious and understandable, the description of the attached symbols is as follows:

100, 200: Active pixel sensing circuit

T1: The first transistor

T2: second transistor

T3: third transistor

T4: The fourth transistor

T5: fifth transistor

C1: Capacitance

110: photodiode

RC: read circuit

OPA: operational amplifier

C2: Capacitance

VDD: the first system voltage terminal

VCOM: second system voltage terminal

VBIAS: system bias terminal

VREF: reference voltage terminal

Vb: control signal

ADC: analog to digital converter

S1: The first control signal

S2: Second control signal

S3: The third control signal

N1, N2, N3: Node

Vout: pixel sensing output voltage

In order to make the above and other objectives, features, advantages and embodiments of the present disclosure more obvious and understandable, the description of the accompanying drawings is as follows: FIG. 1 is a circuit structure diagram of an active pixel sensing circuit according to an embodiment of the disclosure. FIG. 2 is a timing diagram of the control signal of the active pixel sensing circuit in FIG. 1 according to an embodiment. Figure 3 is a circuit state diagram of the active pixel sensing circuit in Figure 1 during the compensation period. Fig. 4 is a circuit state diagram of the active pixel sensing circuit in Fig. 1 during the exposure period. Figure 5 is a circuit state diagram of the active pixel sensing circuit in Figure 1 during the adjustment period. Fig. 6 is a circuit state diagram of the active pixel sensing circuit in Fig. 1 during the reading period. FIG. 7 is a circuit structure diagram of an active pixel sensing circuit according to an embodiment of the disclosure. FIG. 8 is a circuit structure diagram of an active pixel sensing circuit according to an embodiment of the disclosure.

Domestic deposit information (please note in the order of deposit institution, date and number) without Foreign hosting information (please note in the order of hosting country, institution, date, and number) without

100: Active pixel sensing circuit

T1: The first transistor

T2: second transistor

T3: third transistor

T4: The fourth transistor

C1: Capacitance

110: photodiode

RC: read circuit

OPA: operational amplifier

C2: Capacitance

VDD: the first system voltage terminal

VCOM: second system voltage terminal

VBIAS: system bias terminal

VREF: reference voltage terminal

S1: The first control signal

S2: Second control signal

S3: The third control signal

N1, N2, N3: Node

Vout: pixel sensing output voltage

Claims (13)

An active pixel sensing circuit, including: A first transistor, the first terminal of which is electrically coupled to a first system voltage terminal; A capacitor, the first terminal of which is electrically coupled to the second terminal of the first transistor; A photodiode for generating a photocurrent in response to a light irradiation, the first terminal of which is electrically coupled to the second terminal of the capacitor, and the second terminal of which is electrically coupled to a second system voltage terminal; A second transistor, the gate terminal of which is electrically coupled to the first terminal of the capacitor; A third transistor, the first terminal of which is electrically coupled to the second terminal of the second transistor and the second terminal of the capacitor, and the second terminal of which is electrically coupled to a system bias terminal; and A fourth transistor, the first terminal of which is electrically coupled to the first terminal of the second transistor, and the second terminal of which is electrically coupled to a reading circuit, wherein the reading circuit is used for outputting and responding to the light The output voltage of a pixel corresponding to the photocurrent generated by the irradiation is sensed. The active pixel sensing circuit according to claim 1, wherein: The gate terminal of the first transistor is used for receiving a first control signal to transmit a first system voltage of the first system voltage terminal to the first terminal of the capacitor according to the logic level of the first control signal; The third transistor is used for receiving a second control signal to transmit one of the system bias terminals to the second terminal of the capacitor according to the logic level of the second control signal; and The gate terminal of the fourth transistor is used for receiving a third control signal to transmit a reference voltage from the reading circuit to the first terminal of the second transistor according to the logic level of the third control signal. The active pixel sensing circuit according to claim 2, wherein during a reset period, the first control signal, the second control signal, and the third control signal have a first logic level, so that the first control signal A transistor, the third transistor, and the fourth transistor are turned on. The active pixel sensing circuit according to claim 3, wherein during the reset period, the first system voltage is transmitted to the first terminal of the capacitor, and the system bias voltage is transmitted to the second terminal of the capacitor , And transmit the reference voltage to the first terminal of the second transistor. The active pixel sensing circuit according to claim 2, wherein during a compensation period, the first control signal and the third control signal have a first logic level, so that the first transistor and the fourth The transistor is turned on, the second control signal has a second logic level, and the third transistor is turned off. The active pixel sensing circuit according to claim 5, wherein during the compensation period, the first system voltage is transmitted to the first terminal of the capacitor, and the voltage level of the second terminal of the capacitor drops to the second The transistor is off. The active pixel sensing circuit according to claim 2, wherein during an exposure period, the first control signal has a first logic level to turn on the first transistor, the second control signal and the second The three control signals have a second logic level, so that the third transistor and the fourth transistor are turned off. The active pixel sensing circuit according to claim 7, wherein during the exposure period, the first system voltage is transmitted to the first end of the capacitor, and the photodiode is used to generate The photocurrent. The active pixel sensing circuit according to claim 2, wherein during an adjustment period, the second control signal has a first logic level to turn on the third transistor, the first control signal and the second The three control signals have a second logic level, so that the first transistor and the fourth transistor are turned off. The active pixel sensing circuit according to claim 9, wherein during the adjustment period, the system bias is transmitted to the second end of the capacitor. The active pixel sensing circuit according to claim 2, wherein during a reading period, the second control signal and the third control signal have a first logic level, so that the third transistor and the second The four transistors are turned on, the first control signal has a second logic level, and the first transistor is turned off. The active pixel sensing circuit according to claim 11, wherein during the reading period, the first system voltage is transmitted to the first terminal of the capacitor, and the system bias voltage is transmitted to the second terminal of the capacitor And the reading circuit is used for outputting the pixel sensing output voltage corresponding to the photocurrent generated in response to the light irradiation. A driving method for driving the active pixel sensing circuit as described in claim 1, the driving method comprising: During a compensation period, the capacitor is electrically isolated from the bias terminal of the system by turning off the third transistor; During an exposure period, the second transistor is electrically isolated from the reading circuit by turning off the fourth transistor, and the photodiode is used to generate a photocurrent in response to a light irradiation; During an adjustment period, the capacitor is electrically isolated from the first system voltage terminal by turning off the first transistor, and a system bias voltage is transmitted to the capacitor by turning on the third transistor; and During a reading period, by turning on the fourth transistor, the reading circuit outputs a pixel sensing output voltage corresponding to the photocurrent generated in response to the light irradiation.

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