TWI743824B - Display panel and active component array substrate thereof - Google Patents

Abstract

An active component array substrate includes a substrate, a pixel array, a gate driver on array (GOA), an insulation layer, an auxiliary gate, and a temperature Controller. The substrate has a display area and a peripheral area located around the display area. The pixel array is distributed in the display area. The GOA is distributed in the peripheral area and includes a plurality of drive components. Each drive component includes at least one transistor, where the drive components are electrically connected to the pixel array. The insulation layer is disposed on the substrate and covers the pixel array and the GOA. The auxiliary gate is disposed on the insulation layer, where the insulation layer is disposed between the auxiliary gate and the GOA, and the auxiliary gate covers the gate of at least one of the transistors of at least one of the drive component. The temperature controller is electrically connected to the auxiliary gate.

Description

Display panel and active element array substrate thereof

The present invention relates to a display panel and an active device array substrate thereof, and more particularly to an active device array substrate with a gate drive array (Gate Driver on Array, GOA) and a display panel including the active device array substrate.

Existing display panels, such as Liquid Crystal Display Panels (LCD Panels), can normally display images at normal room temperature (for example, 25°C to 27°C). However, in high and low temperature environments, such as cold areas at high latitudes or hot areas at low latitudes, the display panel may not be able to display images normally due to the influence of temperature, thereby degrading image quality.

The present invention provides an active device array substrate, which can help improve the image quality of the display panel in the above-mentioned high temperature and low temperature environment.

The active device array substrate included in at least one embodiment of the present invention includes a substrate, a pixel array, a gate drive array, an insulating layer, an auxiliary gate, and a temperature controller. The substrate has a display area and a peripheral area located at the periphery of the display area. The pixel array is distributed in the display area. The gate driving array is distributed in the peripheral area and includes a plurality of driving elements. Each driving element includes at least one transistor, and these driving elements are electrically connected to the pixel array. The insulating layer is arranged on the substrate and covers the pixel array and the gate drive array. The auxiliary gate is arranged on the insulating layer, wherein the insulating layer is located between the auxiliary gate and the gate driving array, and the auxiliary gate covers a gate of at least one transistor of at least one of these driving elements. The temperature controller is electrically connected to the auxiliary gate.

In at least one embodiment of the present invention, the above-mentioned auxiliary gate completely covers the gate drive array.

In at least one embodiment of the present invention, the auxiliary gate includes a plurality of gate layers, and each gate layer covers the gate of at least one transistor of one of the driving elements.

In at least one embodiment of the present invention, each driving element includes a boost circuit and a boost control circuit, and each gate layer covers the boost circuit and the boost control circuit.

In at least one embodiment of the present invention, the auxiliary gate includes a plurality of gate layers, and each gate layer completely covers one of the driving elements.

In at least one embodiment of the present invention, when the active device array substrate is in the first temperature environment, the temperature controller provides the first bias voltage to the auxiliary gate. When the active device array substrate is in a second temperature environment, the temperature controller provides a second bias voltage to the auxiliary gate, wherein the temperature of the first temperature environment is greater than the temperature of the second temperature environment, and the first bias voltage and the second bias voltage Different from each other.

In at least one embodiment of the present invention, the first bias voltage is smaller than the second bias voltage.

In at least one embodiment of the present invention, the above-mentioned first bias voltage is greater than the second bias voltage.

At least one embodiment of the present invention includes a display panel including the above-mentioned active device array substrate and a counter substrate, wherein the counter substrate is disposed on the opposite side of the active device array substrate and connected to the active device array substrate.

In at least one embodiment of the present invention, the above-mentioned display panel further includes a liquid crystal layer, wherein the liquid crystal layer is sandwiched between the active device array substrate and the counter substrate.

The above-mentioned temperature controller can use the double gate effect to provide appropriate voltages to the active element array substrates in different temperature environments, reduce the temperature impact on the display panel, and help the display panel to display images normally under high or low temperature environments, and then Maintain or improve the image quality of the display panel.

In the following text, in order to clearly present the technical features of the case, the dimensions (such as length, width, thickness, and depth) of the elements (such as layers, films, substrates, and regions) in the drawings will be enlarged in unequal proportions. . Therefore, the description and explanation of the following embodiments are not limited to the size and shape presented by the elements in the drawings, but should cover the size, shape, and deviation of the two caused by actual manufacturing processes and/or tolerances. For example, the flat surface shown in the drawing may have rough and/or non-linear characteristics, and the acute angle shown in the drawing may be round. Therefore, the elements shown in the drawings of this case are mainly used for illustration, and are not intended to accurately depict the actual shape of the elements, nor are they used to limit the scope of the patent application in this case.

Secondly, the words "about", "approximately" or "substantially" appearing in the content of this case not only cover the clearly stated value and range of values, but also cover the understanding of those with ordinary knowledge in the technical field of the invention. The allowable deviation range of, wherein the deviation range can be determined by the error generated during the measurement, and this error is caused by the limitation of the measurement system or the process conditions, for example. In addition, "about" may mean within one or more standard deviations of the above-mentioned value, for example, within ±30%, ±20%, ±10%, or ±5%. The terms "about", "approximately" or "substantially" appearing in this text can be used to select acceptable deviation ranges or standard deviations based on optical properties, etching properties, mechanical properties, or other properties. The standard deviation applies all the above optical properties, etching properties, mechanical properties, and other properties.

FIG. 1A is a schematic cross-sectional view of at least one embodiment of the present invention. 1A, there are many types of display panel 100 in this embodiment, such as a liquid crystal display panel, a micro-LED display panel, or an organic light emitting diode display panel (Organic Light Emitting Diode). Display Panel, OLED Display Panel), where the display panel 100 shown in FIG. 1A is an example of a liquid crystal display panel. However, it is emphasized here that the display panel 100 is not limited to being a liquid crystal display panel.

The display panel 100 includes a counter substrate 110 and an active device array substrate 200, wherein the counter substrate 110 is disposed on the opposite side of the active device array substrate 200 and is connected to the active device array substrate 200. Taking FIG. 1A as an example, the counter substrate 110 may be a color filter substrate, which may include multiple filter layers or multiple photo-emissive quantum dot materials. The display panel 100 may further include a liquid crystal layer 120 and a sealant 130. The liquid crystal layer 120 is sandwiched between the active device array substrate 200 and the opposite substrate 110, and the sealant 130 surrounds the entire liquid crystal layer 120 and connects the active device array substrate 200 and the opposite substrate 110.

FIG. 1B is a schematic top view of the active device array substrate in FIG. 1A. The active device array substrate 200 includes a substrate 210, wherein the substrate 210 has a display area 211 and a peripheral area 212 located at the periphery of the display area 211, and the display area 211 and the peripheral area 212 do not overlap with each other. The active device array substrate 200 further includes a pixel array 220 and a gate driving array 230. The pixel array 220 and the gate driving array 230 are both disposed on the substrate 210 and distributed in the display area 211 and the peripheral area 212 respectively. The gate driving array 230 is disposed in the peripheral area 212 and not distributed in the display area 211.

The pixel array 220 may include a plurality of scan lines 221, and the scan lines 221 are electrically connected to the gate driving array 230. The active device array substrate 200 may further include a source circuit 240, and the pixel array 220 may further include a plurality of data lines 222. The source circuit 240 is also disposed in the peripheral area 212 outside the display area 211, and the data lines 222 are electrically connected to each other. Connect the source circuit 240. Therefore, by using the scan line 221 and the data line 222, the pixel array 220 is electrically connected to the gate driving array 230 and the source circuit 240.

In addition, the pixel array 220 also includes a plurality of pixel units (not shown), and each pixel unit has a pixel electrode and a transistor element. The transistor element is, for example, a thin film transistor, and is electrically connected to the pixel electrode. The transistor elements are electrically connected to the scan lines 221 and the data lines 222, wherein the scan line 221 is connected to the gate electrode of the transistor element, and the data line 222 is connected to the source electrode of the transistor element. In this way, the source circuit 240 and the gate drive array 230 can control the pixel unit via the data line 222 and the scan line 221, respectively, and the source circuit 240 can input the gray-scale voltage to the pixel electrode of the pixel unit via the data line 222. In order to deflect the liquid crystal molecules in the liquid crystal layer 120 above the pixel electrode, the display panel 100 is prompted to display an image.

The pixel array 220 further includes an auxiliary gate 250 and a temperature controller 260, wherein the temperature controller 260 is electrically connected to the auxiliary gate 250. The auxiliary gate 250 may be a conductive layer, and its constituent material is, for example, a metal material or a transparent conductive material. The auxiliary gate 250 is disposed in the peripheral area 212 and above the gate driving array 230, wherein the auxiliary gate 250 can completely cover the gate driving array 230, as shown in FIG. 1B. It should be noted that the coverage described herein may include contact and no contact, that is, the auxiliary gate 250 may completely cover the gate driving array 230, and may also not touch the gate driving array 230.

FIG. 1C is a schematic top view of the active device array substrate in FIG. 1B at its gate drive array. Referring to FIG. 1C, the gate driving array 230 includes a plurality of driving elements 231, and the driving elements 231 are electrically connected to the scan lines 221. Using the scan lines 221, the driving elements 231 are electrically connected to the pixel array 220. In addition, since the auxiliary gate 250 completely covers the gate driving array 230, the auxiliary gate 250 covers these driving elements 231, as shown in FIG. 1C.

FIG. 1D is a schematic top view of the active device array substrate in FIG. 1C at its driving devices. Please refer to FIG. 1C and FIG. 1D. In this embodiment, each driving element 231 may include a pull-up circuit U23a, a boost control circuit U23c, a pull-down circuit D23a, and a step-down circuit U23a. Control circuit D23c. In the same driving element 231, the step-up circuit U23a, the step-up control circuit U23c, the step-down circuit D23a, and the step-down control circuit D23c are electrically connected to each other. Since the auxiliary gate 250 covers these driving elements 231, the auxiliary gate 250 also completely covers the boost circuit U23a, boost control circuit U23c, buck circuit D23a, and buck control circuit D23c of each driving element 231.

FIG. 1E is a schematic cross-sectional view of the active device array substrate in FIG. 1D. Please refer to FIGS. 1D and 1E, where the driving element 231 shown in FIG. 1E can be drawn from the cross section of the boost circuit U23a or the boost control circuit U23c. The active device array substrate 200 further includes an insulating layer 270, wherein the insulating layer 270 is disposed on the substrate 210 and covers the pixel array 220 (see FIGS. 1B and 1C) and the gate driving array 230. The auxiliary gate 250 is disposed on the insulating layer 270, and the insulating layer 270 is located between the auxiliary gate 250 and the gate driving array 230.

Each driving element 231 includes at least one transistor 232. In the embodiment shown in FIG. 1E, the transistor 232 may be a thin film transistor or a field-effect transistor (Field-Effect Transistor, FET), for example, Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). The gate driving array 230 includes a metal layer 232g, an insulating layer 232i, a channel layer 232c, and a metal pattern layer. The metal layer 232g is formed on the substrate 210, and the insulating layer 232i is formed on the metal layer 232g and covers the metal layer 232g.

The channel layer 232c is formed on the insulating layer 232i, so that the insulating layer 232i can be sandwiched between the channel layer 232c and the metal layer 232g, wherein the channel layer 232c is a semiconductor layer. The metal pattern is formed on the channel layer 232c and includes a metal layer 232s and a metal layer 232d, wherein the metal layers 232s and 232d are separated from each other. The metal layers 232s and 232d can be formed by lithography etching. In order to ensure that the metal layers 232s and 232d are separated from each other, back channel etching can be performed to etch away a small part of the channel layer 232c below, thereby forming a groove on the channel layer 232c ( The picture is not marked).

Using the stack of these metal layers 232g, 232s, 232d, insulating layer 232i and channel layer 232c, the transistor 232 is formed, wherein the metal layer 232g is the gate electrode of the transistor 232, and the metal layers 232s and 232d are respectively the gate of the transistor 232 Source and drain. In addition, the auxiliary gate 250 covers the metal layer 232g, that is, the auxiliary gate 250 covers the gate of the transistor 232 of the driving element 231, wherein the auxiliary gate 250 does not contact the metal layer 232g.

It should be noted that although FIG. 1E only shows one transistor 232, the boost circuit U23a, the boost control circuit U23c, the buck circuit D23a, and the buck control circuit D23c may each include at least one transistor 232, so a single transistor 232 The driving element 231 may include a plurality of transistors 232. In addition, in other embodiments, each driving element 231 may include only one transistor 232, so the number of transistors 232 shown in FIG. 1E is for illustration only, and the number of transistors 232 included in each driving element 231 is not limited.

In the transistor 232, the channel layer 232c is sandwiched between two insulating layers 270 and 232i, and the two insulating layers 270 and 232i are also sandwiched between the auxiliary gate 250 and the metal layer 232g. Therefore, a capacitor is formed between the metal layer 232g and the channel layer 232c, and another capacitor is formed between the auxiliary gate 250 and the channel layer 232c.

When the input voltage is applied to the metal layer 232g, an electric field will be generated in the capacitor between the metal layer 232g and the channel layer 232c, and this electric field will change the depletion region in the channel layer 232c, so that the metal layers 232s and 232d are electrically connected to each other. Conduction or non-conduction. Similarly, when the input voltage is applied to the auxiliary gate 250, an electric field will also be generated in the capacitor between the auxiliary gate 250 and the channel layer 232c, and this electric field will also change the depletion region in the channel layer 232c, so that the metal layer 232s And 232d are electrically conductive or non-conductive to each other.

It can be seen that the voltage output by either the metal layer 232g and the auxiliary gate 250 can affect the carrier distribution in the channel layer 232c to control the electrical conduction between the metal layers 232s and 232d. When a voltage is input to the metal layer 232g and the auxiliary gate 250 at the same time, the channel layer 232c will be simultaneously affected by the electric field generated by both the metal layer 232g and the auxiliary gate 250, thereby generating a double gate effect.

1C and 1E, since the temperature controller 260 is electrically connected to the auxiliary gate 250, the temperature controller 260 can provide voltage to the auxiliary gate 250, where the temperature controller 260 can sense temperature and can have a temperature compensation voltage Function. In other words, the temperature controller 260 can output an appropriate voltage to the auxiliary gate 250 according to the sensed temperature to control the operation of the transistor 232.

For example, under the condition that the transistor 232 is an N-type metal oxide semiconductor field effect transistor (NMOSFET), when the active device array substrate 200 is in a high temperature environment, the temperature controller 260 will detect the high temperature, which can be adjusted It is between 40°C and 90°C, but the present invention is not limited to this. At this time, the threshold voltage of the transistor 232 in a high temperature environment usually drops, so that leakage current is likely to occur between the metal layer 232s (source) and the metal layer 232d (drain). At this time, the temperature controller 260 can provide a low voltage, such as a negative bias voltage, to the auxiliary gate 250 to reduce the leakage current.

In view of the above, when the active device array substrate 200 is in a low temperature environment, the temperature controller 260 will detect the low temperature, which may be between 0° C. and -40° C., but the present invention is not limited to this. At this time, the threshold voltage of the transistor 232 in a low-temperature environment usually rises, so that the transistor 232 needs a higher voltage to be turned on. At this time, the temperature controller 260 can provide a relatively high voltage, such as a positive bias voltage, to the auxiliary gate 250 to help turn on the transistor 232, thereby maintaining or improving the driving capability of the transistor 232 in a low temperature environment.

It can be seen that, under the condition that the transistor 232 is an N-type metal oxide semiconductor field effect transistor, when the active device array substrate 200 is in a first temperature environment (for example, a high temperature environment), the temperature controller 260 can provide a first bias A voltage (for example, a negative bias) is applied to the auxiliary gate 250 to reduce leakage current. When the active device array substrate 200 is in a second temperature environment (for example, a low temperature environment), the temperature controller 260 can provide a second bias voltage (for example, a positive bias voltage) to the auxiliary gate 250 to maintain or increase the electric power in the low temperature environment. The driving capability of the crystal 232, wherein the first bias voltage is smaller than the second bias voltage.

In addition, the transistor 232 may also be a P-type metal oxide semiconductor field effect transistor (PMOSFET). Under the condition that the transistor 232 is a P-type metal oxide semiconductor field effect transistor, when the active device array substrate 200 is in a first temperature environment (for example, a high temperature environment), the temperature controller 260 can provide a higher first bias voltage (For example, a positive bias) is applied to the auxiliary gate 250 to reduce leakage current. When the active device array substrate 200 is in a second temperature environment (such as a low temperature environment), the temperature controller 260 can provide a lower second bias voltage (such as a negative bias voltage) to the auxiliary gate 250 to maintain or improve the low temperature environment Under the driving capability of the transistor 232, the first bias voltage is greater than the second bias voltage.

Based on the above, the temperature controller 260 can provide an appropriate voltage to the auxiliary gate 250 according to the temperature measured by it, so as to reduce the leakage current generated by the transistor 232 in a high temperature environment, and to maintain or improve the temperature in a low temperature environment. The driving capability of the transistor 232. In this way, the use of the double gate effect can reduce the influence of temperature on the display panel 100 and help the display panel 100 to display images normally in a high temperature or low temperature environment, thereby maintaining or improving the image quality of the display panel 100.

2 is a schematic partial top view of an active device array substrate according to another embodiment of the invention. Please refer to FIG. 2. The active device array substrate 300 of this embodiment is similar to the active device array substrate 200 of the previous embodiment. Both include the same elements and the same or similar cross-sectional structure (as shown in FIG. 1E), and also have Substantially the same effect. The following mainly describes the differences between the active device array substrates 300 and 200, and the technical features of the two are not repeated in principle.

Different from the active device array substrate 200 in the foregoing embodiment, the auxiliary gate 350 included in the active device array substrate 300 is different from the foregoing auxiliary gate 250, wherein the auxiliary gate 350 does not completely cover the gate drive array 230 and includes A plurality of gate layers 351. These gate layers 351 are electrically connected to each other and are electrically connected to the temperature controller 260. Therefore, the temperature controller 260 can also provide appropriate voltages to the gate layers 351 according to the measured temperature.

The gate layers 351 cover the driving elements 231. Taking FIG. 2 as an example, the gate layers 351 respectively cover the driving elements 231, and each gate layer 351 completely covers one of the driving elements 231. In other words, each gate layer 351 completely covers the step-up circuit U23a, the step-up control circuit U23c, the step-down circuit D23a, and the step-down control circuit D23c of a single driving element 231. In addition, the cross-sectional structure of the driving element 231 under each gate layer 351 can be the same as the cross-sectional structure of the driving element 231 shown in FIG. Gate (the metal layer 232g as shown in Figure 1E).

3 is a schematic partial top view of an active device array substrate according to another embodiment of the invention. Please refer to FIG. 3, the active device array substrate 400 of this embodiment is similar to the active device array substrate 300 of the previous embodiment, and both include the same elements and the same or similar cross-sectional structure (as shown in FIG. 1E), and also have Substantially the same effect. The only difference between the active device array substrate 400 and the active device array substrate 300 is that in the active device array substrate 400, the multiple gate layers 451 of the auxiliary gate 450 do not completely cover the driving element 231.

Specifically, each gate layer 451 partially covers one of the driving elements 231, but does not completely cover the driving elements 231. Taking FIG. 3 as an example, each gate layer 451 completely covers the boost circuit U23a and the boost control circuit U23c of the driving element 231, but does not completely cover the buck circuit D23a and the buck control circuit D23c, as shown in FIG. It can be seen that, according to the embodiments shown in FIG. 1C, FIG. 1D, FIG. 2 and FIG. In addition, the auxiliary gate may only cover the gate of one of the transistors 232 of a single driving element 231. Or, the auxiliary gate may cover all the transistors 232 of the driving element 231. Therefore, there are many ways for the auxiliary gate to cover the driving element 231, and the present invention is not limited to the above-mentioned embodiment.

To sum up, in the display panel of at least one embodiment of the present invention, according to the double gate effect, the appropriate voltage provided by the temperature controller to the auxiliary gate can reduce the effect of temperature on the display panel, and help the display panel to operate at high or low temperatures. The image can be displayed normally under the environment, thereby maintaining or improving the image quality of the display panel.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field of the present invention can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of invention protection shall be subject to the scope of the attached patent application.

100: display panel 110: Opposite substrate 120: liquid crystal layer 130: frame glue 200, 300, 400: Active component array substrate 210: substrate 211: display area 212: Surrounding Area 220: pixel array 221: scan line 222: Data Line 230: gate drive array 231: drive element 232: Transistor 232c: channel layer 232d, 232g, 232s: metal layer 232i, 270: insulating layer 240: source circuit 250, 350, 450: auxiliary gate 260: temperature controller 351, 451: Gate layer D23a: Step-down circuit D23c: Step-down control circuit U23a: Boost circuit U23c: Boost control circuit

FIG. 1A is a schematic cross-sectional view of at least one embodiment of the present invention. FIG. 1B is a schematic top view of the active device array substrate in FIG. 1A. FIG. 1C is a schematic top view of the active device array substrate in FIG. 1B at its gate drive array. FIG. 1D is a schematic top view of the active device array substrate in FIG. 1C at its driving devices. FIG. 1E is a schematic cross-sectional view of the active device array substrate in FIG. 1D. 2 is a schematic partial top view of an active device array substrate according to another embodiment of the invention. 3 is a schematic partial top view of an active device array substrate according to another embodiment of the invention.

200: Active component array substrate

220: pixel array

221: scan line

230: gate drive array

231: drive element

250: auxiliary gate

260: temperature controller

Claims (17)

An active element array substrate, including A substrate having a display area and a peripheral area located at the periphery of the display area; A pixel array distributed in the display area; A gate driving array distributed in the peripheral area and including a plurality of driving elements, and each of the driving elements includes at least one transistor, wherein the driving elements are electrically connected to the pixel array; An insulating layer disposed on the substrate and covering the pixel array and the gate drive array; An auxiliary gate is disposed on the insulating layer, wherein the insulating layer is located between the auxiliary gate and the gate drive array, and the auxiliary gate covers the at least one transistor of at least one of the drive elements A gate; and A temperature controller is electrically connected to the auxiliary gate. The active device array substrate according to claim 1, wherein the auxiliary gate completely covers the gate driving array. The active device array substrate according to claim 1, wherein the auxiliary gate includes a plurality of gate layers, and each of the gate layers covers the gate of the at least one transistor of one of the driving elements. The active device array substrate according to claim 3, wherein each of the driving elements includes a boost circuit and a boost control circuit, and each of the gate layers covers the boost circuit and the boost control circuit. The active device array substrate according to claim 1, wherein the auxiliary gate includes a plurality of gate layers, and each of the gate layers completely covers one of the driving elements. The active device array substrate according to claim 1, wherein when the active device array substrate is in a first temperature environment, the temperature controller provides a first bias voltage to the auxiliary gate; When the active device array substrate is in a second temperature environment, the temperature controller provides a second bias voltage to the auxiliary gate, wherein the temperature of the first temperature environment is greater than the temperature of the second temperature environment, and the first temperature environment A bias voltage and the second bias voltage are different from each other. The active device array substrate according to claim 6, wherein the first bias voltage is less than the second bias voltage. The active device array substrate according to claim 6, wherein the first bias voltage is greater than the second bias voltage. A display panel including: An active device array substrate, including: A substrate having a display area and a peripheral area located at the periphery of the display area; A pixel array distributed in the display area; A gate driving array distributed in the peripheral area and including a plurality of driving elements, and each of the driving elements includes at least one transistor, wherein the driving elements are electrically connected to the pixel array; An insulating layer disposed on the substrate and covering the pixel array and the gate drive array; An auxiliary gate is disposed on the insulating layer, wherein the insulating layer is located between the auxiliary gate and the gate drive array, and the auxiliary gate covers the at least one transistor of at least one of the drive elements A gate A temperature controller electrically connected to the auxiliary gate; and The pair of facing substrates are arranged on the opposite side of the active device array substrate and connected to the active device array substrate. The display panel according to claim 9, further comprising a liquid crystal layer, wherein the liquid crystal layer is sandwiched between the active device array substrate and the counter substrate. The display panel according to claim 9, wherein the auxiliary gate completely covers the gate driving array. The display panel according to claim 9, wherein the auxiliary gate includes a plurality of gate layers, and each of the gate layers covers the gate of the at least one transistor of one of the driving elements. The display panel according to claim 12, wherein each of the driving elements includes a boost circuit and a boost control circuit, and each of the gate layers covers the boost circuit and the boost control circuit. The display panel according to claim 9, wherein the auxiliary gate includes a plurality of gate layers, and each of the gate layers completely covers one of the driving elements. The display panel according to claim 9, wherein when the active device array substrate is in a first temperature environment, the temperature controller provides a first bias voltage to the auxiliary gate; When the active device array substrate is in a second temperature environment, the temperature controller provides a second bias voltage to the auxiliary gate, wherein the temperature of the first temperature environment is greater than the temperature of the second temperature environment, and the first temperature environment A bias voltage and the second bias voltage are different from each other. The display panel according to claim 15, wherein the first bias voltage is less than the second bias voltage. The display panel according to claim 15, wherein the first bias voltage is greater than the second bias voltage.

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