TWI742728B - Memory device and data access method - Google Patents

Memory device and data access method Download PDF

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TWI742728B
TWI742728B TW109120446A TW109120446A TWI742728B TW I742728 B TWI742728 B TW I742728B TW 109120446 A TW109120446 A TW 109120446A TW 109120446 A TW109120446 A TW 109120446A TW I742728 B TWI742728 B TW I742728B
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memory
data
memory cells
memory device
data signal
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TW109120446A
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TW202201419A (en
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鄭翔及
林建忠
張恕豪
蕭夏彩
陳忠宏
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友達光電股份有限公司
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Priority to CN202011444069.5A priority patent/CN112530485B/en
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C17/00Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C17/00Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18Auxiliary circuits, e.g. for writing into memory
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/08Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

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  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)

Abstract

A memory device includes multiple switches and a memory array. The memory array includes multiple memory cells forming multiple rows and columns, wherein each of memory cells includes a memory element and a transistor. The memory element is configured to represent a first memory status and a second memory status different from each other. The transistor coupled between one of the corresponded switches and the memory element is configured to store or access the memory array. The memory cells of the same row are coupled to the same switch, and the memory cells of different row are coupled to different switches.

Description

記憶體裝置與資料存取方法Memory device and data access method

本揭示內容是關於一種記憶體裝置與資料存取方法,特別是關於透過同一選擇開關存取一列記憶體元件的一種記憶體裝置與資料存取方法。The present disclosure relates to a memory device and a data access method, in particular to a memory device and a data access method for accessing a row of memory elements through the same selection switch.

現有記憶體製程中可量產的可編程唯讀記憶體(Programmable Read-Only Memory, PROM),於編程後通常需要進行雷射切割。Programmable Read-Only Memory (PROM), which can be mass-produced in the existing memory system, usually requires laser cutting after programming.

然而,自動化雷射機台昂貴,雷射振鏡組亦為高單價耗材,且以雷射切割技術來編程唯讀記憶體還需要預留切割線與雷射對位標誌而占用龐大布局空間。However, automated laser machines are expensive, and the laser galvanometer group is also a high unit price consumable, and the use of laser cutting technology to program the read-only memory also needs to reserve cutting lines and laser alignment marks, which takes up a huge layout space.

本揭示文件提供一種記憶體裝置,其包含複數個選擇開關以及記憶體陣列。記憶體陣列包含排列為多行與多列的複數個記憶胞,其中上述記憶體胞每一者包含一記憶體元件以及一電晶體。記憶體元件,用於表示彼此不同的第一記憶狀態和第二記憶狀態。電晶體,耦接於上述選擇開關中的對應一者與記憶體元件之間。選擇開關用於存取記憶體陣列,同一列中的記憶胞耦接於相同的選擇開關,且不同列中的記憶胞耦接於不同的選擇開關。The present disclosure provides a memory device, which includes a plurality of selection switches and a memory array. The memory array includes a plurality of memory cells arranged in multiple rows and multiple columns, wherein each of the memory cells includes a memory element and a transistor. The memory element is used to represent a first memory state and a second memory state that are different from each other. The transistor is coupled between the corresponding one of the above-mentioned selection switches and the memory element. The selection switch is used to access the memory array, the memory cells in the same row are coupled to the same selection switch, and the memory cells in different rows are coupled to different selection switches.

本揭示文件提供一種資料存取方法,其適用於一記憶體裝置,其中資料存取方法包含:由時序控制電路產生複數個位元訊號與複數個字元訊號,其中記憶體裝置包含複數個選擇開關,記憶體陣列包含排列為多行與多列的複數個記憶胞,上述選擇開關由位元訊號控制,多行中的記憶胞分別由字元訊號控制;當利用字元訊號的其中之一選擇多行中的對應一行時,上述選擇開關回應位元訊號而依序導通,其中上述選擇開關分別耦接於多列以使上述對應一行中的記憶胞依序接收資料訊號;以及利用資料訊號對上述對應一行中的記憶胞進行資料操作。The present disclosure provides a data access method suitable for a memory device. The data access method includes: generating a plurality of bit signals and a plurality of character signals by a timing control circuit, wherein the memory device includes a plurality of options A switch. The memory array includes a plurality of memory cells arranged in multiple rows and multiple columns. The above-mentioned selection switch is controlled by a bit signal, and the memory cells in the multiple rows are controlled by a character signal; when one of the character signals is used When the corresponding row of the multiple rows is selected, the selection switches are sequentially turned on in response to the bit signal, wherein the selection switches are respectively coupled to the multiple rows so that the memory cells in the corresponding row sequentially receive data signals; and use the data signals Perform data operations on the memory cells in the corresponding row above.

上述的記憶體裝置與資料存取方法,能夠節省可編程唯讀記憶體在製程上的空間與成本。The above-mentioned memory device and data access method can save the space and cost of the programmable read-only memory in the manufacturing process.

下文係舉實施例配合所附圖式作詳細說明,但所描述的具體實施例僅僅用以解釋本發明,並不用來限定本發明,而結構操作之描述非用以限制其執行之順序,任何由元件重新組合之結構,所產生具有均等功效的裝置,皆為本發明揭示內容所涵蓋的範圍。The following is a detailed description of the embodiments in conjunction with the accompanying drawings. However, the specific embodiments described are only used to explain the present invention and are not used to limit the present invention. The description of structural operations is not used to limit the order of its execution. The recombined structure of the components produces devices with equal effects, which are all covered by the disclosure of the present invention.

在全篇說明書與申請專利範圍所使用之用詞(terms),除有特別註明外,通常具有每個用詞使用在此領域中、在此揭露之內容中與特殊內容中的平常意義。某些用以描述本揭露之用詞將於下或在此說明書的別處討論,以提供本領域技術人員在有關本揭露之描述上額外的引導。Unless otherwise specified, the terms used in the entire specification and the scope of the patent application usually have the usual meaning of each term used in this field, in the content disclosed here, and in the special content. Some terms used to describe the present disclosure will be discussed below or elsewhere in this specification to provide those skilled in the art with additional guidance on the description of the present disclosure.

於本文中,當一元件被稱為『連接』或『耦接』時,可指『電性連接』或『電性耦接』。『連接』或『耦接』亦可用以表示二或多個元件間相互搭配操作或互動。此外,雖然本文中使用『第一』、『第二』、…等用語描述不同元件,該用語僅是用以區別以相同技術用語描述的元件或操作。In this text, when an element is referred to as "connection" or "coupling", it can refer to "electrical connection" or "electrical coupling". "Connected" or "coupled" can also be used to mean that two or more components cooperate or interact with each other. In addition, although terms such as “first”, “second”, etc. are used to describe different elements in this document, the terms are only used to distinguish elements or operations described in the same technical terms.

此外,在本文中所使用的用詞『包含』、『包括』、『具有』、『含有』等等,均為開放性的用語,即意指『包含但不限於』。此外,本文中所使用之『及/或』,包含相關列舉項目中一或多個項目的任意一個以及其所有組合。In addition, the terms "include", "include", "have", "contain", etc. used in this article are all open terms, meaning "including but not limited to". In addition, the "and/or" used in this article includes any one or more of the related listed items and all combinations thereof.

第1圖為根據本揭示文件一些實施例所繪示的記憶體裝置100簡化的功能方塊圖。記憶體裝置100包含記憶體陣列110、時序控制電路130、資料處理電路140以及複數個選擇開關SW[0]~SW[n]。FIG. 1 is a simplified functional block diagram of the memory device 100 according to some embodiments of the present disclosure. The memory device 100 includes a memory array 110, a timing control circuit 130, a data processing circuit 140, and a plurality of selection switches SW[0]~SW[n].

時序控制電路130藉由複數條字元線WL[0]~WL[m]耦接至記憶體陣列110,並藉由複數條位元線BL[0]~BL[n]分別耦接至選擇開關SW[0]~SW[n]。資料處理電路140則藉由一資料線DL與選擇開關SW[0]~SW[n] 耦接。The timing control circuit 130 is coupled to the memory array 110 via a plurality of word lines WL[0]~WL[m], and is respectively coupled to the selection via a plurality of bit lines BL[0]~BL[n] Switch SW[0]~SW[n]. The data processing circuit 140 is coupled to the selection switches SW[0]~SW[n] via a data line DL.

在一些實施例中,選擇開關SW[0]~SW[n]可由金屬氧化物半導體場效電晶體實現,或者由薄膜電晶體(thin-film transistor,簡稱TFT)來實現。In some embodiments, the selection switches SW[0] to SW[n] can be implemented by metal oxide semiconductor field effect transistors, or thin-film transistors (TFTs for short).

記憶體陣列110包含排列為多行與多列的複數個記憶胞120。多行中的記憶胞120分別與字元線WL[0]~WL[m]耦接,且選擇開關SW[0]~SW[n]分別由位元線BL[0]~BL[n]控制。多列中的記憶胞120分別與選擇開關SW[0]~SW[n]耦接,其中同一列的記憶胞120耦接選擇開關SW[0]~SW[n]中相同的一者,而不同列中的記憶胞120耦接於選擇開關SW[0]~SW[n]中不同者。The memory array 110 includes a plurality of memory cells 120 arranged in multiple rows and multiple columns. The memory cells 120 in multiple rows are respectively coupled to the word lines WL[0]~WL[m], and the selection switches SW[0]~SW[n] are respectively connected to the bit lines BL[0]~BL[n] control. The memory cells 120 in multiple rows are respectively coupled to the selection switches SW[0]~SW[n], wherein the memory cells 120 in the same row are coupled to the same one of the selection switches SW[0]~SW[n], and The memory cells 120 in different rows are coupled to different ones of the selection switches SW[0]~SW[n].

第2圖為根據本揭示文件一些實施例所繪示的資料存取方法200的流程圖。第3圖為根據本揭示文件一實施例所繪示的記憶體裝置100的訊號時序波形圖。為方便說明,第2圖所示的資料存取方法200係參照第1圖與第3圖來做說明,但不以其為限。FIG. 2 is a flowchart of a data access method 200 according to some embodiments of the present disclosure. FIG. 3 is a signal timing waveform diagram of the memory device 100 according to an embodiment of the present disclosure. For the convenience of description, the data access method 200 shown in FIG. 2 is described with reference to FIG. 1 and FIG. 3, but is not limited thereto.

請先參照第2圖,資料存取方法200用於編程記憶體陣列110,且包含流程S210~S230。於流程S210,時序控制電路130產生複數個字元訊號W[0]~W[m]與複數個位元訊號B[0]~B[n]。時序控制電路130用以藉由字元線WL[0]~WL[m]分別提供字元訊號W[0]~W[m]至記憶體陣列110,以及藉由位元線BL[0]~BL[n]分別提供位元訊號B[0]~B[n]至選擇開關SW[0]~SW[n]。換言之,記憶體陣列110多行中的記憶胞120分別由字元訊號W[0]~W[m]控制,而選擇開關SW[0]~SW[n]分別由位元訊號B[0]~B[n]控制。Please refer to FIG. 2 first, the data access method 200 is used to program the memory array 110 and includes the processes S210 to S230. In the process S210, the timing control circuit 130 generates a plurality of character signals W[0]~W[m] and a plurality of bit signals B[0]~B[n]. The timing control circuit 130 is used to provide the word signals W[0]~W[m] to the memory array 110 through the word lines WL[0]~WL[m] respectively, and through the bit lines BL[0] ~BL[n] provides bit signals B[0]~B[n] to the selector switches SW[0]~SW[n] respectively. In other words, the memory cells 120 in the rows of the memory array 110 are respectively controlled by the character signals W[0]~W[m], and the selection switches SW[0]~SW[n] are respectively controlled by the bit signals B[0] ~B[n] control.

接續流程S210,於流程S220中,當時序控制電路130將字元訊號W[0]~W[m]的其中之一切換至邏輯高準位(例如,高電壓)以選擇多行中的對應一行時,時序控制電路130會將位元訊號B[0]~B[n]依序切換至邏輯高準位以使選擇開關SW[0]~SW[n]依序導通。由於選擇開關SW[0]~SW[n]分別耦接於記憶體陣列110的多列,經選擇的對應一行中的記憶胞120會依序接收資料訊號Data。Following the process S210, in the process S220, when the timing control circuit 130 switches one of the character signals W[0]~W[m] to a logic high level (for example, high voltage) to select the corresponding one of the multiple rows For one line, the timing control circuit 130 will sequentially switch the bit signals B[0]~B[n] to a logic high level to turn on the selection switches SW[0]~SW[n] in sequence. Since the selection switches SW[0]~SW[n] are respectively coupled to the rows of the memory array 110, the selected memory cells 120 in the corresponding row will sequentially receive the data signal Data.

舉例來說,如第3圖所示,時序控制電路130可以於流程S220中選擇耦接於字元線WL[0]的一行記憶胞120(以下稱為第一行記憶胞120)。此時,選擇開關SW[0]~SW[n]回應位元訊號B[0]~B[n]而依序導通。也就是說,在第一行記憶胞120接收到具有邏輯高準位的字元訊號W[0]的期間,選擇開關SW[0]~SW[n]回應位元訊號B[0]~B[n]依次導通,而將資料訊號傳遞至第一行記憶胞120。For example, as shown in FIG. 3, the timing control circuit 130 can select a row of memory cells 120 (hereinafter referred to as the first row of memory cells 120) coupled to the word line WL[0] in the process S220. At this time, the selector switches SW[0]~SW[n] are turned on in order in response to the bit signals B[0]~B[n]. That is, during the period when the first row memory cell 120 receives the character signal W[0] with a logic high level, the selection switches SW[0]~SW[n] respond to the bit signal B[0]~B [n] Turns on sequentially, and transmits the data signal to the first row of memory cells 120.

上述資料訊號Data可以是由資料處理電路140產生,並藉由選擇開關SW[0]~SW[n]提供至記憶體陣列110。如第4圖所示,第4圖為根據本揭示文件一些實施例所繪示的記憶體裝置100的部分示意圖。記憶體陣列110中排列為多行與多列的每一個記憶胞120包含記憶體元件121與電晶體122。The above-mentioned data signal Data may be generated by the data processing circuit 140 and provided to the memory array 110 through the selection switches SW[0]˜SW[n]. As shown in FIG. 4, FIG. 4 is a partial schematic diagram of the memory device 100 according to some embodiments of the present disclosure. Each memory cell 120 arranged in multiple rows and multiple columns in the memory array 110 includes a memory element 121 and a transistor 122.

電晶體122則耦接於選擇開關SW[0]~SW[n]中的對應一者與記憶體元件121之間,且電晶體122的控制端用以接收字元訊號W[0]~W[m]中的對應一者。記憶體元件121耦接於電晶體122和接地端之間,且記憶體元件121用於表示彼此不同的第一記憶狀態和第二記憶狀態。The transistor 122 is coupled between the corresponding one of the selection switches SW[0]~SW[n] and the memory element 121, and the control terminal of the transistor 122 is used to receive the character signal W[0]~W The corresponding one in [m]. The memory element 121 is coupled between the transistor 122 and the ground terminal, and the memory element 121 is used to represent a first memory state and a second memory state that are different from each other.

在記憶體元件121是以反熔絲元件來實現的一些實施例中,第一記憶狀態是指記憶體元件121因接收到資料訊號Data具有高於崩潰臨界電壓的第一電壓準位的脈波,而被編程為低阻值。具有第一記憶狀態的記憶體元件121被讀取時會近似於短路,可用來代表邏輯狀態0。第二記憶狀態是指記憶體元件121因接收到的資料訊號Data低於崩潰臨界電壓,而被編程為高阻值。具有第二記憶狀態的記憶體元件121被讀取時會近似於斷路,可用來代表邏輯狀態1,但本揭示文件並不以此為限。In some embodiments in which the memory element 121 is implemented as an anti-fuse element, the first memory state refers to the pulse wave of the memory element 121 having a first voltage level higher than the breakdown threshold voltage due to the data signal Data received. , And is programmed as a low resistance value. The memory element 121 with the first memory state is similar to a short circuit when read, and can be used to represent the logic state 0. The second memory state means that the memory device 121 is programmed to a high resistance value because the received data signal Data is lower than the breakdown threshold voltage. The memory element 121 with the second memory state is similar to an open circuit when read, and can be used to represent the logic state 1, but the present disclosure is not limited to this.

在另外一些記憶體元件121是以熔絲元件來實現的實施例中,第二記憶狀態是指記憶體元件121接收到資料訊號Data具有高於崩潰臨界電壓的第一電壓準位的脈波,而被編程為高阻值,導致其被讀取時近似於斷路,可用來代表邏輯狀態1。第一記憶狀態是指記憶體元件121接收到的資料訊號Data低於崩潰臨界電壓,而被編程為低阻值,導致其被讀取時近似於短路,可用來代表邏輯狀態0。In some other embodiments in which the memory element 121 is implemented by a fuse element, the second memory state refers to that the memory element 121 receives a pulse wave of the data signal Data having a first voltage level higher than the breakdown threshold voltage. It is programmed to a high resistance value, which causes it to be read as an open circuit, which can be used to represent logic state 1. The first memory state means that the data signal Data received by the memory device 121 is lower than the breakdown threshold voltage and is programmed to a low resistance value, which causes it to be read as a short circuit, which can be used to represent the logic state 0.

於流程S230中,為了編程記憶體陣列110,當選擇開關SW[0]~SW[n]依次導通時,資料訊號Data會提供具有第一電壓準位的一或多個脈波至流程S220中選擇的該對應一行中對應的一或多個記憶胞120。In the process S230, in order to program the memory array 110, when the selection switches SW[0]~SW[n] are turned on sequentially, the data signal Data will provide one or more pulses with the first voltage level to the process S220 One or more memory cells 120 corresponding to the selected corresponding row.

例如,如第3圖所示,若時序控制電路130於流程S220中選取耦接於字元線WL[0]的第一行記憶胞120,資料處理電路140會於流程S230傳送如第3圖所示的資料訊號Data。當選擇開關SW4被位元訊號B[4]的邏輯高準位導通時,資料訊號Data提供具有第一電壓準位的脈波至對應選擇開關SW4的記憶體元件121,而當選擇開關SW3被位元訊號B[3]的邏輯高位導通時,資料訊號提供具有第一電壓準位的脈波至對應選擇開關SW3的記憶體元件121,依此類推,當選擇開關SW1被位元訊號B[1]的邏輯高位導通時,資料訊號Data提供具有第一電壓準位的脈波至對應選擇開關SW1的記憶體元件121。For example, as shown in FIG. 3, if the timing control circuit 130 selects the first row of memory cells 120 coupled to the word line WL[0] in the process S220, the data processing circuit 140 will transmit in the process S230 as shown in FIG. 3 The data signal Data shown. When the selection switch SW4 is turned on by the logic high level of the bit signal B[4], the data signal Data provides a pulse with the first voltage level to the memory element 121 corresponding to the selection switch SW4, and when the selection switch SW3 is turned on When the logic high of the bit signal B[3] is turned on, the data signal provides a pulse with the first voltage level to the memory element 121 corresponding to the selection switch SW3, and so on, when the selection switch SW1 is received by the bit signal B[ When the logic high of 1] is turned on, the data signal Data provides a pulse with the first voltage level to the memory element 121 corresponding to the selection switch SW1.

承上所述,第一行記憶胞120中,對應選擇開關SW4、 選擇開關SW3以及選擇開關SW1的記憶體元件121被編程為第一記憶狀態(低阻值)而代表邏輯狀態0;而其他未接收到資料訊號Data具有第一電壓準位的脈波的記憶體元件121,被編程為第二記憶狀態(高阻值)而代表邏輯狀態1。As mentioned above, in the first row of memory cells 120, the memory elements 121 corresponding to the selection switch SW4, the selection switch SW3, and the selection switch SW1 are programmed to the first memory state (low resistance value) and represent the logic state 0; and the others The memory device 121 that has not received the pulse of the data signal Data having the first voltage level is programmed to the second memory state (high resistance value) and represents the logic state 1.

值得注意的是,在上述的多個實施例中,流程S210~S230可以平行地執行,而無需依序執行。It is worth noting that, in the above-mentioned multiple embodiments, the processes S210 to S230 can be executed in parallel, and do not need to be executed sequentially.

在執行完資料存取方法200後,記憶體裝置100對記憶體陣列110中的一行記憶胞120進行了編程。為完整編程記憶體陣列110,記憶體裝置100可以多次執行資料存取方法200,以依序編程記憶體陣列110中的多行記憶胞120。After the data access method 200 is executed, the memory device 100 programs a row of memory cells 120 in the memory array 110. To program the memory array 110 completely, the memory device 100 may execute the data access method 200 multiple times to program the rows of memory cells 120 in the memory array 110 in sequence.

在一些實施例中,當記憶體裝置100多次執行資料存取方法200時,記憶體裝置100的時序波形圖會如第5圖所示。時序控制電路130是以一正序方向依次將字元訊號W[0]~W[m]切換至邏輯高準位。例如,字元訊號W[0]導通耦接於字元線WL[0]的電晶體122後,字元訊號W[1]再導通耦接於字元線WL[1]的電晶體122,以此類推,直到字元訊號W[m]導通耦接於字元線WL[m]的電晶體122。In some embodiments, when the memory device 100 executes the data access method 200 multiple times, the timing waveform diagram of the memory device 100 is as shown in FIG. 5. The timing control circuit 130 sequentially switches the character signals W[0]~W[m] to a logic high level in a positive sequence direction. For example, after the character signal W[0] turns on the transistor 122 coupled to the word line WL[0], the character signal W[1] then turns on the transistor 122 coupled to the word line WL[1]. By analogy, until the word signal W[m] is turned on the transistor 122 coupled to the word line WL[m].

請再參考第5圖,在一些實施例中,時序控制電路130產生之位元訊號B[0]~B[n]以不同於上述正序方向的反序方向依次導通記憶體裝置100的選擇開關SW[0]~SW[n]。例如,位元訊號B[n] 導通耦接於位元線BL[n]的選擇開關SW[n]後,位元訊號B[n-1] 再導通耦接於位元線BL[n-1]的選擇開關SW[n-1],依此類推,直到位元訊號B[0] 導通耦接於位元線BL[0] 的選擇開關SW[0]。Please refer to FIG. 5 again. In some embodiments, the bit signals B[0]~B[n] generated by the timing control circuit 130 sequentially turn on the selection of the memory device 100 in a reverse sequence direction different from the above-mentioned forward sequence direction. Switch SW[0]~SW[n]. For example, after the bit signal B[n] is turned on and coupled to the selection switch SW[n] of the bit line BL[n], the bit signal B[n-1] is turned on and coupled to the bit line BL[n- The selection switch SW[n-1] of 1], and so on, until the bit signal B[0] turns on the selection switch SW[0] coupled to the bit line BL[0].

換言之,當時序控制電路130以遠離自身的方向依序將字元訊號W[0]~W[m]切換至邏輯高準位時,位元訊號B[0]~B[n]以靠近資料處理電路140的方向依次導通選擇開關SW[0]~SW[n]。In other words, when the timing control circuit 130 sequentially switches the character signals W[0]~W[m] to the logic high level in a direction away from itself, the bit signals B[0]~B[n] are close to the data The direction of the processing circuit 140 sequentially turns on the selection switches SW[0] to SW[n].

由上述可知,字元訊號W[0]~W[m]中的任一者脈波寬度大於位元訊號B[0]~B[n]任一者之脈波寬度,且字元訊號W[0]~W[m]中的任一者之脈波寬度大於或等於位元訊號B[0]~B[n] 每一者之脈波寬度總和。例如,如第3圖和第5圖所示,字元訊號W[0]大於位元訊號B[0]~B[n]任一者之脈波寬度,且字元訊號W[0]的脈波寬度大於或等於位元訊號B[0]~B[n] 每一者之脈波寬度總和。It can be seen from the above that the pulse width of any one of the character signals W[0]~W[m] is greater than the pulse width of any one of the bit signals B[0]~B[n], and the character signal W The pulse width of any one of [0]~W[m] is greater than or equal to the sum of the pulse widths of each of the bit signals B[0]~B[n]. For example, as shown in Figures 3 and 5, the character signal W[0] is greater than the pulse width of any one of the bit signals B[0]~B[n], and the character signal W[0] The pulse width is greater than or equal to the sum of the pulse widths of each bit signal B[0]~B[n].

第6圖為根據本揭示文件一些實施例所繪示的資料存取方法600的流程圖。第7圖為根據本揭示文件一實施例所繪示的記憶體裝置100的訊號時序波形圖。資料存取方法600用於讀取記憶體陣列110,其包含前述的流程S210~S220,且還包含流程S630。流程S210~S220之具體內容已見於前述段落,為簡潔起見,在此不重複贅述。FIG. 6 is a flowchart of a data access method 600 according to some embodiments of the present disclosure. FIG. 7 is a signal timing waveform diagram of the memory device 100 according to an embodiment of the present disclosure. The data access method 600 is used to read the memory array 110, which includes the aforementioned processes S210 to S220, and also includes the process S630. The specific content of the processes S210 to S220 has been seen in the foregoing paragraphs, and for the sake of brevity, the details are not repeated here.

接續流程S220,於流程S630,為了讀取記憶體陣列110,記憶體裝置100將具有第二電壓準位的資料訊號Data提供至流程S220中選擇的該對應一行。Following the process S220, in the process S630, in order to read the memory array 110, the memory device 100 provides the data signal Data having the second voltage level to the corresponding row selected in the process S220.

舉例來說,如第7圖所示,時序控制電路130可以於流程S220中選取耦接於字元線WL[0]的第一行記憶胞120,且第一行記憶胞120中對應於選擇開關SW1、SW3以及SW4的記憶胞120已被編程為第一記憶狀態,而第一行記憶胞120中其餘的記憶胞120已被編程為第二記憶狀態。此時,於流程S630,當資料電壓Data傳遞至第一行記憶胞120中對應於選擇開關SW4、選擇開關SW3以及選擇開關SW1的記憶胞120時,資料電壓Data會自第二電壓準位變化至接地電壓。For example, as shown in FIG. 7, the timing control circuit 130 may select the first row of memory cells 120 coupled to the word line WL[0] in the process S220, and the first row of memory cells 120 corresponding to the selected The memory cells 120 of the switches SW1, SW3, and SW4 have been programmed to the first memory state, and the remaining memory cells 120 in the first row of memory cells 120 have been programmed to the second memory state. At this time, in the process S630, when the data voltage Data is transferred to the memory cells 120 corresponding to the selection switch SW4, the selection switch SW3, and the selection switch SW1 in the first row of memory cells 120, the data voltage Data will change from the second voltage level To ground voltage.

另一方面,當資料訊號Data傳入第一行記憶胞120當中其餘被編程為第二記憶狀態的記憶胞120時,資料訊號Data維持於第二電壓準位。On the other hand, when the data signal Data is transmitted to the remaining memory cells 120 programmed to the second memory state among the memory cells 120 in the first row, the data signal Data is maintained at the second voltage level.

值得注意的是,在上述的多個實施例中,流程S210~S220和S630可以平行地執行,而無需依序執行。It is worth noting that, in the above-mentioned multiple embodiments, the processes S210 to S220 and S630 can be executed in parallel, and do not need to be executed sequentially.

在執行完資料存取方法600後,記憶體裝置100對記憶體陣列110中的一行記憶胞120進行了讀取。為完整讀取記憶體陣列110,記憶體裝置100可以多次執行資料存取方法600,以依序讀取記憶體陣列中的多行記憶胞120。After the data access method 600 is executed, the memory device 100 reads a row of memory cells 120 in the memory array 110. In order to read the memory array 110 completely, the memory device 100 may execute the data access method 600 multiple times to sequentially read the rows of memory cells 120 in the memory array.

在一些實施例中,當記憶體裝置100多次執行資料存取方法600時,記憶體裝置100的時序波形圖會相似於前述的第5圖,差異在於,資料訊號Data最高為第二電壓準位,為簡潔起見,在此不再贅述。In some embodiments, when the memory device 100 executes the data access method 600 for multiple times, the timing waveform diagram of the memory device 100 will be similar to that of Figure 5 above. The difference is that the data signal Data is the highest voltage level of the second voltage. For the sake of brevity, I won’t repeat them here.

在一些實施例中,當記憶體裝置100執行資料存取方法600時,資料處理電路140用以藉由資料線DL上的資料電壓Data判斷記憶體元件122對應於第一記憶狀態或第二記憶狀態。因此,資料處理電路140得以讀取出記憶體裝置100中的儲存內容。In some embodiments, when the memory device 100 executes the data access method 600, the data processing circuit 140 is used to determine whether the memory element 122 corresponds to the first memory state or the second memory based on the data voltage Data on the data line DL state. Therefore, the data processing circuit 140 can read the stored content in the memory device 100.

在一些實施例中,資料處理電路140包含積分器及/或其他具有運算能力的邏輯電路,例如現場可程式化邏輯閘(FPGA)、特殊應用積體電路(ASIC)或微處理器。In some embodiments, the data processing circuit 140 includes an integrator and/or other logic circuits with computing capabilities, such as a field programmable logic gate (FPGA), an application-specific integrated circuit (ASIC), or a microprocessor.

在一些實施例中,第一電壓準位介於15~20伏特之間,第二電壓準位介於5~10伏特之間。In some embodiments, the first voltage level is between 15-20 volts, and the second voltage level is between 5-10 volts.

雖然本揭示內容已以實施方式揭露如上,然其並非用以限定本揭示內容,任何本領域具通常知識者,在不脫離本揭示內容之精神和範圍內,當可作各種之更動與潤飾,因此本揭示內容之保護範圍當視後附之申請專利範圍所界定者為準。Although the content of this disclosure has been disclosed in the above embodiments, it is not intended to limit the content of this disclosure. Anyone with ordinary knowledge in the field can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, the protection scope of this disclosure shall be subject to those defined by the attached patent application scope.

100:記憶體裝置 110:記憶體陣列 120:記憶胞 121:記憶體元件 122:電晶體 130:時序控制電路 140:資料處理電路 200,600:資料存取方法 S210,S220,S230,S630:流程 SW[0]~SW[n]:選擇開關 WL[0]~WL[m]:字元線 BL[0]~BL[n]:位元線 W[0]~W[m]:字元訊號 B[0]~B[n]:位元訊號 Data:資料訊號 DL:資料線 100: Memory device 110: memory array 120: memory cell 121: memory component 122: Transistor 130: timing control circuit 140: data processing circuit 200,600: data access method S210, S220, S230, S630: process SW[0]~SW[n]: selector switch WL[0]~WL[m]: Character line BL[0]~BL[n]: bit line W[0]~W[m]: character signal B[0]~B[n]: bit signal Data: data signal DL: Data line

第1圖為根據本揭示文件一些實施例所繪示的記憶體裝置簡化的功能方塊圖。 第2圖為根據本揭示文件一些實施例所繪示的資料存取方法的流程圖。 第3圖為根據本揭示文件一實施例所繪示的記憶體裝置的訊號時序波形圖。 第4圖為根據本揭示文件一些實施例所繪示的記憶體裝置的部分示意圖。 第5圖為根據本揭示文件一些實施例所繪示的訊號時序波形圖。 第6圖為根據本揭示文件一些實施例所繪示的資料存取方法的流程圖。 第7圖為根據本揭示文件一實施例所繪示的記憶體裝置的訊號時序波形圖。 FIG. 1 is a simplified functional block diagram of a memory device according to some embodiments of the present disclosure. FIG. 2 is a flowchart of a data access method according to some embodiments of the present disclosure. FIG. 3 is a signal timing waveform diagram of the memory device according to an embodiment of the present disclosure. FIG. 4 is a partial schematic diagram of a memory device according to some embodiments of the present disclosure. FIG. 5 is a signal timing waveform diagram drawn according to some embodiments of the present disclosure. FIG. 6 is a flowchart of a data access method according to some embodiments of the present disclosure. FIG. 7 is a signal timing waveform diagram of the memory device according to an embodiment of the present disclosure.

100:記憶體裝置 100: Memory device

110:記憶體陣列 110: memory array

120:記憶胞 120: memory cell

130:時序控制電路 130: timing control circuit

140:資料處理電路 140: data processing circuit

SW[0]~SW[n]:選擇開關 SW[0]~SW[n]: selector switch

WL[0]~WL[m]:字元線 WL[0]~WL[m]: Character line

BL[0]~BL[n]:位元線 BL[0]~BL[n]: bit line

W[0]~W[m]:字元訊號 W[0]~W[m]: character signal

B[0]~B[n]:位元訊號 B[0]~B[n]: bit signal

Data:資料訊號 Data: data signal

DL:資料線 DL: Data line

Claims (12)

一種記憶體裝置,包含:複數個選擇開關,用以接收複數個位元訊號;以及一記憶體陣列,用以接收複數個字元訊號,其中該記憶體陣列包含排列為多行與多列的複數個記憶胞,其中該些記憶體胞每一者包含:一記憶體元件,用於表示彼此不同的一第一記憶狀態和一第二記憶狀態;以及一電晶體,耦接於該些選擇開關中的對應一者與該記憶體元件之間;其中該些選擇開關用於存取該記憶體陣列,同一列中的記憶胞耦接於相同的選擇開關,且不同列中的記憶胞耦接於不同的選擇開關,其中該記憶體陣列用以根據該些字元訊號其中之一選擇該多行中的對應一行記憶胞,該些選擇開關用以回應該些位元訊號而依序導通,以使該對應一行記憶胞依序接收一資料訊號。 A memory device includes: a plurality of selection switches for receiving a plurality of bit signals; and a memory array for receiving a plurality of character signals, wherein the memory array includes a plurality of rows and rows A plurality of memory cells, wherein each of the memory cells includes: a memory element for representing a first memory state and a second memory state that are different from each other; and a transistor coupled to the options Between the corresponding one of the switches and the memory element; wherein the selection switches are used to access the memory array, the memory cells in the same row are coupled to the same selection switch, and the memory cells in different rows are coupled Connected to different selection switches, where the memory array is used to select a corresponding row of memory cells in the plurality of rows according to one of the character signals, and the selection switches are used to sequentially turn on in response to the bit signals , So that the corresponding row of memory cells sequentially receives a data signal. 如請求項1所述之記憶體裝置,其中,該多行中的記憶胞分別與複數條字元線耦接,且該些選擇開關分別由複數條位元線控制,該記憶體裝置更包含:一時序控制電路,用以藉由該些字元線提供該些字元訊號,以及藉由該些位元線提供該些位元訊號。 The memory device according to claim 1, wherein the memory cells in the multiple rows are respectively coupled to a plurality of character lines, and the selection switches are respectively controlled by a plurality of bit lines, the memory device further includes : A timing control circuit for providing the character signals through the word lines, and providing the bit signals through the bit lines. 如請求項2所述之記憶體裝置,其中該些字 元訊號任一者之脈波寬度大於該些位元訊號任一者之脈波寬度。 The memory device according to claim 2, wherein the words The pulse width of any one of the meta signals is greater than the pulse width of any one of the bit signals. 如請求項2所述之記憶體裝置,其中該些字元訊號任一者之脈波寬度大於或等於該些位元訊號每一者之脈波寬度總和。 The memory device according to claim 2, wherein the pulse width of any one of the character signals is greater than or equal to the sum of the pulse widths of each of the bit signals. 如請求項2所述之記憶體裝置,其中:該時序控制電路將該些字元訊號以一正序方向依序切換至邏輯高準位;該時序控制電路產生該些位元訊號以不同於該正序方向的一反序方向依次導通該記憶體裝置的該些選擇開關。 The memory device according to claim 2, wherein: the timing control circuit sequentially switches the character signals to a logic high level in a positive sequence direction; the timing control circuit generates the bit signals different from A reverse sequence direction of the positive sequence direction sequentially turns on the selection switches of the memory device. 如請求項1所述之記憶體裝置,更包含:一資料處理電路,與該些選擇開關耦接於一資料線,用以藉由該些選擇開關提供該資料訊號至該記憶體陣列,其中該資料訊號之脈衝具有一第一電壓準位時,該記憶體裝置處於一編程模式;該資料訊號之脈衝具有一第二電壓準位時,該記憶體裝置處於一讀取模式,且該資料處理電路用以藉由該資料線讀取該記憶體裝置中該些記憶體元件對應的該第一記憶狀態或該第二記憶狀態。 The memory device according to claim 1, further comprising: a data processing circuit coupled to a data line with the selection switches for providing the data signal to the memory array through the selection switches, wherein When the pulse of the data signal has a first voltage level, the memory device is in a programming mode; when the pulse of the data signal has a second voltage level, the memory device is in a read mode, and the data The processing circuit is used for reading the first memory state or the second memory state corresponding to the memory elements in the memory device through the data line. 如請求項6所述之記憶體裝置,其中該第一電壓準位介於15~20伏特之間,該第二電壓準位介於5~10伏特之間。 The memory device according to claim 6, wherein the first voltage level is between 15-20 volts, and the second voltage level is between 5-10 volts. 如請求項6所述之記憶體裝置,其中該記憶體元件為熔絲元件或是反熔絲元件。 The memory device according to claim 6, wherein the memory element is a fuse element or an anti-fuse element. 一種資料存取方法,適用於一記憶體裝置,其中該資料存取方法包含:由一時序控制電路產生複數個位元訊號與複數個字元訊號,其中該記憶體裝置包含複數個選擇開關與一記憶體陣列,該記憶體陣列包含排列為多行與多列的複數個記憶胞,該些選擇開關分別由該些位元訊號控制,該記憶體陣列的該多行分別由該些字元訊號控制;當利用該些字元訊號的其中之一選擇該多行中的對應一行記憶胞時,該些選擇開關回應該些位元訊號而依序導通,其中該些選擇開關分別耦接於該多列以使該對應一行記憶胞依序接收一資料訊號;以及利用該資料訊號對該對應一行記憶胞進行一資料操作。 A data access method is suitable for a memory device, wherein the data access method includes: generating a plurality of bit signals and a plurality of character signals by a timing control circuit, wherein the memory device includes a plurality of selection switches and A memory array including a plurality of memory cells arranged in rows and columns, the selection switches are controlled by the bit signals, and the rows of the memory array are respectively controlled by the characters Signal control; when one of the character signals is used to select the corresponding row of memory cells in the multiple rows, the selection switches are turned on in sequence in response to the bit signals, and the selection switches are respectively coupled to The multiple rows enable the corresponding row of memory cells to sequentially receive a data signal; and use the data signal to perform a data operation on the corresponding row of memory cells. 如請求項9所述之資料存取方法,其中每個記憶胞包含一記憶體元件與一電晶體,其中利用該資料訊號對該對應一行記憶胞進行該資料操作的流程包含:若該資料操作為編程操作,則該資料訊號提供具有一第 一電壓準位的一或多個脈波至該對應一行記憶胞中的一或多個記憶胞;其中該第一電壓高於該記憶體元件的一崩潰臨界電壓,以使該一或多個記憶胞具有一第一記憶狀態,該對應一行記憶胞中不同於該一或多個記憶胞之其餘記憶胞具有一第二記憶狀態。 The data access method according to claim 9, wherein each memory cell includes a memory element and a transistor, and the process of using the data signal to perform the data operation on the corresponding row of memory cells includes: if the data operation For programming operation, the data signal is provided with a first One or more pulses of a voltage level to one or more memory cells in the corresponding row of memory cells; wherein the first voltage is higher than a breakdown threshold voltage of the memory device, so that the one or more The memory cell has a first memory state, and the other memory cells in the corresponding row of memory cells that are different from the one or more memory cells have a second memory state. 如請求項10所述之資料存取方法,利用該資料訊號對該對應一行中的記憶胞進行該資料操作的流程還包含:若該資料操作為讀取操作,則該資料訊號具有一第二電壓準位,其中該第一電壓準位高於該第二電壓準位;其中當該資料訊號傳入該其餘記憶胞時,該資料訊號維持於該第二電壓準位,當該資料訊號傳入該一或多個記憶胞時,該資料訊號自該第二電壓準位變化至一接地電壓。 For the data access method described in claim 10, the process of using the data signal to perform the data operation on the memory cell in the corresponding row further includes: if the data operation is a read operation, the data signal has a second Voltage level, wherein the first voltage level is higher than the second voltage level; wherein when the data signal is transmitted to the remaining memory cells, the data signal is maintained at the second voltage level, and when the data signal is transmitted When entering the one or more memory cells, the data signal changes from the second voltage level to a ground voltage. 如請求項10所述之資料存取方法,其中該些字元訊號任一者之脈波寬度大於或等於該些位元訊號每一者之脈波寬度總和。 The data access method according to claim 10, wherein the pulse width of any one of the character signals is greater than or equal to the sum of the pulse widths of each of the bit signals.
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