TWI742728B - Memory device and data access method - Google Patents

Abstract

A memory device includes multiple switches and a memory array. The memory array includes multiple memory cells forming multiple rows and columns, wherein each of memory cells includes a memory element and a transistor. The memory element is configured to represent a first memory status and a second memory status different from each other. The transistor coupled between one of the corresponded switches and the memory element is configured to store or access the memory array. The memory cells of the same row are coupled to the same switch, and the memory cells of different row are coupled to different switches.

Description

Memory device and data access method

The present disclosure relates to a memory device and a data access method, in particular to a memory device and a data access method for accessing a row of memory elements through the same selection switch.

Programmable Read-Only Memory (PROM), which can be mass-produced in the existing memory system, usually requires laser cutting after programming.

However, automated laser machines are expensive, and the laser galvanometer group is also a high unit price consumable, and the use of laser cutting technology to program the read-only memory also needs to reserve cutting lines and laser alignment marks, which takes up a huge layout space.

The present disclosure provides a memory device, which includes a plurality of selection switches and a memory array. The memory array includes a plurality of memory cells arranged in multiple rows and multiple columns, wherein each of the memory cells includes a memory element and a transistor. The memory element is used to represent a first memory state and a second memory state that are different from each other. The transistor is coupled between the corresponding one of the above-mentioned selection switches and the memory element. The selection switch is used to access the memory array, the memory cells in the same row are coupled to the same selection switch, and the memory cells in different rows are coupled to different selection switches.

The present disclosure provides a data access method suitable for a memory device. The data access method includes: generating a plurality of bit signals and a plurality of character signals by a timing control circuit, wherein the memory device includes a plurality of options A switch. The memory array includes a plurality of memory cells arranged in multiple rows and multiple columns. The above-mentioned selection switch is controlled by a bit signal, and the memory cells in the multiple rows are controlled by a character signal; when one of the character signals is used When the corresponding row of the multiple rows is selected, the selection switches are sequentially turned on in response to the bit signal, wherein the selection switches are respectively coupled to the multiple rows so that the memory cells in the corresponding row sequentially receive data signals; and use the data signals Perform data operations on the memory cells in the corresponding row above.

The above-mentioned memory device and data access method can save the space and cost of the programmable read-only memory in the manufacturing process.

The following is a detailed description of the embodiments in conjunction with the accompanying drawings. However, the specific embodiments described are only used to explain the present invention and are not used to limit the present invention. The description of structural operations is not used to limit the order of its execution. The recombined structure of the components produces devices with equal effects, which are all covered by the disclosure of the present invention.

Unless otherwise specified, the terms used in the entire specification and the scope of the patent application usually have the usual meaning of each term used in this field, in the content disclosed here, and in the special content. Some terms used to describe the present disclosure will be discussed below or elsewhere in this specification to provide those skilled in the art with additional guidance on the description of the present disclosure.

In this text, when an element is referred to as "connection" or "coupling", it can refer to "electrical connection" or "electrical coupling". "Connected" or "coupled" can also be used to mean that two or more components cooperate or interact with each other. In addition, although terms such as “first”, “second”, etc. are used to describe different elements in this document, the terms are only used to distinguish elements or operations described in the same technical terms.

In addition, the terms "include", "include", "have", "contain", etc. used in this article are all open terms, meaning "including but not limited to". In addition, the "and/or" used in this article includes any one or more of the related listed items and all combinations thereof.

FIG. 1 is a simplified functional block diagram of the memory device 100 according to some embodiments of the present disclosure. The memory device 100 includes a memory array 110, a timing control circuit 130, a data processing circuit 140, and a plurality of selection switches SW[0]~SW[n].

The timing control circuit 130 is coupled to the memory array 110 via a plurality of word lines WL[0]~WL[m], and is respectively coupled to the selection via a plurality of bit lines BL[0]~BL[n] Switch SW[0]~SW[n]. The data processing circuit 140 is coupled to the selection switches SW[0]~SW[n] via a data line DL.

In some embodiments, the selection switches SW[0] to SW[n] can be implemented by metal oxide semiconductor field effect transistors, or thin-film transistors (TFTs for short).

The memory array 110 includes a plurality of memory cells 120 arranged in multiple rows and multiple columns. The memory cells 120 in multiple rows are respectively coupled to the word lines WL[0]~WL[m], and the selection switches SW[0]~SW[n] are respectively connected to the bit lines BL[0]~BL[n] control. The memory cells 120 in multiple rows are respectively coupled to the selection switches SW[0]~SW[n], wherein the memory cells 120 in the same row are coupled to the same one of the selection switches SW[0]~SW[n], and The memory cells 120 in different rows are coupled to different ones of the selection switches SW[0]~SW[n].

FIG. 2 is a flowchart of a data access method 200 according to some embodiments of the present disclosure. FIG. 3 is a signal timing waveform diagram of the memory device 100 according to an embodiment of the present disclosure. For the convenience of description, the data access method 200 shown in FIG. 2 is described with reference to FIG. 1 and FIG. 3, but is not limited thereto.

Please refer to FIG. 2 first, the data access method 200 is used to program the memory array 110 and includes the processes S210 to S230. In the process S210, the timing control circuit 130 generates a plurality of character signals W[0]~W[m] and a plurality of bit signals B[0]~B[n]. The timing control circuit 130 is used to provide the word signals W[0]~W[m] to the memory array 110 through the word lines WL[0]~WL[m] respectively, and through the bit lines BL[0] ~BL[n] provides bit signals B[0]~B[n] to the selector switches SW[0]~SW[n] respectively. In other words, the memory cells 120 in the rows of the memory array 110 are respectively controlled by the character signals W[0]~W[m], and the selection switches SW[0]~SW[n] are respectively controlled by the bit signals B[0] ~B[n] control.

Following the process S210, in the process S220, when the timing control circuit 130 switches one of the character signals W[0]~W[m] to a logic high level (for example, high voltage) to select the corresponding one of the multiple rows For one line, the timing control circuit 130 will sequentially switch the bit signals B[0]~B[n] to a logic high level to turn on the selection switches SW[0]~SW[n] in sequence. Since the selection switches SW[0]~SW[n] are respectively coupled to the rows of the memory array 110, the selected memory cells 120 in the corresponding row will sequentially receive the data signal Data.

For example, as shown in FIG. 3, the timing control circuit 130 can select a row of memory cells 120 (hereinafter referred to as the first row of memory cells 120) coupled to the word line WL[0] in the process S220. At this time, the selector switches SW[0]~SW[n] are turned on in order in response to the bit signals B[0]~B[n]. That is, during the period when the first row memory cell 120 receives the character signal W[0] with a logic high level, the selection switches SW[0]~SW[n] respond to the bit signal B[0]~B [n] Turns on sequentially, and transmits the data signal to the first row of memory cells 120.

The above-mentioned data signal Data may be generated by the data processing circuit 140 and provided to the memory array 110 through the selection switches SW[0]˜SW[n]. As shown in FIG. 4, FIG. 4 is a partial schematic diagram of the memory device 100 according to some embodiments of the present disclosure. Each memory cell 120 arranged in multiple rows and multiple columns in the memory array 110 includes a memory element 121 and a transistor 122.

The transistor 122 is coupled between the corresponding one of the selection switches SW[0]~SW[n] and the memory element 121, and the control terminal of the transistor 122 is used to receive the character signal W[0]~W The corresponding one in [m]. The memory element 121 is coupled between the transistor 122 and the ground terminal, and the memory element 121 is used to represent a first memory state and a second memory state that are different from each other.

In some embodiments in which the memory element 121 is implemented as an anti-fuse element, the first memory state refers to the pulse wave of the memory element 121 having a first voltage level higher than the breakdown threshold voltage due to the data signal Data received. , And is programmed as a low resistance value. The memory element 121 with the first memory state is similar to a short circuit when read, and can be used to represent the logic state 0. The second memory state means that the memory device 121 is programmed to a high resistance value because the received data signal Data is lower than the breakdown threshold voltage. The memory element 121 with the second memory state is similar to an open circuit when read, and can be used to represent the logic state 1, but the present disclosure is not limited to this.

In some other embodiments in which the memory element 121 is implemented by a fuse element, the second memory state refers to that the memory element 121 receives a pulse wave of the data signal Data having a first voltage level higher than the breakdown threshold voltage. It is programmed to a high resistance value, which causes it to be read as an open circuit, which can be used to represent logic state 1. The first memory state means that the data signal Data received by the memory device 121 is lower than the breakdown threshold voltage and is programmed to a low resistance value, which causes it to be read as a short circuit, which can be used to represent the logic state 0.

In the process S230, in order to program the memory array 110, when the selection switches SW[0]~SW[n] are turned on sequentially, the data signal Data will provide one or more pulses with the first voltage level to the process S220 One or more memory cells 120 corresponding to the selected corresponding row.

For example, as shown in FIG. 3, if the timing control circuit 130 selects the first row of memory cells 120 coupled to the word line WL[0] in the process S220, the data processing circuit 140 will transmit in the process S230 as shown in FIG. 3 The data signal Data shown. When the selection switch SW4 is turned on by the logic high level of the bit signal B[4], the data signal Data provides a pulse with the first voltage level to the memory element 121 corresponding to the selection switch SW4, and when the selection switch SW3 is turned on When the logic high of the bit signal B[3] is turned on, the data signal provides a pulse with the first voltage level to the memory element 121 corresponding to the selection switch SW3, and so on, when the selection switch SW1 is received by the bit signal B[ When the logic high of 1] is turned on, the data signal Data provides a pulse with the first voltage level to the memory element 121 corresponding to the selection switch SW1.

As mentioned above, in the first row of memory cells 120, the memory elements 121 corresponding to the selection switch SW4, the selection switch SW3, and the selection switch SW1 are programmed to the first memory state (low resistance value) and represent the logic state 0; and the others The memory device 121 that has not received the pulse of the data signal Data having the first voltage level is programmed to the second memory state (high resistance value) and represents the logic state 1.

It is worth noting that, in the above-mentioned multiple embodiments, the processes S210 to S230 can be executed in parallel, and do not need to be executed sequentially.

After the data access method 200 is executed, the memory device 100 programs a row of memory cells 120 in the memory array 110. To program the memory array 110 completely, the memory device 100 may execute the data access method 200 multiple times to program the rows of memory cells 120 in the memory array 110 in sequence.

In some embodiments, when the memory device 100 executes the data access method 200 multiple times, the timing waveform diagram of the memory device 100 is as shown in FIG. 5. The timing control circuit 130 sequentially switches the character signals W[0]~W[m] to a logic high level in a positive sequence direction. For example, after the character signal W[0] turns on the transistor 122 coupled to the word line WL[0], the character signal W[1] then turns on the transistor 122 coupled to the word line WL[1]. By analogy, until the word signal W[m] is turned on the transistor 122 coupled to the word line WL[m].

Please refer to FIG. 5 again. In some embodiments, the bit signals B[0]~B[n] generated by the timing control circuit 130 sequentially turn on the selection of the memory device 100 in a reverse sequence direction different from the above-mentioned forward sequence direction. Switch SW[0]~SW[n]. For example, after the bit signal B[n] is turned on and coupled to the selection switch SW[n] of the bit line BL[n], the bit signal B[n-1] is turned on and coupled to the bit line BL[n- The selection switch SW[n-1] of 1], and so on, until the bit signal B[0] turns on the selection switch SW[0] coupled to the bit line BL[0].

In other words, when the timing control circuit 130 sequentially switches the character signals W[0]~W[m] to the logic high level in a direction away from itself, the bit signals B[0]~B[n] are close to the data The direction of the processing circuit 140 sequentially turns on the selection switches SW[0] to SW[n].

It can be seen from the above that the pulse width of any one of the character signals W[0]~W[m] is greater than the pulse width of any one of the bit signals B[0]~B[n], and the character signal W The pulse width of any one of [0]~W[m] is greater than or equal to the sum of the pulse widths of each of the bit signals B[0]~B[n]. For example, as shown in Figures 3 and 5, the character signal W[0] is greater than the pulse width of any one of the bit signals B[0]~B[n], and the character signal W[0] The pulse width is greater than or equal to the sum of the pulse widths of each bit signal B[0]~B[n].

FIG. 6 is a flowchart of a data access method 600 according to some embodiments of the present disclosure. FIG. 7 is a signal timing waveform diagram of the memory device 100 according to an embodiment of the present disclosure. The data access method 600 is used to read the memory array 110, which includes the aforementioned processes S210 to S220, and also includes the process S630. The specific content of the processes S210 to S220 has been seen in the foregoing paragraphs, and for the sake of brevity, the details are not repeated here.

Following the process S220, in the process S630, in order to read the memory array 110, the memory device 100 provides the data signal Data having the second voltage level to the corresponding row selected in the process S220.

For example, as shown in FIG. 7, the timing control circuit 130 may select the first row of memory cells 120 coupled to the word line WL[0] in the process S220, and the first row of memory cells 120 corresponding to the selected The memory cells 120 of the switches SW1, SW3, and SW4 have been programmed to the first memory state, and the remaining memory cells 120 in the first row of memory cells 120 have been programmed to the second memory state. At this time, in the process S630, when the data voltage Data is transferred to the memory cells 120 corresponding to the selection switch SW4, the selection switch SW3, and the selection switch SW1 in the first row of memory cells 120, the data voltage Data will change from the second voltage level To ground voltage.

On the other hand, when the data signal Data is transmitted to the remaining memory cells 120 programmed to the second memory state among the memory cells 120 in the first row, the data signal Data is maintained at the second voltage level.

It is worth noting that, in the above-mentioned multiple embodiments, the processes S210 to S220 and S630 can be executed in parallel, and do not need to be executed sequentially.

After the data access method 600 is executed, the memory device 100 reads a row of memory cells 120 in the memory array 110. In order to read the memory array 110 completely, the memory device 100 may execute the data access method 600 multiple times to sequentially read the rows of memory cells 120 in the memory array.

In some embodiments, when the memory device 100 executes the data access method 600 for multiple times, the timing waveform diagram of the memory device 100 will be similar to that of Figure 5 above. The difference is that the data signal Data is the highest voltage level of the second voltage. For the sake of brevity, I won’t repeat them here.

In some embodiments, when the memory device 100 executes the data access method 600, the data processing circuit 140 is used to determine whether the memory element 122 corresponds to the first memory state or the second memory based on the data voltage Data on the data line DL state. Therefore, the data processing circuit 140 can read the stored content in the memory device 100.

In some embodiments, the data processing circuit 140 includes an integrator and/or other logic circuits with computing capabilities, such as a field programmable logic gate (FPGA), an application-specific integrated circuit (ASIC), or a microprocessor.

In some embodiments, the first voltage level is between 15-20 volts, and the second voltage level is between 5-10 volts.

Although the content of this disclosure has been disclosed in the above embodiments, it is not intended to limit the content of this disclosure. Anyone with ordinary knowledge in the field can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, the protection scope of this disclosure shall be subject to those defined by the attached patent application scope.

100: Memory device 110: memory array 120: memory cell 121: memory component 122: Transistor 130: timing control circuit 140: data processing circuit 200,600: data access method S210, S220, S230, S630: process SW[0]~SW[n]: selector switch WL[0]~WL[m]: Character line BL[0]~BL[n]: bit line W[0]~W[m]: character signal B[0]~B[n]: bit signal Data: data signal DL: Data line

FIG. 1 is a simplified functional block diagram of a memory device according to some embodiments of the present disclosure. FIG. 2 is a flowchart of a data access method according to some embodiments of the present disclosure. FIG. 3 is a signal timing waveform diagram of the memory device according to an embodiment of the present disclosure. FIG. 4 is a partial schematic diagram of a memory device according to some embodiments of the present disclosure. FIG. 5 is a signal timing waveform diagram drawn according to some embodiments of the present disclosure. FIG. 6 is a flowchart of a data access method according to some embodiments of the present disclosure. FIG. 7 is a signal timing waveform diagram of the memory device according to an embodiment of the present disclosure.

100: Memory device

110: memory array

120: memory cell

130: timing control circuit

140: data processing circuit

SW[0]~SW[n]: selector switch

WL[0]~WL[m]: Character line

BL[0]~BL[n]: bit line

W[0]~W[m]: character signal

B[0]~B[n]: bit signal

Data: data signal

DL: Data line

Claims (12)

A memory device includes: a plurality of selection switches for receiving a plurality of bit signals; and a memory array for receiving a plurality of character signals, wherein the memory array includes a plurality of rows and rows A plurality of memory cells, wherein each of the memory cells includes: a memory element for representing a first memory state and a second memory state that are different from each other; and a transistor coupled to the options Between the corresponding one of the switches and the memory element; wherein the selection switches are used to access the memory array, the memory cells in the same row are coupled to the same selection switch, and the memory cells in different rows are coupled Connected to different selection switches, where the memory array is used to select a corresponding row of memory cells in the plurality of rows according to one of the character signals, and the selection switches are used to sequentially turn on in response to the bit signals , So that the corresponding row of memory cells sequentially receives a data signal. The memory device according to claim 1, wherein the memory cells in the multiple rows are respectively coupled to a plurality of character lines, and the selection switches are respectively controlled by a plurality of bit lines, the memory device further includes : A timing control circuit for providing the character signals through the word lines, and providing the bit signals through the bit lines. The memory device according to claim 2, wherein the words The pulse width of any one of the meta signals is greater than the pulse width of any one of the bit signals. The memory device according to claim 2, wherein the pulse width of any one of the character signals is greater than or equal to the sum of the pulse widths of each of the bit signals. The memory device according to claim 2, wherein: the timing control circuit sequentially switches the character signals to a logic high level in a positive sequence direction; the timing control circuit generates the bit signals different from A reverse sequence direction of the positive sequence direction sequentially turns on the selection switches of the memory device. The memory device according to claim 1, further comprising: a data processing circuit coupled to a data line with the selection switches for providing the data signal to the memory array through the selection switches, wherein When the pulse of the data signal has a first voltage level, the memory device is in a programming mode; when the pulse of the data signal has a second voltage level, the memory device is in a read mode, and the data The processing circuit is used for reading the first memory state or the second memory state corresponding to the memory elements in the memory device through the data line. The memory device according to claim 6, wherein the first voltage level is between 15-20 volts, and the second voltage level is between 5-10 volts. The memory device according to claim 6, wherein the memory element is a fuse element or an anti-fuse element. A data access method is suitable for a memory device, wherein the data access method includes: generating a plurality of bit signals and a plurality of character signals by a timing control circuit, wherein the memory device includes a plurality of selection switches and A memory array including a plurality of memory cells arranged in rows and columns, the selection switches are controlled by the bit signals, and the rows of the memory array are respectively controlled by the characters Signal control; when one of the character signals is used to select the corresponding row of memory cells in the multiple rows, the selection switches are turned on in sequence in response to the bit signals, and the selection switches are respectively coupled to The multiple rows enable the corresponding row of memory cells to sequentially receive a data signal; and use the data signal to perform a data operation on the corresponding row of memory cells. The data access method according to claim 9, wherein each memory cell includes a memory element and a transistor, and the process of using the data signal to perform the data operation on the corresponding row of memory cells includes: if the data operation For programming operation, the data signal is provided with a first One or more pulses of a voltage level to one or more memory cells in the corresponding row of memory cells; wherein the first voltage is higher than a breakdown threshold voltage of the memory device, so that the one or more The memory cell has a first memory state, and the other memory cells in the corresponding row of memory cells that are different from the one or more memory cells have a second memory state. For the data access method described in claim 10, the process of using the data signal to perform the data operation on the memory cell in the corresponding row further includes: if the data operation is a read operation, the data signal has a second Voltage level, wherein the first voltage level is higher than the second voltage level; wherein when the data signal is transmitted to the remaining memory cells, the data signal is maintained at the second voltage level, and when the data signal is transmitted When entering the one or more memory cells, the data signal changes from the second voltage level to a ground voltage. The data access method according to claim 10, wherein the pulse width of any one of the character signals is greater than or equal to the sum of the pulse widths of each of the bit signals.

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