TWI742437B - Operating method for serially-connected computation chips and computing system thereof - Google Patents

Abstract

An operating method for serially-connected computation chips and a computing system thereof are provided. The computing system includes a control circuit and a computation board. The computation board includes a series of connected computation chips. In the operating method, a computation topic is received, and a plurality of sub-topics in the topic are obtained through computation. An instruction set for each of the sub-topics is formed. In the meantime, a length of every instruction and a transmission time for each instruction transmitted to the computation chip are obtained. Therefore, the control circuit can determine a time to transmit the instruction to the computation chip. After obtaining a computation result by enquiry, the control circuit can actively transmit an instruction with respect to a next sub-topic to the computation chip according to the execution time.

Description

Sequential computing chip operation method and computing system

The present invention relates to an operating method of a computing system, in particular to a sequential computing chip operating method and computing system capable of estimating the length of the instruction and the time to be transmitted to the computing chip and actively transmitting the next instruction.

In the conventional technology, when a computer system with multiple processors (or computing chips) handles general tasks, even if the processing capabilities of each processor are different, and the instructions to be processed are different, the overall time spent is different. However, as far as the overall computer system is concerned, these differences are not considered, and because system stability is taken into consideration, differentiated management measures have not been proposed for these differences.

In the above-mentioned computer system, if the method of performing a specific task is to divide the calculation task into multiple sub-topics, each sub-topic is assigned to each processor, and each processor is allowed to calculate each sub-topic separately, and the sub-topics will be divided into Multiple instruction sets are sent to the processor, and the common way is to uniformly set a fixed time (such as setting a fixed instruction length, fixed operation time, etc.), and then dispatch the next instruction according to this fixed time. The conventional technology has not proposed Effective solutions can make full use of the processing power of the computer system.

For example, in the design of mining machines used in blockchain applications, computing power boards with multiple computing chips are generally used, and this design is for the need to solve problems first in order to obtain rewards, or to participate in a Mining pools perform mining problem solving, but in the method of improving the overall computing power, in addition to increasing processing power (such as purchasing mining machines, increasing processor clocks, etc.), more detailed optimization procedures are required.

According to a sequential computing chip operation method disclosed in the disclosure, the method is applied to a computing system formed by a computing power board with multiple computing chips and a control circuit. The main concept of the method is to derive instructions based on computing problems. Length and estimate the time for each instruction to be transmitted to the computing chip, so that the computing system can calculate the time to transmit the next instruction, which can effectively optimize the overall computing performance.

In the sequential computing chip operation method, the control circuit receives the question. The question can be an arithmetic requirement proposed by an external system. The question can be calculated based on the question. The processing unit forms one or more sub-questions after analyzing each sub-question. It can calculate the length of each instruction and calculate the transmission time of each instruction to the computing chip assigned to the subtopic.

Then, the control circuit can determine the time for transmitting the next instruction to the computing chip according to the obtained instruction length and the transmission time of each instruction. Therefore, after each instruction is transmitted to the computing chip, the control circuit can transmit the next instruction to the computing chip according to the obtained transmission instruction time.

Furthermore, when each calculation chip calculates each sub-topic, the control circuit can periodically and continuously issue an inquiry command to the calculation chip to obtain a calculation result.

If the computing system is a mining machine and the external system is a mining pool, the mining machine receives the computing demand with rewards proposed by the mining pool.

Preferably, the control circuit can transmit one or more commands in the subtopics to each computing chip and store them in one or more registers in each computing chip.

In the embodiment of the computing system, the main components of the computing system are the control circuit and the computing power board. The computing power board is provided with multiple computing chips connected in sequence, and each computing chip is equipped with a register and is operated by the control circuit. The above-mentioned sequential formula calculates the chip operation method.

Preferably, the control circuit includes a communication unit for connecting to an external system; a memory unit for storing information transmitted with the external system and data exchanged with the hash board; and a processing unit for processing self The computing requirements received by the external system form multiple sub-topics assigned to each computing chip. In the method, the processing unit further obtains the instruction length of each instruction, estimates the transmission time of each instruction to the assigned computing chip, and obtains the time for each computing chip to transmit the next instruction to the computing chip, and calculates the chip arithmetic When questioning, after the calculation result is obtained through the inquiry instruction in the process, the instruction of the next sub-topic is sent continuously.

In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings about the present invention. However, the provided drawings are only for reference and description, and are not used to limit the present invention.

The following are specific specific examples to illustrate the implementation of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be based on different viewpoints and applications, and various modifications and changes can be made without departing from the concept of the present invention. In addition, the drawings of the present invention are merely schematic illustrations, and are not drawn according to actual dimensions, and are stated in advance. The following embodiments will further describe the related technical content of the present invention in detail, but the disclosed content is not intended to limit the protection scope of the present invention.

It should be understood that although terms such as "first", "second", and "third" may be used herein to describe various elements or signals, these elements or signals should not be limited by these terms. These terms are mainly used to distinguish one element from another, or one signal from another signal. In addition, the term "or" used in this document may include any one or a combination of more of the associated listed items depending on the actual situation.

The disclosure paper proposes a sequential computing chip operation method and computing system. The computing system, such as a mining machine, is connected to an external system such as a mining pool to receive computing requirements with rewards proposed by the mining pool, such as common Perform mathematical problem solving for specific cryptocurrency transactions, that is, mining tasks.

According to the embodiment of the computing system proposed in the disclosure, reference may be made to the structural embodiment diagram of the computing system that implements the sequential computing chip operation method shown in FIG. 105. The purpose of the control circuit 103 is to connect to an external system. The mining pool 101 in this example, after obtaining the calculation problem, allocates the calculation chips (C1, C2, C3, C4, C5...) according to the setting of the calculation board 105. Calculation tasks (subtopics).

The main components of the control circuit 103 include an externally connected communication unit 131 for connecting to external systems, such as the mining pool 101, such as wired or wireless communication modules and corresponding circuits, including the ability to receive calculation problems from the mining pool 101 and return Pass the calculation result to the mining pool 101. The main components of the control circuit 103 include a memory unit 133 for storing information transmitted with the external system and data exchanged with the computing power board 105. The main circuit of the control circuit 103 also includes a processing unit 135 for processing calculation requirements received from an external system, such as a calculation problem proposed by the mining pool 101. The problem will form multiple sub-topics assigned to each computing chip. The processing unit 135 analyzes After the sub-topics, the instruction set in each sub-topic is formed, which can be sent to each computing chip one by one.

In particular, the processing unit 135 is used to process the computing requirements received from the external system, calculate multiple sub-topics assigned to each computing chip, and form the instruction set for each sub-topic. In the embodiment of the sequential computing chip operation method , And calculate (or estimate) the time it takes for each computing chip to process each sub-topic. Among them, the processing unit 135 can obtain the instruction length of each instruction and estimate the transmission time for transmitting each instruction to the assigned computing chip, so that the control circuit 103 can be used to determine the time to transmit the next instruction, thereby reducing the transmission of the instruction to each computing chip. The waiting time of the chip to facilitate subsequent actions can effectively improve the calculation efficiency of the finishing system.

It is mentioned here that the calculation of the command transmission time to the computing chip is based on a baud rate (Baud Rate), and the command transmission time can be calculated as the command length divided by the baud rate. The baud rate is a measure of the symbol transmission rate. For example, 1 baud refers to the transmission of 1 symbol per second. In the sequential computing chip operation method, it can indicate the rate of command transmission. The unit of the transmission rate is the number of symbols transmitted per second, or It is transmitted bits per second (bps), and the design of the actual baud rate is related to the overall system hardware architecture. The power board 105 designed according to each requirement may have a different baud rate.

The parameters based on at least include: the length of each command (L1, L2, L3...), the length of the command will affect the transmission time between commands, and also enable the control circuit 103 to transfer the next command according to the length of the command and the transmission time Time to calculate chips (C1, C2, C3, C4, C5...). It is mentioned here that in actual operation, the control circuit 103 obtains the time interval between the transmission of instructions according to the length of the instruction and the transmission time. Under the architecture of the serially connected computing chip, the control circuit 103 transmits the instruction to the computing power. After the first computing chip on the board 105, the next command can be sent according to the time interval between commands, and the computing chip that receives the command can then be sent to the destination computing chip in sequence according to the destination of the command transfer.

According to the example of the embodiment, the control circuit 103 is electrically connected to the computing power board 105 through a specific connection interface. The computing power board 105 is provided with a plurality of computing chips C1, C2, C3, C4, C5 connected in series (series), etc., the control circuit The connection line 103 is electrically connected to the computing power board 105, such as a Universal Asynchronous Receiver/Transmitter (UART). The computing chip forms the basic computing unit in the computing system. When the instruction is transmitted from the control circuit board 103 to the computing power board 105, and then sent to each computing chip (C1, C2, C3, C4, C5...) through the serial connection, it will be sent first. It is stored in the register of each computing chip, the calculation is performed, and after the calculation is completed, the result is returned to the control circuit 103.

In addition to computing systems or various types of computing nodes that are specifically used to provide computing or storage needs of others, the computing chip on the computing power board proposed in the disclosure can independently participate in the system of allocating computer resources. According to the embodiment, the computing chip 20 operating as the basic computing unit in the computing system can be integrated with the electronic device in a built-in or external manner. For example, the computing chip 20 shown in FIG. The device is connected to participate in the computer resource allocation system. In this way, the terminal node using the computing chip 20 can also obtain compensation from the demand side through the program running in it.

According to Figure 2 shows the implementation of the computing chip 20 proposed in the disclosure, a special application integrated circuit (Application-specific integrated circuit, ASIC) can be used, and various logic combinations of multiple encryption circuits can be used to perform various calculation requirements, including Supports cryptographic hash operations of multiple cryptographic algorithms, such as cryptocurrency arithmetic. In addition to being easily implemented on a built-in or external component connected to an IoT terminal device, it also has a power saving effect and can be used for special applications. The structure of the circuit can be designed for specific computing purposes.

The figure shows the main circuit components of the computing chip 20. For example, there is a processing unit 201 for processing smart contract commands. It is a processor with distributable computing power; it includes a memory unit 202 that stores software programs that run this system. 202 includes one or more registers in the computing chip, which can be used to temporarily store instructions, data, and addresses. In the disclosed computing system, the register in the computing chip 20 is used to store data transmitted by the control circuit. instruction.

The circuit for storing data allows the computing chip 20 to become a contributing storage node, such as the storage unit 203; the communication unit 205 is a circuit for the computing chip 20 to communicate with each other, so that the computing chip 20 can be independently connected to the network, but can still pass through the connected The terminal nodes are connected to the Internet, and the external communication is mainly to actively release the computing power that can participate in the distribution of the computing chip 20, the storage space in the memory, etc., so as to be recorded on the blockchain through a smart contract.

The computing chip 20 further includes a task scheduling unit 204 for processing various computing tasks assigned by the control circuit. The task scheduling unit 204 can schedule according to the computing requirements of the external system. The contract's instructions perform computing tasks to process the data flow, including data proofs in response to the use of computer resources by the smart contract. The computing chip 20 further includes an encryption calculation unit 206 that performs specific-purpose encryption and decryption tasks, and supports various encryption algorithms. For example, the computing chip 20 provides the cryptocurrency in the operating environment to execute the corresponding cryptographic algorithm. Therefore, the corresponding cryptographic algorithm can be executed for the cryptocurrency supported by each node, and the corresponding algorithm can be executed according to various computing requirements. For example, during mining, the encryption calculation unit 206 is required to perform the calculation work required for a specific currency, and the interface control unit 208 connected to a specific electronic device. Therefore, when the computing chip 20 is applied to specific encryption requirements, it can be controlled to change. Encryption algorithm. The computing chip 20 can be connected to other computing chips on the computing power board through the interface control unit 208 to execute receiving instructions and data transmission.

According to the embodiment of the sequential calculation chip operation method, the instruction length and transmission time in each sub-topic are obtained to obtain the time for each instruction to be transmitted. The computing system can consider the characteristics of each instruction and the computing power on the board. The difference between each computing unit and the entire computing system environment proposes an adaptive operation method. This adaptive operation method can improve the overall computing performance.

Figure 3 shows that the control circuit in the computing system receives the calculation task from the external system, as shown in question 3. In order to speed up the efficiency of the calculation results, according to the setting of the computing system in the computing system, the task 3 can be divided into more tasks. A computing chip calculates multiple sub-problems separately, and the sub-problems (31, 32, 33) are sent to different computing chips to perform the calculations.

Each subtopic can include one or more instructions, and the number of instructions depends on actual needs. The illustration shows that subtopic 31 includes instructions 301, 302 and 303, and subtopic 32 includes instructions 304, 305, 306. , Sub-topic three 33 includes instructions 307, 308, 309 and so on. After each sub-topic is sent to each computing chip by the control circuit, it is stored in one or more registers in each computing chip. This example shows that the chip register R1 stores the received commands 301 to 303, and the chip temporarily stores it. The second device R2 stores the received commands 304 to 306, and the third chip register R3 stores the received commands 307 to 309.

According to the embodiment of the sequential calculation chip operation method, before each sub-topic is dispatched, the time for each command to be transmitted to the calculation chip can be obtained according to the length of each command and the transmission time. Figure 4 shows an embodiment of the process flow of the sequential computing chip operation method. The method is more applied to a computing system formed by a computing power board with multiple computing chips and a control circuit. The legend mainly describes how to send commands to each computing chip. The flow of time.

At the beginning, the computing system receives the calculation problem proposed by the external system (step S401). The problem consists of many sub-problems that need to be assigned to multiple computing chips. The processing unit in the control circuit can calculate the sub-problems from each problem (step S401). Step S403), the instructions included in each sub-topic can also be parsed. At this time, in the stage of transmitting the instructions in each sub-topic to each calculation chip, the length of each instruction and each calculated based on the baud rate will be obtained first. The transmission time required for the command.

As described in the flow chart, first obtain the length of each instruction, that is, calculate the processing time of each instruction (parameter one: L1, L2, L3...) (step S405), and estimate the time required to transmit the instruction (parameter two: D1, D2, D3...) (step S407), to estimate the time for the control circuit to transmit the next command based on the length and transmission time of each command (step S409). When the instructions of each subtopic are transferred to the register of the computing chip one by one, the computing chip will start to execute the temporarily stored instructions after completing all the instructions in the subtopics.

Further, according to the flow shown in FIG. 5, it is a flowchart describing an embodiment of a method for the control circuit to execute a sequential computing chip operation.

After the control circuit receives the calculation problem, it can calculate a number of sub-problems according to the power board settings of the computing system, and parse the sub-problems to form one or more instructions. After the above-mentioned embodiment process, as in step S501 , The control circuit has been given the time to transmit each instruction to the computing chip. At this time, in step S503, the control circuit transmits instructions according to the obtained time for transmitting the next instruction, and transmits the instructions of the subtopics one by one. After transmitting the commands of the sub-topics, the control circuit can periodically and continuously transmit the query commands to each computing chip to query the results obtained by each computing chip (step S505).

When the control circuit periodically issues an inquiry instruction to each computing chip, after the sub-problem is solved, the computing chip can respond to the calculation result to the control circuit according to the inquiry instruction. Afterwards, after receiving the calculation results of each calculation chip, the control circuit judges that the problem has not been completed, indicating that there is still the next sub-topic, and continues to transmit one or more instructions for the next sub-topic (step S507), and continues the above steps; On the contrary, if the question has been completed (Yes), the process is completed and the result is generated. It is mentioned here that this result can be a task assigned from the mining pool, so it needs to be delivered to the mining pool and then get compensation from it.

In this process, the command sent by the control circuit according to the calculation problem is the control signal used to control the action of the chip. The control method is to write some meaningful values into the calculation chip through a specific interface (such as UART), and , The instruction length varies with the difference in computing requirements, the instruction length may be between 8 and 128 bits (bits), the said instruction length will be designed differently depending on the requirements, in a computing problem, the structure of the instruction set Different instructions may have different lengths, which is different from the conventional method of using a fixed instruction length to estimate the overall calculation time. The method proposed in the disclosure book will consider the length of each instruction and the transmission time to obtain the time to transmit each instruction .

For example, when the control circuit in the computing system receives a question from an external system (such as a mining pool), it will find some sub-topics based on the relevant encryption and decryption algorithms, and these sub-topics need to pass one or more instructions. The transfer is complete. Assuming that the control circuit now has a sub-topic, the contents of which are "x, y, z" respectively, forming an instruction set. Multiple instructions in each sub-topic instruction set will be transferred to the register X of the computing chip. Multiple commands of the subtopic will be transferred to the register Y of the computing chip; another subtopic has multiple commands, and similarly, these commands will be transferred to the register Z of the chip.

To sum up, the sequential computing chip operation method and computing system described in the above embodiments refer to the ability to estimate the length and transmission time of each instruction in the computing system's computing problem to obtain the time to transmit the next instruction, and Reduce the waiting time for transmitting each instruction at a fixed time, allowing the computing system to actively transmit instructions to the sequential computing chip. The computing system can be applied to mining machines. The method can be optimized by improving the computing efficiency of individual computing chips. Overall computing performance.

The content disclosed above is only the preferred and feasible embodiments of the present invention, and does not limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the description and schematic content of the present invention are included in the application of the present invention. Within the scope of the patent.

101: Mining Pool 103: control circuit 131: Communication unit 133: memory unit 135: Processing Unit 105: Hashboard C1, C2, C3, C4, C5: Computing chip 20: Computing chip 201: Processing Unit 202: memory unit 203: storage unit 204: Task scheduling unit 206: Encrypted Computing Unit 208: Interface Control Unit 205: Communication unit 3: title 31: Subtopic One 32: Subtopic Two 33: Subtopic Three 301,302,303,304,305,306,307,308,309: instructions R1: Chip register one R2: Chip register two R3: Chip register three Steps S401～S409: One of the operation flow of sequential computing chip Steps S501～S507: Sequence calculation chip operation process 2

FIG. 1 shows an embodiment diagram of the architecture of a computing system that implements a sequential computing chip operation method;

Figure 2 shows an embodiment diagram of a circuit block of a computing chip;

Figure 3 shows the relationship diagram between the title and the instruction set;

FIG. 4 is a flowchart of an embodiment of obtaining the time for transmitting instructions to each computing chip in the sequential computing chip operation method; and

FIG. 5 is a flowchart of an embodiment of a method for controlling a sequential computing chip to be executed by a control circuit.

S401: Receive questions

S403: Get sub-topic

S405: Get the length of each instruction in the subtopic (L1, L2, L3...)

S407: Estimate the time required to transmit instructions (D1, D2, D3...)

S409: Calculate the time to transmit the next instruction according to the instruction length and transmission time

Claims (10)

A computing system includes: a control circuit for connecting to an external system to receive a question; a power board, which is electrically connected to the control circuit through a connection interface, and the power board is provided with a plurality of serially connected Calculation chip; wherein the control circuit runs a sequential calculation chip operation method, including: according to the received problem, calculate multiple sub-topics in the problem, and form one or more instructions for each sub-topic; A command length of one or more commands in each sub-topic, an estimated transmission time of each command to each computing chip of the plurality of computing chips, so as to obtain the time for sending the next command; and for the plurality of computing chips Each calculation chip of the calculation chip transmits the next instruction to the allocated calculation chip among the plurality of calculation chips according to the obtained time for transmitting the next instruction. The computing system according to claim 1, wherein the control circuit includes: a communication unit for connecting to the external system; a memory unit for storing information transmitted with the external system and communication with the computing power board Data; and a processing unit for processing the question received from the external system to obtain a plurality of sub-topics assigned to the plurality of computing chips, and the one or more instructions forming each sub-topic; wherein, the processing The unit judges the time to transmit the next instruction based on the instruction length and the transmission time of each instruction. The computing system according to claim 2, wherein the computing system is a mining machine, the external system is a mining pool, and the mining machine receives a computing request with a reward proposed by the mining pool. The computing system according to claim 3, wherein each sub-problem is calculated on each computing chip At this time, the control circuit obtains the calculation result of each calculation chip through an inquiry instruction to obtain the time for transmitting the instruction of the next sub-topic. The computing system according to claim 4, wherein the control circuit periodically and continuously transmits the query command to each computing chip, and each computing chip responds to the calculation result according to the query command. The computing system according to any one of claims 1 to 5, wherein each computing chip of the plurality of computing chips includes one or more registers for temporarily storing the instructions sent by the control circuit. A sequential computing chip operation method, applied to a computing system formed by a computing power board with multiple computing chips and a control circuit, includes: receiving a problem from an external system by the control circuit; in the control circuit, According to the received question, calculate multiple sub-topics in the question, and one or more instructions that form each sub-topic; obtain the individual instruction length of one or more instructions in each sub-topic, and estimate the transmission of each instruction A transmission time to each computing chip of the plurality of computing chips to obtain the time for transmitting the next instruction; and transmitting the next instruction to the assigned one of the plurality of computing chips according to the obtained time for transmitting the next instruction Calculate the wafer. The sequential computing chip operation method according to claim 7, wherein the computing system is a mining machine, the external system is a mining pool, and the mining machine receives a computing request with a reward proposed by the mining pool. The sequential computing chip operation method described in claim 8, wherein when each computing chip calculates each sub-problem, the control circuit obtains the calculation result of each computing chip through an inquiry command to obtain the transfer of the next sub-problem The time of the instruction. The sequential computing chip operation method according to any one of claim items 7 to 9, wherein each computing chip of the plurality of computing chips includes one or more registers for temporarily storing commands sent by the control circuit .

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