TWI740890B - Volatile memory device - Google Patents

Abstract

A volatile memory device includes a refresh controller configured to control a hidden refresh operation performed on a first portion of memory cells while a valid operation is performed on a second portion of the memory cells. The volatile memory device is configured to perform a regular refresh operation in response to receiving a refresh command. The refresh controller is configured to generate refresh information using a performance indicator of the hidden refresh operation during a first part of a reference time. The volatile memory device is configured to perform a desired number of the regular refresh operation during a remaining part of the reference time based on the refresh information. The desired number of the regular refresh operation is an integer based on a difference between a target number of refresh operations during the reference time and a count value of the hidden refresh operation during the reference time.

Description

Volatile memory device [Cross reference of related applications]

This application is based on 35 USC § 119. The Korean Patent Provisional Application No. 10-2016-0013631 filed at the Korean Intellectual Property Office on February 3, 2016 and filed at the Korean Intellectual Property Office on July 11, 2016 Priority of the applied Korean Patent Application No. 10-2016-0087630. The entire contents of each of the above-mentioned applications are incorporated into this case for reference.

Certain exemplary embodiments relate to a semiconductor memory device, and in particular, to a volatile memory device and an electronic device including an update information generator, and an information providing method and/or update control thereof method.

Semiconductor memory devices refer to devices that store data under the control of host devices such as computers, smart phones, and smart tablets. Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (DRAM) or static random access memory (static RAM, SRAM). As an example of a volatile memory device, a dynamic random access memory device periodically performs a refresh operation to make the memory stored in the dynamic random access memory The data in the memory device will not be lost. Generally speaking, in order to limit and/or prevent data conflicts in the update operation, the memory device does not receive write commands or read commands.

In order to provide high-capacity memory to the host, generally speaking, volatile memory components can be implemented in the form of memory modules. The update operation performed on the multiple volatile memory components included in the memory module is managed by the host and the memory controller.

However, according to the trend of high capacity and high integration of memory modules and memory devices, it becomes more complicated for the host (and/or memory controller) to control the update operation of each memory device. In addition, if the number of update commands increases as described above, the efficiency of processing data may be reduced because the memory device does not receive write commands or read commands.

The concept of the present invention relates to a volatile memory element including an update information generator, an electronic element including a volatile memory element, a method for providing update information, and a method for controlling the update of the volatile memory element and/or electronic element The update information generator is used to generate update information related to the update execution status of the volatile memory element.

In some exemplary embodiments, a memory system includes a volatile memory device and a memory controller connected to the volatile memory device. The volatile memory device includes an update controller connected to the memory cell. The volatile memory device is used to perform an effective operation on the second portion of the memory cell while the volatile memory device performs an effective operation on the first portion of the memory cell. Row hidden update operation. The update controller is used to generate update information based on the number of times the volatile memory device performs the hidden update operation during a reference time. The memory controller is used for controlling the scheduling of regular update operations based on the update information. The memory controller is used for controlling the volatile memory device to perform the regular update operation according to the schedule.

In some exemplary embodiments, a memory system includes a volatile memory device and a memory controller connected to the volatile memory device. The volatile memory device includes an update controller connected to the memory cell. The volatile memory element is used for performing a hidden update operation on the first part of the memory cell while the volatile memory element performs an effective operation on the second part of the memory cell. The update controller is used to generate update information based on the number of times the volatile memory device performs the hidden update operation. The update controller is used for refreshing the update information if the volatile memory device performs the hidden update operation. The memory controller is used for controlling the scheduling of regular update operations during the rest of the reference time based on the update information. The memory controller is used for controlling the volatile memory device to perform the regular update operation according to the schedule.

In some exemplary embodiments, a memory system includes a volatile memory device and a memory controller connected to the volatile memory device. The volatile memory device includes an update controller connected to the memory cell. The volatile memory element is used for comparing the volatile memory element to the memory cell The second part of the memory cell performs a hidden update operation while performing effective operations on the first part of the memory cell. The update controller is used to generate update information based on the number of times the volatile memory device performs the hidden update operation during a reference time. The memory controller is used for generating update commands based on the update information to perform regular update operations in the volatile memory device.

In some exemplary embodiments, a memory system includes a volatile memory device and a memory controller. The volatile memory device includes an update controller connected to the memory cell. The volatile memory device is used for performing a first update operation on the first portion of the memory cell while the volatile memory device performs an effective operation on the second portion of the memory cell. The volatile memory device is used for performing a second update operation in response to an update command from the memory controller. The update controller is used for generating update information using the performance index of the first update operation during the first part of the reference time. The memory controller is used for scheduling the second update operation a desired number of times during the remaining part of the reference time based on the update information. The memory controller is used for controlling the volatile memory device to perform the second update operation according to the schedule.

According to certain exemplary embodiments, a volatile memory device includes an update controller connected to a memory cell. The update controller is used for controlling a hidden update operation performed on the first part of the memory cell while the volatile memory element performs an effective operation on the second part of the memory cell. The update controller is used to generate update information, and the update information is based on the volatile The number of times the memory device performs the hidden update operation during the reference time. The volatile memory device is used for performing N regular update operations during the reference time period in response to receiving N update commands from the host. N is an integer corresponding to the difference between the target number of update operations during the reference time and the number of times the volatile memory device performs the hidden update operation during the reference time.

According to certain exemplary embodiments, a volatile memory device includes an update controller connected to a memory cell. The volatile memory element is used for performing a hidden update operation on the first part of the memory cell while the volatile memory element performs an effective operation on the second part of the memory cell. The update controller is used to generate update information to be submitted to the memory controller. The update information is based on the number of times the volatile memory device performs the hidden update operation during the reference time.

According to certain exemplary embodiments, a volatile memory device includes an update controller connected to a memory cell. The update controller is used for controlling a hidden update operation performed on the first part of the memory cell while the volatile memory element performs an effective operation on the second part of the memory cell. The volatile memory device is used to perform regular update operations in response to update commands from an external memory controller. The update controller is used for generating update information using the performance index of the hidden update operation during the first part of the reference time. The volatile memory element is used to perform the regular update operation a desired number of times during the remaining part of the reference time based on the update information do. The expected number of regular update operations is an integer corresponding to the difference between the target number of update operations during the reference time and an update scale, and the update scale includes where the volatile memory element is The number of executions of the hidden update operation during the reference time.

According to certain exemplary embodiments, a volatile memory device includes an update controller connected to a memory cell. The update controller is used for controlling a first update operation performed on the first part of the memory cell while the volatile memory element performs an effective operation on the second part of the memory cell. The volatile memory device is used to perform a second update operation in response to an update command from an external memory controller. The update controller is used for generating update information based on the performance index of the first update operation during the first part of the reference time. The volatile memory element is used for all of the reference time based on the number of times the volatile memory element receives the update command from the external memory controller during the remaining part of the reference time. During the remaining part, the second update operation is performed a desired number of times.

According to certain exemplary embodiments, there is provided a method of operating a memory system including a volatile memory element connected to a memory controller. The volatile memory device includes a memory cell connected to an update controller. The method includes: performing N hidden update operations on the memory cell during a reference time; using an update controller based on the N hidden update operations and performing some operations during the first part of the reference time. Regular update operations to generate update information; and use the memory controller to generate update information based on the update information M additional regular update operations are performed during the remainder of the reference time. M and N are integers.

According to certain exemplary embodiments, there is provided a method of operating a memory system including a volatile memory element connected to a memory controller. The volatile memory device includes a memory cell connected to an update controller. The method includes: performing at least one hidden update operation on the memory cell during a reference time; using the update controller based on the count of the at least one hidden update operation and the number of operations performed during the reference time The number of regular update operations is used to generate update information; and the memory controller is used to perform M additional regular update operations during the remainder of the reference time based on the update information. M corresponds to the difference between the target number of update operations and the count of the at least one hidden update operation during the reference time and the number of regular update operations.

According to certain exemplary embodiments, there is provided a method of operating a memory system including a volatile memory element connected to a memory controller. The volatile memory device includes a memory cell connected to an update controller. The method includes: performing a first update operation on the first part of the memory cell and performing a valid operation on the second part of the memory cell at least once during the first part of the reference time; using The update controller generates update information based on the performance index of the first update operation during the first part of the reference time; provides the update information to the memory controller; uses the memory Based on the update information, the body controller performs the period of the remaining part of the reference time Schedule a second update operation for the desired number of times; and perform the second update operation on the volatile memory device during the remaining part of the reference time according to the schedule.

According to some exemplary embodiments, a memory controller includes: a host interface for receiving data requests from a host; a memory interface for providing commands to a volatile memory element and for receiving from the volatile memory Update information generated by the body component; and update manager. The update information includes one of the following: the performance index of at least one hidden update operation performed by the volatile memory device during the first part of the reference time; and the performance index of the volatile memory device in the The performance index of the at least one hidden update operation performed during the first part of the reference time and at least one of the memory device performed during the first part of the reference time are regularly The performance index of the update operation. The update manager is used to schedule the regular update operation for a desired number of times during the rest of the reference time based on the update information. The update manager is used for controlling the volatile memory device to perform the regular update operation according to the schedule. The expected number of times is based on a reference value and a count value of the at least one hidden update operation and the at least one regular update operation performed during the first portion of the reference time, respectively Difference.

1: Electronic components

10: host

50: memory controller

52: host interface

54: Memory interface

56: Update Manager

58: Error correction circuit

100: memory device/volatile memory device

110, 210: command decoder

120, 220: address latch

130, 230: memory cell array

130_1: first memory cell array

130_2: second memory cell array

130_n-1: n-1th memory cell array

130_n: nth memory cell array

131, 231: Sense amplifier

131_1: the first sense amplifier

131_2: second sense amplifier

131_n-1: n-1th sense amplifier

131_n: nth sense amplifier

140, 240: line decoder

140_1: first row decoder

140_2: second line decoder

140_n-1: line n-1 decoder

140_n: the nth row decoder

150, 250: Active controller

150_1: the first active controller

150_2: second active controller

150_n-1: n-1th active controller

150_n: nth active controller

160, 260, 1160, 1260: update controller

160_1: First update controller

160_2: second update controller

160_n-1: n-1th update controller

160_n: nth update controller

161: Update address generator

162: address comparator

163, 163a, 163b, 163c: update information generator

164: Oscillator

165, 165a, 165b: update counter

166: Flag Generator

170, 270: column decoder

170_1: first column decoder

170_2: second column decoder

170_n-1: Decoder for column n-1

170_n: nth column decoder

180, 280: data input driver

190, 290: data output driver

195: Multi-purpose register

200: Memory component

1000: Stacked memory components

1100, 2100, 3100: the first memory device

1200, 2200, 3200: second memory device

1300: Logic Die

1360: register

1400: Solder Ball

2000: Memory Module/Type A Memory Module

2300: Command/Address Register

2400: Update the information transmission line

3000: Memory module/Type B memory module

3300: memory buffer

3400: Transmission line

4000: user system

4100: image processing unit

4110: lens

4120: Image sensor

4130: image processor

4140: display unit

4200: wireless transceiver unit

4210: Antenna

4230: Modulator/demodulator/modem

4240: Transceiver

4300: Audio processing unit

4310: Audio processor

4320: Microphone

4330: speaker

4400: Image file generation unit

4500: memory

4600: User interface

4700: Controller

ACT: active signal

ADD_act: current address

ADDR: Address/Address Pad

ADD_rfr: update address

BANK0, Bank1: the first bank

Bank2: second bank

Bankn-1: Bank n-1

Bankn: Bank n

BL0: The first bit line

BL1: The second bit line

CA: Command/Address Transmission Line

CMD: Command/Command Pad

DATA: data/data pad/data transmission line

DES: No signal selected

DQ_G: independent transmission line

MAT0: The first memory array chip

MAT1: second memory array chip

MAT2: The third memory array chip

MAT3: The fourth memory array chip

MATn: (n+1)th memory array chip

MC: Memory cell

MRR: Multi-purpose register read command

N×tREFI: ``N'' regular update execution cycles

(N-M+a)×tRFC: Time

REF: update command/first update command

RFR: Regularly update the active signal

RFR_dnd: update demand count

RFR_en: Update the current signal

RFR_H: Hidden update active signal

RFR_inf: Update information

RST: reset signal

SA0: The first sense amplifier array

SA1: The second sense amplifier array

SA2: The third sense amplifier array

SA3: The fourth sense amplifier array

SAn: (n+1)th sense amplifier array

T: terminal resistor

t0, t1, t2, t3, t4, t5, t6, t7, t8, t9: time

tREFI: Regular update execution cycle

tRFC: update execution time

Valid: valid command

WL0_0, WL1_0, WL2_0, WL3_0: the first character line

S110, S120, S130, S140, S210, S220, S230: Operation

FIG. 1 is a diagram illustrating an electronic component including a memory component according to some exemplary embodiments of the inventive concept.

FIG. 2 is a block diagram illustrating the memory device shown in FIG. 1 according to some exemplary embodiments of the inventive concept.

FIG. 3 is a flowchart illustrating the operation of the memory device shown in FIG. 2 according to some exemplary embodiments of the inventive concept.

Fig. 4 is a diagram for explaining the hidden update operation.

FIG. 5 is a block diagram illustrating the memory cell array shown in FIG. 2 including a plurality of banks according to some exemplary embodiments of the inventive concept.

FIG. 6 is a block diagram illustrating the update controller illustrated in FIG. 3 according to some exemplary embodiments of the inventive concept.

7 and 8 are block diagrams illustrating the update information generator illustrated in FIG. 6 according to some exemplary embodiments of the inventive concept.

FIG. 9 is a timing diagram for explaining the operation of the update information generator shown in FIG. 7 and FIG. 8.

FIG. 10 is a block diagram illustrating the update information generator illustrated in FIG. 6 according to some exemplary embodiments of the inventive concept.

FIG. 11 is a timing chart for explaining the operation of the update information generator shown in FIG. 10.

FIG. 12 is a flowchart illustrating the operation of the electronic component shown in FIG. 1 according to some exemplary embodiments of the inventive concept.

FIG. 13 is a timing diagram illustrating the operation of the electronic component shown in FIG. 1 according to some exemplary embodiments of the inventive concept.

FIG. 14 is a timing diagram illustrating the operation of the electronic component shown in FIG. 1 according to some exemplary embodiments of the inventive concept.

FIG. 15 is a block diagram illustrating a memory device according to some exemplary embodiments of the inventive concept.

FIG. 16 is a block diagram illustrating a stacked memory device to which a memory device according to some exemplary embodiments of the inventive concept is applied.

17 and 18 are diagrams illustrating memory modules according to some exemplary embodiments of the inventive concept.

FIG. 19 is a block diagram illustrating a user system to which a memory device or a memory module according to some exemplary embodiments of the inventive concept is applied.

Hereinafter, to the extent that a person with ordinary knowledge in the art can implement the concept of the present invention, certain exemplary embodiments of the concept of the present invention will be explained in detail and clearly.

FIG. 1 is a diagram illustrating an electronic component including a memory component according to some exemplary embodiments of the inventive concept. 1, the electronic device 1 may include a host 10, a memory controller 50, and a memory device 100. For example, the electronic component 1 may be a single system including the host 10, the memory controller 50, and the memory component 100. Alternatively, the host 10, the memory controller 50, and/or the memory device 100 of the electronic component 1 may be implemented as separate components. For example, the host 10 can be located outside the memory controller 50 and the memory device 100. The memory controller 50 may be located outside the host 10 and connected to the memory device 100 via a system bus (not shown in the figure). Alternatively, the memory controller 50 may be located outside the memory device 100 and be a part of the host 10.

The memory controller 100 can be connected to the memory device 50. Memory control The device 50 may include a host interface 52 (for example, a bus interface), a memory interface 54, an error correction circuit (ECC) 58, and an update manager 56. The memory controller 50 can be used to control the memory device 100 according to requests and/or data from the host 10. The memory controller 50 can receive data requests (for example, read requests, write requests) and/or data from the host 10. The memory controller 50 can receive data requests from the host 10 through the host interface 52, and provide commands to the volatile memory device 100 through the memory interface 54 and/or receive update information from the volatile memory device 100. The ECC circuit 58 can perform an error correction circuit operation on the read data from the memory device 100 and/or the write data written to the memory device 100 to correct bit errors. The update manager 56 can be used to provide commands to the memory device 100 and/or receive update information RFR_inf from the memory device 100. The memory controller can provide the command CMD, address ADDR, and data DATA to the memory device 100, and can receive update information RFR_inf and data DATA from the memory device 100.

The host 10 may be an electronic component or a processor circuit including a general-purpose processor or an application processor. Alternatively, the host 10 may be the following computing components including one or more processors: personal computers, peripheral components, digital cameras, personal digital assistants (PDAs), portable media players (portable media players) player, PMP), smart phone, or wearable device. However, the concept of the present invention is not limited to this.

The memory device 100 can store data provided from the host 10 or data to be provided to the host 10. The memory device 100 may include all types of volatile memory. There are storage media to implement. For example, the memory device 100 may include dynamic random access memory, static random access memory, thyristor RAM (TRAM), zero capacitor RAM (zero capacitor RAM, Z-RAM), twin transistor RAM (TTRAM), magnetoresistive RAM (MRAM), etc. The exemplary embodiments of the inventive concept can also be applied to all storage media including volatile memory. For example, the memory device 100 may include an unbuffered dual in-line memory module (UDIMM), a registered dual in-line memory module (registered DIMM, RDIMM), and a reduced load. Load reduced DIMM (LRDIMM), non-volatile dual in-line memory module (Non Volatile DIMM, NVDIMM), etc. The above examples are only examples for explaining the concept of the present invention, and the concept of the present invention is not limited thereto.

Hereinafter, for the convenience of description, a single dynamic random access memory device will be described as an example of the memory device 100 shown in FIG. 1. However, the concept of the present invention can be applied to various storage devices including volatile memory.

The memory device 100 can communicate with the host 10 and the memory controller 50. For example, the memory device 100 can communicate with the host 10 and the memory controller 50 based on one or more of the following: various wired communication protocols, such as universal serial bus (BUS), small computer System interface (small computer system interface, SCSI), fast peripheral component interconnection (Peripheral Component Interconnect Express, PCIe), mobile fast peripheral component interconnection (mobile PCIe, M-PCIe), advanced technology attachment (ATA), parallel advanced technology attachment (parallel ATA, PATA), serial advanced technology attachment (serial ATA, SATA), serial attachment to small computers System interface (serial attached SCSI, SAS), integrated drive electronics (IDE), FireWire, universal flash storage (UFS), transmission control protocol/Internet protocol (transmission control protocol/Internet) protocol, TCP/IP), and various wireless communication protocols, such as long term evolution (LTE), worldwide interoperability for microwave access (WiMax), global system for mobile communication, GSM), code division multiple access (CDMA), high speed packet access (HSPA), Bluetooth, near field communication (NFC), wireless fidelity , Wi-Fi), and radio frequency identification (RFID). However, the concept of the present invention is not limited to this.

The memory device 100 can perform a write operation, a read operation, or an update operation in response to the command CMD and the address ADDR from the memory controller 50. For example, the memory controller 50 can apply a read command or a write command to the memory device 100 in response to receiving a data read request or a data write request from the host 10. As described above, the memory device 100 includes a volatile memory. The volatile memory has such a characteristic that the data stored in the volatile memory disappears after a certain time. In order to maintain the stored data, the volatile memory periodically executes Row update operation. The update operation is an operation to periodically rewrite the data stored in the volatile memory. The write operation, read operation, and update operation of the memory device 100 are performed as follows.

In the write operation, in response to a write request from the host 10, the memory controller 50 provides the current command and the column address together with the clock to the memory device 100. After a certain time, the memory controller 50 provides the write command and the row address together with the clock to the memory device 100. Subsequently, the memory controller 50 receives the data to be written from the host 10, and the memory controller 50 provides the memory device 100 with the data to be written. The memory device 100 writes the received data into the memory area selected by the row address and the row address.

In the read operation, in response to a read request from the host 10, the memory controller 50 provides the current command and the column address together with the clock to the memory device 100. After a certain time, the memory controller 50 provides the read command and the row address together with the clock to the memory device 100. The memory device 100 provides the data requested to be read to the memory controller 50 after a certain time. The memory controller 50 can provide the data requested to be read to the host 10.

In the refresh operation, the memory controller 50 can provide the refresh command together with the clock to the memory device 100 at every regular refresh execution period tREFI. Hereinafter, the update operation performed in accordance with the update command of the memory controller 50 is referred to as a "regular update operation". Alternatively, the memory controller 50 may provide the update command to the memory device 100 after delaying or stopping the regular update execution period tREFI. In the following, it is assumed that the period tREFI is performed by regular update Delay or stop and perform "N" regular update operations for "N" regular update execution cycles (N×tREFI). In addition, hereinafter, "N" regular update execution cycles (N×tREFI) are referred to as "reference time". In this case, there is no need to periodically input the update command to the memory device 100 in each regular update execution cycle tREFI, but for "N" regular update execution cycles (N×tREFI) Perform "N" regular update operations at any point in time when the update operation can be performed. In the memory device 100, the maximum value of "N" can be defined by the Joint Electron Device Engineering Council (JEDEC) standard.

The memory device 100 performs an update operation on the memory cell having the update address generated in the memory device 100 based on the update command. When the update operation is performed according to the command, the memory device 100 does not receive a write command or a read command during the update execution time tRFC. The reason is that if a read command or a write command is processed during the update operation, the data of the memory cell to be accessed by the write operation or read operation will have the same column address as the update operation. The data conflict of the memory cell. In addition, in addition to regular update operations, the memory device 100 can also perform special-purpose update operations in response to update commands from the memory controller 50. The command of the corresponding update operation will be explained with reference to FIG. 13.

The memory device 100 performs an update operation on all memory cells of the memory device 100 during one update cycle. That is, one update cycle includes multiple regular update execution cycles tREFI and multiple reference times. Generally speaking, the period of the update cycle is fixed. Since all the memory cells of the memory device 100 The update operation is performed, so the regular update execution period tREFI and the update execution time tRFC can be changed according to the memory capacity of the memory device 100. The regular update implementation cycle tREFI and update implementation time tRFC are defined by the standards of the Joint Committee on Electronic Components Engineering and Design. If one update cycle ends, the memory device 100 performs an update operation on all memory cells of the memory device 100 again during the new update cycle.

According to certain exemplary embodiments of the inventive concept, the memory device 100 performs regular update operations in response to commands from the memory controller 50, or performs update operations where the commands from the memory controller 50 are not required The hidden update operation. Hereinafter, the hidden update operation is referred to as an update operation performed without receiving a command (for example, an update command) from the memory controller 50 while the memory device 100 processes a write command or a read command.

The memory device 100 according to some exemplary embodiments of the inventive concept includes an update controller 160. The update controller 160 controls the hidden update operation so that the access address of the write command or the read command does not conflict with the update address, and the number of times the hidden update operation can be executed (hereinafter referred to as "execution frequency") And the number of times that regular update operations are performed is counted. Hereinafter, the total value of the execution frequency of each of the regular update operation and the hidden update operation is referred to as the "execution count". The update controller 160 can generate update information RFR_inf based on the following: the performance index of the hidden update operation (for example, the count value of the hidden update operation, the hidden update active signal RFR_H described in FIG. 6) or the hidden update operation and Regular update operation performance indicators of both (for example, hidden update operation and regular The count value of the update operation, the count value of the update active signal RFR_en described in FIG. 6), but the concept of the present invention is not limited to this. For example, the update controller 160 may generate update information RFR_inf based on the execution count. In addition, the update controller 160 can provide the update information RFR_inf to the memory controller 50 when an internal flag is generated or the update controller 160 receives a request from the memory controller 50. Therefore, the memory controller 50 can efficiently control the refresh operation of the memory device 100 including a plurality of volatile memories.

FIG. 2 is a block diagram illustrating the memory device shown in FIG. 1 according to some exemplary embodiments of the inventive concept. 2, the memory device 100 includes a command decoder 110, an address latch 120, a memory cell array 130, a sense amplifier 131, a row decoder 140, an active controller 150, an update controller 160, and a column decoder A device 170, a data input driver 180, a data output driver 190, and a multi-purpose register 195.

The command decoder 110 receives various commands through the command pad CMD. The command decoder 110 provides commands to circuit blocks including the row decoder 140, the active controller 150, the update controller 160, and the like.

The address latch 120 receives the address of the memory cell to be accessed through the address pad ADDR. In the case where data is stored in a memory cell or data is read from a memory cell, the address latch 120, row decoder 140, active controller 150, update controller 160, and The row decoder 170 provides the memory cell array 130 with the address ADDR used to select the memory cell.

The data stored in the memory cell array 130 can be provided to the data output driver 190 by the sense amplifier 131. Alternatively, you can use The sense amplifier 131 stores the data received from the data input driver 180 in the area of the memory cell array 130 corresponding to the given location. The address ADDR of the memory cell associated with the data to be input/output of the memory cell array 130 can be provided to the row decoder 140 and the column decoder 170.

The memory cell array 130 may include, for example, multiple banks. Each of the libraries may include multiple memory array mats. Each of the memory array slices may include a plurality of memory cells. In certain exemplary embodiments, an active controller 150 and an update controller 160 may be provided for each bank to control each bank. This configuration will be explained with reference to FIG. 5.

The active controller 150 generates the active address and active signal for the write operation or the read operation based on the address ADDR and the command CMD provided by the address latch 120 and the command decoder 110, respectively, and the active controller 150 will The current address and current signal are provided to the column decoder 170.

The update controller 160 can be connected to the memory cell by the row decoder 170 and the character line connecting the row decoder 170 to the memory cell in the memory cell array 100. The update controller 160 can be used to control the memory device 100 to perform an effective operation (for example, a write operation or a read operation) on the second part of the memory cell in the memory device 100 at the same time as the first part of the memory cell. Part of the first update operation performed. The first update operation may be a hidden update operation. The second update operation may be performed in response to receiving the update command from the memory controller 50, and the second update operation may be a regular update operation. In addition, as described in FIG. 13, the memory device 100 can respond to an update command from the memory controller 50. Perform update operations for special purposes.

As in the active controller 150, the update controller 160 according to certain exemplary embodiments of the inventive concept generates an active address and an active signal, and compares the active address with the hidden update address. The update controller 160 generates a hidden update active signal based on the comparison value, and provides the hidden update active signal to the column decoder 170. The update controller 160 can generate a hidden update address based on the active signal. The update controller 160 generates a column address for which regular update or hidden update is to be performed, and provides the column address to the column decoder 170. In addition, the update controller 160 generates an execution count by counting the regular update execution frequency and the hidden update execution frequency, and generates update information RFR_inf based on the execution count. The update controller 160 can provide the update information RFR_inf to the multi-purpose register 195. For example, the update information RFR_inf may include an execution count, a hidden update execution count, or an update end flag. The execution count, the hidden update execution count, and the update end flag will be explained with reference to FIG. 7, FIG. 8, and FIG. 10.

The row decoder 170 controls the operation of the memory cell array 130 based on the current address, the current signal, the update current signal, the update address, etc., together with the active controller 150 and the update controller 160. The data input driver 180 can receive data through the data pad DATA, and can provide the received data to the sense amplifier 131. The data output driver 190 can output the data read from the memory cell array 130 through the data pad DATA. Although not illustrated in FIG. 2, the data input driver 180 can receive the data selection communication number through the data strobe pad (for example, DQS) when receiving data. In addition, the data output driver 190 can select data when outputting data. Select the communication number for output data through the pad.

The multi-purpose register 195 can store information about operations performed in the memory device 100. The multi-purpose register 195 can store the update information RFR_inf provided by the self-update controller 160, for example. In addition, in the multi-purpose register (MPR) read mode defined in the standards of the Joint Committee on Electronic Components Engineering Design, the data output driver 190 can be used to store in the multi-purpose register 195 The update information RFR_inf is provided to the memory controller 50.

The reset signal may be provided by the reset command received from the memory controller 50 via the command pad CMD and the command decoder 110. The update information RFR_inf and the value stored in the multi-purpose register 195 can be randomly reset according to the request of the memory controller 50. Alternatively, the reset command may be received from the memory controller 50 periodically. That is, the update information RFR_inf and the value stored in the multi-purpose register 195 can be periodically reset according to the reset command received from the memory controller 50 at each reference time.

In the case where the memory device 100 is a dynamic random access memory device, the memory device 100 operates in synchronization with the clock. To this end, the memory device 100 may further include components including a clock buffer, a delay locked loop circuit, and a duty correction circuit. Such components are not associated with the exemplary embodiment of the inventive concept, and therefore will not be described in detail.

FIG. 3 is a flowchart illustrating the operation of the memory device shown in FIG. 2 according to some exemplary embodiments of the inventive concept. FIG. 3 will be explained with reference to FIG. 1 and FIG. 2. 3, the memory device 100 can generate update information RFR_inf, and can The generated update information RFR_inf is provided to the memory controller 50.

In operation S110, the memory device 100 performs a refresh operation. As described above, the memory device 100 can perform regular update operations in response to the update command of the memory controller 50. In addition, the memory device 100 can also perform hidden update operations in addition to regular update operations.

In operation S120, the memory device 100 generates an execution count by counting the regular update execution frequency and the hidden update execution frequency, and generates update information RFR_inf based on the execution count. The update information RFR_inf can be stored in the multi-purpose register 195. As described above, the update information RFR_inf may include an execution count, a hidden update execution count, or an update end flag.

In operation S130, the memory device 100 determines whether the memory controller 50 requests the update information RFR_inf. If the memory controller 50 does not send a request for the update information RFR_inf (No), the memory device 100 performs operation S130 again. However, in this case, the memory device 100 can additionally perform a hidden update operation or a regular update operation, and the update information RFR_inf can be refreshed. The refreshed and updated information RFR_inf is stored in the multi-purpose register 195 again. If the memory controller 50 sends a request for the update information RFR_inf (Yes), the memory device 100 performs operation S140 and sends the update information RFR_inf to the memory controller 50.

In operation S140, the memory device 100 provides the update information RFR_inf to the memory controller 50. The memory device 100 provides the update information RFR_inf stored in the multi-purpose register 195 based on the request of the memory controller 50 and the address of the register storing the update information RFR_inf contained in the multi-purpose register 195. Supplied to the memory controller 50. However, the memory device 100 may be configured to omit operation S130 or perform operation S140 based on the characteristics of the update information RFR_inf. For example, after the update end flag included in the update information RFR_inf is generated, the update end flag included in the update information RFR_inf can be provided to the memory controller 50 without a request. This is to restrict and/or prevent the execution of extra during the rest of the reference time by providing the update end flag to the memory controller 50 even in the case where the request of the memory controller 50 does not exist. Update operation. Therefore, it is possible to limit and/or prevent the power consumption of the memory device 100 and limit and/or prevent unnecessary generation of commands. This is only an example, and the memory device 100 may be configured such that the update end flag is provided to the memory controller 50 only in response to a request of the memory controller 50.

As described above, the memory device 100 can reset the update information RFR_inf and the multi-purpose register 195. The reason is that the update information RFR_inf stored in the multi-purpose register 195 is only valid within the corresponding reference time.

Fig. 4 is a diagram for explaining the hidden update operation. FIG. 4 will be explained with reference to FIG. 1. As described above, the memory cell array 130 may include multiple banks. The first bank Bank0 is illustrated in FIG. 4 as an example. The first bank Bank0 may include first memory array chips MAT0 to (n+1)th memory array chips MATn and first sense amplifier array SA0 to (n+1)th sense amplifier arrays SAn. The first sense amplifier array SA0 to the (n+1)th sense amplifier array SAn may constitute the sense amplifier 131. The hidden update operation of the first bank Bank0 can be applied to the remaining banks.

The first memory array chip MAT0 to the (n+1)th memory array chip MATn Each of these may include multiple character lines. In each memory array chip, the word line is selected by the column address. Each of the word lines is connected to a plurality of memory cells MC (for example, DRAM memory cells). In addition, the proximity sensor amplifier senses the data stored in the memory cell connected to a word line.

The general data sensing operation is as follows. For example, the first sense amplifier (not shown in the figure) of the first sense amplifier array SA0 senses the memory cells connected to the first word line WL1_0 of the second memory array chip MAT1 that are connected to the first The data of the memory cell of the bit line BL0. However, in order to compare the voltage of the data read from the selected memory cell with the reference voltage, the first sense amplifier of the first sense amplifier array SA0 receives the first bit line of the first memory array chip MAT0 The precharge voltage of BL0. In addition, the first sense amplifier (not shown in the figure) of the second sense amplifier array SA1 senses the memory cell connected to the first word line WL1_0 of the second memory array chip MAT1, which is connected to the second bit. The data of the memory cell of the element line BL1. The sensor amplifier for sensing data is selected according to the structure of the memory cell array.

In the following, the hidden update operation will be explained. Assume that the memory element 100 is connected to the first bit line BL0 and the memory cell of the first word line WL1_0 of the second memory array chip MAT1 (hereinafter referred to as "the first memory cell of the second memory array chip MAT1 Memory cell") performs a read operation. Generally speaking, in order to increase the reading speed or the writing speed, the memory device 100 driven in a double data rate (DDR) mode simultaneously reads or writes each data piece by prefetching data. That is, the memory device 100 in which the double data rate 3 (double data rate 3. In the case of a memory device operating in the DDR3 mode, the memory device 100 performs a prefetch operation on eight bits (23). For example, the memory element 100 is connected to the memory cells of the second bit line BL1 to the eighth bit line BL7 and the first word line WL1_0 of the second memory array chip MAT1 (hereinafter referred to as " The second memory cell to the eighth memory cell of the second memory array chip MAT1") perform a read operation. In this case, the first sense amplifier array SA0 and the second sense amplifier array SA1 adjacent to the second memory array sheet MAT1 sense each data sheet.

It is assumed that the memory device 100 performs an update operation on the first word line WL0_0 or WL2_0 of the first memory array chip MAT0 or the third memory array chip MAT2, together with the above-mentioned read operation. Generally speaking, the update operation is performed on all memory cells connected to the selected character line. That is, for all memory cells connected to the first character line WL0_0 of the first memory array chip MAT0 (hereinafter referred to as the first memory cell to the (n+th) of the first memory array chip MAT0 1) Memory cells) or all memory cells connected to the first character line WL2_0 of the third memory array chip MAT2 (hereinafter referred to as the first memory cells of the third memory array chip MAT2 to The (n+1)th memory cell) performs the update operation.

To perform the update operation, the first sense amplifier (not illustrated in the figure) of the first sense amplifier array SA0 senses the data of the first memory cell of the first memory array chip MAT0. In addition, to perform a read operation, the first sense amplifier (not illustrated in the figure) of the first sense amplifier array SA0 senses the data of the first memory cell of the second memory array chip MAT1. As mentioned above, the sense amplifier can receive the data of the memory cell and the reference voltage to perform the sensing operation. In this case, due to the The corresponding sense amplifier receives two pieces of data, so the corresponding sense amplifier cannot compare the data with the reference voltage.

This problem also occurs at the second sense amplifier (not illustrated in the figure) of the second sense amplifier array SA1. That is, the second sense amplifier of the second sense amplifier array SA1 receives the data of the second memory cell of the second memory array chip MAT1 and the data of the second memory cell of the third memory array chip MAT2 As input. Therefore, the corresponding sense amplifier cannot compare the data with the reference voltage. This problem also occurs at the third to the eighth memory cell of the second memory array chip MAT1.

Therefore, the hidden update operation is performed on the memory array chip that is not adjacent to the memory array chip to be accessed according to the write operation or the read operation. For example, it is possible to perform a hidden update operation on the first part of the memory cell MC while performing a valid operation (for example, a write operation or a read operation) on the second part of the memory cell MC. The first part and the second part of the memory cell MC may be respectively located in memory array chips that are not adjacent to each other. For example, in the above example, the hidden update operation can be performed on the fourth memory array chip MAT3 to the (n+1)th memory array chip MATn. In this case, the data line used to input or output the data accessed according to the write operation or the read operation can be controlled so that the memory array chip on which the hidden update operation is performed is not connected to the data String. The operation and configuration of the update controller that generates addresses for the hidden update operation will be explained with reference to FIG. 6.

5 is a block diagram illustrating the memory cell array shown in FIG. 2 including multiple banks according to some exemplary embodiments of the inventive concept. Refer to Figure 5 for each library The row decoder 140, the active controller 150, the update controller 160, and the column decoder 170 shown in FIG. 1 are provided to operate independently on the memory cell array 130 and the sense amplifier 131. The memory cell array 130 Each of the sense amplifier 131, the row decoder 140, the active controller 150, the update controller 160, and the column decoder 170 is divided into "n" banks, respectively.

That is, the memory cell array 130 may include a first memory cell array 130_1 to an n-th memory cell array 130_n, and the sense amplifier 131 may include a first sense amplifier 131_1 to an n-th sense amplifier 131_n, and The decoder 140 may include a first row decoder 140_1 to an n-th row decoder 140_n. The active controller 150 may include the first active controller 150_1 to the nth active controller 150_n, the update controller 160 may include the first update controller 160_1 to the nth update controller 160_n, and the column decoder 170 may include the first column The decoder 170_1 to the n-th column decoder 170_n.

Each of the first update controller 160_1 to the nth update controller 160_n may perform a hidden update operation on each of the first bank Bank1 to the nth bank Bankn. Here, as described with reference to FIG. 4, in a situation where the current address conflicts with the update address in one library, the first update controller 160_1 to the nth update controller 160_n may be configured to The bank Bank1 to the nth bank Bankn perform hidden update operations. Alternatively, in a situation in which the current address conflicts with the update address in the library, the first update controller 160_1 to the nth update controller 160_n may be configured to control the location in which the update address does not occur except for the corresponding library. The remaining libraries with address conflicts perform hidden update operations. The remaining operations of the above-mentioned components of each of the first bank Bank1 to the nth bank Bankn except those described with reference to FIG. 5 are the same as the reference diagram What is described in 1 to 5, and therefore will not be repeated here.

FIG. 6 is a block diagram illustrating the update controller illustrated in FIG. 3 according to some exemplary embodiments of the inventive concept. 6, the update controller 160 may include an update address generator 161, an address comparator 162, a logic gate (for example, an OR gate), and an update information generator 163. As described with reference to FIG. 4, the update controller 160 determines whether the current address and the update address conflict with each other, and generates a signal for performing a hidden update operation based on the determination result. In addition, the update controller 160 counts the regular update execution frequency and the hidden update execution frequency, and generates update information based on the counting result. The following describes an example in which the logic gate is an OR gate, but the concept of the present invention is not limited to this.

)。 The update address generator 161 generates the column address on which the update operation will be performed. Generally speaking, update operations are performed sequentially on the column addresses. In this case, the update address generator 161 may include, for example, a counter. The update address generator 161 generates an update address ADD_rfr (also known as a hidden update address), and provides the update address ADD_rfr to the address comparator 162 (

).

)。 According to the write command or the read command, the address comparator 162 is provided with an active signal ACT and an active address ADD_act. The address comparator 162 determines whether the current address ADD_act conflicts with the update address ADD_rfr, and generates a hidden update active signal RFR_H(

).

)。 The logical OR generates the update active signal RFR_en(

).

中產生的更新位址ADD_rfr提供至列解碼器170(

)。此外，將更新現用訊號RFR_en饋送返回至位址比較器162，以使得位址比較器162刷新更新位址ADD_rfr。之後，圖2所示列解碼器170對更新位址ADD_rfr進行解碼，並因應於更新現用訊號RFR_en而對記憶體胞元陣列130的與所解碼更新位址對應的記憶體胞元執行更新操作。 The update active signal RFR_en is fed back to the address comparator 162, so that the

The updated address ADD_rfr generated in ADD_rfr is provided to the column decoder 170 (

). In addition, the update current signal RFR_en is fed back to the address comparator 162, so that the address comparator 162 refreshes the update address ADD_rfr. After that, the column decoder 170 shown in FIG. 2 decodes the update address ADD_rfr, and in response to the update active signal RFR_en, performs an update operation on the memory cell of the memory cell array 130 corresponding to the decoded update address.

The update information generator 163 generates update information RFR_inf in response to the update of the current signal RFR_en. The update information generator 163 can use the hidden update active signal RFR_H to generate the update information RFR_inf, because the or gate can generate the update active signal RFR_en based on the comparison result between the regular update active signal RFR and the hidden update active signal RFR_H . The update information generator 163 can also be reset randomly or periodically by the reset signal RST provided from the memory controller 50 at each reference time. An exemplary configuration of the update information generator 163 will be explained with reference to FIGS. 7, 8, and 10.

7 and 8 are block diagrams illustrating the update information generator illustrated in FIG. 6 according to some exemplary embodiments of the inventive concept. 7 and 8 will be explained with reference to FIG. 6.

Referring to FIG. 7, the update information generator 163a may include an oscillator 164 and an update counter 165a. The update information generator 163a shown in FIG. 7 can generate an execution count or a hidden update execution count.

Oscillator 164 will increment every regular update execution cycle tREFI The count-up signal is provided to the update counter 165a. For example, the memory controller 50 can provide a regular update execution period tREFI.

The update counter 165a is provided with an up counting signal and an update active signal RFR_en. The update counter 165a increases the count value in response to the count-up signal, and decreases the count value in response to the update of the current signal RFR_en. The update counter 165a outputs the generated count value as the update information RFR_inf. The change of the update information RFR_inf over time will be explained with reference to FIG. 9. The count value means the number of times that the hidden update operation is executed, and is called the "hidden update execution count". The memory controller 50 can calculate the number of update operations to be performed in the remaining part of the reference time based on the update information RFR_inf.

In addition, the update counter 165a can generate an execution count by counting the update active signal RFR_en. That is, the update information RFR_inf may include hidden update execution count and execution count.

Referring to FIG. 8, the update information generator 163b may include an update counter 165b. As described with reference to FIG. 7, the update counter 165b shown in FIG. 8 can generate an execution count by counting the update active signal RFR_en. In this case, the update information RFR_inf may include the execution count.

The update information RFR_inf generated by the update information generator 163a or 163b shown in FIG. 7 or FIG. 8 can be stored in the multi-purpose register 195. The update information RFR_inf stored in the multi-purpose register 195 can be provided to the memory controller 50 at the request of the memory controller 50. The update counters 165a and 165b shown in FIGS. 7 and 8 can be reset by the reset signal RST.

FIG. 9 is a timing diagram for explaining the operation of the update information generator shown in FIG. 7 and FIG. 8. FIG. 9 will be explained with reference to FIG. 2, FIG. 7, and FIG. 8. The memory device 100 shown in FIG. 1 may include at least one of the update information generators 163a and 163b shown in FIGS. 7 and 8. Referring to FIG. 9, the update information generator 163a or 163b shown in FIG. 7 or FIG. 8 can refresh the update information RFR_inf based on the performance indicators of the hidden update operation and/or the performance indicators of both the hidden update operation and the regular update operation. . In this way, the update information generator 163a or 163b can refresh the update information RFR_inf regardless of whether the hidden update operation is completely performed or the regular update operation is performed. Regardless of whether the update information RFR_inf is refreshed or not, the update information RFR_inf can be stored in the multi-purpose register 195. In the following, it will not be repeated. As described with reference to FIG. 1, below, "N" regular update execution cycles (N×tREFI) are defined as "reference time". The reference time is defined by the time period between t0 and t7. The new reference time starts after the time point t7.

In the example shown in FIG. 9, the memory device 100 receives the update command REF from the memory controller 50 in every regular update execution period tREFI. Each of the multiple regular update execution periods tREFI includes the update execution time tRFC. The update execution time tRFC is the minimum time required for the memory device 100 to perform regular update operations. During the update execution time tRFC, the memory device 100 does not receive commands associated with active operations such as read operations or write operations. Therefore, during the update execution time tRFC, the non-select signal DES is provided to the memory device 100 so that only the update operation is performed. The update information generator 163a or 163b shown in FIG. 7 or FIG. 8 operates as follows.

At t0, the memory device 100 receives the update command REF. After that, the memory device 100 performs regular update operations. For the update information generator 163a shown in FIG. 7, the update counter 165a generates a down count in response to the update of the active signal RFR_en. In addition, the update counter 165a receives an up count from the oscillator 164 when the regular update execution period tREFI starts. Therefore, the update counter 165a outputs the count "0" as the update information RFR_inf. In this case, since a regular update operation is being performed, the hidden update operation is not performed.

For the update information generator 163b shown in FIG. 8, the update counter 165b receives the update active signal REF_en to output a count "1" as the update information RFR_inf.

At t1, the memory device 100 receives a valid command Valid such as a write command or a read command. Although not illustrated in FIG. 9, the memory device 100 receives address information associated with valid commands. The memory device 100 performs an active operation corresponding to a valid command on the received address. It is assumed that the received address and the updated address do not conflict with each other. Under this assumption, a hidden update active signal RFR_H is generated. In this case, the update counter 165a of the update information generator 163a shown in FIG. 7 generates a count down in response to the update of the active signal RFR_en. That is, the update counter 165a outputs the count "-1" as the update information RFR_inf.

For the update information generator 163b shown in FIG. 8, the update counter 165b receives the update active signal REF_en and outputs a count "2" as the update information RFR_inf.

Therefore, during the reference time from t0 to t1, the controller 160 is updated The update information generator 163a shown in FIG. 7 can generate update information based on the performance index of the hidden update operation (for example, receiving the update active signal RFR_en at t1 after the regular update execution period tREF1 starts at t0). In other exemplary embodiments, the update information generator 163 may generate update information based on different performance indicators indicating that the hidden update operation has been performed (for example, the value of the hidden update active signal RFR_H (for example, if RFR_H is equal to 1)) .

Similarly, during the reference time from t0 to t1, the update information generator 163b shown in FIG. 8 of the update controller 160 can generate update information based on the hidden update operation and the performance index of the regular update operation. For example, the update information generator 163b may determine that a hidden update operation or a regular update operation has been performed based on the use of the update active signal RFR_en to generate the update information. However, those with ordinary knowledge in the art will understand that the update information generator 163 shown in FIG. 6 can use different performance indicators of hidden update operations and regular update operations to generate update information RFR_inf. For example, the update information generator 163 shown in FIG. 6 can alternately generate the update information RFR_inf based on the following: the update command REF or the non-select signal DES is detected as the performance indicator of the regular update operation, and the instruction is detected The value of the hidden update active signal RFR_H for which the hidden update operation has been performed (for example, if RFR_H=1).

At t2, the memory device 100 receives a valid command Valid including a write command or a read command, as described at t1. However, in this case, since the received address and the update address conflict with each other, the hidden update active signal RFR_H (for example, RFR_H is equal to "0") may not be generated. Therefore, the update shown in Figure 7 The update counter 165a of the information generator 163a maintains the previous count "-1" without refreshing the count. The update information generator 163a repeats multiple regular update execution cycles tREFI operations before t3. The update counter 165b of the update information generator 163b shown in FIG. 8 maintains the previous count "2" without refreshing the count. In other words, since regular update operations or hidden update operations are not performed at t2, no performance indicator indicating that the performance is regular update information or hidden update information is provided.

At t3, based on the previous regular update operation or hidden update operation, the update counter 165a of the update information generator 163a illustrated in FIG. 7 outputs the count "-i" as the update information RFR_inf. The update counter 165b of the update information generator 163b shown in FIG. 8 counts (N-1) regular update operations and "i" hidden update operations performed before t3, and outputs a count "(N-1) )+i" as the update information RFR_inf.

At t4, the memory device 100 performs a hidden update operation. In this case, the update counter 165a of the update information generator 163a illustrated in FIG. 7 outputs the count "-(i+1)" as the update information RFR_inf. The update counter 165b of the update information generator 163b illustrated in FIG. 8 outputs the count "(N-1)+i+1" as the update information RFR_inf.

At t5, the update counter 165a shown in FIG. 7 or the update counter 165b shown in FIG. 8 performs the same operation as that performed at t3. That is, the update counter 165a shown in FIG. 7 outputs "-(i+1)", and the update counter 165b shown in FIG. 8 outputs "(N+i+1)". At t6, the update counter 165a shown in FIG. 7 or the update counter 165b shown in FIG. 8 performs the same operation as that performed at t4. Therefore, Figure 7 The update counter 165a shown outputs "-(i+2)", and the update counter 165b shown in FIG. 8 outputs "(N)+i+2". The memory controller 50 can request the update information RFR_inf from the memory device 100, and the memory device 100 can provide the memory controller 50 with the update information RFR_inf at each time point in response to the request. The memory controller 50 can be provided with information about the update execution frequency including the regular update execution frequency and the hidden update execution frequency or the hidden update execution frequency at each time point, and the memory controller 50 can be based on the received Information to control the update command of the memory device 100. The update command control method of the memory controller 50 will be explained with reference to FIGS. 12 and 13.

At t7, the memory device 100 starts the update operation associated with the new reference time. For example, as described above, the memory device 100 can receive a reset command and an update command REF at each reference time. The update information RFR_inf and the value stored in the multi-purpose register 195 can be periodically reset to the initial value or the basic value (for example, RFR_inf=0) by the reset signal. For example, if the time interval corresponding to the reference time ends, the reset signal can be provided from the memory controller 50 and/or the host 10 to the update controller 160 through the command decoder 110. The reset operation can be performed before the update information generator 163a shown in FIG. 7 or the update information generator 163b shown in FIG. 8 generates the update information RFR_inf. The reason is that the update information generator 163a/163b newly generates the reset update information RFR_inf in response to the first update command REF associated with the new reference time. As described above, the reset signal can be provided by the command received via the command pad CMD and the command decoder 110. This is just an example. As mentioned above, it can be controlled by the memory before the time point t7 when the new reference time starts. The command of the controller 50 provides a reset signal. During the new reference time, the update information generator 163a shown in FIG. 7 and the update information generator 163b shown in FIG. 8 can generate (or refresh) the update information RFR_inf in the same manner as described above.

Referring to FIGS. 1, 6-9, the update controller 160 shown in FIG. 6 can generate update information to be submitted to the memory controller 50 based on the number of hidden update operations performed by the volatile memory device 100 during the reference time. RFR_inf. In addition, the update controller 160 can be used to refresh the update information RFR_inf if the volatile memory device 100 performs at least one of a regular update operation and a hidden update operation. For example, as described above, at times t1, t4, and t6, the update information generator 163a shown in FIG. 7 and the update information generator 163b shown in FIG. 8 can be performed in different ways according to the hidden update operation being performed Adjust the update information RFR_inf. In addition, at times t0, t3, and t5, in response to the regular update operation being performed, the update information generator 163a shown in FIG. 7 can maintain the value of the update information RFR_inf and the update information generator 163b shown in FIG. 8 can be adjusted Update information RFR_inf.

FIG. 10 is a block diagram illustrating the update information generator illustrated in FIG. 6 according to some exemplary embodiments of the inventive concept. FIG. 10 will be explained with reference to FIG. 6. Referring to FIG. 10, the update information generator 163c may include a flag generator 166.

The flag generator 166 is provided with the update demand count RFR_dnd and the update current signal RFR_en. The update demand count RFR_dnd means the number of update operations performed on each of the banks of the memory cell array 130 shown in FIG. 1 during a reference time. For example, the update demand count RFR_dnd may correspond to a value obtained by dividing the reference time by the regular update execution period tREFI. For example In other words, for the reference time corresponding to "N" regular update execution cycles (N×tREFI), the update demand count RFR_dnd may have a value of "N".

For example, the update demand count RFR_dnd can be provided from the memory controller 50. Alternatively, the update information generator 163c may further include a counter (not shown in the figure) that generates the update demand count RFR_dnd. In this case, the counter (not illustrated in the figure) can generate the update demand count RFR_dnd based on the reference time and the regular update execution period tREFI received from the memory controller 50.

The flag generator 166 generates an execution count by counting the update active signal RFR_en. The flag generator 166 may output the execution count as the update information RFR_inf. The flag generator 166 generates an update end flag when the execution count is greater than or equal to the update demand count RFR_dnd. The flag generator 166 may output the update end flag as the update information RFR_inf. That is, the update end flag means that "N" update operations are all executed within the reference time. The flag generator 166 may output the execution count including the update information RFR_inf. In this case, the update information RFR_inf may include an execution count and an update end flag.

As described with reference to FIG. 3, the update end flag can be generated in response to the request of the memory controller 50 or without the request of the memory controller 50, and the update end flag can be set within a given time. Provided to the memory controller 50. For example, the update information generator 163 may be configured to include one of the update information generator 163a shown in FIG. 7, the update information generator 163b shown in FIG. 8, and the update information generator 163c shown in FIG. One or more combinations.

FIG. 11 is a timing chart for explaining the operation of the update information generator shown in FIG. 10. FIG. 11 will be explained with reference to FIG. 2 and FIG. 10. Referring to FIG. 11, in the case where the number of times the hidden update operation or the regular update operation is performed is greater than or equal to the update demand count RFR_dnd, the update information generator 163c shown in FIG. 10 may output the update end flag as the update information RFR_inf . The definitions of the reference time corresponding to "N" regular update execution cycles (N×tREFI), update command REF, valid command Valid, regular update execution cycle tREFI, and update execution time tRFC are the same as those shown in Fig. 9 The definition of the narrative, and therefore will not be repeated.

In FIG. 11, it is assumed that the update demand count RFR_dnd is "N". The update information generator 163c can generate an execution count. In this case, the update information RFR_inf may include an execution count or an update end flag. The update information generator 163c refreshes the execution count when performing a hidden update operation or a regular update operation. In some exemplary embodiments, the update information RFR_inf can be stored in the multi-purpose register 195 regardless of whether the count is refreshed or not. Alternatively, the update end flag may not be stored in the multi-purpose register 195, but the update end flag may be directly provided to the memory controller 50.

At t0, the memory device 100 performs a regular update operation in response to the update command REF, and provides the flag generator 166 with the update active signal RFR_en according to the update operation. In this case, the flag generator 166 refreshes the execution count to "1". However, the update end flag may not be generated. The flag generator 166 outputs the execution count as the update information RFR_inf.

At t1, the memory device 100 performs a hidden update operation, and therefore The flag generator 166 refreshes the value of the execution count to "2". At t2, since the memory device 100 does not perform a hidden update operation, the flag generator 166 maintains the value of the execution count, that is, "2". During the time period between t2 and t3, the memory device 100 may perform multiple regular update operations or multiple hidden update operations. At t3, based on the previous regular update operation or hidden update operation, the update counter 165 outputs the count value "(N-1)" as the update information RFR_inf.

At t4, the memory device 100 performs a hidden update operation, and therefore the update information RFR_inf is "N". In this case, the flag generator 166 generates an update end flag. As described above, the update end flag can be generated in response to the request of the memory controller 50 or without the request of the memory controller 50, and the update end flag can be provided to the memory within a given time. Body controller 50. In response to the update end flag, the memory controller 50 can stop providing the update command REF or can control the update operation of the memory device 100 so that the hidden update operation is not performed. This will be explained with reference to FIG. 13.

If the update controller 160 determines that the sum of the count value of the update operation hidden during the reference time and the count value of the regular update operation is greater than or equal to the threshold value corresponding to the update demand count RFR_dnd, the update controller 160 may limit and /Or prevent the volatile memory device 100 from performing additional hidden update operations or additional regular update operations during the rest of the reference time. At t5, a new regular update execution period tREFI begins. However, since the update command REF is no longer provided after the update end flag is provided to the memory controller 50, the memory device 100 can receive the valid command Valid. The operations performed at t6 and t7 are the same as at The operation performed at t5. Therefore, the memory device 100 may not perform an update operation, but the memory device 100 may perform an operation corresponding to the valid command Valid. Therefore, the data processing efficiency of the memory device 100 can be improved.

During the first part of the reference time (for example, from t0 to t3), the update controller 160 may generate the update information RFR_inf based on the performance index (for example, the count value) of the hidden update information. The update information RFR_inf can be generated based on the performance indicators of regular update operations and hidden update operations (for example, the sum of the number of regular update operations performed during the first part of the reference time and the number of hidden update operations) .

As described at t7 shown in FIG. 8, at t8, for the new reference time, a reset signal and an update command REF can be provided to the memory device 100. The following operations are the same as those described with reference to the time period between t1 and t7.

FIG. 12 is a flowchart illustrating the operation of the electronic component shown in FIG. 1 according to some exemplary embodiments of the inventive concept. Referring to FIG. 12, the memory controller 50 can control the update operation of the memory device 100 based on the update information RFR_inf received from the memory device 100.

In operation S210, the update controller 160 may generate update information RFR_inf based on the performance indicators of the hidden update operations or the performance indicators of the hidden update operations and the regular update operations during the first part of the reference time. For example, for the corresponding reference time, the memory device 100 may generate an execution count by counting the regular update execution frequency and the hidden update execution frequency, and generate the update information RFR_inf based on the execution count. For example, refer to Figure 1 to Figure As described in 11, the update information RFR_inf may include an execution count, a hidden update execution count, or an update end flag. However, the concept of the present invention is not limited to this.

In operation S220, the memory device 100 provides the update information RFR_inf to the memory controller 50 in response to the request of the memory controller 50. In operation S230, the memory controller 50 may control the update operation of the memory device 100 corresponding to the rest of the reference time based on the update information RFR_inf. The update manager 56 of the memory controller 50 can regularly schedule the desired number of update operations during the rest of the reference time based on the update information RFR_inf. The update manager 56 can control the volatile memory device 100 to perform regular update operations according to the schedule. The expected number of regular update operations performed may be based on the reference value (or the target number of update operations) and the performance indicators of the hidden update operations performed during the first part of the reference time and the regular update operations (for example, Count value). The expected number of regular update operations can also be based on performance indicators (for example, count values) for special-purpose update operations. The update manager 56 may refresh the schedule when the update information RFR_inf is refreshed and provided to the memory controller 50. The update manager 56 can control the volatile memory device so that the volatile memory device 100 performs a target number of update operations during the reference time, and the target number of update operations can correspond to the volatile memory device 100 performing the update operations during the reference time. The sum of the number of regular update operations, the number of hidden update operations, and the number of special-purpose update operations as needed. Operation S230 will be explained in detail with reference to FIG. 13.

FIG. 13 is a diagram illustrating some exemplary embodiments according to the concept of the present invention. Shows the timing chart of the operation of the electronic components. FIG. 13 will be explained with reference to FIG. 1, FIG. 2, and FIG. 9. The definitions of the reference time corresponding to "N" regular update execution cycles (N×tREFI), update command REF, valid command Valid, regular update execution cycle tREFI, and update execution time tRFC are the same as those shown in Fig. 9 The definition of the narrative, and therefore will not be repeated. In the example shown in FIG. 13, it is assumed that the update operation of the memory device 100 is performed at the last point in time of the reference time because "N" regular update operations are postponed. As described in FIG. 11, in addition, it is assumed that the update demand count RFR_dnd is "N", and N can be regarded as the target number of update operations.

During the time period between t0 and t3, the memory device 100 performs multiple hidden update operations in response to the valid command Valid. Because of the hidden update operation, the update information RFR_inf will be refreshed. At t4, the memory controller 50 can provide the multi-purpose register read command MRR to the memory device 100. The multi-purpose register read command MRR may include a mode register set (MRS) command and an address command defined by the standards of the Joint Committee on Electronic Components Engineering and Design. However, this is not related to the exemplary embodiment of the inventive concept, and therefore it may not be described in detail. The update information RFR_inf stored in the multi-purpose register 195 can be provided to the memory controller 50 by the multi-purpose register read command MRR. Here, it is assumed that the memory device 100 performs "M" hidden update operations before t4. Based on the update information RFR_inf, the memory controller 50 can determine that the memory device 100 performs "M" hidden update operations. In other words, the performance index of the hidden update operation can be included in the first part of the reference time (for example, t0 to t4) The update scale (for example, count value) corresponding to the number of hidden update operations performed during the period.

During the time period between t5 and t9, the memory controller 50 can control the schedule of the refresh operation of the memory device 100 so that the refresh operation is executed "N-M+a" times. In this case, the memory controller 50 can control the memory device to hide the update operation to be suspended during the time period between t5 and t9. Therefore, the memory controller 50 may not provide the valid command Valid to the memory device 100 during the time "(N-M+a)×tRFC" required to execute the update operation "N-M+a" times. The time "(N-M+a)×tRFC" is illustrated in FIG. 13 as corresponding to the time from t5 to t9.

Here, "a" refers to the number of special-purpose update operations different from hidden update operations and regular update operations. For example, the special purpose is to improve the data reliability of the memory cell connected to a specific character line. "A" can include "0" and natural numbers. That is, in the case where "a" is "0", the memory controller 50 can control the memory device 100 to perform the update operation "N-M" times. Alternatively, in the case where "a" is a natural number, even if the memory device 100 performs "N" update operations from t0 to t5, the memory controller 50 can also control the memory device 100 to perform additional operations Used for special-purpose update operations "a" times.

The memory controller 50 can generate an update command based on the update information RFR_inf. For example, if the memory device 100 responds to a request from the memory controller 50 (for example, the multi-purpose register read command MRR), the information will be updated at t5 RFR_inf is sent to the memory controller 50, and the memory controller 50 can provide the update command REF to the memory device 100 (N-M) times. Thereafter, during the remaining part of the reference time (for example, from t5 to t9), the memory device 100 can perform (N-M) regular update operations in response to N-M update commands REF from the memory controller 50. In addition, to perform "a" update operations, the memory controller 50 can provide the memory device 100 with the update command REF "a" times, or can provide the memory device 100 with a separate update command different from the update command REF.

In other words, the memory controller 50 is provided with a hidden update execution frequency, and the memory controller 50 provides an update command to the memory device 100 at a frequency other than the hidden update execution frequency. In addition, the memory controller 50 can control the memory device 100 to perform the update operation up to the number of times the update operation is performed for a special purpose. Based on the above description, the memory controller 50 can provide the valid command Valid to the memory device 100 during the time period of "M×tRFC", thereby improving the command efficiency. The command efficiency can be defined as the ratio of the number of valid commands Valid among the total number of commands received by the memory device 100 from the memory controller 50.

At t5, if the count value M of the hidden update operation is equal to the threshold value (for example, N minus the value of "a"), the update controller 160 can perform the rest of the reference time (for example, t5 to t9) Period limits and/or prevents volatile memory components from performing additional hidden update operations.

FIG. 14 is a timing diagram illustrating the operation of the electronic component shown in FIG. 1 according to some exemplary embodiments of the inventive concept. Except for the following differences, FIG. 14 is the same (or similar to) the timing diagram discussed in FIG. 13.

Referring to FIG. 14, at t0, the memory device 100 receives the update command REF and performs a regular update operation. At times t1 and t2, the memory device 100 performs multiple hidden update operations in response to the valid command Valid. Because of the hidden update operation, the update information RFR_inf will be refreshed.

At t3, the memory controller 50 can provide the multi-purpose register read command MRR to the memory device 100. The memory device 100 can provide update information RFR_inf to the memory controller 50 in response to the MRR command. Based on the update information RFR_inf, the memory controller 50 can determine that the volatile memory device 100 has performed R regular update operations and M hidden update operations during the part t0 to t3 of the reference time. During the time period between t4 and t8, the memory controller 50 may control the schedule of the refresh operation of the memory device 100 so that the refresh operation is executed "N-M-R+a" times. For example, from t4 to t8, the memory controller 50 can provide update commands to the memory device 100 for (NM-R+a) times, and the memory device 100 can perform regular updates in response to the update commands operate. In addition, as in the timing chart in FIG. 13, "a" refers to the number of update operations for special purposes, and the hidden update operations can be suspended during the period from t4 to t8.

FIG. 15 is a block diagram illustrating a memory device according to some exemplary embodiments of the inventive concept. 15, the memory device 200 includes a command decoder 210, an address latch 220, a memory cell array 230, a sense amplifier 231, a row decoder 240, an active controller 250, an update controller 260, and a column decoder 270, a data input driver 280, and a data output driver 290. The memory device 200 shown in FIG. 15 is substantially the same as the memory device 100 shown in FIG. 2, except that the memory device The component 200 does not include the multi-purpose register 195, and therefore will not be described in detail.

The memory device 200 shown in FIG. 15 includes a dedicated pad for RFR_inf for providing update information RFR_inf to the memory controller 50. The memory device 200 can provide the update information RFR_inf to the memory controller 50 in real time via a dedicated pad. In this case, the memory controller 50 may include a register for storing the update information RFR_inf.

FIG. 16 is a block diagram illustrating a stacked memory device to which a memory device according to some exemplary embodiments of the inventive concept is applied. 16, the stacked memory device 1000 may include a first memory device 1100 and a second memory device 1200, a logic die 1300, and a solder ball 1400. The number of stacked memory devices is not limited to the number illustrated in FIG. 16.

Each of the first memory device 1100 and the second memory device 1200 may include the memory device 100/200 described with reference to FIGS. 1 to 15. Therefore, the first memory device 1100 and the second memory device 1200 may include update controllers 1160 and 1260, respectively. The first memory device 1100 and the second memory device 1200 can be implemented based on any one of the memory devices 100 and 200 described with reference to FIGS. 1 to 15. Each of the update controllers 1160 and 1260 may include any of the update controllers 160/260 described with reference to FIGS. 1-15. The first memory device 1100 and the second memory device 1200 can be connected to each other by a through silicon via (TSV). In addition, the first memory device 1100 and the second memory device 1200 can be connected to the logic die 1300 by silicon vias.

The logic die 1300 may include a register 1360. Although not stated, but the logic The die 1300 may further include the memory controller 50 described in FIG. 1. The register 1360 can store update information provided from each of the first memory device 1100 and the second memory device 1200 connected to each other through silicon vias. In addition, in response to the host's request, the logic die 1300 can provide the host with the update information stored in the register 1360 through the input/output pad (not shown in the figure) and one or more solder balls 1400. With the above configuration, the update information about the first memory element and the second memory element can be provided to the host by one command, thereby improving the efficiency of managing update information.

In FIG. 15, the structure of the memory device stacked by silicon vias is illustrated as an example of the stacked memory device 1000. However, the concept of the present invention is not limited to this. It is easy to understand that the example shown in FIG. 15 is applicable to all types of stackable memory including package on package (PoP) and through-silicon vias.

17 and 18 are diagrams illustrating memory modules according to some exemplary embodiments of the inventive concept.

The memory module 2000 illustrated in FIG. 17 and the memory module 3000 illustrated in FIG. 18 have a dual in-line memory module (DIMM) structure. Each of the memory modules 2000 and 3000 may include a plurality of memory devices 100 or a plurality of memory devices 200 described with reference to FIGS. 1 to 15 or a stacked memory device 1000 described with reference to FIG. 16. However, for ease of description, the first memory element and the second memory element among the plurality of memory elements will be described as examples. The memory modules 2000 and 3000 may include a terminating resistor T located on the transmission line of the command/address (CA) signal.

Shown in Figure 17 is a type A with a registered dual in-line memory module form Memory module 2000. The A-type memory module 2000 may include a first memory device 2100 and a second memory device 2200, a command/address register 2300, and an update information transmission line 2400. The first memory device 2100 and the second memory device 2200 are connected to the command/address register 2300. In order to reduce the load on the output part of the host, the command/address register 2300 can be used to send data from the host (and/or the memory controller) to the first memory device 2100 and the second memory device 2200. The clock or address is used for buffering.

In the registered dual in-line memory module structure, in the case where the memory controller accesses the first memory device 2100 and the second memory device 2200, the memory controller can be directly connected through the independent transmission line DQ_G Exchange data with each of the first memory device 2100 and the second memory device 2200. In contrast, the memory controller can provide an address or command to each of the first memory device 2100 and the second memory device 2200 through the command/address register 2300.

The command/address register 2300 can store the update information provided by each of the first memory element 2100 and the second memory element 2200 connected through the update information transmission line 2400. In addition, in response to a request from the host, the command/address register 2300 provides the stored update information to the memory controller through the command/address transmission line CA. In some exemplary embodiments, the command/address transmission line CA may be bidirectional. With the above configuration, the memory controller can be provided with update information about the first memory element 2100 and the second memory element 2200 by one command, thereby making it easy to manage the update information. The memory controller can extract the update information and data retrieved from the first memory element 2100 and the second memory element 2200 Supplied to the host. The memory controller can provide addresses or commands to the first memory device 2100 and the second memory device 2200 in response to a request from the host. Alternatively, the memory controller can be part of the host.

In FIG. 18, a B-type memory module 3000 in the form of a load-reducing dual-in-line memory module is illustrated. The B-type memory module 3000 may include a first memory element 3100 and a second memory element 3200, a memory buffer 3300, and a transmission line 3400. The first memory device 3100 and the second memory device 3200 are connected to the memory buffer 3300 through the transmission line 3400. The memory buffer 3300 plays a role in reducing the load of the output part of the memory controller.

In the dual in-line memory module structure with reduced load, in the case where the memory controller accesses the first memory element 3100 and the second memory element 3200, the memory controller uses the memory buffer 3300 And the transmission line 3400 to indirectly exchange data, commands, and addresses with the first memory device 3100 and the second memory device 3200.

The memory buffer 3300 can store the update information provided by each of the first memory device 3100 and the second memory device 3200 connected by the transmission line 3400. In addition, in response to a request from the host (and/or the memory controller), the memory buffer 3300 provides the stored update information to the host through the data transmission line DATA. With the above configuration, the memory controller can be provided with update information about the first memory element 3100 and the second memory element 3200 by one command, thereby making it easy to manage the update information. As mentioned above, the update information can be reset randomly or periodically by the reset command provided from the memory controller RFR_inf, the value stored in the command/address register 2300 shown in FIG. 17, and the value stored in the memory buffer 3300 shown in FIG. 18. The memory controller can provide update information and data retrieved from the first memory element 3100 and the second memory element 3200 to the host. The memory controller can provide addresses or commands to the first memory device 3100 and the second memory device 3200 in response to a request from the host. Alternatively, the memory controller can be part of the host.

FIG. 19 is a block diagram illustrating a user system to which a memory device or a memory module according to some exemplary embodiments of the inventive concept is applied. The user system 4000 may include an image processing unit 4100, a wireless transceiver unit 4200, an audio processing unit 4300, an image file generating unit 4400, a memory 4500, a user interface 4600, and a controller 4700.

The image processing unit 4100 may include an image sensor 4120, an image processor 4130, and a display unit 4140. The image processing unit 4100 can be connected to the through mirror 4110. The wireless transceiver unit 4200 includes an antenna 4210, a transceiver 4240, and a modulator/demodulator (modem) 4230. The audio processing unit 4300 includes an audio processor 4310, a microphone 4320, and a speaker 4330.

Memory 4500 can be memory module (dual in-line memory module), memory card (multimedia card (MMC), embedded multimedia card (embedded MMC, eMMC), secure digital (SD) card , Micro secure digital card, etc.). The controller 4700 can drive application programs, operating systems, and other system chips for implementation. The controller 4700 may include an image processor 4130 or a modem 4230.

The memory 4500 can be implemented with reference to the memory device 100 or 200 including the update controller 160 or 260 described in FIG. 1 to FIG. 15. Alternatively, the memory 4500 can be implemented with reference to the stacked memory device 1000 described in FIG. 16 or the memory module 2000 or 3000 described with reference to FIG. 17 or 18. In this case, since the memory 4500 provides update information to the controller 4700, the controller 4700 can efficiently control the update commands. The controller 4700 may include the memory controller 50 in FIG. 1.

According to certain exemplary embodiments of the inventive concept, it is possible to restrict and/or prevent unnecessary execution of update operations and unnecessary generation of update commands. This may mean an increase in the efficiency of controlling the update operation. In other words, the data processing efficiency of the volatile memory and the memory module can be improved.

In some exemplary embodiments, in the case where the memory controller is a part of the host, the host may include a memory (not shown in the figure) for storing functions related to the memory controller, so that When the host executes the instructions of the memory, the processor circuit or one or more processors of the host are configured as a dedicated processor circuit or one (more) processors for performing the functions of the memory controller. Therefore, in an exemplary embodiment, the memory controller (and/or the host when the memory controller is part of the host) can improve the function of the memory device by increasing the efficiency of controlling the update operation.

Although certain exemplary embodiments have been specifically shown and described, those skilled in the art should understand that changes in form and details can be made without departing from the spirit and scope of the scope of the patent application.

100: memory device/volatile memory device

110: Command decoder

120: address latch

130: Memory cell array

131: sense amplifier

140: Line decoder

150: active controller

160: update controller

170: column decoder

180: data input driver

190: data output driver

195: Multi-purpose register

ADDR: Address/Address Pad

CMD: Command/Command Pad

DATA: data/data pad/data transmission line

RFR_inf: Update information

Claims (19)

A volatile memory device includes: a memory cell; and an update controller connected to the memory cell, and the volatile memory element is used to perform hiding of a first part of the memory cell An update operation, while the volatile memory element performs an effective operation on the second part of the memory cell, the update controller is used to generate update information to be submitted to the memory controller, the update information is based on The number of times the volatile memory device executes the hidden update operation during a reference time, wherein the update controller is used to receive an update command from the memory controller to execute the hidden update operation in the volatile memory device Regular update operations, and the update command is based on the update information. A volatile memory device includes: a memory cell; and an update controller connected to the memory cell, the update controller being used to control the hidden update performed on the first part of the memory cell At the same time, the volatile memory element performs an effective operation on the second part of the memory cell, and the volatile memory element is used to execute a regular operation in response to an update command from an external memory controller Update operation, the update controller is used to use all the data during the first part of the reference time The performance index of the hidden update operation is used to generate update information, and the update information is sent to the external memory controller, wherein the volatile memory element is used to respond to all the information from the external memory controller The update command executes the expected number of regular update operations during the remaining part of the reference time, the update command is generated based on the update information, and the regular update operation The expected number of times is an integer corresponding to the difference between the target number of update operations during the reference time and an update scale, the update scale including the volatile memory device performing the hiding during the reference time The number of update operations. The volatile memory device according to claim 2, wherein the performance index of the hidden update operation corresponds to the performance index of the hidden update operation during the first part of the reference time Count value. The volatile memory device according to claim 2, wherein the update controller is used to use the performance index of the hidden update operation during the first part of the reference time and the The performance index of the regular update operation during the reference time period is used to generate the update information. The volatile memory device described in claim 2, wherein the update controller is used for resetting the update information if the update controller receives a reset signal from the memory controller Into the initial value. The volatile memory device described in item 2 of the scope of patent application, wherein The volatile memory device is used to perform the hidden update operation without receiving an update command from the memory controller. A volatile memory device includes: a memory cell; and an update controller connected to the memory cell, the update controller being used for controlling a first update performed on a first part of the memory cell At the same time, the volatile memory element performs an effective operation on the second part of the memory cell, and the volatile memory element is used to perform a second update in response to an update command from an external memory controller Operation, the update controller is used to generate update information based on the performance index of the first update operation during the first part of the reference time, and send the update information to the external memory controller, and the The volatile memory element is used for the remaining part of the reference time based on the number of times the volatile memory element receives the update command from the external memory controller The second update operation is performed a desired number of times during a partial period, wherein the update command is generated based on the update information. The volatile memory device described in claim 7, wherein the expected number of times of the second update operation is based on the difference between the target number of update operations during the reference time and the update scale Integer, the update scale includes that the volatile memory device performs the first update during the reference time The number of new operations. The volatile memory device according to claim 7, wherein the performance index of the first update operation corresponds to the count value of the update operation hidden during the first part of the reference time . The volatile memory device according to claim 7, wherein the update controller is configured to perform at least one of the first update operation and the second update operation on the volatile memory device , Refresh the update information. The volatile memory device according to claim 7, wherein the volatile memory device is used to send the update information to the external memory in response to a request from the external memory controller And the volatile memory element is used for sending the update information to the external memory controller based on the characteristics of the update information. The volatile memory device according to claim 7, wherein the update controller is configured to perform the first update operation during the first part of the reference time if the update controller determines If the count value is equal to the threshold, the volatile memory device is prevented from performing an additional first update operation during the remaining part of the reference time. The volatile memory device described in item 7 of the scope of patent application, which The update controller is used for controlling the first if the update controller receives the active address corresponding to the second part of the memory cell and the active signal corresponding to the effective operation Update operation, and the update controller is used to generate an update address that corresponds to the first part of the memory cell and does not conflict with the current address to perform the update operation from the external memory controller Controlling the first update operation in the case of receiving the update command. The volatile memory device according to item 13 of the scope of patent application, wherein the first update operation is a hidden update operation, the second update operation is a regular update operation, and the update controller includes an address A comparator, an update address generator, a logic gate, and an update information generator. The update address generator is used to generate a hidden update address based on the update active signal, and the address comparator is used to generate a hidden update address based on the hidden update address. Updating the address and the current address to generate a hidden update active signal, and the logic gate is used to generate the update active signal based on performing logical operations on the regular update active signal and the hidden update active signal, And the update information generator is used for using the hidden update active signal to generate the update information. The volatile memory device according to claim 7, wherein the update controller includes an update counter, and the update counter is used to adjust if the volatile memory device performs the first update operation The update information, and the update controller includes an oscillator for maintaining the value of the update information if the volatile memory device performs the second update operation. The volatile memory device according to claim 7, wherein the external memory controller is configured to generate a reset command and send the reset command if the time interval corresponding to the reference time expires To the volatile memory device, the update controller of the volatile memory device is used to reset the update information to the base in response to receiving the reset command from the external memory controller Value, and the update controller is used to refresh the update information based on the performance index of the first update operation during the first part of the new reference time. The volatile memory device according to claim 7, wherein the update controller is used for if the volatile memory device performs one of the first update operation and the second update operation, Generating an update active signal, the update active signal being the performance indicator of the first update operation, The update active signal is a performance indicator of the second update operation, and the update controller is used to generate the update information based on the count value of the update active signal during the first part of the reference time . The volatile memory device according to claim 7, wherein the first part and the second part of the memory cell are located in a memory array chip that is not adjacent to each other. The volatile memory device according to claim 7, wherein the update controller is used to use the performance index and the performance index of the first update operation during the first part of the reference time The performance indicator of the second update operation to generate the update information, the performance indicator of the first update operation corresponds to the count value of the first update operation during the first part of the reference time, And the performance indicator of the second update operation corresponds to the count value of the second update operation during the first part of the reference time.

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