TWI740761B - Data processing apparatus, artificial intelligence chip - Google Patents

Abstract

The present disclosure provides a data processing apparatus and artificial intelligence chip. The apparatus includes a first/second selection unit provided with multiple input and output terminals, and multiple arithmetic units. The input terminals of the first selection unit are configured to connect with its output terminals. At least a part of the output terminals of the first selection unit connect with input terminals of the arithmetic units. Output terminals of the arithmetic units connect with the input terminals of the second selection unit. The input terminals of the second selection unit connect with its output terminals. At least a part of the output terminals of the second selection unit connect with the input terminals of the first selection unit, and/or with a data output port of the apparatus. Such connection enables the arithmetic units to construct different pathways for arithmetic operation.

Description

Data processing device, artificial intelligence chip

The present disclosure relates to the field of data processing technology, in particular to data processing devices and artificial intelligence chips.

In various application scenarios (for example, neural network application scenarios), there are a variety of operations, including basic simple function operations, such as addition, subtraction, multiplication, division, etc., as well as a large number of unconventional complex operations , And the forms of complex calculations included in different application scenarios are also varied, and new types of complex calculation combinations are also emerging in an endless stream. As the types of operations increase and the amount of operations increases, the area and power consumption of data processing devices that perform operations also increase correspondingly.

The present disclosure provides a data processing device and artificial intelligence chip.

According to a first aspect of the embodiments of the present disclosure, there is provided a data processing device, the device comprising: a first selection unit having a plurality of input terminals and a plurality of output terminals, and a second selection unit having a plurality of input terminals and a plurality of output terminals , And multiple arithmetic units; multiple input terminals of the first selection unit are configurably connected to multiple output terminals of the first selection unit, and at least a part of the multiple output terminals of the first selection unit is connected The input ends of the multiple arithmetic units, the output ends of the multiple arithmetic units are connected to the multiple input ends of the second selection unit, and the multiple input ends of the second selection unit are configurably connected to the The multiple output terminals of the second selection unit, at least a part of the multiple output terminals of the second selection unit are connected to the multiple input terminals of the first selection unit, and/or are connected to the data of the data processing device The output ports are connected so that the multiple arithmetic units form different arithmetic paths.

In some embodiments, the device further includes: a first register for storing first configuration information, and the first configuration information is used for configuring: the plurality of input terminals of the first selection unit and the The connection relationship between the multiple output terminals of the first selection unit, and/or the connection relationship between the multiple input terminals of the second selection unit and the multiple output terminals of the second selection unit.

In some embodiments, the device further includes: a second register for storing second configuration information, and the second configuration information is used for configuring the operation type of at least a part of the plurality of arithmetic units.

In some embodiments, the multiple input terminals of the first selection unit include at least one first input terminal, and the first input terminal is connected to the data input port of the data processing device for inputting the original operand.

In some embodiments, the arithmetic unit is used to detect valid identification information in the input data, and in response to detecting the valid identification information in the input data, perform operations on the input data.

In some embodiments, the device further includes: at least one delay unit; the input terminal of the delay unit is connected to the output terminal of the first selection unit, and the output terminal of the delay unit is connected to the second selection unit. The input terminal of the unit; the delay unit is used to delay processing the data received from the output terminal of the first selection unit, and transmit the delayed processed data to the input terminal of the second selection unit .

In some embodiments, the device further includes: at least one third register, the input terminal of the third register is connected to the output terminal of the second selection unit, and the output of the third register The terminal is connected to the input terminal of the first selection unit, or connected to the data output port of the data processing device.

In some embodiments, the multiple input terminals of the first selection unit include at least one second input terminal, and the second input terminal is connected to the output terminal of the second selection unit through a connecting line, or through a connecting line. Connect with the fourth register for storing operation parameters.

In some embodiments, the multiple operation units include at least one arithmetic operation unit and/or at least one logic operation unit.

According to a second aspect of the embodiments of the present disclosure, an artificial intelligence chip is provided, and the artificial intelligence chip includes the data processing device described in any one of the embodiments.

In some embodiments, the artificial intelligence chip further includes: a control unit configured to control the data processing device so that multiple arithmetic units in the data processing device form different arithmetic paths.

In some embodiments, the control unit is further configured to configure the configuration information of the data processing device, so that multiple arithmetic units in the data processing device form different arithmetic paths.

In some embodiments, the configuration information includes at least any one of the following: first configuration information for configuring the relationship between the multiple input terminals of the first selection unit and the multiple output terminals of the first selection unit The connection relationship, and/or the connection relationship between the multiple input terminals of the second selection unit and the multiple output terminals of the second selection unit, and the second configuration information is used to configure the multiple arithmetic units At least part of the operation type.

In some embodiments, the multiple input terminals of the first selection unit include at least one first input terminal; the control unit is further configured to: write the original operand into the at least one first input terminal of the first selection unit. Input terminal.

The data processing device of the embodiment of the present disclosure can form different data processing paths by changing the internal connection mode of the first selection unit and the second selection unit. Through the non-cured device connection mode, the efficient multiplexing of the computing unit is realized. Save the area of the data processing device. In addition, after the internal connection modes of the first selection unit and the second selection unit are configured, the solution of the embodiment of the present disclosure can automatically form a pipeline operation of multiple arithmetic units in the arithmetic path, complete efficient data processing, and save data. Processing power consumption, to obtain a higher energy consumption ratio.

It should be understood that the above general description and the following detailed description are only exemplary and explanatory, rather than limiting the present disclosure.

The exemplary embodiments will be described in detail here, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

The terms used in the present disclosure are only for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. The singular forms of "a", "said" and "the" used in the present disclosure and appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and/or" as used herein refers to and includes any or all possible combinations of one or more associated listed items. In addition, the term "at least one" herein means any one of a plurality of types or any combination of at least two of the plurality of types.

It should be understood that although the terms first, second, third, etc. may be used in this disclosure to describe various information, the information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present disclosure, the first information can also be referred to as second information, and similarly, the second information can also be referred to as first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "when" or "in response to determination".

In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present disclosure, and to make the above-mentioned objectives, features, and advantages of the embodiments of the present disclosure more obvious and understandable, the following describes the technology in the embodiments of the present disclosure with reference to the accompanying drawings. The plan is explained in further detail.

In many application scenarios, there are often various data processing operations, for example, arithmetic operations. Taking neural network application scenarios as an example, the operation of activation function in neural network may include basic simple function operations, such as addition, subtraction, multiplication and division, etc., and may also include a large number of unconventional complex operations. , And the forms of complex operations included in different neural networks are also varied; at the same time, new types of neural networks are also emerging in endlessly. Therefore, when designing a data processing device for performing data processing operations, it is often faced with the problems of multiple types of arithmetic units and a large amount of data processing. In addition, the data processing device is also required to take into account the design requirements of small area and low power consumption. .

An embodiment of the present disclosure provides a data processing device. As shown in FIG. 1, the device may include: a first selection unit 101 with multiple input terminals and multiple output terminals, and a first selection unit 101 with multiple input terminals and multiple output terminals. Two selection units 102, and multiple operation units 103.

The multiple input terminals of the first selection unit 101 are configurably connected to multiple output terminals of the first selection unit 101, and at least a part of the multiple output terminals of the first selection unit 101 is connected to the multiple output terminals. The input terminal of the arithmetic unit 103.

The output terminals of the multiple arithmetic units 103 are connected to the multiple input terminals of the second selection unit 102.

The multiple input terminals of the second selection unit 102 are configurably connected to multiple output terminals of the second selection unit 102, and at least a part of the multiple output terminals of the second selection unit 102 is connected to the first The multiple input terminals of the selection unit 101 are connected, and/or are connected with the data output port of the data processing device, so that the multiple arithmetic units 103 form different arithmetic paths.

In the embodiment of the present disclosure, the first selection unit 101 and the second selection unit 102 may each include multiple input terminals and multiple output terminals, and the first selection unit 101 configurable Part or all is connected to part or all of the output terminal; in the same way, the second selection unit 102 can also be configured to connect part or all of the input terminal to part or all of the output terminal, so that it is connected to the first A plurality of arithmetic units 103 between a selection unit 101 and the second selection unit 102 can form different data processing paths. In practical applications, the number of input terminals of the first selection unit 101 and the number of output terminals of the first selection unit 101 may be the same or different; the number of input terminals of the second selection unit 102 and the number of output terminals of the second selection unit 102 It can be the same or different; the number of input terminals of the first selection unit 101 and the number of output terminals of the second selection unit 102 can be the same or different.

In the embodiments of the present disclosure, the internal connection relationship of the selection unit can be configured according to requirements, for example, the connection relationship between the input terminal and the output terminal of the selection unit, or the external connection relationship of the selection unit can be configured, for example, the connection relationship of the selection unit The connection relationship between the input or output and other units, and so on.

The connection mode between the input terminal and the output terminal of the first selection unit 101 and the connection mode between the input terminal and the output terminal of the second selection unit 102 can be determined according to the first configuration information. The first configuration information may be pre-configured. When the first configuration information changes, the connection between the input terminal and the output terminal of the first selection unit 101 and the connection between the input terminal and the output terminal of the second selection unit 102 can be changed, so that multiple computing units 103 constitutes different data processing paths. The connection mode includes the output terminal of the first selection unit 101 connected to each input terminal of the first selection unit 101, and the output terminal of the second selection unit 102 connected to each input terminal of the second selection unit 102 end.

As shown in FIG. 2, in some embodiments, the device further includes: a first register 104 for storing first configuration information, and the first configuration information is used for configuring: the first selection unit 101 The connection relationship between the multiple input terminals of the first selection unit 101 and the multiple output terminals of the first selection unit 101, and/or the multiple input terminals of the second selection unit 102 and the multiple output terminals of the second selection unit 102 The connection relationship between the output terminals. The first selection unit 101 may be connected to the first register 104 to obtain the first configuration information from the first register 104. Similarly, the second selection unit 102 can also be connected to the first register 104 to obtain the first configuration information from the first register 104. The number of the first register 104 can be one or more, and the number can be determined according to the length of the first configuration information and the width of the first register 104.

As shown in FIG. 3A and FIG. 3B, it is a schematic diagram of the connection mode of the first selection unit 101 and the second selection unit 102 in some embodiments of the present disclosure, and the data processing path formed by each arithmetic unit 103 in this connection mode. Schematic. In FIG. 3A, the input terminal 1 and the output terminal 2, the input terminal 2 and the output terminal 4, and the input terminal 3 and the output terminal 1 of the first selection unit 101 are connected correspondingly, and the input terminal 1 and the output terminal 1 of the second selection unit 102 , The input terminal 2 and the output terminal 2, the input terminal 4 and the output terminal 3 are connected correspondingly. The data processing path thus constituted includes arithmetic unit 2, arithmetic unit 4, and arithmetic unit 1 in sequence.

4A and 4B are schematic diagrams of the connection modes of the first selection unit 101 and the second selection unit 102 in some other embodiments of the present disclosure, and the data processing path formed by each arithmetic unit 103 in this connection mode Schematic diagram. In FIG. 4A, the input terminal 1 and the output terminal 1, the input terminal 2 and the output terminal 2, the input terminal 3 and the output terminal 3, and the input terminal 4 and the output terminal 4 of the first selection unit 101 are connected correspondingly, and the second selection unit 102 The input terminal 1 and the output terminal 2, the input terminal 2 and the output terminal 3, the input terminal 3 and the output terminal 4, and the input terminal 4 and the output terminal 1 are connected correspondingly. The data processing path thus constructed includes arithmetic unit 1, arithmetic unit 2, arithmetic unit 3, and arithmetic unit 4 in sequence.

Those skilled in the art can understand that the above connection modes and the embodiments of the data processing path are only exemplary descriptions, and the present disclosure is not limited thereto. In practical applications, the number of input terminals and the number of output terminals of the first selection unit 101 and the connection mode can be set according to needs. In addition, both the first selection unit 101 and the second selection unit 102 may be a single selection unit, or may be a selection unit composed of multiple selection units. The implementation of the selection unit is not limited in the present disclosure, as long as the selection function described in the above example can be realized. For example, the selection unit can be realized by a combinational logic constructed by a basic gate circuit.

Among them, the arithmetic unit 103 may include various types of arithmetic units. Regarding the implementation of the arithmetic unit, there is no limitation in this disclosure. For example, the computing unit can directly call IP cores from common eda vendors. The type of operation unit may include but is not limited to at least one of an arithmetic operation unit and a logic operation unit, or at least one of a vector operation unit, a scalar operation unit, and a matrix operation unit, and so on. Among them, the arithmetic operation unit may include but is not limited to at least one of the following: addition and subtraction operation unit, multiplication operation unit, division operation unit, exponent operation unit, logarithm operation unit, square root operation unit, trigonometric function operation unit, derivative operation unit, integral Operation unit, convolution operation unit, rounding operation unit, etc. The logical operation unit may include an AND operation unit, an OR operation unit, a negation operation unit, and so on. The number of each type of arithmetic unit can be one or more. Each arithmetic unit 103 may include one or more input terminals, and may also include one or more output terminals. When an arithmetic unit 103 includes multiple input terminals, each input terminal of the arithmetic unit 103 is connected to an output terminal of the first selection unit 101; when an arithmetic unit 103 includes multiple output terminals, the arithmetic Each output terminal of the unit 103 is connected to an input terminal of the second selection unit 102.

The operation type of one or more of the operation units 103 can be configured according to actual conditions. For example, the selection comparator can be configured to find the maximum value, find the minimum value, find the maximum value of accumulation, etc.; the addition and subtraction operation unit can be configured to perform addition or subtraction operations; the accumulation operation unit can be configured to find accumulation or perform addition operations ; The exponent of the exponent operation unit can be configured as the operand or the opposite of the operand. In some embodiments, the device further includes: a second register 105 for storing second configuration information, and the second configuration information is used for configuring the operation type of at least a part of the plurality of arithmetic units 103 . At least a part of the plurality of arithmetic units 103 can be connected to the second register 105 to obtain the second configuration information from the second register 105. The number of the second register 105 can be one or more, and the number can be determined according to the length of the second configuration information and the width of the second register 105.

In some embodiments, the first register 104 and the second register 105 may be the same register, and a part of the storage space in the register is used for storing the first configuration information, and the other part of the storage space is used for Store the second configuration information. For example, bits 1 to N1 of the register are used to store first configuration information, and bits N1+1 to N2 are used to store second configuration information. In some embodiments, the first register 104 and the second register 105 may also be different registers.

In some embodiments, the multiple input terminals of the first selection unit 101 include at least one first input terminal, and the first input terminal is connected to the data input port of the data processing device for inputting the original operand. . The first input terminal is also referred to as an operand input terminal. The data input port of the data processing device can obtain the original operand from a random access memory, an external control unit or other data processing devices. In practical applications, the connection of the first input terminal to the data input port of the data processing device may also include the case where the first input terminal itself is used as the data input port of the data processing device.

When performing an operand operation, first input an operand to an operand input terminal of the first selection unit 101, and the first selection unit 101 outputs the operand to one or more output terminals of the first selection unit 101, and then The output is output to the arithmetic unit 103 connected to the one or more output terminals for calculation, and an intermediate calculation result is obtained. The intermediate operation result is output to the input terminal of the second selection unit 102 connected to the operation unit 103 through the output terminal of the operation unit 103, and then output from the input terminal of the second selection unit 102 to the output terminal of the second selection unit 102, and then by The output terminal of the second selection unit 102 is output to the input terminal of the first selection unit 101, and the above process is repeated, and so on, until the final operation result is obtained, and the final operation result can be output to the data through the second selection unit 102 The data output port of the processing device. The operand input to the first selection unit 101 can also be used as the final operation result after the operation unit 103 performs the operation, and then is directly output to the data output port of the data processing device through the second selection unit 102.

In some embodiments, the arithmetic unit 103 is configured to detect valid identification information in the input data, and in response to detecting the valid identification information in the input data, perform operations on the input data. The input data may be the original operand or the intermediate operation result after the operation unit 103. After the operation unit 103 calculates the original operand and obtains the intermediate operation result, the effective identification information can be combined with the intermediate operation result. The calculation result is output to the second selection unit 102 together.

In this embodiment, the calculation operation is started by writing valid identification information to the first selection unit 101. Only after the valid identification information is written, the calculation operation is started, otherwise, the calculation operation is not performed. During an operation, when the number of a set of operands input to a certain input terminal of the first selection unit 101 is multiple, each operand in the set of operands can carry the effective identification information.

For example, when the data input to the operand input terminal of the first selection unit 101 is {1, x, 2, x, 3}, only the three operands 1, 2, and 3 are valid operands that need to be operated on. Both x are invalid operands. At this time, operands 1, 2 and 3 can carry the effective identification information, and x does not carry the effective identification information, so that effective operands and invalid operands can be distinguished. Only when the operand carries the valid identification information, the arithmetic unit 103 will process the operand, and the operand that does not carry the valid identification information will not be processed, thereby saving the power consumption of the data processing device. .

In some embodiments, the device further includes: at least one delay unit 106; the input terminal of the delay unit 106 is connected to the output terminal of the first selection unit 101, and the output terminal of the delay unit 106 is connected to the output terminal of the first selection unit 101. The input terminal of the second selection unit 102; the delay unit 106 is used to delay processing the data received from the output terminal of the first selection unit 101, and transmit the delayed processed data to the The input terminal of the second selection unit 102. Since different types of arithmetic units require different time to perform operations, the delay unit 106 time-aligns the data at each input end of the arithmetic unit 103 to ensure that each input data of the arithmetic unit 103 with multiple inputs arrives effectively at the same time. In the example of the present disclosure, the delay unit may be implemented by a register tap (for example, by a shift register).

這一運算，首先需要通過指數運算單元對操作數進行指數運算，再將指數運算的結果輸入到加法運算單元的第一輸入端，將運算參數1輸入到加法運算單元的第二輸入端，然後由加法單元對兩個輸入端的數據進行相加運算。由於加法運算單元的第一輸入端的數據相對於第二輸入端的數據會存在延遲，因此，可以將運算參數1先輸入到一個延遲單元進行延遲處理，再輸入到加法運算單元的第二輸入端，以使加法運算單元的第一輸入端和第二輸入端的數據同時到達。 For example, for

This operation first needs to perform exponential operation on the operand through the exponential operation unit, and then input the result of the exponential operation to the first input terminal of the addition operation unit, and input the operation parameter 1 into the second input terminal of the addition operation unit, and then The addition unit performs the addition operation on the data at the two input terminals. Since the data at the first input terminal of the addition operation unit is delayed relative to the data at the second input terminal, the operation parameter 1 can be input to a delay unit for delay processing, and then input to the second input terminal of the addition operation unit. So that the data of the first input terminal and the second input terminal of the addition unit arrive at the same time.

In some embodiments, the device further includes: at least one third register 107, the input terminal of the third register 107 is connected to the output terminal of the second selection unit 102, and the third register The output terminal of the device 107 is connected to the input terminal of the first selection unit 101, or is connected to the data output port of the data processing device. Wherein, the output terminal of the third register 107 is connected to the data output port of the data processing device, and may also include the output terminal of the third register 107 as the data output port of the data processing device Situation. The data output port can be connected to a random access memory or other data processing device. By providing the third register 107, the data transmission delay inside the data processing device can be reduced.

In some embodiments, the multiple input terminals of the first selection unit 101 include at least one second input terminal, and the second input terminal is connected to the output terminal of the second selection unit 102 through a connecting line, or through The connection line is connected to the fourth register for storing the operation parameters. The connection line represents the connection of the two unit ports, and is correspondingly implemented as a metal trace on the chip. The operation parameter is a constant operation parameter. For example, for the operation function y=1+x, "1" is the operation parameter. The number of the fourth register may be one or more, and each fourth register may be used to store operation parameters with different values, for example, 0, ±1, ±2, ±Max, etc. The connecting line can selectively connect the second input terminal of the first selection unit 101 to the output terminal of the second selection unit 102 or the fourth register according to the third configuration information.

The third register and the fourth register may be the same or different registers. In some embodiments, the data processing device may include a shared cache memory unit for the multiple computing units to share, or The second selection unit and/or the first selection unit are further provided for temporarily storing data, for example, temporarily storing one or more of original operands, operation parameters, and operation results, which is not done in the embodiment of the present disclosure. limited.

In actual application scenarios, the above various configuration information (including first configuration information, second configuration information, third configuration information, and fourth configuration information) may all be configuration codes or other types of configuration information. The above various configuration information can be different parts of the same configuration information, or different configuration information.

The configuration information of some embodiments of the present disclosure is shown in FIG. 5. For example, bits 1 to c1 are the first configuration information, bits c1+1 to c1+c2 are second configuration information, and bits c1+c2+1 to c1+c2+c3 are third Configuration information, bits c1+c2+c3+1 to bits c1+c2+c3+c4 are the fourth configuration information. The fourth configuration information can be used to configure the number of delay cycles of the delay unit 106. According to different fourth configuration information, the number of delay cycles of the delay unit 106 can be configured as one or more clock cycles. By configuring the internal connection mode of the first selection unit 101 and the second selection unit 102, the operation type of each arithmetic unit 103, and/or the connection mode of the connecting line, it is possible to adapt to various complex operation types and improve the complexity of the data processing device. Utilization rate.

The above-mentioned values of c1, c2, and c3 can be the same or different, and the order of each part in the configuration information can also be adjusted according to actual needs. For example, the first to c2 bits in the configuration information can be the second configuration information , The c2+1th bit to the c1+c2th bit may be the first configuration information. The function and length of each part of the configuration information can be set in advance.

The above configuration information (first, second, third, fourth configuration information, etc.) can respectively correspond to each part of the total configuration information, or it can be separate configuration information; when it is separate configuration information, it can be stored In the same register, it can also be stored in different registers.

In one operation, the configuration information remains unchanged. After an operation is completed, the configuration information can be changed to change the operation type of the operation path or at least one operation unit on the operation path. Wherein, the one-time operation process refers to the process from inputting a set of operands to one or more input terminals of the first selection unit 101 until outputting a set of final operation results corresponding to the set of operands, where the first A set of operands input by each input terminal of the selection unit 101 may include one or more operands, and a set of operands from the same input terminal are input to the input terminal in turn.

，

，……，

，m為每組原始操作數中的原始操作數的總數，則首先分別向k個輸入端輸入

，再分別向k個輸入端輸入

，以此類推，對應得到最終運算結果

。從輸入

，直到得到

的過程稱為一次運算過程。當需要同時向第一選擇單元101的多個輸入端輸入原始操作數時，各個輸入端輸入的原始操作數可以先經過時間對齊再輸入到第一選擇單元101的多個輸入端。 Suppose that a set of original operands are input to each of the k input terminals of the first selection unit 101, and the original operands of each input terminal of each input terminal are respectively

,

,...,

, M is the total number of original operands in each group of original operands, first input to k input terminals

, And then input to the k input terminals respectively

, And so on, corresponding to the final calculation result

. Input from

Until you get

The process is called an operation process. When the original operands need to be input to multiple input terminals of the first selection unit 101 at the same time, the original operands input by each input terminal may be time-aligned before being input to the multiple input terminals of the first selection unit 101.

In the embodiment of the present disclosure, through two configurable selection units, one or more original operands are mapped and connected to the input of the arithmetic unit, and then the operation result of the arithmetic unit is remapped and connected to the input of the next arithmetic unit until Get the final calculation result and output it. In this way, data and calculations "flow". During a calculation process, the configuration information is kept unchanged, so that the calculation path is solidified during a calculation process, and multiple arithmetic unit pipeline operations are automatically formed according to the configuration information to complete efficient calculations. Before the final operation result is obtained, the operation result output by each operation unit can be directly input to the next operation unit to continue the operation without being stored in the random access memory. In this way, the number of accesses is reduced and the work is reduced. Consumption. Further, if the arithmetic function is more complicated, you can perform operations on a part of the arithmetic function first, write the final operation result obtained into the random access memory, and then read the final operation result from the random access memory. Perform an operation on another part of the arithmetic function, and then write the final operation result of the other part into the random access memory, and repeat this many times to obtain the final operation result of the entire arithmetic function. After completing an operation process, the configuration information can be re-input to change the connection mode between the various operation units, so that the device of the embodiment of the present disclosure can be applied to multiple types of calculation formulas, realize the efficient reuse of resources, and save area and work. To obtain a higher energy consumption ratio.

In the embodiment of the present disclosure, different configuration information can be determined in advance for different arithmetic functions, and then the determined configuration information can be stored. Later, when different arithmetic functions need to be used, different configuration information can be called. When the configuration information changes, the connection relationship of the line will also change accordingly.

In the embodiments of the present disclosure, the number of arithmetic units, the number of connecting lines, and the width of the configuration code can be configured differently according to actual needs, so as to realize more types of operations and have stronger scalability. The input original operand can be a vector or a scalar, can be a fixed-point number, or a floating-point number, as long as the type of the arithmetic unit and the bit width of the delay unit can be adjusted.

The total number of arithmetic units, the total number of delay units, the total number of input terminals used by the first selection unit to input operands, and the total number of input terminals connected to the second selection unit among the input terminals of the first selection unit can be the same or different , The above quantities can be set according to actual needs.

The following uses a specific embodiment as an example to describe the solution of the embodiment of the present disclosure. Sigmoid (y=1/(e-x+1)) is a common activation function in neural networks. Its calculation process involves basic operations such as exponential operation, addition operation and division operation. The Sigmoid function can be shown in Figure 6. The device shown is implemented. As shown in Figure 6, in this embodiment, the device function is reconstructed into a Sigmoid activation function operation through reasonable configuration. The specific configuration method is as follows:

Step 1: Sigmoid is a unary function with only one operand. Assuming that it comes from the operand input terminal 1 of the first selection unit, connect the operand input terminal 1 to the input terminal of the exponential unit through configuration;

Step 2: Connect the output terminal of the exponent unit to an input terminal of the addition unit through configuration;

Step 3: The connecting line 1 is configured to connect one output terminal of the third register for outputting operation parameter 1 to the other input terminal of the addition unit and to the dividend input terminal of the division unit at the same time;

Step 4: Connect the output terminal of the addition unit to the divisor input terminal of the division unit through configuration;

Step 5: Configure the operation mode of the exponent unit as exp(-x), and configure the addition unit to perform addition operation;

Step 6: Connect the output terminal of the division unit to the final result output terminal through configuration.

The above-mentioned calculation path formed by configuration realizes the complete Sigmoid function calculation. The embodiment of the present disclosure can cover a large number of simple and complex operation types through limited operation units and connecting lines by modifying the configuration code.

The embodiments of the present disclosure can realize an efficient, flexible, configurable, and highly expandable data processing device, and can efficiently realize a variety of complex operations, while taking into account area and power consumption. The devices of the embodiments of the present disclosure can be used to implement various types of activation function operations in neural network operations. Most of the activation functions appearing in neural network operations are complex functions, and hardware devices that support neural network operations have certain requirements in terms of versatility and scalability. Using the embodiments of the present disclosure, one device can be used to achieve multiple activations. function.

The embodiments of the present disclosure also provide an artificial intelligence chip, which includes the data processing device described in any of the above embodiments. For the embodiment of the data processing device in the artificial intelligence chip, please refer to the embodiment of the above-mentioned data processing device for details, which will not be repeated here.

In some embodiments, the artificial intelligence chip further includes: a control unit configured to control the data processing device so that multiple arithmetic units in the data processing device form different arithmetic paths.

In some embodiments, the control unit is further configured to configure the configuration information of the data processing device, so that multiple arithmetic units in the data processing device form different arithmetic paths. In the embodiments of the present disclosure, the implementation form of the control unit is not limited, as long as each module or unit or component can be configured and corresponding operands can be provided. For example, the control unit can be implemented as some qualified ones. Peripheral circuits, etc.

In some embodiments, the configuration information includes at least any one of the following: first configuration information for configuring the relationship between the multiple input terminals of the first selection unit and the multiple output terminals of the first selection unit The connection relationship, and/or the connection relationship between the multiple input terminals of the second selection unit and the multiple output terminals of the second selection unit, and the second configuration information is used to configure the multiple arithmetic units At least part of the operation type.

In some embodiments, the multiple input terminals of the first selection unit include at least one first input terminal; the control unit is further configured to: write the original operand into the at least one first input terminal of the first selection unit. Input terminal.

The embodiment of the data processing device in the aforementioned artificial intelligence chip is the same as the embodiment of the aforementioned data processing device, and will not be repeated here. For an example of the configuration information configured through the control unit in the artificial intelligence chip, please refer to the configuration information in the embodiment of the aforementioned data processing device, which will not be repeated here.

Those skilled in the art will easily think of other embodiments of the present disclosure after considering the specification and practicing the specification disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptive changes of the present disclosure. These variations, uses, or adaptive changes follow the general principles of the present disclosure and include common knowledge or conventional technical means in the technical field that are not disclosed in the present disclosure. . The description and the embodiments are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are pointed out by the following claims.

It should be understood that the present disclosure is not limited to the precise structure that has been described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.

The above are only the preferred embodiments of the present disclosure and are not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the present disclosure. Within the scope of protection.

101: The first selection unit 102: The second selection unit 103: arithmetic unit 104: The first register 105: second register 106: Delay unit 107: Third register

Fig. 1 is a schematic structural diagram of a data processing device according to an embodiment of the present disclosure. Fig. 2 is a schematic structural diagram of a data processing device according to other embodiments of the present disclosure. FIG. 3A is a schematic diagram of the connection mode of each unit in the data processing device of some embodiments of the present disclosure. Fig. 3B is a schematic diagram of a data processing path corresponding to the connection shown in Fig. 3A. FIG. 4A is a schematic diagram of the connection modes of the units in the data processing device according to other embodiments of the present disclosure. Fig. 4B is a schematic diagram of a data processing path corresponding to the connection shown in Fig. 4A. FIG. 5 is a schematic diagram of configuration information of an embodiment of the present disclosure. Fig. 6 is a schematic structural diagram of a data processing device according to a specific embodiment of the present disclosure.

101: The first selection unit 102: The second selection unit 103: arithmetic unit

Claims (14)

A data processing device includes: a first selection unit with a plurality of input terminals and a plurality of output terminals; a second selection unit with a plurality of input terminals and a plurality of output terminals; and a plurality of arithmetic units; A plurality of input terminals are configurably connected to a plurality of output terminals of the first selection unit, at least a part of the plurality of output terminals of the first selection unit is connected to the input terminals of the plurality of arithmetic units, and the plurality of The output terminals of the arithmetic unit are connected to the multiple input terminals of the second selection unit, and the multiple input terminals of the second selection unit are configurably connected to the multiple output terminals of the second selection unit. At least a part of the multiple output terminals of the selection unit is connected to the multiple input terminals of the first selection unit, and/or is connected to the data output port of the data processing device, so that the multiple arithmetic units have different configurations的Computer Path. The data processing device according to claim 1, further comprising: a first register for storing first configuration information, and the first configuration information is used for configuring: a plurality of input terminals of the first selection unit and The connection relationship between the multiple output terminals of the first selection unit, and/or the connection relationship between the multiple input terminals of the second selection unit and the multiple output terminals of the second selection unit. The data processing device according to claim 1 or 2, further comprising: a second register for storing second configuration information, and the second configuration information is used for The operation type of at least a part of the plurality of operation units is configured. The data processing device according to claim 1 or 2, wherein the multiple input terminals of the first selection unit include at least one first input terminal, and the first input terminal is connected to the data input port of the data processing device Connection, used to enter the original operand. The data processing device according to claim 1 or 2, wherein the arithmetic unit is used to detect valid identification information in the input data, and in response to detecting the valid identification information in the input data, perform processing on the input data Perform calculations. The data processing device according to claim 1 or 2, further comprising: at least one delay unit; the input terminal of the delay unit is connected to the output terminal of the first selection unit, and the output terminal of the delay unit is connected to the output terminal of the first selection unit. The input terminal of the second selection unit; the delay unit is used to delay processing the data received from the output terminal of the first selection unit, and transmit the delayed processed data to the second selection The input terminal of the unit. The data processing device according to claim 1 or 2, further comprising: at least one third register, the input terminal of the third register is connected to the output terminal of the second selection unit, and the third temporary register The output terminal of the memory is connected to the input terminal of the first selection unit, or is connected to the data output port of the data processing device. The data processing device according to claim 1 or 2, wherein the multiple input terminals of the first selection unit include at least one second input terminal, and the second input terminal The input terminal is connected to the output terminal of the second selection unit through a connecting line, or is connected to a fourth register for storing operation parameters through a connecting line. The data processing device according to claim 1 or 2, wherein the multiple operation units include at least one arithmetic operation unit and/or at least one logical operation unit. An artificial intelligence chip, comprising the data processing device according to any one of claims 1 to 9. The artificial intelligence chip according to claim 10, further comprising: a control unit configured to control the data processing device so that a plurality of arithmetic units in the data processing device form different arithmetic paths. The artificial intelligence chip according to claim 11, wherein the control unit is further configured to configure the configuration information of the data processing device so that the multiple arithmetic units in the data processing device constitute different operations path. The artificial intelligence chip according to claim 12, wherein the configuration information includes at least any one of the following: first configuration information for configuring the multiple input terminals of the first selection unit and the first selection unit The connection relationship between the multiple output terminals, and/or the connection relationship between the multiple input terminals of the second selection unit and the multiple output terminals of the second selection unit, and the second configuration information is used for configuration The operation type of at least a part of the plurality of operation units. The artificial intelligence chip according to any one of claims 11 to 13, wherein the multiple input terminals of the first selection unit include at least one first input terminal; the control unit is further configured to: write the original operand At least one first input terminal of the first selection unit.

Images