TWI740467B - Resistive memory apparatus and adjusting method for write-in voltage thereof - Google Patents

Abstract

A resistive memory apparatus and an adjusting method for write-in voltage thereof are provided. The adjusting method includes: selecting a tested memory cell array of a resistive memory; performing N times reset operations on a plurality of memory cells of the tested memory cell array according to a reset voltage, and performing N times set operations on the memory cells of the tested memory cell array according to a set voltage, where N is an integer larger than 1; calculating a reset time variation rate of the reset operations and a set time variation rate of the set operations; and adjusting a voltage value of one of the set voltage and the reset voltage according to the reset time variation rate and the set time variation rate.

Description

Resistive memory device and its writing voltage adjustment method

The present invention relates to a resistive memory device, and more particularly to a method for adjusting the writing voltage of the resistive memory device.

In the technical field of resistive memory, environmental factors, process drift, and other possible causes may cause uneven physical characteristics of multiple memory cells between a single integrated circuit and between a die and a die. In such a situation, how to set the write voltage (including the set voltage and the reset voltage) of the resistive memory so that the reset time and the set time of the memory cell can be balanced has become an important issue.

The invention provides a resistive memory and a method for adjusting its write voltage, which can balance the time required for the reset operation and the setting operation.

The method for adjusting the write voltage of the present invention is suitable for resistive memory. The method for adjusting the writing voltage includes: selecting the memory cell array under test in the resistive memory; performing N reset operations for the memory cells in the memory cell array under test according to a reset voltage, and Perform N setting actions on the memory cell according to the set voltage, where N is an integer greater than 1; calculate the reset time change rate of the reset action and the set time change rate of the set action; and according to the reset time change rate and the set time change Rate to adjust one of the set voltage and the reset voltage.

The resistive memory device of the present invention includes a memory cell array under test and a controller. The controller is coupled to the memory cell array under test. The controller is used to execute the above-mentioned adjustment method of the write voltage.

Based on the above, the embodiment of the present invention performs multiple reset actions and multiple setting actions for part of the memory cell array under test in the resistive memory. And according to the reset time change rate of the reset action and the set time change rate of the setting action, to adjust one of the reset voltage and the setting voltage, so that the reset action of the resistive memory and the setting action can be adjusted. The required writing time can be balanced, and the use efficiency of the resistive memory can be improved.

Please refer to FIG. 1. FIG. 1 is a flowchart of a method for adjusting a write voltage according to an embodiment of the present invention. The method for adjusting the write voltage of this embodiment is suitable for resistive memory. The write action of the resistive memory includes a reset action and a setting action, and the write voltage includes a reset voltage and a set voltage. In step S110, the resistive memory can be selected to select one of the memory arrays as the memory cell array to be tested. Next, in step S120, the multiple memory cells in the memory cell array under test are respectively performed N reset operations according to a reset voltage, and the multiple memory cells are set N times according to a set voltage. Action, where N is an integer greater than 1. Here, in the above-mentioned one reset operation, after a reset voltage is applied to the memory cell for a period of time, the resistance value of the memory cell can be verified to know whether the reset operation is completed. If the verification result indicates that the resistance value of the memory cell is still If it is not high enough, the reset voltage is applied to the memory cell again. The aforementioned reset voltage application action can be performed one or more times until the resistance value of the memory cell is greater than the preset threshold value. Similarly, in the one-time setting action mentioned above, after applying the setting voltage to the memory cell for a period of time, the resistance value of the memory cell can be verified to know whether the setting action is completed. If the verification result indicates that the resistance value of the memory cell is not low enough , Then apply the set voltage to the memory cell again. The above-mentioned application of the set voltage can be performed one or more times until the resistance value of the memory cell is less than another preset threshold.

Next, in step S130, the reset time change rate of the multiple reset operations described above is calculated, and the set time change rate of the multiple set operations described above is calculated. Please note here that the memory cell of resistive memory may change its physical characteristics due to multiple write operations. Therefore, the first time required to perform the first reset action on the memory cell may be different from the second time required to perform the Nth reset action on the memory cell. Generally, the second time is greater than the first time. time. In the same way, the third time required to perform the first setting action for the memory cell may be different from the fourth time required to perform the Nth setting action for the memory cell, usually the fourth time is greater than the third time .

The change rate of the reset time in step S130 can be calculated based on the first time and the second time mentioned above. In this embodiment, the change rate of the reset time is equal to the difference between the second time and the first time divided by the first time. For a time. Similarly, the set time change rate can be calculated based on the aforementioned third time and fourth time. In this embodiment, the set time change rate is equal to the difference between the fourth time and the third time, divided by the third time.

Next, in step S140, the set voltage is adjusted according to the reset time change rate and the set time change rate obtained in step S130 to reset the voltage value of one of the voltages. In detail, in step S140, the reset time change rate and the set time change rate can be compared first, and when the absolute value of the difference between the reset time change rate and the set time change rate is greater than the preset threshold At the time, the adjustment mechanism of setting the voltage to reset the voltage value of one of the voltages is activated. Wherein, if the set time change rate is greater than the reset time change rate, the set voltage is selected for adjustment, and if the reset time change rate is greater than the set time change rate, the reset voltage is selected for adjustment.

Here, when the setting time change rate is too large, it means that after multiple setting actions, the memory cell needs a longer setting time to perform the setting action. Therefore, in this embodiment, by increasing the absolute value of the setting voltage, the setting time of the memory cell can be shortened, and the setting time required for the memory cell to perform the setting operation and the reset operation required for the reset operation can be shortened. The reset time can be close to each other, maintaining the time balance between the reset action and the reset action of the memory cell. Of course, when the reset time change rate is too large, it means that after multiple reset actions, the memory cell needs a longer reset time to perform the setting action. Therefore, in this embodiment, the reset time of the memory cell can be shortened by increasing the absolute value of the reset voltage, thereby maintaining the time balance between the setting action and the reset action of the memory cell.

Please refer to FIG. 2. FIG. 2 is a flowchart of a test operation of a resistive memory according to an embodiment of the present invention. Wherein, in step S210, a forming operation is performed for all memory cells in the resistive memory. Here, for the formation of the resistive memory cell, a bias voltage can be applied to the memory cell. When the electric field on the memory cell exceeds a critical value, the dielectric layer will collapse like a phenomenon, and the dielectric layer will be transformed into a resistive memory cell. Change characteristics. The forming action is used to initialize the resistive memory cell.

Then, step S220 executes a test initialization action, and step S230 executes a user function test for the resistive memory. In step S240, the memory cell array under test is selected from the resistive memory, and the writing time collection action is performed for the memory cell array under test. And in step S250, the analysis operation of the written data obtained in step S240 is executed. Note here that the writing time collection action of step S240 can be performed by performing N setting actions and N reset actions on multiple memory cells of the memory cell array under test, and the reset action of the reset action can be calculated. Time change rate and set time change rate of setting action. The aforementioned N is any integer greater than one.

Please note that the above N can be set by the designer without a fixed limit.

In step S260, the calculation of the absolute value (|Tset-Treset|) of the difference between the set time change rate Tset and the reset time change rate Treset is performed. When the absolute value of the difference between the set time change rate Tset and the reset time change rate Treset is greater than the preset threshold X, the reset voltage or the adjustment mechanism of the set voltage is activated, and step S270 is executed. If the absolute value of the difference between the set time change rate Tset and the reset time change rate Treset is not greater than the preset critical value X, the test procedure is ended. Next, in step S270, it is determined whether the set time change rate Tset is greater than the reset time change rate Treset. When the set time change rate Tset is greater than the reset time change rate Treset, step S271 is executed. On the other hand, when the set time change rate Tset is less than the reset time change rate Treset, step S281 is executed.

In step S271, the reset time change rate Treset is subtracted from the set time change rate Tset, and it is determined whether the change rate difference between the set time change rate Tset and the reset time change rate Treset is greater than a preset reference value Y. When the above-mentioned change rate difference is greater than the reference value Y, it indicates that the set voltage needs to be adjusted relatively greatly. Therefore, in step S272, the set voltage V_SET is added to the first voltage AV to increase the voltage value of the set voltage. When the above-mentioned change rate difference is less than the reference value Y, it means that the setting voltage only needs a relatively low amplitude adjustment. Therefore, in step S273, the setting voltage V_SET is added to the second voltage BV to increase the voltage value of the setting voltage. The first voltage AV is greater than the second voltage BV.

In step S281, the reset time change rate Treset is subtracted from the set time change rate Tset, and it is determined whether the change rate difference between the reset time change rate Treset and the set time change rate Tset is greater than the preset reference value Y. When the aforementioned change rate difference is greater than the reference value Y, it indicates that the reset voltage needs to be adjusted by a relatively large amount. Therefore, in step S282, the reset voltage V_RESET is added to the third voltage aV to increase the voltage value of the reset voltage. When the above-mentioned change rate difference is less than the reference value Y, it means that the reset voltage only needs a relatively low amplitude adjustment. Therefore, in step S283, the reset voltage V_RESET is added to the fourth voltage bV to increase the reset voltage. value. The third voltage aV is greater than the fourth voltage bV.

Finally, in step S290, the above-mentioned reset voltage and setting voltage adjustment information are written into the storage device, and then the test process is ended. Please note here that the adjustment information of the reset voltage and the set voltage can be written into the storage device in the form of digital data. The storage device can be any volatile or non-volatile memory element, and there is no fixed limit.

In this embodiment, the process of FIG. 2 can be executed when the resistive memory is performing a test action. Moreover, when the test operation is completed, the resistive memory adjusts the reset voltage and the set voltage of the initialization according to the adjustment information of the reset voltage and the set voltage to operate all the memory arrays except the tested memory array.

It is worth mentioning that the memory cell array under test can be a part of resistive memory. In other words, the steps S240 to S290 in FIG. 2 can be performed only for a small part of the resistive memory, which can speed up the adjustment of the write voltage.

3A, FIG. 3B, FIG. 4A, and FIG. 4B respectively show examples in which the writing time shifts after multiple operations. The example in the figure is to perform multiple reset actions on multiple memory cells of the tested memory cell array, and after multiple setting actions are performed on multiple memory cells of the tested memory cell array, multiple reset actions are recorded respectively To obtain the curve CV1, and record the setting time of multiple setting actions to obtain the curve CV2.

Hereinafter, referring to FIG. 3A, FIG. 3B, FIG. 4A, and FIG. 4B, the method for adjusting the write voltage of the present invention will be described. In FIG. 3A, the first reset time tWT1_1 required to perform the first reset action is, for example, 0.6 milliseconds; the second reset time tWT1_N required to perform the Nth reset action is, for example, 0.69 milliseconds; The first setting time tWT0_1 required for the second setting action is, for example, 0.7 milliseconds; the second setting time tWT0_N required to perform the Nth setting action is, for example, 1.0 milliseconds. Based on this, the reset time change rate = (tWT1_N-tWT1_1) / tWT1_1 = 0.15 can be calculated, and the set time change rate = (tWT0_N – tWT0_1) / tWT0_1 = 0.43. Furthermore, the difference between the set time change rate and the reset time change rate = 0.28 can be calculated.

Under the premise that the set time change rate is greater than the reset time change rate, by judging whether the difference between the set time change rate and the reset time change rate is greater than the preset reference value Y, step S272 or S273 of Figure 2 can be executed to adjust the setting The voltage value of the voltage, and increase the energy of the set action.

In FIG. 3B, the first reset time tWT1_1 required to perform the first reset action is, for example, 1.0 millisecond; the second reset time tWT1_N required to perform the Nth reset action is, for example, 1.15 milliseconds; The first setting time tWT0_1 required for the second setting action is, for example, 0.7 milliseconds; the second setting time tWT0_N required for performing the Nth setting action is, for example, 1.1 milliseconds. Based on this, the reset time change rate = (tWT1_N-tWT1_1) / tWT1_1 = 0.15 can be calculated, and the set time change rate = (tWT0_N – tWT0_1) / tWT0_1 = 0.57. Furthermore, the difference between the set time change rate and the reset time change rate = 0.42 can be calculated. Similarly, on the premise that the set time change rate is greater than the reset time change rate, by determining whether the difference between the set time change rate and the reset time change rate is greater than the preset reference value Y, step S272 or S273 of FIG. 2 can be executed. Adjust the voltage value of the set voltage and increase the energy of the set action.

In FIG. 4A, the first reset time tWT1_1 required to perform the first reset action is, for example, 1.0 millisecond; the second reset time tWT1_N required to perform the Nth reset action is, for example, 1.5 milliseconds; The first setting time tWT0_1 required for the second setting action is, for example, 0.8 milliseconds; the second setting time tWT0_N required for performing the Nth setting action is, for example, 0.92 milliseconds. Based on this, the reset time change rate = (tWT1_N-tWT1_1) / tWT1_1 = 0.50, and the set time change rate = (tWT0_N – tWT0_1) / tWT0_1 = 0.15 can be calculated. Furthermore, the difference between the reset time change rate and the set time change rate = 0.35 can be calculated.

Based on the reset time change rate being greater than the set time change rate, and then by judging whether the difference between the reset time change rate and the set time change rate is greater than the preset reference value Y, step S282 or S283 of Figure 2 can be executed to adjust the reset voltage And increase the energy of the reset action.

In FIG. 4B, the first reset time tWT1_1 required to perform the first reset action is, for example, 0.7 milliseconds; the second reset time tWT1_N required to perform the Nth reset action is, for example, 1.05 milliseconds; The first setting time tWT0_1 required for the second setting action is, for example, 1.0 millisecond; the second setting time tWT0_N required for performing the Nth setting action is, for example, 1.15 milliseconds. Based on this, the reset time change rate = (tWT1_N-tWT1_1) / tWT1_1 = 0.50, and the set time change rate = (tWT0_N – tWT0_1) / tWT0_1 = 0.15 can be calculated. Furthermore, the difference between the reset time change rate and the set time change rate = 0.35 can be calculated.

Also based on the reset time change rate being greater than the set time change rate, and then by judging whether the difference between the reset time change rate and the set time change rate is greater than the preset reference value Y, step S282 or S283 of Figure 2 can be executed to adjust the reset The voltage value of the voltage, and increase the energy of the reset action.

Please refer to FIG. 5. FIG. 5 is a schematic diagram of a resistive memory device according to an embodiment of the present invention. The resistive memory device 500 includes a memory block 510, a controller 520, a storage device 530, and a voltage generator 540. When performing the write voltage adjustment operation, the controller 520 can select a memory cell array 511 under test from the memory block 510, and execute the write voltage adjustment process as shown in FIG. 1 for the memory cell array 511 under test. The details of the actions performed by the controller 520 are described in the foregoing embodiments and implementations in detail, and will not be repeated here.

The controller 520 can also write the adjustment information IFO of the reset voltage VRESET and the set voltage VSET into the storage device 530. The storage device 530 can be any form of memory, and there is no specific limitation. The voltage generator 540 is used to provide the reset voltage VRESET and the setting voltage VSET to the memory block 510. The controller 530 can adjust the voltage values of the reset voltage VRESET and the set voltage VSET generated by the voltage generator 540 according to the adjustment information IFO of the reset voltage VRESET and the set voltage VSET recorded by the storage device 530.

In terms of hardware architecture, the controller 520 may be a processor with computing capability. Alternatively, the controller 520 can be designed through hardware description language or other well-known digital circuit design methods, and implemented through field programmable logic gate arrays, complex programmable logic devices, or integrated circuits for special applications. The hardware circuit.

In summary, the present invention performs multiple reset actions and setting actions on part of the memory cell array under test in the resistive memory. By recording the reset time change rate of the reset action and the reset time change rate of the setting action, determine whether the set energy of the set action and the reset energy of the reset action are insufficient, and adjust the set voltage or reset accordingly The voltage value of the voltage. In this way, the reset action and setting action of the resistive memory can be balanced, and the use efficiency can be improved.

S110~S140: Steps to adjust the write voltage S210~S290: Steps to test actions CV1, CV2: Curve tWT1_1, tWT1_N: reset time tWT0_1, tWT0_N: set time 500: Resistive memory device 510: memory block 520: Controller 530: storage device 540: Voltage Generator 511: Tested memory cell array VRESET: reset voltage VSET: set voltage IFO: adjustment information

FIG. 1 shows a flowchart of a method for adjusting a write voltage according to an embodiment of the present invention. FIG. 2 is a flowchart of a test operation of a resistive memory according to an embodiment of the present invention. 3A, FIG. 3B, FIG. 4A, and FIG. 4B respectively show schematic diagrams of operations of the write voltage adjustment method according to different embodiments of the present invention. FIG. 5 is a schematic diagram of a resistive memory device according to an embodiment of the invention.

S110~S140: Steps to adjust the write voltage

Claims (15)

A method for adjusting the writing voltage, which is suitable for a resistive memory, includes: selecting a tested memory cell array in the resistive memory; according to a reset voltage to target a plurality of the tested memory cell arrays The memory cells perform N reset actions, and perform N setting actions on the memory cells according to a set voltage, where N is an integer greater than 1, and calculate a reset time change rate of the reset actions and the Setting a set time change rate of the setting action; and adjusting one of the set voltage and the reset voltage according to the reset time change rate and the set time change rate includes: comparing the reset time change rate and The set time change rate is used to determine the voltage value of the reset voltage or the voltage value of the set voltage. The adjustment method according to claim 1, wherein the step of calculating the reset time change rate of the reset actions includes: calculating a first reset time of the first reset action and the Nth reset action A second reset time, the difference between the second reset time and the first reset time is divided by the first reset time to generate the reset time change rate. The adjustment method according to claim 1, wherein the step of calculating the setting time change rate of the setting actions includes: Calculate a first setting time of the first setting action and a second setting time of the Nth setting action, and divide the difference between the second setting time and the first setting time by the first setting time to generate the Set the time rate of change. The adjustment method according to claim 1, wherein when the reset time change rate is greater than the set time change rate, the voltage value of the reset voltage is selected to be adjusted; when the set time change rate is greater than the reset time change rate , Select and adjust the voltage value of the set voltage. The adjustment method according to claim 4, wherein when the reset time change rate is greater than the set time change rate, it further comprises: calculating a change rate difference between the reset time change rate and the set time change rate; When the change rate difference is greater than a preset reference value, increase the reset voltage to a first voltage; and when the change rate difference is not greater than the reference value, increase the reset voltage to a second voltage, The first voltage is greater than the second voltage. The adjustment method according to claim 4, wherein when the set time change rate is greater than the reset time change rate, the method further includes: calculating a change rate difference between the set time change rate and the reset time change rate; When the change rate difference is greater than a preset reference value, increase the set voltage by a first voltage; and when the change rate difference is not greater than the reference value, increase the set voltage by a second voltage, where The first voltage is greater than the second voltage. The adjustment method according to claim 1, further comprising: recording adjustment information of the reset voltage and the set voltage in a storage device. A resistive memory device includes: a memory cell array under test; and a controller, coupled to the memory cell array under test, for: according to a reset voltage to target the number of memory cell arrays under test Memory cells perform N reset actions, and perform N setting actions on the memory cells according to a set voltage, where N is an integer greater than 1, calculate a reset time change rate of the reset actions and the A set time change rate of the setting actions; and adjust one of the set voltage and the reset voltage according to the reset time change rate and the set time change rate, wherein the controller compares the reset time change And the set time change rate to determine the voltage value of the reset voltage or the voltage value of the set voltage. The resistive memory device according to claim 8, wherein the controller calculates a first reset time of the first reset action and a first reset time of the Nth reset action Two reset time, the difference between the second reset time and the first reset time is divided by the first reset time to generate the reset time change rate. The resistive memory device according to claim 8, wherein the controller calculates a first setting time of the first setting action and a second setting time of the Nth setting action, so that the second setting time is the same as the first setting time The difference of a set time is divided by the first set time to generate the set time change rate. The resistive memory device according to claim 8, wherein when the reset time rate of change is greater than the set time rate of change, the controller selects to adjust the voltage value of the reset voltage; when the set time rate of change is greater than the reset time rate When the time rate of change is set, the controller chooses to adjust the voltage value of the set voltage. The resistive memory device according to claim 11, wherein when the reset time change rate is greater than the set time change rate, the controller is configured to: calculate the reset time change rate and a change rate of the set time change rate When the change rate difference is greater than a preset reference value, increase the reset voltage a first voltage; and when the change rate difference is not greater than the reference value, increase the reset voltage one The second voltage, wherein the first voltage is greater than the second voltage. The resistive memory device according to claim 11, wherein when the set time change rate is greater than the reset time change rate, the controller is configured to: Calculate a change rate difference between the set time change rate and the reset time change rate; when the change rate difference is greater than a preset reference value, increase the set voltage by a first voltage; and when the change rate When the difference is not greater than the reference value, increase the set voltage by a second voltage, where the first voltage is greater than the second voltage. The resistive memory device according to claim 8, further comprising: a storage device coupled to the controller for recording adjustment information of the reset voltage and the set voltage. The resistive memory device according to claim 8, further comprising: a write voltage generator, coupled to the controller and the memory cell array under test, for generating the setting voltage and the reset voltage.

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